Thin film transistor substrate

Abstract

To effectively assemble an oxide semiconductor TFT to a thin film transistor circuit.SOLUTION: A first oxide semiconductor film contains: a first resistance region; a second resistance region; and a channel region of a first thin-film transistor that overlaps a gate electrode. Each of the first resistance region and the second resistance region contains a source / drain region of the first thin-film transistor. A second oxide semiconductor film contains: a third resistance region; a fourth resistance region; and a channel region of a second thin-film transistor. Each of the third resistance region and the fourth resistance region contains the source / drain region of the second thin-film transistor. One part of a region extended from the source / drain region of the first thin-film transistor of the first resistance region constructs a bottom gate electrode that overlaps the channel region of the second thin-film transistor.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a thin film transistor substrate. [Background technology]

[0002] Oxide semiconductor thin film transistors (TFTs) such as IGZO (Indium-Gallium-Zinc-Oxide) are used in displays such as liquid crystal display panels and OLED (Organic Light-Emitting Diode) displays, as well as other devices. Oxide semiconductor TFTs have low leakage current, which allows the power consumption of the device to be reduced. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent Application No. 2021 / 0013245 [Patent Document 2] U.S. Patent Application No. 2011 / 0049507 Summary of the Invention [Problem to be solved by the invention]

[0004] Generally, oxide semiconductor TFTs have a lower mobility than low-temperature polysilicon TFTs. Therefore, oxide semiconductor TFTs with higher mobility are being developed. However, there are some reports that high-mobility oxide semiconductor TFTs are less reliable than low-mobility oxide TFTs. Therefore, it is required to appropriately configure oxide semiconductor TFTs including oxide semiconductor films with different characteristics on the same substrate in response to various requirements for thin-film transistor circuits. [Means for solving the problem]

[0005] A thin film transistor substrate according to an embodiment of the present disclosure includes a first oxide semiconductor film, a second oxide semiconductor film having different characteristics from the first oxide semiconductor film and located above the first oxide semiconductor film, a first insulating film below the second oxide semiconductor film and covering the first oxide semiconductor film, and a gate electrode of a first thin film transistor. The first oxide semiconductor film includes a first low resistance region, a second low resistance region, and a channel region of the first thin film transistor overlapping with the gate electrode between the first low resistance region and the second low resistance region. The first low resistance region and the second low resistance region each include a source / drain region of the first thin film transistor. The second oxide semiconductor film includes a third low resistance region, a fourth low resistance region, and a channel region of a second thin film transistor between the third low resistance region and the fourth low resistance region. The third low resistance region and the fourth low resistance region each include a source / drain region of the second thin film transistor. A part of the first low resistance region extending from the source / drain region of the first thin film transistor constitutes a bottom gate electrode overlapping a channel region of the second thin film transistor. Effect of the Invention

[0006] According to one aspect of the present disclosure, an oxide semiconductor TFT can be effectively incorporated into a thin film transistor circuit. [Brief description of the drawings]

[0007] [Figure 1] 1 illustrates an example configuration of an OLED display device according to an embodiment of the present specification. [Diagram 2] 2A and 2B are schematic diagrams showing examples of the cross-sectional structure of an oxide semiconductor TFT that can be incorporated into a pixel circuit or a peripheral circuit of a TFT substrate. [Figure 3A] The interface in a stacked structure of a low-temperature polysilicon layer and two insulating layers is shown diagrammatically. [Figure 3B] 13A and 13B are schematic diagrams illustrating an interface between an oxide semiconductor layer and two insulating films in a stacked structure. [Figure 4] 1 shows an example of the configuration of a pixel circuit of an OLED display device. [Diagram 5] 5A and 5B are schematic diagrams showing examples of the cross-sectional structure of an oxide semiconductor TFT that can be incorporated into the pixel circuit shown in FIG. [Figure 6A] FIG. 6 is a plan view showing some of the components shown in FIG. 5. [Figure 6B] FIG. 6 is a plan view showing some of the components shown in FIG. 5. [Figure 7] 5 is a schematic diagram showing another example of a cross-sectional structure of an oxide semiconductor TFT that can be incorporated into the pixel circuit shown in FIG. [Figure 8] FIG. 8 is a plan view showing some of the components shown in FIG. 7. [Figure 9] 2A and 2B are schematic diagrams illustrating another example of a cross-sectional structure of an oxide semiconductor TFT. [Figure 10] 2A and 2B are schematic diagrams illustrating another example of a cross-sectional structure of an oxide semiconductor TFT. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. It should be noted that this embodiment is merely an example for realizing the present invention and does not limit the technical scope of the present invention. The same reference symbols are used for common configurations in each drawing. For ease of explanation, the dimensions and shapes of the objects shown in the drawings may be exaggerated.

[0009] [Overview] The following describes the configuration of a thin film transistor substrate (TFT substrate) including an oxide semiconductor thin film transistor according to the present disclosure. The TFT substrate according to an embodiment of the present specification can be applied to various devices, such as a sensor device or a display device.

[0010] There are various demands, such as reduction in power consumption, reduction in circuit size, and improvement in reliability. In order to meet such various demands, one embodiment of the present disclosure configures oxide semiconductor TFTs including oxide semiconductor regions with different characteristics on the same substrate. The oxide semiconductor TFTs with different characteristics include, for example, oxide semiconductor regions with different elemental compositions. The different elemental compositions include different types of constituent elements or different composition ratios of the same element type.

[0011] In one embodiment of the present specification, the oxide semiconductor region of the first type of oxide semiconductor TFT is on and in contact with a first insulating layer, and the oxide semiconductor region of the second type of oxide semiconductor TFT is on and in contact with a second insulating layer different from the first insulating layer. This configuration allows the oxide semiconductor material to be selected from many oxide semiconductor materials for use on the TFT substrate.

[0012] For example, oxide semiconductor TFTs have low leakage current and low temperature dependency. In order to reduce the circuit size, for example, it is possible to use an oxide semiconductor material with high mobility. However, in general, the reliability of oxide semiconductor materials decreases when the mobility is high. In order to increase the reliability of oxide TFTs, it is possible to use an oxide semiconductor material with a large band gap or small mobility.

[0013] The characteristics that are important for an oxide semiconductor TFT change depending on the function of the TFT in a circuit. For example, an oxide semiconductor TFT used as a switch can be constructed using an oxide semiconductor material with high mobility, and an oxide semiconductor TFT that changes current in an analog manner can be constructed using an oxide semiconductor material with low mobility. For example, in a circuit that controls the light emission of a light-emitting element, a TFT that changes current in an analog manner adjusts the amount of drive current supplied to the light-emitting element in response to a data signal (control signal) given via a switch TFT.

[0014] In one embodiment of the present specification, a part of a low resistance region of an oxide semiconductor film, including a source / drain region of an oxide semiconductor TFT, is used as an electrode of another circuit element. In one embodiment of the present specification, a part of a low resistance region of an oxide semiconductor film is used as a source / drain region of an oxide semiconductor TFT, and another part is used as a gate electrode of another oxide semiconductor TFT.

[0015] The oxide semiconductor region of an oxide semiconductor TFT includes source / drain regions and a channel region therebetween. The source / drain regions are in contact with the channel region in the in-plane direction, respectively. The resistance of the channel region is lower than the resistance of the source / drain regions. The source / drain region is a general term for the source region and the drain region. The source / drain region can be either the source region or the drain region depending on the direction of the carriers flowing through the channel region. In a configuration in which a source / drain region is shared by two TFTs, the source / drain region can be the source region of one TFT and the drain region of the other TFT.

[0016] In one embodiment of the present specification, the low resistance region of the oxide semiconductor film includes the source / drain region of one oxide semiconductor TFT, and further extends therefrom to include the bottom gate electrode of another oxide semiconductor TFT. The bottom gate electrode is a gate electrode located below the oxide semiconductor region of the oxide semiconductor TFT, that is, closer to the substrate. This eliminates the need for contact holes connecting the source / drain electrodes and the bottom gate electrode of different oxide semiconductor TFTs.

[0017] [Display device configuration] 1 shows an example of the configuration of an OLED (Organic Light-Emitting Diode) display device 1 according to an embodiment of the present specification. The OLED display device 1 includes a TFT substrate 10 on which OLED elements and TFTs are formed, a sealing substrate 20 for sealing the OLED elements, and a joint (glass frit seal) 30 for joining the TFT substrate and the sealing substrate. Dry nitrogen, for example, is filled between the TFT substrate 10 and the sealing substrate 20, and the TFT substrate 10 and the sealing substrate 20 are sealed by the joint. The sealing substrate 20 and the joint 30 are one of the sealing structures, and as another example, the sealing structure may have, for example, a thin film encapsulation (TFE) structure.

[0018] Scan drivers 31 and 32, a protection circuit 33, a driver IC 34, and a demultiplexer 36 are arranged around the outside of the display area 25 of the TFT substrate 10. The scan drivers 31 and 32 and the protection circuit 33 are peripheral circuits formed on the TFT substrate. The number of each type of circuit in the peripheral circuits can vary depending on the design.

[0019] For example, the scan driver 31 drives the scan lines of the TFT substrate 10, and the scan driver 32 drives the control lines to control the light emission period of each pixel and to provide a reference potential to each pixel. The protection circuit 33 prevents damage to elements in the pixel circuit due to static electricity. The driver IC 34 provides power and timing signals (control signals) to the scan drivers 31 and 32. The driver IC 34 also provides power and data signals to the demultiplexer 36. The demultiplexer 36 switches the output data line of the data signal from the driver IC 34 d times during the scanning period, thereby driving data lines d times the number of output pins of the driver IC 34.

[0020] [TFT substrate configuration] 2 shows a schematic cross-sectional structure of an example of an oxide semiconductor TFT that can be incorporated into a pixel circuit or peripheral circuit of the TFT substrate 10. Similar oxide semiconductor TFTs can be incorporated into thin film transistor circuits of liquid crystal displays or other devices.

[0021] 2 shows a schematic cross-sectional structure example of the first oxide semiconductor TFT 170 and the second oxide semiconductor TFT 130. For example, the second oxide semiconductor TFT 130 is a driving TFT that adjusts the amount of driving current to an OLED element, and the first oxide semiconductor TFT 170 is a switch TFT that transmits a data signal (gate signal) to the gate electrode of the driving TFT 130.

[0022] The first oxide semiconductor TFT 170 and the second oxide semiconductor TFT 130 are formed on a flexible or inflexible insulating substrate 113 made of resin or glass. In the following description, of two layers stacked in contact with each other (two layers forming an interface), the layer closer to the insulating substrate 113 is the lower layer, and the layer farther from the insulating substrate 113 is the upper layer.

[0023] The oxide semiconductor film (first oxide semiconductor film) 173 of the first oxide semiconductor TFT 170 and the oxide semiconductor film (second oxide semiconductor film) 133 of the second oxide semiconductor TFT 130 have different characteristics. In this example, the mobility of the second oxide semiconductor film 133 is smaller than the mobility of the first oxide semiconductor film 173. In addition, the band gap of the first oxide semiconductor film 173 is smaller than the band gap of the second oxide semiconductor film 133.

[0024] Examples of oxide semiconductor materials applicable to the first oxide semiconductor film 173 include ITZO, IGZTO, In-Zn-Ti-O, and In-WZO. Examples of oxide semiconductor materials applicable to the second oxide semiconductor film 133 include IGZO, GaZnO, and IGO. The first oxide semiconductor film 173 and the second oxide semiconductor film 133 are composed of the same element type, for example, IGZO, and may have different element composition ratios.

[0025] An oxide semiconductor film (first oxide semiconductor film) 173 of the first oxide semiconductor TFT 170 is formed on and in contact with the first insulating film 115. An oxide semiconductor film (second oxide semiconductor film) 133 of the second oxide semiconductor TFT 130 is formed on and in contact with the second insulating film 119. The second insulating film 119 is located above the first insulating film 115. The first oxide semiconductor film 173 is located below the second oxide semiconductor film 133.

[0026] 2, the first oxide semiconductor film 173 is entirely formed on and in contact with the first insulating film 115. The second oxide semiconductor film 133 is entirely formed on and in contact with the second insulating film 119.

[0027] An insulating film 117 is present between the first insulating film 115 and the second insulating film 119. The insulating film 117 is formed on and in contact with the oxide semiconductor film 173 and the first insulating film 115. The insulating film 117 covers at least a portion of the oxide semiconductor film 173 and at least a portion of the first insulating film 115. A portion of the second insulating film 119 is formed on and in contact with the insulating film 117.

[0028] The first oxide semiconductor TFT 170 includes an oxide semiconductor region of a first oxide semiconductor film 173, a top gate electrode 171 located above the first oxide semiconductor film 133, and a gate insulating film present between the top gate electrode 171 and the first oxide semiconductor film 173 in the stacking direction. The gate insulating film is a part of the insulating film 117. The gate insulating film is in contact with and sandwiched between a lower surface of the top gate electrode 171 and an upper surface of the oxide semiconductor film 173. The top gate electrode 171 is covered with a second insulating film 119. A part of the second insulating film 119 is formed on and in contact with the top gate electrode 171.

[0029] The first oxide semiconductor film 173 includes an oxide semiconductor region of the first oxide semiconductor TFT 170. The oxide semiconductor region includes two source / drain regions 174, 176 and a channel region 172 between the source / drain regions 174, 176. The source / drain regions 174, 176 are included in different low resistance regions, and the channel region 172 is included in a high resistance region. The channel region 172 is covered by a top gate electrode 171 with a gate insulating film sandwiched therebetween in the stacking direction. The source / drain electrode 177 includes a contact portion 181 that penetrates the insulating films 122, 121, 119, and 117 and contacts an upper surface of the source / drain region 176.

[0030] The low-resistance region 175 of the first oxide semiconductor film 173 extends from the source / drain region 174 to the opposite side of the channel region 172, and a part of it constitutes the bottom gate electrode 150 of the second oxide semiconductor TFT 130. In this manner, by having a part of the low-resistance region 175 of the first oxide semiconductor film 173 constitute the bottom gate electrode of the second oxide semiconductor TFT 130, the number of contact holes can be reduced.

[0031] The second oxide semiconductor TFT 130 includes an oxide semiconductor region of the second oxide semiconductor film 133, a top gate electrode 131 above the second oxide semiconductor film 133, and a gate insulating film between the top gate electrode 131 and the second oxide semiconductor film 133 in the stacking direction. The gate insulating film is a part of the insulating film 121. The gate insulating film is in contact with and sandwiched between a lower surface of the top gate electrode 131 and an upper surface of the oxide semiconductor film 133.

[0032] The insulating film 121 is located above the second insulating film 119, and the insulating film 122 is located above the insulating film 121. The insulating film 121 is located between the second insulating film 119 and the insulating film 122. The insulating film 121 is formed on and in contact with the oxide semiconductor film 133 and the second insulating film 119. The insulating film 121 covers at least a part of the oxide semiconductor film 133 and at least a part of the second insulating film 119. A part of the insulating film 121 is formed on and in contact with the second insulating film 119. The top gate electrode 131 is covered by the insulating film 122. A part of the insulating film 122 is formed on and in contact with the top gate electrode 131. A part of the insulating film 122 is formed on and in contact with the insulating film 121.

[0033] The source / drain electrode 135 includes a contact portion 138 that penetrates the insulating films 122 and 121 and contacts the upper surface of the source / drain region 134. The source / drain electrode 137 includes a contact portion 139 that penetrates the insulating films 122 and 121 and contacts the upper surface of the source / drain region 136.

[0034] The second oxide semiconductor film 133 includes an oxide semiconductor region of the second oxide semiconductor TFT 130. The oxide semiconductor region includes two source / drain regions 134, 136 and a channel region 132 between the source / drain regions 134, 136. The source / drain regions 134, 136 are included in different low resistance regions, and the channel region 132 is included in a high resistance region. The channel region 132 is covered by the top gate electrode 131 with a gate insulating film sandwiched therebetween in the stacking direction.

[0035] As described above, a part of the region of the low-resistance region 175 extending from the source / drain region 174 of the first oxide semiconductor TFT constitutes the bottom gate electrode 150 overlapping with the channel region 132 of the second oxide semiconductor TFT. The bottom gate electrode 150 is included in the low-resistance region 175 and faces the channel region 132 across a part of the laminated insulating films 117 and 119. The part of the laminated insulating films 117 and 119 is the gate insulating film of the bottom gate electrode 150. This makes it possible to make the slope of the Id-Vgs characteristics of the second oxide semiconductor TFT gentler.

[0036] The insulating substrate 113 may be made of, for example, glass or a flexible or inflexible resin. An example of the resin is polyimide. The first insulating film 115 may be made of, for example, silicon nitride (SiNx), silicon oxide (SiOx), or a multilayer thereof.

[0037] The oxide semiconductor film 173 may be composed of, for example, ITZO, IGZTO, In-Zn-Ti-O, or In-WZO. The low resistance region can be formed, for example, by injecting impurity ions (for example, boron ions) into the region of the oxide semiconductor film through the insulating film 117 using the top gate electrode 171 as a mask (self-alignment). This can reduce ΔL, which is advantageous for miniaturizing the TFT. The low resistance region can also be formed by exposing the region to He plasma.

[0038] The insulating film 117, a part of which constitutes the gate insulating film of the first oxide semiconductor TFT 170, can be formed of, for example, silicon nitride, silicon oxide, or a multilayer of these. Any material can be used for the top gate electrode 171, and for example, a single layer or a multilayer of Mo, W, Nb, Al, Ta, Cr, Ti, or an alloy thereof can be used. The second insulating film 119 covering the top gate electrode 171 can be formed of, for example, silicon nitride, silicon oxide, or a multilayer of these.

[0039] The oxide semiconductor film 133 existing on and in contact with the second insulating film 119 can be made of, for example, IGZO, GaZnO, or IGO. The low resistance region can be formed, for example, by injecting impurity ions (for example, boron ions) into the region of the oxide semiconductor film through the insulating film 121 using the top gate electrode 131 as a mask (self-alignment). This can reduce ΔL, which is advantageous for miniaturizing the TFT. The low resistance region can also be formed by exposing the region to He plasma.

[0040] The insulating film 121, a part of which constitutes the gate insulating film of the second oxide semiconductor TFT 130, can be formed of, for example, silicon nitride, silicon oxide, or a multilayer of these. Any material can be used for the top gate electrode 131, and for example, a single layer or a multilayer of Mo, W, Nb, Al, Ta, Cr, Ti, or the like, or an alloy thereof can be used. The insulating film 122 covering the top gate electrode 131 can be formed of, for example, silicon nitride, silicon oxide, or a multilayer of these.

[0041] The source / drain electrodes 135, 137, 177 can be formed simultaneously using the same material. The source / drain electrodes 135, 137, 177 can have a laminated structure such as Ti / Al / Ti or Mo / Al / Mo. The source / drain electrodes 135, 137, 177 can have a single layer structure or can be made of a metal material different from the above metal materials.

[0042] 2, a low-resistance region including the source / drain regions of the first oxide semiconductor TFT 170 extends, and a part of the region forms the bottom gate electrode of the second oxide semiconductor TFT 130. The low-resistance region of the oxide semiconductor film is flatter and has fewer grain boundaries than a polysilicon film, and therefore, better characteristics of the second oxide semiconductor TFT 130 can be obtained.

[0043] 3A and 3B are schematic enlarged views of the portion enclosed by the dashed rectangle 38 in FIG. 2. Fig. 3A shows a schematic diagram of an interface in a laminated structure of a low-temperature polysilicon (LTPS) layer and two insulating films. Fig. 3B shows a schematic diagram of an interface in a laminated structure of an oxide semiconductor layer and two insulating films.

[0044] As shown in Fig. 3A, the surface of the low-temperature polysilicon shows significant irregularities, and the laminated insulating film on it also shows irregularities reflecting the shape. In addition, impurities such as H and C are localized at high density at the grain boundaries of the low-resistance polysilicon. Therefore, when the first oxide semiconductor TFT 170 is replaced with a low-temperature polysilicon TFT, the influence of the irregularities and impurities at the channel interface of the second oxide semiconductor TFT 130 becomes significant, which may degrade the characteristics.

[0045] On the other hand, as shown in FIG. 3B, the surface of the oxide semiconductor is flat, and the laminated insulating film thereon is also flat, reflecting the shape of the surface. Furthermore, the oxide semiconductor has substantially no grain boundaries and no localized impurities. Therefore, it is possible to prevent the characteristics of the second oxide semiconductor TFT 130 from being degraded.

[0046] The bottom gate insulating film of the second oxide semiconductor includes upper and lower insulating films 117 and 119 sandwiching the top gate electrode of the first oxide semiconductor TFT 170, so that the Id-Vgs characteristics of the second oxide semiconductor TFT 130 can be made gentle. On the other hand, the gate insulating film of the first oxide semiconductor TFT 170 is formed from a part of the insulating film 117, so that high driving performance can be obtained. In addition, by using an oxide semiconductor, it is possible to achieve a short channel of the first oxide semiconductor TFT 170 (for example, 2 μm or less).

[0047] 2, a bottom gate electrode may be present instead of or in addition to the top gate electrode 171 of the first oxide semiconductor TFT 170. When the top gate electrode 171 is omitted, the insulating film 119 or 117 may be omitted. The top gate electrode 131 of the second oxide semiconductor TFT 130 may be omitted.

[0048] [Configuration of TFT substrate in pixel circuit] Fig. 4 shows an example of the configuration of a pixel circuit of the OLED display device 1. The pixel circuit controls a current supplied to an anode electrode of an OLED element E1. The pixel circuit includes a drive transistor T1, a selection transistor T2, a control transistor T3, and a storage capacitor C1. The pixel circuit controls the light emission of the OLED element E1. In the example of Fig. 4, the transistors T1 to T3 are n-channel oxide semiconductor TFTs.

[0049] The selection transistor T2 is a switch for selecting a pixel. A scanning signal S1 is input to the gate terminal of the selection transistor T2. One source / drain terminal is connected to the data line 15. The other source / drain terminal is connected to the first gate terminal of the driving transistor T1. The second gate terminal of the driving transistor T1 is connected to its source terminal.

[0050] The driving transistor T1 is a transistor for driving the OLED element E1. The first gate terminal of the driving transistor T1 is connected to the source / drain terminal of the selection transistor T2. The drain terminal of the driving transistor T1 is connected to the power supply line 18 (Vdd). The source terminal is connected to the second gate terminal and the source / drain terminal of the control transistor T3. A storage capacitor C1 is formed between the first gate terminal and the source terminal of the driving transistor T1.

[0051] When the selection transistor T2 is turned on, the data voltage is stored in the storage capacitor C1 from the data line 15. The storage capacitor C1 holds the stored voltage throughout one frame period. The hold voltage causes the conductance of the drive transistor T1 to change in an analog manner, and the drive transistor T1 supplies a forward bias current corresponding to the emission gradation to the OLED element E1.

[0052] The control transistor T3 controls the electrical connection between the reference voltage supply line 11, which provides the reference voltage Vref, and the anode of the OLED element E1. This control is performed by supplying a control signal S2 to the gate terminal of the control transistor T3. The control transistor T3 can be used for various purposes. For example, the control transistor T3 may be used for the purpose of temporarily resetting the anode electrode of the OLED element E1 to a voltage sufficiently low below the black signal level in order to suppress crosstalk caused by leakage current between the OLED elements E1.

[0053] Alternatively, the control transistor T3 may be used to measure the characteristics of the drive transistor T1. For example, by selecting bias conditions so that the drive transistor T1 operates in the saturation region and the control transistor T3 operates in the linear region and measuring the current flowing from the power supply line 18 to the reference voltage supply line 11, the voltage-current conversion characteristics of the drive transistor T1 can be accurately measured. If a data signal that compensates for the difference in the voltage-current conversion characteristics of the drive transistor T1 between subpixels is generated by an external circuit, a highly uniform display image can be realized.

[0054] On the other hand, if the drive transistor T1 is turned off and the control transistor T3 is operated in the linear region, and a voltage that causes the OLED element E1 to emit light is applied from the reference voltage supply line 11, the voltage-current characteristics of the OLED element E1 can be accurately measured. For example, even if the OLED element E1 deteriorates due to long-term use, a data signal that compensates for the amount of deterioration can be generated by an external circuit to achieve a longer life. Note that FIG. 4 shows only one example of a pixel circuit, and the features of the present application can be applied to pixel circuits of any other configuration.

[0055] Fig. 6 is a schematic cross-sectional view showing an example of a cross-sectional structure of an oxide semiconductor TFT that can be incorporated into the pixel circuit shown in Fig. 4. Fig. 6 is a schematic cross-sectional view showing a device structure of the transistors T1 and T2 and the storage capacitor C1 in Fig. 4. The first oxide semiconductor TFT 170 corresponds to the transistor T2, and the second oxide semiconductor TFT 130 corresponds to the transistor T1. The bottom gate electrode 150 of the second oxide semiconductor TFT 130 corresponds to the first gate terminal of the transistor T1, and the top gate electrode 131 corresponds to the second gate terminal.

[0056] In the following, components different from those shown in Fig. 4 will be mainly described with reference to Fig. 6. A planarization film 161 is present on the source / drain electrodes 135, 137, 177 and the insulating film 122. The planarization film 161 may be composed of a coating-type organic film having excellent planarity, such as acrylic or polyimide. An anode electrode 163 is present on and in contact with the planarization film 161.

[0057] The anode electrode 163 is connected to the source / drain electrode 135 (source terminal) of the second oxide semiconductor TFT 130 via a contact portion 165 that penetrates the planarization film 161. The anode electrode 163 can be a laminated film of ITO and a metal material with high reflectivity, such as aluminum or silver.

[0058] A pixel definition layer 167 is formed on the anode electrode 163. The pixel definition layer 167 can be made of an organic film such as acrylic or polyimide. A part of the anode electrode 163 is exposed in an opening of the pixel definition layer 167, and a multi-layer organic film and a cathode electrode (not shown) are laminated on top of the exposed part. The organic film emits light when a current is supplied. The cathode electrode of each pixel is part of a single conductive film, and is supplied with a common cathode power supply potential. The cathode electrode can be made of, for example, ITO.

[0059] In the upper oxide semiconductor film 133, at least a part of the low-resistance region 141 including the source / drain region 134 faces at least a part of the low-resistance region 175 of the lower oxide semiconductor film 173 via the insulating films 119 and 117. In this region, at least a part of the storage capacitance C1 is configured.

[0060] Fig. 6A is a plan view showing some components shown in Fig. 5. In the configuration example shown in Fig. 5, the top gate electrode 131 of the second oxide semiconductor TFT 130 is not connected to the source / drain electrodes 135. A predetermined potential is applied to the top gate electrode 131 via a path that bypasses the source / drain electrodes 135.

[0061] A part of the conductive film 307 constitutes the top gate electrode 171 of the first oxide semiconductor TFT 170. The top gate electrode 171 is a portion of the conductive film 307 that overlaps with a channel region (high resistance region, not shown in FIG. 6A) of the oxide semiconductor film 173.

[0062] The bottom gate electrode 150 is a region facing a channel region of the upper oxide semiconductor film 133 in the low resistance region 175 of the oxide semiconductor film 173. Although not indicated by a reference symbol in FIG. 6, the top gate electrode 131 of the second oxide semiconductor TFT 130 may be a region of the conductor film 303 that overlaps with the bottom gate electrode 150 in a plan view.

[0063] A part of the low resistance region 175 of the lower oxide semiconductor film 173 overlaps with the low resistance region 141 of the upper oxide semiconductor film 133 in a plan view. A part of the storage capacitor C1 is configured in this region. By configuring the low resistance region 175 of the lower oxide semiconductor film 173 as an electrode of the storage capacitor in this manner, the circuit area can be reduced.

[0064] In the configuration example of FIG. 6A, the low-resistance region 175 and the low-resistance region 141 have a strip shape extending in the horizontal direction of FIG. 6A. The low-resistance region 175 and the low-resistance region 141 extend in a direction intersecting with the conductive films 303 and 307. In a region where the low-resistance region 175 and the low-resistance region 141 overlap in a planar view, the width W of the low-resistance region 175 is smaller than the width of the low-resistance region 141. In this region, an end that defines the width W of the low-resistance region 175 is covered by the low-resistance region 141 in a planar view. The width is the length in the vertical direction in FIG. 6A.

[0065] 6B is a plan view showing some components shown in FIG. 5. Compared with the configuration example of FIG. 6A, the channel width of the first oxide semiconductor TFT 170 is larger than the channel width of the second oxide semiconductor TFT 130. The width W of the oxide semiconductor film 173 and the low-resistance region 175 is larger. In a region where the low-resistance region 175 and the low-resistance region 141 overlap in a planar view, the width W of the low-resistance region 175 is larger than the width of the low-resistance region 141. In this region, an end that defines the width of the low-resistance region 141 overlaps with the low-resistance region 175 in a planar view. Therefore, the region where the low-resistance region 175 and the low-resistance region 141 overlap in a planar view is increased, and the area of ​​the storage capacitance C1 can be made larger.

[0066] Fig. 7 shows a schematic diagram of another example of the cross-sectional structure of an oxide semiconductor TFT that can be incorporated into the pixel circuit shown in Fig. 4. The differences from the configuration example shown in Fig. 5 will be mainly described. In this configuration example, the top gate electrode 131 of the second oxide semiconductor TFT 130 is connected to the source / drain electrode 135. In the configuration example shown in Fig. 7, the source / drain electrode 135 is connected to the top gate electrode 131 via a contact portion 145 that penetrates the insulating film 122 and contacts the upper surface of the top gate electrode 131. Therefore, the source / drain electrode 135 and the top gate electrode 131 have the same potential.

[0067] Fig. 8 is a plan view showing some components shown in Fig. 7. Differences from the configuration example shown in Fig. 6 will be mainly described. As described with reference to Fig. 7, the source / drain electrodes 135 of the second oxide semiconductor TFT 130 are connected to the top gate electrode 131 via the contact portion 145. Here, the contact portion 145 is in contact with the upper surface of the conductive film 303 including the top gate electrode 131, and the contact position is off the upper surface of the top gate electrode 131. The top gate electrode 131 is a region of the conductive film 300 that overlaps with the channel region (high resistance region) of the second oxide semiconductor TFT 130.

[0068] In this configuration example, there is a capacitance constituting a storage capacitance C1 in addition to the capacitance constituted by the opposing low-resistance regions of the two oxide semiconductor films 133 and 173. Specifically, the capacitance C1A is a capacitance in which a part of the low-resistance region 175 of the oxide semiconductor film 173 serves as a lower electrode and a part of the low-resistance region 141 of the oxide semiconductor film 133 serves as an upper electrode. Insulating films 117 and 119 are present between these electrodes.

[0069] Capacitors C1B and C1C each have a lower electrode that is a part of the low-resistance region 175 of the oxide semiconductor film 173 and an upper electrode that is a part of the conductor film 303 including the top gate electrode 131. Insulating films 117, 119, and 121 are present between these electrodes. Capacitors C1A, C1B, and C1C are separated without overlapping in a plan view and are parallel in the circuit.

[0070] 8, the region of the oxide semiconductor film 173 overlapping with the conductive film 303 extends along the conductive film 303. For example, the size in the channel width direction (vertical direction in FIG. 8) of the region of the oxide semiconductor film 173 overlapping with the conductive film 303 is larger than the size in the same direction of the contact portion 138 of the oxide semiconductor film 173. This can increase the capacitances C1B and C1C. For example, the total area where the conductive film 303 and the low-resistance region 175 face each other via multiple insulating films is larger than the area of ​​the channel region of the second oxide semiconductor TFT 130.

[0071] [Other configuration examples] Another example of the configuration of the second oxide semiconductor TFT will be described below. FIG. 9 shows a schematic diagram of another example of the cross-sectional structure of the oxide semiconductor TFT. In the following, differences from the configuration example shown in FIG. 2 will be mainly described. The first oxide semiconductor TFT 170 has a common configuration in the two configuration examples. In addition, since the insulating film 122 is omitted compared to the configuration example in FIG. 2, the upper end of the source / drain electrode 177 is in contact with the upper surface of the insulating film 121.

[0072] The upper second oxide semiconductor TFT 330 is a bottom gate type TFT that does not include a top gate electrode and includes only a bottom gate electrode, and is an ESL (Etch-Stop-Layer) type TFT.

[0073] The second oxide semiconductor TFT 330 includes an oxide semiconductor region of a second oxide semiconductor film 333 that exists on and in contact with the second insulating film 119. The oxide semiconductor region of the second oxide semiconductor film 333 includes source / drain regions 334, 336 and a channel region 332 therebetween. An end face of the channel region 332 is in contact with an end face of the source / drain regions 334, 336 in the in-plane direction.

[0074] The source / drain electrode 335 includes a contact portion 338 that penetrates the insulating film 121 and contacts the upper surface of the source / drain region 134. The source / drain electrode 337 includes a contact portion 339 that penetrates the insulating film 121 and contacts the upper surface of the source / drain region 336. The channel region 332 is covered with the insulating film 121. Therefore, it is possible to prevent the channel region 332 from being exposed to an etchant when the insulating film 121 is etched to form the source / drain electrodes 335, 337. The first oxide semiconductor TFT 170 and the second oxide semiconductor TFT 330 are covered with the planarization film 161.

[0075] Fig. 10 is a schematic diagram showing another example of the cross-sectional structure of an oxide semiconductor TFT. In the following, differences from the configuration example shown in Fig. 2 will be mainly described. The two configuration examples have the same configuration of the first oxide semiconductor TFT 170. Note that, compared to the configuration example in Fig. 2, the insulating films 121 and 122 are omitted, and therefore the upper ends of the source / drain electrodes 177 are in contact with the upper surface of the insulating film 119.

[0076] The upper second oxide semiconductor TFT 430 is a bottom gate type TFT that does not include a top gate electrode and includes only a bottom gate electrode, and the second oxide semiconductor TFT 330 is a BCE (Back-Channel-Etch) type TFT.

[0077] The second oxide semiconductor TFT 430 includes an oxide semiconductor region of a second oxide semiconductor film 433 that exists on and in contact with the second insulating film 119. The oxide semiconductor region of the second oxide semiconductor film 433 includes source / drain regions 434, 436 and a channel region 432 therebetween. An end face of the channel region 432 is in contact with an end face of the source / drain regions 434, 436 in the in-plane direction.

[0078] The source / drain electrode 435 is in contact with the upper surface and side surfaces of the source / drain region 434 without an insulating film therebetween. A portion of the source / drain electrode 435 is in contact with the upper surface of the insulating film 119. The source / drain electrode 437 is in contact with the upper surface and side surfaces of the source / drain region 436 without an insulating film therebetween. A portion of the source / drain electrode 437 is in contact with the upper surface of the insulating film 119. The planarizing film 161 is in contact with and covers the source / drain electrodes 435, 437 as well as the channel region 432.

[0079] Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments. A person skilled in the art can easily change, add, or convert each element of the above embodiments within the scope of the present disclosure. It is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. [Explanation of symbols]

[0080] 1 OLED display device, 10 TFT substrate, 11 reference voltage supply line, 15 data line, 18 power supply line, 20 sealing substrate, 25 display area, 30 junction, 31, 32 scan driver, 33 protection circuit, 34 driver IC, 36 demultiplexer, 113 insulating substrate, 115, 117, 119, 219, 315, insulating film, 131, 171 gate electrode, 132, 172 gate insulating film, 133, 173 oxide semiconductor film, 135, 137, 177 source / drain electrode, 132, 172 channel region, 134, 136, 174, 176 source / drain region, C1 storage capacitance, C1A, C1B, C1C capacitance, E1 OLED element, T1 to T3 transistor, 130, 170 oxide semiconductor TFT

Claims

1. A thin film transistor substrate, a first oxide semiconductor film; a second oxide semiconductor film located above the first oxide semiconductor film; a first insulating film covering the first oxide semiconductor film below the second oxide semiconductor film; a gate electrode of the first thin film transistor; Including, the first oxide semiconductor film includes a first low-resistance region, a second low-resistance region, and a channel region of the first thin film transistor between the first low-resistance region and the second low-resistance region, the channel region overlapping with the gate electrode; the first low-resistance region and the second low-resistance region each include a source / drain region of the first thin film transistor; the second oxide semiconductor film includes a third low-resistance region, a fourth low-resistance region, and a channel region of a second thin film transistor between the third low-resistance region and the fourth low-resistance region; the third low-resistance region and the fourth low-resistance region each include a source / drain region of the second thin film transistor; a part of a region of the first low resistance region extending from the source / drain region of the first thin film transistor forms a bottom gate electrode overlapping with a channel region of the second thin film transistor; Thin film transistor substrate.

2. 2. The thin film transistor substrate according to claim 1, further comprising a second insulating film located above the first insulating film; the gate electrode of the first thin film transistor is a top gate electrode; the second insulating film covers the top gate electrode; a portion of the first insulating film is present between the top gate electrode and a channel region of the first thin film transistor, and another portion of the first insulating film is present between the bottom gate electrode and a channel region of the second thin film transistor; a thin film transistor substrate, wherein a portion of the second insulating film is present between the bottom gate electrode and a channel region of the second thin film transistor;

3. 3. The thin film transistor substrate according to claim 2, another part of the first low-resistance region extending from the source / drain region of the first thin film transistor overlaps with a part of the third low-resistance region, with a multi-insulating film including the first insulating film and the second insulating film sandwiched therebetween, to form a first capacitance element; Thin film transistor substrate.

4. 4. The thin film transistor substrate according to claim 3, The second thin film transistor further includes a conductive film including a top gate electrode thereof; the conductive film is connected to the third low-resistance region, a part of the first low-resistance region and a part of the conductor film overlap with an insulating film sandwiched therebetween, thereby forming a second capacitance element in parallel with the first capacitance element; Thin film transistor substrate.

5. 2. The thin film transistor substrate according to claim 1, the first thin film transistor is a switch transistor, the second thin film transistor is a transistor that adjusts the amount of current in a channel region in response to a control signal; Thin film transistor substrate.

6. 6. The thin film transistor substrate according to claim 5, The mobility of the channel region of the second thin film transistor is lower than the mobility of the channel region of the first thin film transistor; Thin film transistor substrate.

7. 2. The thin film transistor substrate according to claim 1, the first oxide semiconductor film and the second oxide semiconductor film are different in material or composition ratio; Thin film transistor substrate.

8. 2. The thin film transistor substrate according to claim 1, The second thin film transistor further includes a top gate electrode. Thin film transistor substrate.

9. 2. The thin film transistor substrate according to claim 1, The channel width of the first thin film transistor is larger than the channel width of the second thin film transistor; Thin film transistor substrate.

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