Reference current circuit

Abstract

To provide a reference current circuit capable of supplying a stable reference current with high accuracy against temperature changes and capable of reducing an area.SOLUTION: A reference current circuit 100 includes: a current mirror circuit 110 which supplies Iout based on Iin; an E-type MOS 130 in which a gate 130G is connected to a drain 130D to which Iout is supplied, and a source 130S is grounded; a D-type MOS 140 in which the E-type MOS 130 and gate terminals are connected, and which generates Vref; a voltage division circuit 150 which outputs a divided voltage Vdiv of Vref; and a D-type MOS 160 which supplies Iin according to Vdiv. The E-type MOS 130 has the same channel conductivity type and impurity concentration as the D-type MOS 130, but has a different Fermi level of the gate electrode from the D-type MOS 130. The voltage division circuit 150 outputs Vdiv, which is higher than a threshold voltage and lower than a cross point X of the D-type MOS 160, to the gate terminal of the D-type MOS 160.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a reference current circuit. [Background technology]

[0002] Mobile devices, wearable devices, and other such devices are used in a variety of locations and climates, and so they are required to operate stably even in changing operating environments. In addition, as these devices become increasingly miniaturized, the semiconductor chips and other components mounted on them are also required to become smaller. Many of the semiconductor chips mounted on such devices include analog circuits, and the analog circuits are supplied with a reference current output from a reference current source as a bias current.

[0003] Some reference current circuits supply a reference current by converting a reference voltage generated by a reference voltage circuit into a current using a highly accurate resistor element. Various proposals have been made for such reference current circuits with the aim of supplying a stable reference current.

[0004] For example, many reference voltage circuits have been proposed that can suppress fluctuations in the reference voltage due to changes in the ambient temperature. One example is a reference voltage circuit that can reduce manufacturing variations by standardizing the structure of elements that are affected by changes in ambient temperature. Specifically, a reference voltage circuit has been proposed that has a pair of transistors equipped with gates with different Fermi levels and channels with the same conductivity type and the same impurity concentration, thereby offsetting the effects of changes in the conductivity coefficient of the channel (see Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2001-284464 A Summary of the Invention [Problem to be solved by the invention]

[0006] An object of one aspect of the present invention is to provide a reference current circuit that can supply a stable reference current with high accuracy despite changes in ambient temperature and that can reduce the layout area. [Means for solving the problem]

[0007] The reference current circuit according to an embodiment of the present invention comprises: a current mirror circuit formed of a pair of MOS transistors whose gate terminals are connected to each other, and which supplies an output current from one of the MOS transistors based on an input current input to the other MOS transistor; an output MOS transistor for supplying a reference current according to the voltage of the gate terminal of the MOS transistor pair; an enhancement type MOS transistor having a gate terminal connected to a drain terminal to which the output current is supplied from the current mirror circuit and a source terminal grounded; a first depletion-type MOS transistor, the gate terminal of which is connected to the enhancement-type MOS transistor, for generating a reference voltage based on a difference between a voltage at a source terminal of the enhancement-type MOS transistor and a voltage at a source terminal of the first depletion-type MOS transistor; a voltage divider circuit connected to a source terminal of the first depletion type MOS transistor and outputting a divided voltage of the reference voltage; a second depletion type MOS transistor that supplies a current corresponding to the divided voltage as the input current to the current mirror circuit; having the enhancement type MOS transistor has a channel of the same conductivity type and impurity concentration as the first depletion type MOS transistor, and has a gate electrode of a Fermi level different from that of the first depletion type MOS transistor; The voltage divider circuit outputs the divided voltage in a voltage range that is higher than a threshold voltage of the second depletion type MOS transistor and lower than a cross point at which the gate voltage-drain current characteristics of the second depletion type MOS transistor are independent of temperature to the gate terminal of the second depletion type MOS transistor. Effect of the Invention

[0008] An object of one aspect of the present invention is to provide a reference current circuit that can supply a stable reference current with high accuracy despite changes in ambient temperature and that can reduce the layout area. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a circuit diagram showing a reference current circuit according to the present embodiment. [Diagram 2] FIG. 2 is an explanatory diagram showing the operation of the reference voltage source using paired transistors in this embodiment. [Figure 3A] FIG. 3A is a schematic cross-sectional view showing the enhancement type MOS transistor shown in FIG. [Figure 3B] FIG. 3B is a schematic cross-sectional view showing the first depletion-type MOS transistor shown in FIG. [Figure 4] FIG. 4 is a band diagram showing the dependence of the Fermi level in silicon on temperature and impurity concentration. [Diagram 5] FIG. 5 is a graph showing the temperature characteristics of the reference voltage generated by the reference voltage source in this embodiment. [Figure 6] FIG. 6 is a graph showing the gate voltage-drain current characteristics of a depletion-type MOS transistor used as a constant current source in this embodiment. [Figure 7] FIG. 7 is an explanatory diagram showing the temperature characteristics of the input current supplied by the depletion-type MOS transistor in this embodiment. [Figure 8] FIG. 8 is a circuit diagram showing a modification of the voltage divider circuit shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and duplicate explanations may be omitted. In addition, the X-axis, Y-axis, and Z-axis shown in the drawings are mutually perpendicular. The X-axis direction may be referred to as the "width direction", the Y-axis direction as the "depth direction", and the Z-axis direction as the "height direction" or "thickness direction". The surface of each film on the +Z direction side may be referred to as the "front surface" or "upper surface", and the surface on the -Z direction side as the "rear surface" or "lower surface". Furthermore, the drawings are schematic, and the ratios of width, depth, and thickness are not as shown. The number, position, shape, structure, size, etc. of a plurality of films or layers, or a semiconductor element obtained by structurally combining them, are not limited to the embodiments shown below, and may be any number, position, shape, structure, size, etc. that is preferable for implementing the present invention.

[0011] FIG. 1 is a circuit diagram showing a reference current circuit according to the present embodiment. As shown in FIG. 1, the reference current circuit 100 includes a current mirror circuit 110, an output MOS transistor 120, an enhancement type MOS transistor 130, depletion type MOS transistors 140 and 160, and a voltage divider circuit 150. The current mirror circuit 110 includes a current mirror circuit 110, an output MOS transistor 120, an enhancement type MOS transistor 130, depletion type MOS transistors 140 and 160, and a voltage divider circuit 150.

[0012] The current mirror circuit 110 supplies an output current Iout based on an input current Iin supplied from a depletion-type MOS transistor 160. The current mirror circuit 110 is formed by a pair of MOS transistors 111 and 112 whose gate terminals are connected to each other.

[0013] The MOS transistor 111 is a P-channel MOS transistor, and has a gate terminal connected to a drain terminal and a source terminal connected to a power supply terminal. The drain terminal of this MOS transistor 111 is connected to a depletion-type MOS transistor 160, and an input current Iin from the depletion-type MOS transistor 160 flows between the source and drain.

[0014] The MOS transistor 112 is a P-channel MOS transistor, with a gate terminal connected to the gate terminal of the MOS transistor 111 and a source terminal connected to a power supply terminal. The MOS transistor 112 supplies an output current Iout from the drain terminal to the enhancement type MOS transistor 130. In addition, the gate terminal of the MOS transistor 112 is connected to the gate terminal of the output MOS transistor 120 .

[0015] The output MOS transistor 120 is a P-channel MOS transistor, and has a source terminal connected to a power supply terminal. The output MOS transistor 120 has a gate terminal connected to the gate terminal of the MOS transistor 112, and therefore supplies a reference current Iref according to the voltage of the gate terminal of the MOS transistor 112.

[0016] The MOS transistors 111 and 112 and the output MOS transistor 120 are formed in the same process. Therefore, the output current Iout has the same current value as the input current Iin due to the current mirror circuit 110, and the reference current Iref has the same current value as the output current Iout.

[0017] The enhancement type MOS transistor 130 is an N-channel MOS transistor, and has a gate terminal 130G connected to a drain terminal 130D to which an output current Iout is supplied from the current mirror circuit 110. Moreover, the enhancement type MOS transistor 130 has a gate terminal 130G connected to a gate terminal 140G of the depletion type MOS transistor 140, and a source terminal 130S grounded. The back gate of the enhancement type MOS transistor 130 is connected to a source terminal 130S and is grounded.

[0018] The depletion-type MOS transistor 140 as the first depletion-type MOS transistor is an N-channel MOS transistor. The depletion-type MOS transistor 140 has a gate terminal connected to the enhancement-type MOS transistor 130, and a source terminal 140S connected to the voltage divider circuit 150.

[0019] The pair of transistors, the enhancement-type MOS transistor 130 and the depletion-type MOS transistor 140, connected in this manner can generate a reference voltage Vref at the source terminal 140S of the depletion-type MOS transistor 140. If the current flowing through the depletion-type MOS transistor 140 is made approximately the same as the current flowing through the enhancement-type MOS transistor 130, the reference voltage Vref approaches the following equation: Vref=Vtne+|Vtnd|, where Vtne is the threshold voltage of the enhancement-type MOS transistor 130, and Vtnd is the threshold voltage of the depletion-type MOS transistor 140. The operation, structure and temperature characteristics of the pair of transistors used as the reference voltage source will be described later.

[0020] Moreover, the depletion-type MOS transistor 140 has a drain terminal 140D connected to a power supply terminal and a source terminal 140S connected to the voltage dividing circuit 150. Therefore, the depletion-type MOS transistor 140 functions as a source follower and a buffer, eliminating the need for a buffer using a differential amplifier that requires a large layout area, and thus reducing the layout area. In this embodiment, the drain terminal 140D is directly connected to the power supply terminal, but this is not limiting, and for example, a switching element, an ESD protection resistor, etc. may be connected in series.

[0021] The voltage divider circuit 150 is configured by connecting resistors 151 and 152 in series, and a predetermined voltage division ratio is set according to the ratio of the resistance values ​​of the resistors. When a reference voltage Vref is applied to the source terminal 140S of the depletion-type MOS transistor 140, the voltage divider circuit 150 divides the reference voltage Vref and outputs a divided voltage Vdiv to the gate terminal of the depletion-type MOS transistor 160. The voltage divider circuit 150 may include a trimming circuit using fuses or the like so that the voltage division ratio can be finely adjusted.

[0022] The depletion-type MOS transistor 160 serving as the second depletion-type MOS transistor is an N-channel MOS transistor. The depletion-type MOS transistor 160 has a drain terminal connected to the MOS transistor 111 of the current mirror circuit 110 and a source terminal grounded. The back gate of the depletion-type MOS transistor 160 is connected to the source terminal and is grounded.

[0023] The depletion-type MOS transistor 160 functions as a constant current source that supplies a current according to the divided voltage Vdiv applied to the gate terminal from the voltage divider circuit 150 to the current mirror circuit 110 as an input current Iin. Considering the temperature characteristics of the depletion-type MOS transistor 160, the voltage divider circuit 150 applies a divided voltage Vdiv in a predetermined voltage range to the gate terminal, so that the reference current circuit 100 can supply a stable reference current Iref with high accuracy against changes in the ambient temperature. Adjustment of the temperature characteristics of this reference current Iref will be described later.

[0024] - Operation and structure of reference voltage source - Next, a reference voltage source formed by a pair of transistors, the enhancement type MOS transistor 130 and the depletion type MOS transistor 140, will be described. FIG. 2 is an explanatory diagram showing the operation of the reference voltage source using paired transistors in this embodiment. 2, the combined resistance value of the voltage divider circuit 150 is adjusted in advance so that a current Id flows through the depletion-type MOS transistor 140 that is approximately the same as the current Ie (output current Iout) flowing through the enhancement-type MOS transistor 130. Since the gate terminals of this pair of transistors are connected to each other and the source terminal 130S of the enhancement-type MOS transistor 130 is grounded, a reference voltage Vref can be generated at the source terminal 140S of the depletion-type MOS transistor 140.

[0025] Moreover, the enhancement-type MOS transistor 130 has the same channel conductivity type and impurity concentration as the depletion-type MOS transistor 140, but has a different Fermi level of the gate electrode from that of the depletion-type MOS transistor 140. In other words, the enhancement-type MOS transistor 130 can be formed by the same process as the depletion-type MOS transistor 140, except for the part of the gate electrode where the Fermi level is different. This makes it possible to offset manufacturing variations in the channels of the enhancement-type MOS transistor 130 and the depletion-type MOS transistor 140, and generate the reference voltage Vref with high precision. As a result, the variation in the divided voltage Vdiv can be reduced, and the reference current circuit 100 can supply the reference current Iref with high precision.

[0026] Specifically, the structures of the enhancement-type MOS transistor 130 and the depletion-type MOS transistor 140 will be described with reference to FIGS. 3A, 3B, and 4. FIG. FIG. 3A is a schematic cross-sectional view showing the enhancement type MOS transistor shown in FIG. As shown in FIG. 3A, an enhancement type MOS transistor 130 has a gate electrode 130g, a drain region 130d, and a source region 130s connected to a gate terminal 130G, a drain terminal 130D, and a source terminal 130S shown in FIG. 1, respectively.

[0027] The gate electrode 130g is of P+ type with a high concentration of boron implanted, and has a Fermi level close to the valence band in the band diagram of Fig. 4. The channel 130c located below the gate electrode 130g is of N- type conductivity, and is formed by implanting a low concentration of phosphorus into the surface of the P-type silicon substrate 130b. Since the Fermi level of the gate electrode 130g is close to the valence band, the Fermi level of this channel 130c is raised toward the valence band and depleted. As a result, for example, when the potential difference between the gate and source is 0 V, no current path is formed in this N- type channel 130c even between the N+ type drain region 130d and the N+ type source region 130s, which have the same conductivity type. In this respect, the enhancement type MOS transistor 130 differs from a general enhancement type MOS transistor in which no impurities are implanted into the channel.

[0028] FIG. 3B is a schematic cross-sectional view showing the first depletion-type MOS transistor shown in FIG. As shown in FIG. 3B, the depletion-type MOS transistor 140 has a gate electrode 140g, a drain region 140d, and a source region 140s connected to the gate terminal 140G, the drain terminal 140D, and the source terminal 140S shown in FIG. 1, respectively.

[0029] The gate electrode 140g is of N+ type with a high concentration of phosphorus implanted therein, and has a Fermi level close to the conduction band in the band diagram of Fig. 4. The channel 140c located below the gate electrode 140g is of N- type conductivity, and is formed by implanting a low concentration of phosphorus into the surface of a P-type silicon substrate 140b in the same process as the channel 130c of the enhancement type MOS transistor 130. As a result, even if the potential difference between the gate and source is 0V, for example, a current path is formed in this N-type channel 140c between the N+ type drain region 140d and the N+ type source region 140s, which have the same conductivity type.

[0030] In this way, since the channel 130c has the same conductivity coefficient and temperature coefficient of the conductivity coefficient as the channel 140c, the cause of the variation based on the conductivity type and impurity concentration of the channel 130c and the channel 140c can be suppressed. Therefore, the pair transistor of the enhancement type MOS transistor 130 and the depletion type MOS transistor 140 can generate the reference voltage Vref with high accuracy. This can reduce the variation of the divided voltage Vdiv, so that the reference current circuit 100 can supply the reference current Iref with high accuracy.

[0031] Moreover, in order to achieve low current consumption in a semiconductor chip, it is necessary to reduce the current flowing through each element. For example, in the reference voltage source described in Patent Document 1, since the source and gate of the depletion-type MOS transistor are connected, the channel length must be increased in order to reduce the current. Also, in order to reduce manufacturing variations and generate a highly accurate reference voltage, the channel length of the paired enhancement-type MOS transistor must also be increased. Thus, this reference voltage source requires each channel length to be equally long, which results in a large layout area.

[0032] In this regard, in the reference voltage source of this embodiment, the current flowing through the enhancement-type MOS transistor 130 is limited by the output current Iout, and the current flowing through the depletion-type MOS transistor 140 is limited by the combined resistance of the voltage divider circuit 150. For this reason, the channel lengths of the enhancement-type MOS transistor 130 and the depletion-type MOS transistor 140 can be set to the minimum size permitted by the process, and can each be made at least shorter than the channel length of the depletion-type MOS transistor 160. This allows the reference current circuit 100 to shorten the channel length of each of the pair of transistors of the reference voltage source, thereby reducing the layout area.

[0033] Furthermore, from the viewpoint of reducing current consumption, it is preferable that the current flowing through the depletion-type MOS transistor 140 is larger than the current flowing when the gate voltage of the depletion-type MOS transistor 140 is the threshold voltage, and smaller than the current flowing when the gate voltage of the depletion-type MOS transistor 140 is the same potential as the source voltage. It is also preferable that the current flowing through the enhancement-type MOS transistor 130 is approximately the same as the small current flowing through the depletion-type MOS transistor 140. The current flowing through the depletion-type MOS transistor 140 can be adjusted by the combined resistance of the voltage divider circuit 150. The current flowing through the enhancement-type MOS transistor 130 can be adjusted by the output current Iout output from the current mirror circuit 110, for example, by changing the ratio of the current mirror circuit 110 or by adjusting the input current Iin.

[0034] -Temperature characteristics of reference voltage source- FIG. 5 is a graph showing the temperature characteristics of the reference voltage generated by the reference voltage source in this embodiment. As shown in Fig. 5, the reference voltage Vref has temperature characteristics that decrease as the ambient temperature increases. This is because, as shown in the band diagram of Fig. 4, in the depletion-type MOS transistor 140, as the Fermi level of the gate electrode 140g decreases as the ambient temperature increases, the threshold voltage Vtnd increases (in the positive direction) and the absolute value |Vtnd| of the threshold voltage decreases. In addition, in the enhancement-type MOS transistor 130, as the Fermi level of the gate electrode 130g increases as the ambient temperature increases, the threshold voltage Vtne decreases (in the negative direction). If the current flowing through the depletion-type MOS transistor 140 is made to be approximately the same as the current flowing through the enhancement-type MOS transistor 130, the reference voltage Vref approaches the following equation, Vref = |Vtnd| + Vtne, and has temperature characteristics that decrease as the ambient temperature increases.

[0035] In this way, the reference voltage Vref has a temperature characteristic that decreases as the ambient temperature rises. This reference voltage Vref is divided by the voltage divider circuit 150 to become the divided voltage Vdiv, which is applied to the gate terminal of the depletion-type MOS transistor 160 (see FIG. 1). In other words, the divided voltage Vdiv has a temperature characteristic that decreases as the ambient temperature rises, similar to the temperature characteristic of the reference voltage Vref.

[0036] Next, a description will be given of stabilizing the reference current Iref against changes in the ambient temperature by canceling the temperature characteristic of the divided voltage Vdiv using the temperature characteristic of the depletion-type MOS transistor 160.

[0037] -Temperature characteristics of depletion type MOS transistors- FIG. 6 is a graph showing the gate voltage-drain current characteristics of a depletion-type MOS transistor used as a constant current source in this embodiment. 6, in the depletion-type MOS transistor 160, like a general MOS transistor, no drain current flows when the gate voltage is equal to or lower than the threshold voltage Vth, and a drain current flows with a slope based on the conductivity coefficient when the gate voltage exceeds the threshold voltage Vth. Also, when the ambient temperature rises, the threshold voltage Vth and the conductivity coefficient decrease, and the slope of the gate voltage-drain current characteristic decreases. For this reason, there exists a cross point X where the gate voltage-drain current characteristic does not show a temperature characteristic. When a gate voltage below the cross point X is applied, the drain current increases as the ambient temperature rises, and when a gate voltage above the cross point X is applied, the drain current decreases as the ambient temperature rises.

[0038] In this embodiment, when the ambient temperature rises, the divided voltage Vdiv decreases, but in the depletion-type MOS transistor 160, a gate voltage (that is, the divided voltage Vdiv) higher than the threshold voltage and lower than the cross point X is applied. This allows the depletion-type MOS transistor 160 to supply the current mirror circuit 110 with an input current Iin that is stable regardless of changes in the ambient temperature.

[0039] 7 is an explanatory diagram showing the temperature characteristic of the input current supplied by the depletion-type MOS transistor in this embodiment. In FIG. 7, the left graph shows the temperature characteristic of the divided voltage Vdiv obtained by dividing the reference voltage Vref shown in FIG. 5 by the voltage divider circuit 150. The right graph shows the temperature characteristic of the depletion-type MOS transistor 160, which is an enlarged view of the vicinity of the cross point X by switching the vertical and horizontal axes of the gate voltage-drain current characteristic shown in FIG. 6. FIG. 7 shows the relationship between the temperature characteristic of the divided voltage Vdiv output from the voltage divider circuit 150 and the temperature characteristic of the input current Iin when this divided voltage Vdiv is applied to the gate terminal of the depletion-type MOS transistor 160.

[0040] As shown in FIG. 7, in the reference current circuit 100, the voltage division ratio of the voltage divider circuit 150 is adjusted so that a gate voltage (divided voltage Vdiv) lower than the cross point X shown in FIG. 6 is applied to the gate terminal of the depletion-type MOS transistor 160. As a result, when the ambient temperature rises, the divided voltage Vdiv decreases, but the drain current increases accordingly due to the temperature characteristics of the depletion-type MOS transistor 160, and as a result, the input current Iin can be stabilized against changes in ambient temperature. In addition, because the divided voltage Vdiv can be adjusted by setting the voltage division ratio, an impurity implantation process for adjusting the threshold voltage of the depletion-type MOS transistor 160 more deeply is not required. Therefore, the reference current circuit 100 can supply a stable reference current Iref against changes in the ambient temperature via the current mirror circuit 110 to which the input current Iin is input.

[0041] In this way, even if the ambient temperature rises and the divided voltage Vdiv drops, the drain current of the depletion-type MOS transistor 160 increases in the reference current circuit 100, so that the reference current Iref can be supplied with high accuracy and stability against changes in ambient temperature. Also, since the depletion-type MOS transistor 140 in the reference current circuit 100 functions as a source follower and a buffer, a buffer using a differential amplifier that requires a large layout area is not required, and the layout area can be reduced. Furthermore, the reference current circuit 100 can shorten the channel length of each of the pair transistors of the reference voltage source, thereby further reducing the layout area.

[0042] (Modification) The voltage divider circuit 150 may include a trimming circuit capable of adjusting the divided voltage Vdiv so that the divided voltage Vdiv can be easily adjusted. 8, the voltage dividing circuit 250 includes a first resistor section 250A, a second resistor section 250B, a third resistor section 250C, and a fourth resistor section 250D. The first resistor section 250A, the second resistor section 250B, and the third resistor section 250C are connected in series. The fourth resistor section 250D is connected in parallel to the third resistor section 250C.

[0043] The first resistor section 250A includes a plurality of resistor elements connected in series and a switching element connected to each node of the plurality of resistor elements. The first resistor section 250A performs coarse adjustment of the divided voltage Vdiv by selectively turning on the switching elements. The fourth resistor section 250D includes a plurality of resistor elements connected in series and a switching element connected to each node of the plurality of resistor elements. The fourth resistor section 250D divides the potential difference in the fourth resistor section 250D into small steps by the plurality of resistor elements, and selectively turns on the switching elements to finely adjust the divided voltage Vdiv and output it from the OUT terminal.

[0044] In this way, the voltage divider circuit 250 is provided with a trimming circuit, which allows fine adjustment of the divided voltage Vdiv, and therefore can supply a stable reference current Iref with high accuracy against changes in the ambient temperature.

[0045] As described above, the reference current circuit in one embodiment of the present invention has a current mirror circuit formed of a pair of MOS transistors whose gate terminals are connected to each other, and supplies an output current based on an input current, and an output MOS transistor that supplies a reference current according to the voltage of the gate terminals of the MOS transistor pair. The reference current circuit has a pair of transistors, an enhancement type MOS transistor and a first depletion type MOS transistor, and functions as a reference voltage source. The enhancement type MOS transistor has a gate terminal connected to a drain terminal to which an output current is supplied from the current mirror circuit, and a source terminal grounded. The enhancement type MOS transistor has the same channel conductivity type and impurity concentration as the first depletion type MOS transistor, and has a different Fermi level of the gate electrode from that of the first depletion type MOS transistor. The first depletion type MOS transistor has a gate terminal connected to that of the enhancement type MOS transistor, and generates a reference voltage based on the difference between the voltage of the source terminal of the enhancement type MOS transistor and the voltage of the source terminal of the first depletion type MOS transistor. Furthermore, the reference current circuit has a voltage divider circuit connected to the source terminal of the first depletion type MOS transistor and outputting a divided voltage of the reference voltage, and a second depletion type MOS transistor that supplies a current corresponding to the divided voltage as an input current to the current mirror circuit. The voltage divider circuit outputs a divided voltage in a voltage range that is higher than the threshold voltage of the second depletion type MOS transistor and lower than a cross point at which the gate voltage-drain current characteristics of the second depletion type MOS transistor are independent of temperature to the gate terminal of the second depletion type MOS transistor.

[0046] As a result, this reference current circuit can supply a stable reference current Iref with high accuracy despite changes in the ambient temperature, and can reduce the layout area. [Explanation of symbols]

[0047] 100 Reference current circuit 110 Current mirror circuit 111, 112 MOS transistors 120 Output MOS transistor 130 Enhancement-type MOS transistor 140 (first) depletion type MOS transistor 150, 250 voltage divider circuit 160 (second) depletion type MOS transistor Iin Input current Iout Output current Iref Reference current Vdiv Divided voltage Vref Reference voltage

Claims

1. a current mirror circuit formed by a pair of MOS transistors whose gate terminals are connected to each other, and which supplies an output current from one of the MOS transistors based on an input current input to the other MOS transistor; an output MOS transistor that supplies a reference current according to the voltage of the gate terminal of the MOS transistor pair; an enhancement type MOS transistor having a gate terminal connected to a drain terminal to which the output current from the current mirror circuit is supplied and a source terminal grounded; a first depletion-mode MOS transistor having a gate terminal connected to the enhancement-mode MOS transistor and generating a reference voltage based on the difference between the voltage of its source terminal and the voltage of the source terminal of the enhancement-mode MOS transistor; a voltage divider circuit connected to the source terminal of the first depletion type MOS transistor and outputting a divided voltage of the reference voltage; a second depletion-type MOS transistor that supplies a current corresponding to the divided voltage as the input current to the current mirror circuit; and the enhancement-type MOS transistor has the same channel conductivity type and impurity concentration as the first depletion-type MOS transistor, and has a gate electrode Fermi level different from that of the first depletion-type MOS transistor; the voltage divider circuit outputs the divided voltage to the gate terminal of the second depletion-type MOS transistor, the divided voltage being in a voltage range that is higher than the threshold voltage of the second depletion-type MOS transistor and lower than a cross point at which the gate voltage-drain current characteristics of the second depletion-type MOS transistor are independent of temperature.

2. 2. The reference current circuit according to claim 1, wherein the channel lengths of said enhancement-mode MOS transistor and said first depletion-mode MOS transistor are shorter than that of said second depletion-mode MOS transistor.

3. the current flowing through the first depletion-type MOS transistor is a current flowing within a voltage range higher than a threshold voltage and lower than 0 V; 3. The reference current circuit according to claim 2, wherein the current flowing through said enhancement-type MOS transistor is approximately the same as the current flowing through said first depletion-type MOS transistor.

4. 4. The reference current circuit according to claim 1, wherein said voltage divider circuit includes a trimming circuit capable of adjusting said divided voltage.

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