Back contact type solar battery and manufacturing method of the same
Patent Information
- Application Number
- JP2023186538
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-02-10
- Filing Date
- 2023-10-31
- Publication Date
- 2025-02-25
- Estimated Expiration
- 2043-10-31
AI Technical Summary
Back-contact solar cells face issues with reverse current leakage exceeding standard values due to incomplete etching of diffusion bonds, leading to high process difficulty and variability between cells.
The solution involves a back-contact solar cell design with first and second emitters of different doping types, separated by isolation regions, and optionally an insulating layer, to prevent electrical leakage. This design includes a silicon substrate with emitters and isolation regions, and electrodes connected to these emitters, with specific passivation and antireflection layers to enhance performance.
The design effectively prevents electrical leakage beyond standard values by isolating emitters, improving cell efficiency and reducing process complexity.
Smart Images
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Abstract
Description
[Technical field]
[0001] This application relates generally to photovoltaic technology, and more particularly to back-contact solar cells and methods for fabricating back-contact solar cells. [Background technology]
[0002] Combined with passivation contact technology, the full back contact solar cell has a photoelectric conversion efficiency of over 26%, making it highly applicable.
[0003] Back contact batteries have a problem of reverse leakage. In order to solve the problem of reverse leakage, a tunnel oxide layer is often used as an etching stopper layer to prevent the formation of pyramid suede structure on the back side of the cell in the suede process step and to remove the diffusion junction remaining in the P region. However, this process has the problems of a narrow process window and high process difficulty, and the leakage difference between cells of different lots is large due to incomplete etching of the diffusion junction, so that the reverse leakage exceeds the standard value.
[0004] Therefore, eliminating the reverse leakage current of back-contact batteries that exceeds the standard value is an issue that must be resolved as soon as possible. Summary of the Invention [Problem to be solved by the invention]
[0005] An object of the present application is to provide a back-contact solar cell capable of solving the problem of reverse leakage current exceeding the standard value of a back-contact cell, and a method for manufacturing the back-contact solar cell. [Means for solving the problem]
[0006] In order to solve the above problems, the back-contact solar cell of the present application comprises a silicon substrate of a first doping type having opposing front and back surfaces, a first emitter and a second emitter arranged on the back surface of the silicon substrate, a second isolation region surrounding the second emitter and a first isolation region surrounding the second isolation region, and a second electrode having a first portion in contact with the second emitter and a second portion disposed on a side of the corresponding first emitter away from the silicon substrate, wherein the first isolation region surrounds a first portion of the second electrode, or the entire second electrode contacts the second emitter and the first isolation region surrounds the entire second electrode, the first emitter is of a second doping type, and the second emitter is of a first doping type.
[0007] In one embodiment of the present application, the semiconductor device further comprises an insulating layer disposed between the second electrode of the second portion and the corresponding first emitter.
[0008] In one embodiment of the present application, the entire second electrode is in contact with the second emitter, and the first isolation region surrounds the entire second electrode.
[0009] In one embodiment of the present application, the first emitter includes a diffusion layer, a tunnel oxide layer, and a polysilicon layer sequentially disposed on the back surface of the silicon substrate, the diffusion layer being of the second doping type, and the polysilicon layer being of the second doping type.
[0010] In one embodiment of the present application, the semiconductor device further comprises a first passivation layer and an anti-reflection layer disposed in sequence on the front side of the silicon substrate.
[0011] In one embodiment of the present application, the first passivation layer includes a chemical passivation layer disposed on a front side of the silicon substrate and a field passivation layer disposed on a side of the chemical passivation layer remote from the silicon substrate.
[0012] In one embodiment of the present application, the semiconductor device further comprises a second passivation layer disposed on the rear surface of the silicon substrate.
[0013] In order to solve the above technical problem, the present application further provides a method for manufacturing a back-contact solar cell, the method including the steps of: providing a silicon substrate of a first doping type having opposing front and back surfaces; forming a first emitter and a second emitter on the back surface of the silicon substrate; forming a second isolation region surrounding the second emitter and a first isolation region surrounding the second isolation region on the back surface of the silicon substrate; and forming a second electrode having a first portion in contact with the second emitter and a second portion located on a side of the corresponding first emitter away from the silicon substrate, wherein the first isolation region surrounds a first portion of the second electrode, or the entire second electrode contacts the second emitter and the first isolation region surrounds the entire second electrode, the first emitter is of a second doping type, and the second emitter is of a first doping type.
[0014] In one embodiment of the present application, the first emitter includes a diffusion layer, a tunnel oxide layer, and a polysilicon layer sequentially disposed on the back surface of the silicon substrate, the diffusion layer and the polysilicon layer being of the second doping type.
[0015] In one embodiment of the present application, a first passivation layer and an anti-reflection layer are sequentially formed on the front side of the silicon substrate.
[0016] In one embodiment of the present application, the first passivation layer includes a chemical passivation layer disposed on a front side of the silicon substrate and a field passivation layer disposed on a side of the chemical passivation layer remote from the silicon substrate. Effect of the Invention
[0017] The back-contact solar cell of the present application avoids leakage current exceeding the standard value of the solar cell due to contact between the first emitter and the second emitter by isolating the first emitter and the second emitter by a first isolation region and a second isolation region.
[0018] In order to make the above objects, features, and advantages of the present application more clearly and comprehensibly, specific embodiments of the present application are described in detail with reference to the accompanying drawings below. [Brief description of the drawings]
[0019] [Figure 1] FIG. 2 is a schematic bottom view of a back-contact solar cell according to one embodiment of the present application. [Diagram 2] 2 is a schematic cross-sectional view showing a cross section along the line AA in FIG. 1. [Diagram 3] 2 is a schematic cross-sectional view showing a cross section along line BB in FIG. 1. [Figure 4] FIG. 2 is a schematic bottom view of a back-contact solar cell according to another embodiment of the present application. [Diagram 5] 1 is an exemplary flow chart of a method for manufacturing a back-contact solar cell in accordance with one embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0020] In order to make the above objectives, features, and advantages of the present application clearer and more comprehensible, specific embodiments of the present application are described in detail below in conjunction with the accompanying drawings.
[0021] In the following description, numerous specific details are set forth in order to facilitate a thorough understanding of the present application; however, the present application may be practiced in other ways than as described, and therefore the present application is not limited to the specific examples disclosed below.
[0022] As used herein and in the claims, unless the context clearly indicates otherwise, terms such as "a," "one," "a kind," and / or "the" do not specifically refer to the singular but may include the plural. In general, the terms "comprising" and "including" are used only to indicate the inclusion of specifically identified steps and elements, and do not constitute an exclusive list of steps and elements, and a method or apparatus may include other steps or elements.
[0023] It should also be explained that the use of terms such as "first" and "second" to limit the components is merely to facilitate distinction between corresponding components, and that unless otherwise stated, the above terms have no special meaning and therefore cannot be understood as limitations on the scope of protection of the present application. Furthermore, although the terms used in the present application are selected from known terms, some of the terms described in the specification of the present application are selected by the applicant at his / her own discretion, and their detailed meanings will be explained in the relevant parts of the description of this specification. It is also required to understand the present application not only based on the actual terms used but also on the meanings contained in each term.
[0024] In the present application, the operations performed by the system according to the embodiment of the present application are described in a flowchart. It should be understood that the above or following operations are not necessarily performed in exact order. Conversely, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations may be added to these processes, or one or more operations of steps may be removed from these processes.
[0025] Next, the back contact type solar cell of the present application will be described using specific examples.
[0026] FIG. 1 is a schematic bottom view of a back-contact solar cell according to an embodiment of the present application, and FIG. 2 is a schematic cross-sectional view taken along line AA in FIG. 1. As shown in FIGS. 1 and 2, the back-contact solar cell 100 includes a silicon substrate 110, a first emitter 120, a first isolation region 130, a second isolation region 140, and a second emitter 150. Due to limitations in the scope of the drawing, FIG. 2 shows only a portion of the cross-sectional view taken along line AA. As can be seen from FIG. 2, the first isolation region 130 and the second isolation region 140 are covered with other material layers on the surfaces away from the silicon substrate 110 in the thickness direction D2, so that the first isolation region 130 and the second isolation region 140 cannot actually be seen in the bottom view of FIG. 1. However, in this specification, for convenience of explanation, the positions of the first isolation region 130 and the second isolation region 140 are shown in FIG. 1 in a schematic manner.
[0027] 2, the silicon substrate 110 has a front surface 111 and a back surface 112 facing each other in a thickness direction D2, and the silicon substrate 110 is of a first doping type. Here, the first doping type may be P-type, i.e., the silicon substrate 110 may be a P-type silicon substrate, or may be N-type, i.e., the silicon substrate 110 may be an N-type silicon substrate. The present application does not limit the specific doping elements forming the P-type silicon substrate and the N-type silicon substrate.
[0028] 2, the first emitter 120, the first isolation region 130, the second isolation region 140, and the second emitter 150 are provided along a first direction D1 on the rear surface 112 of the silicon substrate 110, the first emitter 120 is of a second doping type, and the second emitter 150 is of a first doping type. In FIG. 2, the right side of the first isolation region 130 contacts the first emitter 120, the left side of the first isolation region 130 contacts the right side of the second isolation region 140, and the left side of the second isolation region 140 contacts the second emitter 150. It should be understood that the above description of the positional relationship among the first emitter 120, the first isolation region 130, the second isolation region 140, and the second emitter 150 applies to the second emitter 150 and the first emitter 120, the first isolation region 130, and the second isolation region 140 located to the right of the second emitter 150. The above description may be referred to for the positional relationship among the second emitter 150 and the first emitter 120, the first isolation region 130, and the second isolation region 140 located to the left of the second emitter 150, and therefore the description will be omitted here.
[0029] The positional relationship between the first emitter 120, the first isolation region 130, the second isolation region 140, and the second emitter 150 is not limited to the embodiment of Fig. 1. For example, in some other embodiments, the first isolation region 130 and the second isolation region 140 are arranged between the first emitter 120 and the second emitter 150 along the first direction D1 so as not to contact each other, or the first isolation region 130 and the second isolation region 140 are in contact with each other, and the first isolation region 130 is not in contact with the first emitter 120, and the second isolation region 140 is not in contact with the second emitter 150.
[0030] As shown in FIG. 1 and FIG. 2, in one embodiment, the back-contact solar cell 100 further includes a first electrode 161 and a second electrode 162. The first electrode 161 is electrically connected to the first emitter 120 by contacting the first emitter 120. Similarly, the second electrode 162 is electrically connected to the second emitter 150 by contacting the second emitter 150. Here, the second electrode 162 and the second emitter 150 are electrically connected in a case 1 where a part of the second electrode 162 is in contact with the second emitter 150, and in a case 2 where the entire second electrode 162 is in contact with the second emitter 150. The above two cases will be described below.
[0031] Case 1: A portion of the second electrode is in contact with the second emitter.
[0032] As explained with reference to Figure 1, Figure 1 shows the back surface of the back contact solar cell 100. Unlike the first electrode 161 and the second electrode 162 shown in Figure 2, the first electrode 161 and the second electrode 162 are shown as line segments in Figure 1. It can be understood that this is due to the angle of the drawing.
[0033] In FIG. 1, the first isolation region 130 surrounds the second isolation region 140, and in combination with FIG. 2, the second isolation region 140 surrounds the second emitter 150, and the first portion 162a of the second electrode 162 is surrounded by the first isolation region 130. Referring to the schematic cross-sectional view of the line BB in FIG. 1 shown in FIG. 3, the second portion 162b of the second electrode 162 is provided on the side of the corresponding first emitter 120 away from the silicon substrate 110. In other words, in FIG. 1, the first isolation region 130 is represented as a rectangular frame, the second electrode located within the rectangular frame is the first portion 162a of the second electrode, and the second electrode located outside the rectangular frame is the second portion 162b of the second electrode.
[0034] As shown in FIG. 1 and FIG. 2, the first emitter 120 and the second emitter 150 are not visible in FIG. 1 because the surfaces of the first emitter 120 and the second emitter 150 that are away from the silicon substrate 110 are covered with other material layers. In order to more clearly understand the layout of the second electrode in Case 1, the first emitter and the second emitter are described here based on FIG. 1. In FIG. 1, the second emitter is located below the first portion 162a of the second electrode, the first emitter (as shown in FIG. 3) is distributed below the second portion 162b of the second electrode, and an insulating layer (not shown) is provided between the second portion 162b of the second electrode and the first emitter located therebelow, so that the second electrode is not electrically connected to the first emitter. The above "below" means facing into the paper.
[0035] 2 and 3, back-contact solar cell 100 further includes second passivation layer 170 and third passivation layer 180 provided in this order along thickness direction D2 on the back surface of silicon substrate 110. Second portion 162b of the second electrode is provided on a surface of third passivation layer 180 that is away from third passivation layer 180 in thickness direction D2. In some embodiments, the back-contact solar cell 100 further includes an insulating layer (not shown) disposed between the second electrode second portion 162b and the third passivation layer 180 as shown in Figure 3, or the second passivation layer 170 and the third passivation layer 180 where the second electrode second portion 162b in Figure 3 is located are removed using a method such as etching to expose the first emitter 120, and an insulating layer is disposed between the second electrode second portion 162b and the corresponding first emitter 120. In some embodiments, if the back-contact solar cell 100 does not include the second passivation layer 170 and the third passivation layer 180, the insulating layer is disposed between the second electrode second portion 162b and the corresponding first emitter 120. Returning to FIG. 1 , the first isolation region 130 surrounds the first portion 162a of the second electrode, and an insulating layer is provided between the second portion 162b of the second electrode and the corresponding first emitter 120, so that the second electrode 162 is not electrically connected to the first emitter 120.
[0036] In one embodiment, the second passivation layer and the third passivation layer are a composite of one or more of silicon nitride, aluminum oxide, titanium oxide, silicon oxide, and silicon oxynitride.
[0037] 1 and 2, the second emitter 150 is surrounded by the second isolation region 140, and the second isolation region 140 is surrounded by the first isolation region 130. In this manner, the first emitter 120 and the second emitter 150 are separated by the first isolation region 130 and the second isolation region 140, so that leakage of the cell due to contact between the first emitter 120 and the second emitter 150 can be avoided.
[0038] Case 2: The entire second electrode is in contact with the second emitter.
[0039] Referring to the schematic bottom view of the back contact type solar cell of another embodiment of the present application shown in FIG. 4 and FIG. 2, the schematic cross-sectional view shown in FIG. 2 may be a schematic cross-sectional view taken along the CC line in FIG. 4. Different from FIG. 1, in FIG. 4, the second electrode 162 is entirely in contact with the second emitter 150, and the second isolation region 140 entirely surrounds the second electrode 162, and the first isolation region 130 surrounds the second isolation region 140. It can be seen that the first isolation region 130 entirely surrounds the second electrode 162 in FIG. 4.
[0040] Furthermore, similar to case 1, the first emitter 120 and the second emitter 150 are separated by the first isolation region 130 and the second isolation region 140 to avoid cell leakage due to contact between the first emitter 120 and the second emitter.
[0041] In the above embodiment, the second emitter has been described. Next, the first emitter of the present application will be described.
[0042] As shown in FIG. 2, the first emitter 120 includes a diffusion layer 121, a tunnel oxide layer 122, and a polysilicon layer 123. The diffusion layer 121, the tunnel oxide layer 122, and the polysilicon layer 123 are sequentially arranged on the back surface of the silicon substrate 110 in a thickness direction D2, and the diffusion layer 121 and the polysilicon layer 123 are all of a second doping type. In one embodiment, the tunnel oxide layer 122 has a thickness of 1 to 20 nm, and the polysilicon layer 123 has a thickness of 20 to 1000 nm. The tunnel oxide layer 122 may be implemented as silicon dioxide. The tunnel oxide layer 122 and the polysilicon layer 123 can realize selective collection of carriers, i.e., majority carriers are easy to pass through the tunnel oxide layer 122, and minority carriers are difficult to pass through the tunnel oxide layer 122.
[0043] In order to more clearly understand the technical effect of isolating the first emitter and the second emitter by the first isolation region and the second isolation region in the above-mentioned embodiment, the first isolation region and the second isolation region of the present application will now be further described.
[0044] As shown in FIG. 2, a first separation region 130 is provided between the first emitter 120 and the second separation region 140 along a first direction D1. The first separation region 130 of the present application may be implemented as a silicon substrate located between the first emitter 120 and the second separation region 140, or as another material, such as a second passivation layer, located between the first emitter 120 and the second separation region 140. In other words, the first separation region 130 located between the first emitter 120 and the second separation region 140 along the first direction D1 has the technical effect of separating the first emitter 120 and the second emitter 150. In some embodiments, the first separation region 130 is of a first doped type, and as shown in FIG. 2, the first separation region 130 may have a pyramidal suede appearance on a surface adjacent to the silicon substrate 110 along the thickness direction D2.
[0045] 2, the entire second isolation region 140 is of the second doping type. In this case, the second isolation region 140 may be the diffusion layer 121 remaining in the P region. In some other embodiments, the doping type of the second isolation region 140 may be such that a part of the second isolation region is of the first doping type and another part of the second isolation region is of the second doping type, and the "part" and "another part" may constitute the entire second isolation region, may not constitute the entire second isolation region, or the entire second isolation region may be of the first doping type.
[0046] In order to more clearly understand the first isolation region and the second isolation region in the back contact solar cell of the present application, an example is provided here to illustrate the process of forming the first isolation region and the second isolation region.
[0047] 2, the tunnel oxide layer 122 and the polysilicon layer 123 cover a part of the back surface of the silicon substrate 110. The tunnel oxide layer 122 and the polysilicon layer 123 that partially cover the back surface of the silicon substrate 110 are formed as follows. After forming the tunnel oxide layer 122 that covers the entire back surface of the silicon substrate 110, the polysilicon layer 123 that covers the tunnel oxide layer 122 is formed on the surface of the tunnel oxide layer 122, and then the unnecessary tunnel oxide layer 122 and the polysilicon layer 123 are removed by a method such as etching so as to leave the tunnel oxide layer 122 and the polysilicon layer 123 in the first emitter 120 portion. When the polysilicon layer located in the P region is reserved, the entire second isolation region 140 is of the second doping type, when a part of the polysilicon layer in the P region is reserved, the part of the second isolation region 140 is of the first doping type and the other part is of the second doping type, when the entire polysilicon layer in the P region is removed, the entire second isolation region 140 is of the first doping type. Note that the above-mentioned embodiment is merely one example of the case of forming the first isolation region and the second isolation region, and the method of forming the first isolation region and the second isolation region of the present application is not limited to the above-mentioned example.
[0048] 2, the surface of the first isolation region 130 close to the silicon substrate 110 has a pyramid suede appearance. The pyramid suede appearance of the first isolation region 130 and the pyramid suede appearance on the front surface of the silicon substrate 110 are formed in the same suede process step, and the separation process step of forming the first isolation region 130 and the second isolation region 140 may be merged with the suede process step to simplify the process. In some other embodiments, the surface of the second isolation region 140 in the thickness direction D2 away from the silicon substrate 110 is flattened. Here, it may be flattened by chemical mechanical polishing (CMP).
[0049] In one embodiment, as shown in FIG. 2, a first passivation layer 190 and an anti-reflective layer 210 are sequentially formed on the front surface 111 of the silicon substrate 110 in a thickness direction D2. The first passivation layer 190 and the anti-reflective layer 210 are formed by chemical vapor deposition (CVD) and / or physical vapor deposition (PVD). In some embodiments, the first passivation layer 190 includes a chemical passivation layer and a field passivation layer, and the first passivation layer 190 is formed by first forming a chemical passivation layer on the front surface 111 of the silicon substrate 110, and then forming a field passivation layer on a surface of the chemical passivation layer that is away from the silicon substrate 110. In some embodiments, the front surface 111 of the silicon substrate 110, and the first passivation layer 190 and the anti-reflective layer 210 disposed on the front surface 111 have a pyramidal suede appearance. When the solar cell is in operation, sunlight enters the silicon substrate 110 from the front side of the silicon substrate 110, and the pyramid suede can trap the light and reduce surface reflection, thereby improving the light utilization rate of the solar cell.
[0050] In the above-described embodiment of the present application, the first emitter and the second emitter are separated by the first isolation region and the second isolation region, thereby preventing leakage current exceeding the reference value of the solar cell due to contact between the first emitter and the second emitter.
[0051] Another aspect of the present application further provides a method for fabricating a back-contact solar cell, which will be described hereinafter in the examples.
[0052] 5 is an exemplary flow chart of a method for manufacturing a back-contact solar cell according to an embodiment of the present application. As shown in FIG. 5, the manufacturing method of this embodiment includes: Step S310 of providing a first doping type silicon substrate having opposing front and back surfaces; Step S320 of forming a first emitter of a second doping type, a first isolation region, a second isolation region, and a second emitter of a first doping type on a back surface of the silicon substrate; Including, A second isolation region is surrounded by the first isolation region, and a second emitter is surrounded by the second isolation region.
[0053] The above-mentioned steps S310 and S320 will now be described in detail.
[0054] 2, in step S310, a silicon substrate 110 is provided having a front surface 111 and a back surface 112 opposed to each other in a thickness direction D2, where the silicon substrate 110 is of a first doping type.
[0055] In step S320, a first emitter 120 of a second doping type, a first isolation region 130, a second isolation region 140, and a second emitter 150 of a first doping type are formed on the rear surface 112 of the silicon substrate 110. As shown in FIG. 1, the first isolation region 130 surrounds the second isolation region 140, and the second isolation region 140 surrounds the first emitter 120, so that the first emitter 120 and the second emitter 150 are separated by the first isolation region 130 and the second isolation region 140, and contact between the first emitter 120 and the second emitter 150 is avoided.
[0056] 1 and 2, in one embodiment, a first electrode 161 in contact with the first emitter 120 and a second electrode 162 in contact with the second emitter 150 are formed. This realizes an electrical connection between the first electrode 161 and the first emitter 120, and an electrical connection between the second electrode 162 and the second emitter 150.
[0057] In one embodiment, the first portion 162a of the second electrode contacts the second emitter 150, the second portion 162b of the second electrode is disposed on a side of the corresponding first emitter away from the silicon substrate 110, an insulating layer (not shown) is disposed between the second portion 162b of the second electrode and the corresponding first emitter, and the first isolation region 130 surrounds the first portion 162a of the second electrode as shown in FIG. 1 .
[0058] In another embodiment, referring to FIG. 4, unlike FIG. 2, the entire second electrode 162 contacts the second emitter 150, and the first isolation region 130 surrounds the entire second electrode 162.
[0059] As shown in FIG. 2, in one embodiment, the first emitter 120 includes a diffusion layer 121, a tunnel oxide layer 122, and a polysilicon layer 123. As shown in FIG. 2, the diffusion layer 121 is disposed on the back surface of the silicon substrate 110, the tunnel oxide layer 122 is disposed on the surface of the diffusion layer 121 away from the silicon substrate 110 in the thickness direction D2, and the polysilicon layer 123 is disposed on the surface of the tunnel oxide layer 122 away from the silicon substrate 110 in the thickness direction D2. The tunnel oxide layer 122 and the polysilicon layer 123 can realize selective collection of carriers, that is, majority carriers are easy to pass through the tunnel oxide layer 122, and minority carriers are difficult to pass through the tunnel oxide layer 122. Here, the diffusion layer 121 and the polysilicon layer 123 are both of the second doping type.
[0060] In one embodiment, as shown in FIG. 2, a first passivation layer 190 and an anti-reflective layer 210 are sequentially formed on the front surface of the silicon substrate 110 in a thickness direction D2. The first passivation layer 190 and the anti-reflective layer 210 can be formed by chemical vapor deposition (CVD) and / or physical vapor deposition (PVD). In some embodiments, the first passivation layer 190 includes a chemical passivation layer and a field passivation layer, and the first passivation layer 190 can be formed by first forming a chemical passivation layer on the front surface of the silicon substrate 110, and then forming a field passivation layer on the surface of the chemical passivation layer away from the silicon substrate 110.
[0061] 2, in one embodiment, the first isolation region 130 has a pyramid suede appearance. To form the pyramid suede appearance, an alkaline solution may be used to etch the surface of the first isolation region 130 away from the silicon substrate 110. In one embodiment, the pyramid suede of the first isolation region 130 is formed in the same suede process step as the pyramid suede on the front surface of the silicon substrate 110, which simplifies the process. In other embodiments, the surface of the second isolation region 140 in the thickness direction D2 away from the silicon substrate 110 is flat. Here, it may be planarized by chemical mechanical polishing (CMP).
[0062] In the above-described embodiment of the present application, the first emitter and the second emitter are separated by the first isolation region and the second isolation region, thereby preventing leakage current exceeding the reference value of the solar cell due to contact between the first emitter and the second emitter.
[0063] Although the basic concept has been described above, it is obvious to those skilled in the art that the above disclosure is merely an example, and is not intended to limit the present application. Although not expressly stated herein, those skilled in the art may make various modifications, improvements, and amendments to the present application. Such modifications, improvements, and amendments are proposed in the present application and therefore fall within the spirit and scope of the exemplary embodiments of the present application.
[0064] At the same time, the present application uses certain terms to describe the embodiments of the present application. For example, "one embodiment," "an embodiment," and / or "some embodiments" refer to features, configurations, or characteristics associated with at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment" or "one embodiment" or "an alternative embodiment" mentioned more than once in different places in this specification do not necessarily refer to the same embodiment. Furthermore, some features, configurations, or characteristics in one or more embodiments of the present application may be combined as appropriate.
[0065] In some examples, numbers are used to describe the number of components, attributes, and it should be understood that the numbers describing such examples are modified in some instances using the modifiers "about," "approximately," or "approximately." Unless otherwise specified, "about," "approximately," or "approximately" means that the numerical value is allowed to vary by ±20%. Thus, in some examples, the numerical parameters used in the specification and claims are approximations, and these approximations may be modified depending on the characteristics required for each particular example. In some examples, the numerical parameters should be calculated using a common method of preserving digits, taking into account the number of significant digits given. In some examples of the present application, the numerical fields and parameters used to determine the breadth of their ranges are approximations, but in certain examples, such numerical values are set as precisely as possible within the limits of feasibility. [Explanation of symbols]
[0066] 110 Silicon substrate 111 Front 112 Back side 120 First Emitter 121 Diffusion Layer 122 Tunnel oxide layer 123 Polysilicon layer 130 First Separation Region 140 Second Separation Region 150 Second Emitter 161 First electrode 162 Second Electrode 162a First Part 162b Second Part 170 Second passivation layer 180 Third passivation layer 190 First passivation layer 210 Anti-reflection layer
Claims
1. 1. A back contact solar cell, comprising: a first doping type silicon substrate having opposing front and back surfaces; a first emitter and a second emitter disposed on a rear surface of the silicon substrate; a second isolation region surrounding the second emitter and a first isolation region surrounding the second isolation region; a second electrode having a first portion in contact with the second emitter and a second portion disposed on a side of the first emitter away from the silicon substrate; a first portion of the second electrode is surrounded by the first isolation region; 13. A back contact solar cell, wherein the first emitter is of a second doping type and the second emitter is of the first doping type.
2. 10. The back contact solar cell of claim 1 further comprising an insulating layer disposed between said second electrode and said first emitter of said second portion.
3. the first emitter includes a diffusion layer, a tunnel oxide layer, and a polysilicon layer, which are sequentially disposed on a rear surface of the silicon substrate; the diffusion layer is of the second doping type; 2. The back contact solar cell of claim 1 wherein said polysilicon layer is of said second doping type.
4. 10. The back contact solar cell of claim 1, further comprising a first passivation layer and an anti-reflection layer disposed sequentially on a front surface of the silicon substrate.
5. The first passivation layer comprises a chemical passivation layer disposed on the front side of the silicon substrate; 5. The back contact solar cell of claim 4, further comprising a field passivation layer disposed on a surface of said chemical passivation layer remote from said silicon substrate.
6. 10. The back contact solar cell of claim 1 further comprising a second passivation layer disposed on a back surface of the silicon substrate.
7. 1. A method for manufacturing a back contact solar cell, comprising the steps of: providing a silicon substrate of a first doping type having opposing front and back surfaces; forming a first emitter and a second emitter on a back surface of the silicon substrate; forming a second isolation region surrounding the second emitter and a first isolation region surrounding the second isolation region on a back surface of the silicon substrate; forming a second electrode, the first portion of which contacts the second emitter and the second portion of which is located on a side of the corresponding first emitter away from the silicon substrate; the first portion of the second electrode is surrounded by the first isolation region; the first emitter is of a second doping type; 2. A method for producing a back contact solar cell, wherein the second emitter is of a first doping type.
8. the first emitter includes a diffusion layer, a tunnel oxide layer, and a polysilicon layer, which are sequentially disposed on a rear surface of the silicon substrate; 8. The method of claim 7, wherein said diffusion layer and said polysilicon layer are both of said second doping type.
9. 8. The method of claim 7, further comprising sequentially forming a first passivation layer and an anti-reflection layer on the front surface of the silicon substrate.
10. The first passivation layer comprises: a chemical passivation layer disposed on the front side of the silicon substrate; 10. The method of claim 9, further comprising: a field passivation layer disposed on a surface of said chemical passivation layer remote from said silicon substrate.