Semiconductor device and manufacturing method of them

Abstract

To improve a performance of a semiconductor device as a semiconductor chip which has a semiconductor element, and in which a terminal is exposed.SOLUTION: A semiconductor device includes: a semiconductor substrate 5 that has a main surface S1, a main surface S2 that is opposite to the main surface S1 and a semiconductor element; a terminal 2 that is connected to a source electrode 2a provided to the main surface S1 so as to be contacted via a bonding material 2b having a conductive performance; a terminal 4 that is connected to a drain electrode 4a provided so as to be contacted to the main surface S2 via the bonding material 4b having the conductive performance, and is isolated from the terminal 2; an insulation material 6 that seals each one part of the terminal 2 and the terminal 4 and the semiconductor substrate 5; and a main surface S3 that is positioned to the bonding material 2b side against the semiconductor substrate 5, and in which the terminal 2 and the terminal 4 are exposed; and a main surface S4 that is opposite to the side of the main surface S3. The terminal 4 is led to the main surface S3 side by a leading electrode 4c separated from a lamination body containing the semiconductor substrate 5, the source electrode 2a, and the bonding material 2b, and a space of the terminal 2 and the terminal 4 is isolated by the insulation material 6.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention can be used in a semiconductor device and a method for manufacturing the same. [Background technology]

[0002] In recent years, power conversion devices using semiconductor module devices equipped with SiC (silicon carbide) power semiconductor chips have begun to be introduced to the market. Wide band gap power semiconductors, such as SiC, have smaller conduction losses than conventional Si (silicon) power semiconductors, making it possible to fabricate small semiconductor modules using small semiconductor chips. However, since SiC has lower substrate quality and process maturity than Si, the yield of its semiconductor chips is low, so it is necessary to thoroughly inspect each semiconductor chip and remove defective chips before modularization.

[0003] A semiconductor chip may have a structure in which electrodes are provided on both the front surface and the back surface on the opposite side. In response to this, Patent Document 1 (JP Patent Publication 2007-184553 A) describes forming a through electrode in a through hole that penetrates from the front surface to the back surface of a semiconductor substrate, the through electrode being electrically connected to a metal film (electrode) on the back surface side. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2007-184553 A Summary of the Invention [Problem to be solved by the invention]

[0005] When conducting characteristic inspections by passing electricity through each semiconductor chip, it is necessary to prevent discharge. When electrodes are provided on both the front and back surfaces of a semiconductor chip, the terminals on both surfaces must be open, which increases the constraints for preventing discharge. In addition, since it is difficult to contact a small semiconductor chip with a probe, it is possible to conduct inspections after connecting multiple chips in parallel to form a module. However, if one semiconductor chip is defective, the other multiple semiconductor chips connected in parallel are also treated as defective, which reduces the yield in the manufacturing of the module and causes high costs. These problems are particularly noticeable in SiC chips, which are smaller in size than Si chips.

[0006] Furthermore, when a semiconductor chip has electrodes on both the front and back sides, it is necessary to connect a conductor such as a bonding wire, which has a relatively small cross-sectional area, to the electrodes on the front side, which leads to an increase in the resistance of the semiconductor device, an increase in the size of the semiconductor device, and an increase in the manufacturing cost of the semiconductor device.

[0007] Furthermore, in such semiconductor chips, heat is likely to rise on the front side where the bonding wires are connected, so it is possible to provide a mechanism for cooling both the front and back sides. However, providing a cooling mechanism for both sides leads to an increase in the size of the semiconductor device and an increase in manufacturing costs.

[0008] The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0009] A brief outline of a representative embodiment of the present invention will be described below.

[0010] A semiconductor device according to a representative embodiment includes a semiconductor substrate having a first main surface, a second main surface opposite to the first main surface, and a semiconductor element, a first terminal connected to a first electrode provided in contact with the first main surface via a first bonding material having electrical conductivity, a second terminal connected to a second electrode provided in contact with the second main surface via a second bonding material having electrical conductivity and insulated from the first terminal, an insulating material sealing a portion of each of the first terminal and the second terminal and the semiconductor substrate, a third main surface located on the first bonding material side of the semiconductor substrate and exposing the first terminal and the second terminal, and a fourth main surface opposite to the third main surface. The second terminal is drawn to the third main surface side by a drawing electrode separated from a stack including the semiconductor substrate, the first electrode, and the first bonding material, and the first terminal and the second terminal are insulated from each other by the insulating material.

[0011] A method for manufacturing a semiconductor device according to another representative embodiment includes the steps of: (a) preparing a semiconductor substrate having a first main surface, a second main surface opposite to the first main surface, and a semiconductor element, the semiconductor substrate having a first electrode in contact with the first main surface and a second electrode in contact with the second main surface; (b) connecting a first conductor to the first electrode via a first bonding material having electrical conductivity; (c) preparing a second conductor having a first convex portion on a surface thereof; (d) separating a laminate including the semiconductor substrate and the first electrode from the first convex portion, and connecting the second electrode to the surface of the second conductor via a second bonding material having electrical conductivity; and (e) after steps (a) to (d), sealing the semiconductor substrate, the first conductor, and the second conductor with an insulating material. Here, the semiconductor device has a third main surface to which a first terminal made of the first conductor and a second terminal made of the second conductor are exposed, and a fourth main surface opposite the third main surface, the third main surface being located on the first bonding material side of the semiconductor substrate, the first terminal and the second terminal being insulated from each other, and the second terminal being extended toward the third main surface by the first convex portion. Effect of the Invention

[0012] According to the exemplary embodiment, the performance of the semiconductor device can be improved, and in particular, the size of the semiconductor device can be reduced.

[0013] According to another representative embodiment, the yield of semiconductor devices can be improved, and in particular, inspection of individual semiconductor chips becomes possible. [Brief description of the drawings]

[0014] [Figure 1] 1 is a plan view showing a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Diagram 3] 1 is a cross-sectional view showing a semiconductor module equipped with a semiconductor device according to a first embodiment. [Figure 4] 4 is a flow chart showing a manufacturing process of the semiconductor device according to the first embodiment. [Diagram 5] 1 is a cross-sectional view of the semiconductor device in the manufacturing process according to the first embodiment. [Figure 6] 2 is a plan view showing an example of a layout of conductors used in manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 7] 6 is a cross-sectional view of the semiconductor device during the manufacturing process continued from FIG. 5. [Figure 8] 8 is a cross-sectional view of the semiconductor device during the manufacturing process continued from FIG. 7. [Figure 9] 9 is a cross-sectional view of the semiconductor device during the manufacturing process continued from FIG. 8. [Figure 10] 10 is a cross-sectional view of the semiconductor device during the manufacturing process continued from FIG. [Figure 11] 11 is a cross-sectional view of the semiconductor device during the manufacturing process continued from FIG. [Figure 12] FIG. 2 is a plan view showing a semiconductor device according to a first modification of the first embodiment. [Figure 13] FIG. 2 is a plan view showing a semiconductor device according to a first modification of the first embodiment. [Figure 14] FIG. 2 is a plan view showing a semiconductor device according to a first modification of the first embodiment. [Figure 15]FIG. 11 is a cross-sectional view showing a semiconductor device according to a second modification of the first embodiment. [Figure 16] 11 is a flow chart showing a manufacturing process of a semiconductor device according to Modification 2 of the first embodiment. [Figure 17] 11A to 11C are cross-sectional views of a semiconductor device according to Modification 2 of the first embodiment during a manufacturing process. [Figure 18] 18 is a cross-sectional view of the semiconductor device during the manufacturing process continued from FIG. 17. [Figure 19] 19 is a cross-sectional view of the semiconductor device during the manufacturing process continued from FIG. 18. [Figure 20] FIG. 11 is a plan view showing a semiconductor device according to a second embodiment. [Figure 21] 21 is a cross-sectional view taken along line BB in FIG. 20. [Figure 22] 21 is a cross-sectional view taken along line CC in FIG. 20. [Diagram 23] 11 is a flow chart showing a manufacturing process of a semiconductor device according to a second embodiment. [Figure 24] 11A to 11C are cross-sectional views of a semiconductor device in a manufacturing process according to a second embodiment. [Diagram 25] 25 is a cross-sectional view of the semiconductor device during the manufacturing process continued from FIG. 24. [Figure 26] 26 is a cross-sectional view of the semiconductor device during the manufacturing process continued from FIG. 25. [Figure 27] 27 is a cross-sectional view of the semiconductor device during the manufacturing process continued from FIG. 26. [Figure 28] 27A to 27C are cross-sectional views of the semiconductor device during the manufacturing process. [Figure 29] FIG. 11 is a cross-sectional view showing a semiconductor device according to a modified example of the second embodiment. [Diagram 30] FIG. 11 is a cross-sectional view showing a semiconductor device according to a modified example of the second embodiment. [Diagram 31] 13 is a flow chart showing a manufacturing process of a semiconductor device according to a modification of the second embodiment. [Diagram 32] 13A to 13C are cross-sectional views of a semiconductor device according to a modification of the second embodiment during a manufacturing process. [Diagram 33] FIG. 11 is a cross-sectional view showing a semiconductor device according to a comparative example. [Diagram 34]FIG. 1 is a plan view showing a semiconductor module according to a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, the same reference numerals are used for the members having the same functions, and the repeated explanations are omitted. In addition, in the embodiments, the explanations of the same or similar parts are not repeated as a rule, except when it is particularly necessary.

[0016] (Embodiment 1) <Structure of Semiconductor Device> The structure of the semiconductor device of this embodiment will be described below with reference to Figs. 1 to 3. As shown in Fig. 1, the semiconductor chip 1, which is the semiconductor device of this embodiment, has terminals 2, 3, and 4 on the main surface S3 side. As shown in Fig. 2, the semiconductor chip 1 has a main surface S3 and a main surface S4 opposite to the main surface S3. Both the main surface S3 and the main surface S4 are surfaces along the X direction and the Y direction. The X direction and the Y direction are directions perpendicular to each other. The thickness direction (height direction) of the semiconductor chip 1 is the Z direction perpendicular to each of the X direction and the Y direction. In this application, a planar view means viewing an object along the Z direction.

[0017] As shown in FIG. 2, the semiconductor chip 1 has a semiconductor substrate 5 therein. The semiconductor substrate 5 is made of, for example, Si (silicon), SiC (silicon carbide), GaN (gallium nitride), Ga2O3 (gallium oxide), or diamond. The shape of the semiconductor substrate 5 in a plan view is rectangular. The semiconductor substrate 5 has a main surface S1 and a main surface S2 opposite to the main surface S1. The main surface S1 is a surface of the semiconductor substrate 5 and is located on the main surface S3 side, and the main surface S2 is a surface of the semiconductor substrate 5 and is located on the main surface S4 side. That is, the main surface S3 is located on the bonding material (conductive connection layer) 2b side and the bonding material (conductive connection layer) 3b side with respect to the semiconductor substrate 5. The main surface S4 is located on the bonding material (conductive connection layer) 4b side with respect to the semiconductor substrate 5.

[0018] A source electrode 2a and a gate electrode 3a are connected to the main surface S1 of the semiconductor substrate 5. A drain electrode 4a is connected to the main surface S2 of the semiconductor substrate 5. The source electrode 2a, the gate electrode 3a, and the drain electrode 4a are spaced apart from each other and insulated from each other. The outermost surfaces (surfaces on the main surface S3 side) of the source electrode 2a and the gate electrode 3a are made of, for example, Ni (nickel) or Cu (copper). The outermost surface (surface on the main surface S4 side) of the drain electrode 4a is made of, for example, Ni (nickel), Cu (copper), or Au (gold).

[0019] Although not shown, the semiconductor substrate 5 is not composed of only semiconductors, but has a laminated structure including wiring and an insulating layer on its main surface, and is provided with a semiconductor element. Examples of the semiconductor element formed on the semiconductor substrate 5 include transistors such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors). The semiconductor element formed on the semiconductor substrate 5 may also be a rectifying element such as a diode.

[0020] Here, a case where the semiconductor substrate 5 is equipped with a MOSFET will be described as an example. Therefore, the semiconductor substrate 5 is a three-terminal element. If the semiconductor element included in the semiconductor substrate 5 is a two-terminal element such as a diode, only one electrode and terminal will be connected to the surface on the main surface S3 side of the semiconductor substrate 5. There may be three or more electrodes and terminals connected to the surface on the main surface S3 side of the semiconductor substrate 5. For example, in addition to the source terminal (terminal 2) and gate terminal (terminal 3), a source sense terminal, a temperature detection terminal, and the like may be provided on the main surface S3 of the semiconductor substrate 5.

[0021] A terminal 2 is connected to the surface of the source electrode 2a on the main surface S3 side via a bonding material 2b. A terminal 3 is connected to the surface of the gate electrode 3a on the main surface S3 side via a bonding material 3b. A terminal 4 is connected to the surface of the drain electrode 4a on the main surface S4 side via a bonding material 4b. That is, the terminal 2 is electrically connected to the semiconductor substrate 5 via the bonding material 2b and the source electrode 2a. The terminal 3 is electrically connected to the semiconductor substrate 5 via the bonding material 3b and the gate electrode 3a. The terminal 4 is electrically connected to the semiconductor substrate 5 via the bonding material 4b and the drain electrode 4a. Each of the terminals 2, 3, and 4 is made of, for example, Cu (copper), W (tungsten), Al (aluminum), or Mo (molybdenum). Each of the bonding materials (bonding layers) 2b, 3b, and 4b is a conductive bonding portion, and is made of, for example, solder, sintered material, or bump.

[0022] The terminal 4 extends outward in the Y and X directions with respect to a stacked body consisting of a semiconductor substrate 5, a source electrode 2a, a gate electrode 3a, a drain electrode 4a, bonding materials 2b, 3b, 4b, and terminals 2 and 3 stacked in the Z direction, and has an extraction electrode 4c extending toward the main surface S3 at a position separated from the stacked body. The extraction electrode 4c, which is a part of the terminal 4, extends in the Z direction and is exposed on the main surface S3. The shape of the stacked body in a plan view is rectangular. As shown in FIG. 1, the extraction electrode 4c (terminal 4) has an L-shaped planar layout in which a portion extending along one side of the stacked body extending in the Y direction and a portion extending along one side of the stacked body extending in the X direction are connected to each other.

[0023] 2, the terminal 4 has a plate-like portion in contact with the bonding material 4b and extending along the XY plane, an extraction electrode 4c extending along the XZ plane, and an extraction electrode 4c extending along the YZ plane. Therefore, the terminal 4 has an L-shaped cross section. The plate-like portion extending along the XY plane and the extraction electrode 4c may be integrated, or may be joined to each other via a bonding material. When the plate-like portion and the extraction electrode 4c are integrated, the manufacturing method of the terminal 4 (the conductor 20 described later) is simple, but since material processing is required, the manufacturing cost is higher than when the plate-like portion and the extraction electrode 4c are joined.

[0024] An insulating material (sealing material) 6 is embedded between the laminate and the extraction electrode 4c. The insulating material 6 is embedded between the laminate consisting of the source electrode 2a, the bonding material 2b, and the terminal 2 and the laminate consisting of the gate electrode 3a, the bonding material 3b, and the terminal 3. The insulating material 6 continuously covers and seals the side surfaces in the X direction and the Y direction of the structure consisting of the terminal 4, the semiconductor substrate 5, the source electrode 2a, the gate electrode 3a, the drain electrode 4a, the bonding materials 2b, 3b, 4b, and the terminals 2, 3, and 4, and the surface on the main surface S4 side of the terminal 4. The insulating material 6 is made of, for example, a mold resin.

[0025] The terminals 4 are led out from the positions where they are joined to the bonding material 4b to the main surface S3 by the plate-like portions extending along the XY plane and the lead-out electrodes 4c. The terminals are not exposed on any surface of the semiconductor chip 1 other than the main surface S3. In other words, all surfaces of the semiconductor chip 1 other than the main surface S3 are covered with the insulating material 6.

[0026] The shape of the semiconductor chip 1 in a plan view and the shape of each side surface are rectangular. In other words, the shape of the semiconductor chip 1 is a rectangular parallelepiped. The side surfaces in the X and Y directions of the semiconductor chip 1 and the main surface S4 are made of the insulating material 6, and the surface of the terminal 4 on the main surface S4 side is not exposed. On the main surface S3, the insulating material 6 and the respective surfaces of the terminals 2, 3, and 4 are exposed. In other words, the main surface S3 is made up of the insulating material 6 and the respective surfaces of the terminals 2, 3, and 4. The main surface S3 is flat. On the main surface 3, the periphery of each of the terminals 2, 3, and 4 is completely surrounded by the insulating material 6.

[0027] The shape of the terminal (gate terminal) 3 in a plan view is rectangular. In a plan view, the area of ​​the terminal (gate terminal) 3 is smaller than that of the terminal (source terminal) 2. It is preferable that the shortest distance between each of 2, 3, and 4 is equal to or less than the length of one side (short side) of the terminal 3 in a plan view. This is because if the shortest distance is large, an increase in the size of the semiconductor device becomes a problem.

[0028] The semiconductor substrate 5 is obtained by cutting a semiconductor wafer into individual pieces. The semiconductor substrate 5 having the semiconductor element, the source electrode 2a, the gate electrode 3a, and the drain electrode 4a may be called a semiconductor chip, but here, the substrate having the semiconductor element is called the semiconductor substrate 5, and the semiconductor substrate 5 with the terminals 2, 3, and 4 electrically connected and sealed is called the semiconductor chip 1.

[0029] <Structure of semiconductor module> A cross-sectional view of a semiconductor module 100 on which a semiconductor device (semiconductor chip 1) of this embodiment is mounted is shown in Fig. 3. The semiconductor chip 1 shown in Fig. 3 is the semiconductor chip 1 shown in Fig. 2 turned upside down, and the position of the cross section shown in Fig. 3 is the same as the position of the cross section shown in Fig. 2.

[0030] As shown in Fig. 3, each of the terminals 2, 3, and 4 on the main surface S3 of the semiconductor chip 1 is connected to a separate wiring 8 via a bonding material 7. The wiring 8 is a wiring pattern made of a conductor provided on the main surface of an insulating substrate 9. The bonding material 7 is made of, for example, solder, a sintered material, or a bump. The insulating substrate 9 is made of, for example, AlN (aluminum nitride). Although not shown, the semiconductor module shown in Fig. 3 may be disposed in, for example, a resin case, and the structure including the semiconductor chip 1 on the main surface of the insulating substrate 9 may be sealed with resin poured into the resin case.

[0031] Here, all terminals of the semiconductor chip 1 are surface-mounted on the insulating substrate 9 side on the main surface S3 side using only the bonding material 7. In other words, since the terminals of the semiconductor chip 1 are not exposed on the main surface S4 side of the semiconductor chip 1, the semiconductor chip 1 and the wiring 8 are not connected using bonding wires, conductive ribbons, or the like.

[0032] <Method of Manufacturing Semiconductor Device> Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to the flow in FIG. 4 and with reference to FIGS.

[0033] First, as shown in FIG. 5, a plurality of conductors 10 are prepared (step S11 in FIG. 4). The conductors 10 are made of, for example, Cu (copper), W (tungsten), Al (aluminum), or Mo (molybdenum). The conductors 10 have a plate-shaped support portion and two convex portions 10a spaced apart from each other and arranged on the surface of the support portion. These two convex portions 10a are portions that will later become the terminals 2 and 3. As shown in FIG. 6, the plurality of conductors 10 may be connected to each other via the connection portion 10c and integrated. The conductors 10 shown in FIG. 5 have already been singulated. The singulated conductors 10 have the advantage of low material cost, but require a lot of work to align them with the semiconductor substrate to be connected in a later process. The integrated conductors 10 in FIG. 6 have the advantage of easy alignment, but high material cost.

[0034] Next, as shown in Fig. 7, each of the multiple conductors 10 is connected to each of the multiple semiconductor substrates 5 (step S12 in Fig. 4). Specifically, a plurality of semiconductor substrates 5 are prepared, each of which has a main surface S1 and a main surface S2 opposite to the main surface S1, with a source electrode 2a and a gate electrode 3a provided on the main surface S1 and a drain electrode 4a provided on the main surface S2. Next, the source electrode 2a is connected to one of the two protruding portions 10a of each conductor 10 via a bonding material 2b, and the gate electrode 3a is connected to the other of the two protruding portions 10a via a bonding material 3b.

[0035] Next, as shown in FIG. 8, a plurality of conductors 20 are connected to each of the plurality of semiconductor substrates 5 (step S13 in FIG. 4). That is, a plurality of conductors 20 are prepared, each of which is configured by connecting a plate-like portion extending along the XY plane, an extraction electrode (convex portion) 4c extending along the XZ plane, and an extraction electrode (convex portion) 4c extending along the YZ plane. The extraction electrode 4c is connected to the surface of the plate-like portion, which is a support portion, and is formed on the surface. Note that the plurality of semiconductor substrates 5 may be prepared at the time of step S11, and the plurality of conductors 20 may be prepared at the time of step S11 or S12. Steps S12 and S13 may be performed simultaneously. That is, the conductors 10 and 20 may be connected to the semiconductor substrate 5 at the same time. Also, step S13 may be performed before step S12.

[0036] Here, first, the conductor 10 and the semiconductor substrate 5, which are connected to each other, are turned upside down. Next, the drain electrode 4a on the main surface S4 side of the semiconductor substrate 5 is connected via the bonding material 4b to the surface of the plate-like portion of each conductor 20 extending along the XY plane, from which the lead electrode 4c protrudes. Here, the laminate consisting of the semiconductor substrate 5, the source electrode 2a, the gate electrode 3a, the drain electrode 4a, the bonding materials 2b, 3b, 4b, and the terminals 2 and 3 is connected to the surface of the plate-like portion with the lead electrode 4c spaced apart in the Y and X directions. Each of the bonding materials 2b, 3b, and 4b is, for example, a solder, a sintered material, or a bump.

[0037] Next, as shown in FIG. 9, the semiconductor substrates 5 and the conductors 10 and 20 are each sealed with an insulating material 6 (step S14 in FIG. 4). The insulating material 6 is made of, for example, a mold resin. In FIG. 9, the entire surfaces of the conductors 10 and 20 are sealed, but a part of the surfaces of the conductors 10 and 20 (the upper ends of the conductors in FIG. 9) may be exposed above the bonding materials 2b and 3b. In addition, in the Z direction, the height positions of the upper surface of the conductor 10 (the surface opposite to the semiconductor substrate 5 side) and the uppermost surface of the conductor 20 may not coincide with each other but may be shifted. This is because these upper surfaces will be flattened by grinding performed in a later step S15.

[0038] Next, as shown in Fig. 10, the conductors 10 and 20 are ground from above to flatten the surfaces of the insulating material 6, conductors 10 and conductors 20 (step S15 in Fig. 4). Here, the support portion constituting the conductor 10 is removed, and grinding is continued until the two protruding portions 10a are separated from each other. The two protruding portions 10a of the conductor 10 that remain as a result thereof constitute the terminals 2 and 3, respectively. Furthermore, the conductor 20, which has been partially ground, constitutes the terminal 4. The respective surfaces of the insulating material 6 and terminals 2, 3 and 4 flattened in this grinding process constitute the main surface S3.

[0039] 11, dicing is performed to cut the insulating material 6 between adjacent terminals 4, thereby obtaining a plurality of individual semiconductor chips 1 (step S16 in FIG. 4). The bottom surface of the insulating material 6, i.e., the surface opposite to the main surface S3, constitutes the main surface S4. With the above steps, the semiconductor device of this embodiment is substantially completed.

[0040] When manufacturing the semiconductor module shown in Figure 3, the above-mentioned semiconductor chip 1 and an insulating substrate 9 having a pattern of wiring 8 on its main surface are prepared, and then each of the terminals 2, 3, and 4 exposed on the main surface S3 of the semiconductor chip 1 is connected to each of the wiring 8 via a bonding material 7.

[0041] <Effects of this embodiment> In the manufacturing process of semiconductor devices, a continuity test is performed on semiconductor chips. The test is performed by applying a voltage to each terminal of the semiconductor chip, so it is necessary to prevent air discharge between the terminals when performing tests to evaluate off characteristics. For example, when testing elements such as SiC power semiconductor elements, which are applied with a higher voltage than Si semiconductor elements, a high electric field is applied, so measures must be taken to prevent discharge. To prevent discharge, possible test methods include immersing the semiconductor device in an insulating liquid or performing measurements while under pressure, but it is difficult to measure in the chip state.

[0042] In addition, it is difficult to make a probe contact and pass a large current through a miniaturized semiconductor chip in an inspection for evaluating the on-state characteristics. Since the chip size of a SiC semiconductor element is smaller than that of a Si semiconductor element, it is particularly difficult to perform a probe inspection on the semiconductor chip.

[0043] Due to these constraints, sufficient testing cannot be performed on a single semiconductor chip, so testing can be performed after multiple semiconductor chips are connected in parallel (see Figure 34), sealed with insulating material, and modularized with a bus bar for connecting the main current path. As a result, a defect in one semiconductor chip causes the other multiple semiconductor chips connected in parallel to be treated as defective, reducing the yield in module manufacturing and increasing the manufacturing cost of the semiconductor device.

[0044] Furthermore, when semiconductor chips are connected in parallel to form a semiconductor module, it is possible to use bonding wires 41, as shown as comparative examples in Fig. 33 and Fig. 34. In Fig. 33, the insulating material (sealing material) is omitted, and in Fig. 34, the insulating material and some of the bonding wires 41 are omitted.

[0045] 33, the semiconductor chip 1x, which is a semiconductor device of the comparative example, is different from the semiconductor chip 1 shown in FIG 1 in that it is not formed with an electrode (terminal) that is electrically connected to the drain electrode 4a of the semiconductor substrate 5 and that draws the drain to the source electrode 2a and gate electrode 3a sides. Also, it is not formed with electrodes that are electrically connected to each of the source electrode 2a and gate electrode 3a of the semiconductor substrate 5 and that draw the source and gate to the drain electrode 4a side.

[0046] The drain electrode 4a is connected to a wiring 8 via a bonding material 7 directly below the semiconductor substrate 5, and the source electrode 2a and the gate electrode 3a are each connected to the wiring 8 via a bonding wire 41 in contact with their upper surfaces.

[0047] To form such a semiconductor module 100a of the comparative example, a wire bonding process is required in addition to the surface mounting process for connecting the drain electrode 4a to the wiring 8, which increases the manufacturing cost of the semiconductor device. Also, if the bonding wire 41 is formed at a high position as shown in Fig. 33, the resin layer for sealing the semiconductor chip 1x and the bonding wire 41 needs to be thickened, which causes a problem of an increase in the size of the semiconductor device.

[0048] In addition, even if a large current is to be passed through the semiconductor module 100a that has been wire-bonded during the above-mentioned inspection, it is difficult to pass a large current because the bonding wire 41 (or ribbon) has a small cross-sectional area. In addition, in the completed semiconductor module, there is a problem that the wiring resistance becomes high due to the use of the bonding wire 41 having a small cross-sectional area.

[0049] Furthermore, in the semiconductor chip 1x of the comparative example, heat is likely to rise on the front surface side to which the bonding wire 41 is connected. For this reason, it is conceivable to provide a mechanism for cooling both the front surface side to which the bonding wire 41 is connected only to the gate, and the back surface side to which the terminal 4 is connected. However, providing a cooling mechanism for both surfaces leads to an increase in the size of the semiconductor device (semiconductor module) and an increase in manufacturing costs.

[0050] To address these issues, it is possible to extend the terminals on the main surface side to the main surface side of the semiconductor chip. One possible method for this is to provide a through electrode that penetrates the semiconductor substrate and is electrically connected to the back electrode (drain electrode). However, in the process of forming a semiconductor substrate with such a structure, dust adhesion due to the formation of the through hole, processing variations in the through hole, and defective filling (insufficient filling) of the through electrode are likely to occur, and there is a risk of a decrease in the yield in the manufacture of the semiconductor device.

[0051] Therefore, in this embodiment, instead of providing a through electrode in the semiconductor substrate 5, an extraction electrode 4c is provided at a position spaced apart from the semiconductor substrate 5, which extracts the terminal 4 on the main surface S4 side of the semiconductor chip 1 to the main surface S3 side. As a result, all the terminals 2, 3, and 4 for electrically connecting the semiconductor chip 1 to the outside are gathered on the main surface S3 of the semiconductor chip 1.

[0052] As a result, in the inspection process of the semiconductor device, it is possible to inspect the semiconductor chip 1 as a single chip without connecting multiple semiconductor chips in parallel. This is because the semiconductor chip 1 is sealed with the insulating material 6, and also because inspection is easy with the main surface S4 adhered or adsorbed. Since there are no terminals on the main surface S4, it is also easy to inspect the semiconductor chip 1 by immersing it in an insulating liquid or applying pressure by fixing the main surface S4. This prevents discharge and enables inspection of the semiconductor chip 1 as a single chip at high voltage. This eliminates the need to connect multiple semiconductor chips in parallel for inspection, and prevents other semiconductor chips from being treated as defective due to a defect in one semiconductor chip. This improves the yield of the semiconductor device and prevents an increase in the manufacturing cost of the semiconductor device.

[0053] Moreover, since no terminals are exposed on the main surface S4 opposite to the main surface S3 to be surface mounted, a wire bonding process is not required. Therefore, the semiconductor device can be mounted only through the surface mounting process using the bonding material 7, and the manufacturing cost of the semiconductor device can be reduced. Furthermore, since no bonding wire is required, the size of the semiconductor device can be reduced. As a result, the resin layer for sealing the semiconductor chip 1 can be made thinner than in the comparative example, and the size of the semiconductor device can be reduced.

[0054] Furthermore, even when a continuity test is performed after the semiconductor chip 1 is mounted on the insulating substrate 9, since no bonding wire is required, the test can be easily performed using a large current passing through only the bonding material 7. Furthermore, since the completed semiconductor module 100 does not require a bonding wire with a small cross-sectional area, the wiring resistance can be reduced. Furthermore, since there is no bonding wire, the problem of heat easily rising on the main surface side of the semiconductor chip to which the bonding wire is connected, as in the comparative example, can be prevented. Therefore, there is no need to provide a mechanism for cooling both the main surface S3 and the main surface S4, and it is sufficient to cool only the main surface S3 side on which the chip is mounted. This allows the semiconductor device (semiconductor module) to be reduced in size and the manufacturing cost to be reduced.

[0055] In this embodiment, since no through holes and through electrodes are formed penetrating the semiconductor substrate 5, it is possible to prevent the occurrence of dust adhesion, processing variations of the through holes, and defective filling of the through electrodes due to the formation of the through holes and through electrodes, etc. As a result, it is possible to improve the yield in the manufacture of semiconductor devices.

[0056] <Variation 1> The planar layout of the terminals 4 (lead electrodes 4c) on the main surface S3 of the semiconductor chip 1 is not limited to an L-shape, and may be a shape as shown in FIGS. 12 and 13. In the planar layout shown in FIG. 12, the terminals 4 have an I-shape extending only along one side of the terminals 2, which have a substantially rectangular planar shape. In the planar layout shown in FIG. 13, the terminals 4 have a U-shape extending continuously along three sides of the terminals 2. In the planar layout shown in FIG. 14, the terminals 4 have a continuous rectangular ring-shaped structure extending along the four sides of the terminals 2.

[0057] <Variation 2> 15, on the main surface S4 of the semiconductor chip 1a, the surface of the terminal 4 may be exposed from the insulating material 6. Here, among the portions constituting the terminal 4, a plate-shaped portion that contacts the bonding material 4b and extends along the XY plane is partially exposed. In other words, among the surfaces of the plate-shaped portion, the surface opposite to the semiconductor substrate 5 is exposed from the insulating material 6.

[0058] Next, a method for manufacturing the semiconductor device of this modified example will be described with reference to the flow of FIG. 16 and with reference to FIGS.

[0059] First, steps similar to steps S11 to S13 in FIG. 4 are performed (steps S21 to S23 in FIG. 16).

[0060] 17, the plurality of semiconductor substrates 5 and the plurality of conductors 10 and 20 are each sealed with an insulating material 6 (step S24 in FIG. 16). Here, sealing is performed in a state where the surface (bottom surface) of each of the plurality of conductors 20 opposite the semiconductor substrate 5 side is covered (protected) by adhering it to a tape (not shown).

[0061] However, rather than using tape to prevent sealing, conductor 20 may be sealed as in step S14 of FIG. 4, and then grinded to expose the surface (bottom surface) of conductor 20 opposite to semiconductor substrate 5, thereby obtaining the structure shown in FIG. 17.

[0062] Next, as shown in FIG. 18, a grinding step similar to step S15 in FIG. 4 is performed to form terminals 2, 3, and 4 (step S25 in FIG. 16).

[0063] 19, a dicing step similar to step S16 in FIG 4 is performed to obtain a plurality of individual semiconductor chips 1a (step S26 in FIG 16). Through the above steps, the semiconductor device of this modified example is substantially completed.

[0064] In this modified example, the same effects as those of the semiconductor device described with reference to Figures 1 to 3 can be obtained. In addition, since there is no insulating material 6 covering the terminals 4 on the main surface S4, the size of the semiconductor device can be reduced and the cooling effect on the main surface S4 side is increased. Also, it is possible to perform inspection and measurement by contacting a probe with both the main surface S3 side and the main surface S4 side. The exposed area of ​​the terminals 4 on the main surface S4 side is larger than the exposed area of ​​the terminals 4 on the main surface S3 side. Therefore, probe inspection of the terminals 4 becomes easier.

[0065] (Embodiment 2) In the above embodiment 1, it has been described that the terminal 4 connected to the drain electrode 4a is extended toward the other terminals 2 and 3. However, in the following, it will be described with reference to Figures 20 to 28 that the terminals 2 and 3 are extended toward the main surface S4 on which the terminal 4 is formed.

[0066] FIG. 20 shows the main surface S4 of the semiconductor chip 1b, unlike FIG. 1. The main surface S4 of the semiconductor chip 1b exposes a terminal 4 connected to the drain electrode 4a of the semiconductor substrate 5 via a bonding material 4b. The main surface S4 also exposes a terminal 2 (extraction electrode 2c) connected to the source electrode 2a of the semiconductor substrate 5 via a bonding material 2b. The main surface S4 also exposes a terminal 3 (extraction electrode 3c) connected to the gate electrode 3a of the semiconductor substrate 5 via a bonding material 3b. The terminal 2 on the main surface S4 has an L-shaped layout. However, the shapes of the terminals 2 and 3 on the main surface S4 may be any of the L-shaped, I-shaped, and U-shaped shapes described with reference to FIGS. 1, 12, and 13.

[0067] FIG. 21 shows a cross-sectional view taken along line BB in FIG. 20, and FIG. 22 shows a cross-sectional view taken along line CC in FIG. 20. As shown in FIG. 21, the terminal 3 has a plate-shaped portion extending along the XY plane in contact with the bonding material 3b, and an extraction electrode 3c extending along the XZ plane. As shown in FIG. 21 and FIG. 22, the terminal 2 has a plate-shaped portion extending along the XY plane in contact with the bonding material 2b, an extraction electrode 2c extending along the XZ plane, and an extraction electrode 2c extending along the YZ plane. Each of the extraction electrodes 2c and 3c extends in the Z direction, and one end of the extension direction terminates at the main surface S4. The terminals 2 and 3 arranged side by side in the X and Y directions are spaced apart from each other.

[0068] In other words, the entire surface of the semiconductor chip 1b is covered with the insulating material 6 except for the main surface S4.

[0069] Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to the flow of FIG. 23 and with reference to FIGS.

[0070] First, as shown in FIG. 24, a plurality of conductors 10 are prepared (step S31 in FIG. 23). The conductor 10 has a support portion, and has two protruding portions 10a spaced apart from each other on the surface of the support portion. The two protruding portions 10a are portions that will later become the terminals 2 and 3. Each of the two protruding portions 10a further has a protruding portion 10b protruding from its upper surface. In other words, the protruding portion 10a is formed on the surface of the support portion via the protruding portion 10b. The two protruding portions 10b are portions that will later become the extraction electrodes 2c and 3c that are parts of the terminals 2 and 3, respectively. The conductor 10 is composed of the support portion and the protruding portions 10a and 10b.

[0071] Next, as shown in FIG. 25, each of the conductors 10 is connected to each of the semiconductor substrates 5 (step S32 in FIG. 23). Specifically, a plurality of semiconductor substrates 5 are prepared, each of which has a main surface S1 and a main surface S2 opposite to the main surface S1, with a source electrode 2a and a gate electrode 3a provided on the main surface S1 and a drain electrode 4a provided on the main surface S2. Next, the source electrode 2a is connected to one of the two protruding portions 10a of each conductor 10 via a bonding material 2b, and the gate electrode 3a is connected to the other of the two protruding portions 10a via a bonding material 3b. The semiconductor substrate 5 is connected to the protruding portion 10a at a position spaced apart from the protruding portion 10b. That is, the stack including the semiconductor substrate 5 and the drain electrode 4a is spaced apart from the protruding portion 10b, and the source electrode 2a and the gate electrode 3a are connected to the surface of the plurality of protruding portions 10a, which is the surface of the conductor 10, via the bonding materials 2b and 3b.

[0072] Next, as shown in FIG. 26, a plurality of conductors 20 are connected to each of the plurality of semiconductor substrates 5 (step S33 in FIG. 23). The conductors 20 are made of only plate-like portions extending along the XY plane, and form terminals 4. Here, the drain electrode 4a on the main surface S2 side of the semiconductor substrate 5 is connected to the surface of each conductor 20 via a bonding material 4b. The conductors 20 are connected to the semiconductor substrate 5 at a position spaced apart from the protruding portion 10b. Steps S32 and S33 may be performed simultaneously. That is, the conductors 10 and 20 may be connected to the semiconductor substrate 5 at the same time. Also, step S33 may be performed before step S32.

[0073] Next, as shown in Fig. 27, the plurality of semiconductor substrates 5 and the plurality of conductors 10 and 20 are each sealed with an insulating material 6 (step S34 in Fig. 23). In Fig. 27, a portion of the surface of the conductors 10 and 20 is exposed, but the entire surface of the conductors 10 and 20 may be sealed. Also, the height positions of the upper surface of the conductor 20 (the surface opposite to the semiconductor substrate 5) and the uppermost surface of the conductor 10 (protrusion 10b) in the Z direction may not coincide with each other but may be shifted. This is because these upper surfaces will be flattened by grinding performed later in step S35.

[0074] Next, as shown in FIG. 28, the conductor 10 and the conductor 20 are ground from both sides in the Z direction (step S35 in FIG. 23).

[0075] Here, first, the structure including the semiconductor substrate 5, the conductors 10, 20, and the insulating material 6 is turned upside down. Next, the conductor 10 is ground from above. That is, the conductor 10 and the insulating material 6 are ground until the support portion constituting the conductor 10 is removed and the two protruding portions 10a are separated from each other. As a result, the remaining pair of protruding portions 10a, 10b constitutes the terminal 2, and the other pair of protruding portions 10a, 10b constitutes the terminal 3.

[0076] Next, a sealing process is performed again (step S36 in FIG. 23). Here, the terminals 2, 3 (protruding portions 10a) exposed by the grinding are covered with an insulating material 6. Note that the insulating material 6 and the insulating material 6 formed in step S34 are formed in separate processes, but are given the same reference numerals here and are shown integrated with each other in FIG. 28.

[0077] Next, dicing is performed to cut the insulating material 6 between adjacent semiconductor substrates 5, thereby obtaining a plurality of individual semiconductor chips 1b (step S37 in FIG. 23). In the semiconductor chip 1b, a flat surface including the insulating material 6 exposed on the lower side of FIG. 28 (the bonding material 4b side relative to the semiconductor substrate 5) and the respective surfaces of the terminals 2, 3, and 4 constitutes the main surface S4. The upper surface of the insulating material 6, which is the surface on the opposite side of the main surface S4 of the semiconductor chip 1b (the surface on the bonding material 2b side relative to the semiconductor substrate 5) and which has been formed in the above-mentioned second sealing process, constitutes the main surface S3. With the above steps, the semiconductor device of this embodiment is substantially completed.

[0078] The semiconductor device and manufacturing method thereof according to this embodiment provide the same effects as those of the first embodiment. Furthermore, the semiconductor chip 1b according to this embodiment has higher heat dissipation than the semiconductor chip 1 according to the first embodiment. This is because the surface area of ​​the semiconductor chip 1b in plan view occupied by conductors (terminals) is larger on the surface on which the drain electrode 4a is formed than on the surface on which the source electrode 2a and the gate electrode 3a are formed. That is, in this embodiment, heat can be dissipated from almost the entire main surface S4, so that the thermal resistance is low.

[0079] <Modification> 29 and 30, on the main surface S3 of the semiconductor chip 1c, the surfaces of the terminals 2 and 3 may be exposed from the insulating material 6. Here, of the surfaces of the terminals 2 and 3, the surfaces opposite to the main surface S1 of the semiconductor substrate 5 are exposed from the insulating material 6. The cross sections shown in FIGS. 29 and 30 are at locations corresponding to the cross sections shown in FIGS. 21 and 22.

[0080] Next, a method for manufacturing the semiconductor device of this modification will be described with reference to FIG. 32 and the flow of FIG.

[0081] First, steps similar to steps S31 to S34 in FIG. 23 are performed (steps S41 to S44 in FIG. 31).

[0082] Next, as shown in Fig. 32, both surfaces of the conductor 10 and the conductor 20 in the Z direction are ground to flatten both surfaces of the insulating material 6, the conductor 10, and the conductor 20 (step S45 in Fig. 31), and then dicing is performed (step S46 in Fig. 31). Here, after grinding the terminals 2 and 3 (protruding portion 10a), no sealing process is performed again. As a result, the surfaces of the terminals 2 and 3 remain exposed from the insulating material 6.

[0083] Subsequently, dicing is performed to obtain a plurality of individual semiconductor chips 1c. In the semiconductor chip 1c, a flat surface including the insulating material 6 and the respective surfaces of the terminals 2, 3, and 4 exposed on the bonding material 4b side relative to the semiconductor substrate 5 constitutes the main surface S4. A flat surface on the opposite side of the main surface S4 of the semiconductor chip 1c (the surface on the bonding material 2b side relative to the semiconductor substrate 5) including the respective surfaces of the insulating material 6 and the respective surfaces of the terminals 2 and 3 constitutes the main surface S3. With the above, the semiconductor device of this modified example is substantially completed.

[0084] In this modification, the same effects as those of the semiconductor device described with reference to Figures 20 to 22 can be obtained. In addition, since there is no insulating material 6 covering the terminals 2 and 3 on the main surface S3, the size of the semiconductor device can be reduced and the cooling effect on the main surface S3 side is improved. Also, it becomes possible to perform inspection and measurement by bringing a probe into contact with both the main surface S3 side and the main surface S4 side.

[0085] The invention made by the present inventors has been specifically described above based on the embodiments thereof. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the invention. [Explanation of symbols]

[0086] 1, 1a-1c, 1x Semiconductor chip 2, 3, 4 terminals 2a Source electrode 2b, 3b, 4b, 7 Bonding material 2c, 3c, 4c Extraction electrodes 3a Gate electrode 4a Drain electrode 5. Semiconductor Substrates 6. Insulation Materials 8 Wiring 9. Insulating Substrate 10, 20 Conductor 10a, 10b Convex portion 10c Connection 41 Bonding Wire 100, 100a Semiconductor module S1, S2, S3, S4 main surface

Claims

1. A semiconductor substrate including a first main surface, a second main surface opposite to the first main surface, and a semiconductor element; a first terminal connected to a first electrode provided in contact with the first main surface via a first bonding material having electrical conductivity; a second terminal connected to a second electrode provided in contact with the second main surface via a second bonding material having electrical conductivity and insulated from the first terminal; an insulating material that seals a portion of each of the first terminal and the second terminal and the semiconductor substrate; a third main surface located on the first bonding material side of the semiconductor substrate, from which the first terminal and the second terminal are exposed; a fourth major surface opposite the third major surface; and having the second terminal is extended to the third principal surface side by an extension electrode spaced from a stacked body including the semiconductor substrate, the first electrode, and the first bonding material; the first terminal and the second terminal are insulated from each other by the insulating material, the first terminal, the second terminal and the insulating material have the same height on the third main surface.

2. 2. The semiconductor device according to claim 1, A semiconductor device, wherein terminals are not exposed on any surface other than the third main surface.

3. 2. The semiconductor device according to claim 1, the second terminal is exposed at the fourth main surface.

4. 2. The semiconductor device according to claim 1, A plurality of the first terminals are formed, a plurality of first terminals are connected to the plurality of first electrodes formed in contact with the first main surface via the first bonding material, a plurality of the first terminals are exposed on the third main surface.

5. 2. The semiconductor device according to claim 1, The second terminals are formed in plurality, a plurality of second terminals are connected to the plurality of second electrodes formed in contact with the second main surface via the second bonding material, a plurality of the second terminals are exposed on the third main surface.

6. 6. The semiconductor device according to claim 5, a plurality of the second terminals are exposed on the fourth main surface.

7. 6. The semiconductor device according to claim 5, the first terminal exposed on the third main surface has a substantially rectangular shape in a plan view, the second terminal exposed at the third main surface extends along one side, two sides, three sides, or four sides of the first terminal in a plan view.

8. A method for manufacturing a semiconductor device, comprising the steps of: (a) preparing a semiconductor substrate including a first main surface, a second main surface opposite to the first main surface, and a semiconductor element, a first electrode being in contact with the first main surface, and a second electrode being in contact with the second main surface; (b) connecting a first conductor to the first electrode via a first bonding material having electrical conductivity; (c) preparing a second conductor having a first protrusion on a surface thereof; (d) separating a stacked body including the semiconductor substrate and the first electrode from the first protrusion, and connecting the second electrode to the surface of the second conductor via a second bonding material having electrical conductivity; (e) after steps (a) to (d), sealing the semiconductor substrate, the first conductors, and the second conductors with an insulating material; Here, the semiconductor device has a third main surface to which a first terminal made of the first conductor and a second terminal made of the second conductor are exposed, and a fourth main surface opposite to the third main surface, the third main surface is located on the first bonding material side with respect to the semiconductor substrate, The first terminal and the second terminal are insulated from each other, On the third main surface, the first terminal, the second terminal and the insulating material have the same height, The second terminal is extended toward the third main surface by the first protrusion.

9. 9. The method of manufacturing a semiconductor device according to claim 8, (f) after the step (e), removing a portion of the insulating material by grinding to expose the first conductors and the second conductors from the insulating material on the third main surface; The method for manufacturing a semiconductor device further comprises:

10. 10. The method of manufacturing a semiconductor device according to claim 9, (b1) before the step (b), preparing the first conductor having a first support portion and a plurality of second protrusions arranged on a surface of the first support portion; and In the step (a), the semiconductor substrate is prepared, the first main surface of which is in contact with a plurality of first electrodes that are insulated from one another; In the step (b), the second protrusions are connected to the first electrodes via the first bonding material, respectively; In the step (f), a part of the insulating material and the first support portion are removed by grinding to expose the second protrusions and the second conductors spaced apart from each other on the third main surface from the insulating material; In the first conductor prepared in the step (b1), the first support portion and the second protrusions are integral with each other, the second protrusions exposed at the third main surface constitute the first terminals which are insulated from one another.

11. 9. The method of manufacturing a semiconductor device according to claim 8, In the step (e), the semiconductor substrate, the first conductor, and the second conductor are sealed with the insulating material, except for a surface of the second conductor that constitutes the fourth main surface.

12. 10. The method of manufacturing a semiconductor device according to claim 9, (f1) after the step (e), removing a portion of the insulating material by grinding to expose the second conductor from the insulating material on the fourth principal surface; The method for manufacturing a semiconductor device further comprises:

13. 9. The method of manufacturing a semiconductor device according to claim 8, (f2) after the step (e), removing a portion of the insulating material and a portion of the second conductor by grinding; and In the step (a), the semiconductor substrate is prepared, the second main surface of which is in contact with a plurality of second electrodes that are insulated from one another; In the step (c), the second conductor is provided with a second support portion, a plurality of third protrusions formed on a surface of the second support portion, and a plurality of the first protrusions formed on the surface of the second support portion via each of the plurality of third protrusions; In the step (d), the laminate including the second electrodes is spaced from the first protrusions, and the second electrodes are connected to surfaces of the third protrusions, which are the surfaces of the second conductors, via the second bonding material, respectively; In the step (f2), the part of the insulating material and the second support portion that is the part of the second conductor are removed by grinding to expose the third protrusions spaced apart from each other on the fourth main surface from the insulating material; the third protrusions exposed at the fourth main surface constitute the second terminals which are insulated from one another.

14. 14. The method of manufacturing a semiconductor device according to claim 13, (f3) after the step (f2), sealing the second terminals on the fourth main surface; The method for manufacturing a semiconductor device further comprises:

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