Solid-state imaging element and imaging apparatus

Abstract

To solve the problem of a noise generated in a pixel, in an imaging element.SOLUTION: The imaging element includes a photoelectric conversion part for converting light into an electric charge, a first charge storage part for storing the electric charge, and a second charge storage part for storing the electric charge transferred from the photoelectric conversion part and the electric charge transferred from the first charge storage part.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a solid-state imaging device and an imaging apparatus. [Background technology]

[0002] Image sensors having a memory in each pixel are known (see, for example, Patent Document 1). Conventionally, noise generated in pixels has been a problem. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2011-188410 A Summary of the Invention

[0004] According to a first aspect, an imaging element includes a photoelectric conversion unit that converts light into electric charges, a first charge accumulation unit that accumulates the electric charges, and a second charge accumulation unit that accumulates the electric charges transferred from the photoelectric conversion unit and the electric charges transferred from the first charge accumulation unit. [Brief description of the drawings]

[0005] [Figure 1] 1 is a cross-sectional view illustrating a schematic configuration of an example of an imaging device using an imaging element according to an embodiment. [Diagram 2] FIG. 1 is a diagram illustrating a schematic configuration of an example of an imaging element according to an embodiment. [Diagram 3] FIG. 3 is a circuit diagram of the pixel shown in FIG. [Figure 4] 4 is a timing chart showing an exposure process in the pixel shown in FIG. [Diagram 5] 13A is a potential distribution diagram in the reset process, FIG. 13B is a potential distribution diagram in the accumulation process, and FIG. 13C is a potential distribution diagram in the first charge transfer process. [Figure 6] 13A is a diagram showing the potential distribution during the FD reset process, and FIG. 13B is a diagram showing the potential distribution during the second charge transfer process. [Figure 7] 13A is a diagram showing the potential distribution in the reverse transfer process, and FIG. 13B is a diagram showing the potential distribution in the first charge transfer process. [Figure 8] FIG. 11 is a circuit diagram of a pixel according to a second embodiment. [Figure 9] 9 is a timing chart showing an exposure process in the pixel shown in FIG. 8. [Figure 10] 13A is a diagram showing the potential distribution during the accumulation process, and FIG. 13B is a diagram showing the potential distribution during the first charge transfer process. [Figure 11] 13A is a potential distribution diagram in the third charge transfer process, and FIG. 13B is a potential distribution diagram in the reverse transfer process. [Figure 12] 13A is a diagram showing the potential distribution during the accumulation process, and FIG. 13B is a diagram showing the potential distribution during the first charge transfer process. [Figure 13] 1A is a diagram showing the potential distribution in the first charge transfer process, and FIG. 1B is a diagram showing the potential distribution in the second charge transfer process. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] (Configuration and Function of Imaging Device Using Imaging Element According to the Embodiment) 1 is a cross-sectional view showing a schematic configuration of an example of an imaging device using an imaging element according to embodiment 1. The imaging device 1 includes an imaging optical system 2, an imaging element 3, a control unit 4, a lens driving unit 5, and a display unit 6.

[0007] The imaging optical system 2 forms a subject image on the imaging surface of the image sensor 3. The imaging optical system 2 is formed by a lens 2a, a focusing lens 2b, and a lens 2c. The focusing lens 2b is a lens for adjusting the focus of the imaging optical system 2. The focusing lens 2b is configured to be drivable in the direction of the optical axis O. Note that the imaging optical system 2 is just an example, and may be formed by other optical systems.

[0008] The lens driving unit 5 has an actuator (not shown). The lens driving unit 5 drives the focusing lens 2b by a desired amount in the direction of the optical axis O by an actuator (not shown). The imaging element 3 captures an image of a subject and outputs a pixel signal. The control unit 4 has a memory unit and a calculation unit, and controls each unit such as the imaging element 3. For example, the control unit 4 performs image processing or the like on the pixel signal output by the imaging element 3 to generate an image signal. The control unit 4 records the image signal in the memory unit of the control unit 4, and displays the image on the display unit 6. The display unit 6 is a display device having a display member such as a liquid crystal panel.

[0009] 2 is a diagram showing a schematic configuration of an example of the image sensor 3. The image sensor 3 includes an imaging section 20, a row scanning circuit 21, a horizontal control line 22, a column signal processing circuit 23, a vertical signal line 24, a column scanning circuit 25, a horizontal signal line 26, an output terminal 27, and a pixel current source 28. The structure of the image sensor 3 may be a back-illuminated type or a front-illuminated type.

[0010] The imaging section 20 has a plurality of pixels 30 arranged in a matrix. The number of pixels 30 in the imaging section 20 is, for example, 20 million or more. Each of the plurality of pixels 30 is connected to a vertical signal line 24 on a column basis. Also, each of the plurality of pixels 30 is connected to a horizontal control line 22 on a row basis.

[0011] The row scanning circuit 21 is formed by logic circuits such as a shift register and an address decoder, and is electrically connected to each of the multiple pixels 30 on a row-by-row basis via a horizontal control line 22. The row scanning circuit 21 controls the multiple pixels 30 on a row-by-row basis by outputting a control signal to the multiple pixels 30 via the horizontal control line 22. For example, the row scanning circuit 21 selects each of the multiple pixels 30 on a row-by-row basis by outputting a row readout signal RSEL to the multiple pixels 30 on a row-by-row basis via a row selection line 205 included in the horizontal control line 22. The horizontal control line 22 includes a plurality of control lines.

[0012] The column signal processing circuit 23 includes a correlated double sampling (CDS) circuit, an amplifier circuit, an AD conversion circuit, and the like, and is electrically connected to each of the pixels 30 for each column via the vertical signal line 24. The circuits included in the column signal processing circuit 23 are arranged for each pixel column. The column signal processing circuit 23 performs a predetermined signal processing on a signal input from the pixel 30 of a row selected by the row scanning circuit 21 via the vertical signal line 24. The column signal processing circuit 23 performs signal processing including a correction process for correcting fixed pattern noise and reset noise, a signal amplification process for amplifying an analog signal input from the pixel 30, and an AD conversion process for converting the amplified analog signal into a digital signal. The column signal processing circuit 23 stores the digital signals that have been subjected to the signal processing for each column. In the column signal processing circuit 23, the correction process is performed by the CDS circuit, the amplification process is performed by the amplifier circuit, and the AD conversion process is performed by the AD conversion circuit. The correction process may be performed on an analog signal before the AD conversion process, or on a digital signal after the AD conversion process.

[0013] The column scanning circuit 25 is formed by logic circuits such as a shift register and an address decoder, and is electrically connected to the column signal processing circuits 23. The column scanning circuit 25 sequentially selects the column signal processing circuits 23 for each column, and sequentially outputs the digital signals stored in the column signal processing circuits 23 as pixel signals to an output terminal 27 via a horizontal signal line 26. The control unit 4 generates an image signal from the pixel signals output by the output terminal 27.

[0014] The pixel current source 28 has a constant current source arranged for each column, and supplies a bias current to each of the pixels 30 via the vertical signal line 24 .

[0015] In the imaging device 1, image data for live view (LV) is generated by repeatedly performing a process of reading out signals based on charges accumulated in pixels 30 in a pixel array at a predetermined cycle. When capturing a still image, a long-second exposure operation that exceeds this predetermined cycle may be performed. During the long-second exposure operation, signals for generating image data for LV cannot be read out, and therefore image data for LV cannot be generated during this time.

[0016] The imaging element of the embodiment has a second charge storage section that stores charges transferred from a first charge storage section capable of reading out the charges, so that the charges read out from the first charge storage section while a long exposure operation is being performed can be used when generating image data for LV.

[0017] FIG. 3 is a circuit diagram of pixel 30.

[0018] The pixel 30 includes a photoelectric conversion section, a first charge accumulation section, and a second charge accumulation section. The pixel 30 further includes a first transfer section, a second transfer section, an output section, and a reset section. The output section includes an amplifier section and a selection section. The first transfer section, the second transfer section, the amplifier section, the selection section, and the reset section are each configured with a transistor having at least a gate terminal. The first transfer section, the second transfer section, the amplifier section, the selection section, and the reset section may each be configured with a gate terminal, a source terminal, and a drain terminal. Each transistor will be described later.

[0019] In FIG. 3, the pixel 30 has a photodiode (PD) 101, a first transfer transistor 102, a second transfer transistor 103, a memory 104, and a floating diffusion (FD) 105. The pixel 30 further has an amplification transistor (AMP) 106, a selection transistor 107, and a reset transistor 108. In response to various signals being input to a first charge transfer line 201, a second charge transfer line 202, a memory voltage application line 203, a reset line 204, and a row selection line 205 included in a horizontal control line 22, the pixel 30 outputs a signal based on the charge accumulated in the PD 101 to the column signal processing circuit 23 via a vertical signal line 24. The first transfer transistor 102, the second transfer transistor 103, the AMP 106, the selection transistor 107, and the reset transistor 108 are, for example, nMOS transistors, but the type of the transistor is not limited thereto.

[0020] The photoelectric conversion unit converts incident light into an electric charge. An example of the photoelectric conversion unit is a photodiode (PD) 101.

[0021] The first transfer section transfers the charge photoelectrically converted by the photoelectric conversion section to the second charge accumulation section. An example of the first transfer section is a first transfer transistor 102. The first transfer transistor 102 has a gate. The gate of the first transfer transistor 102 can electrically connect the PD 101 and the memory 104. The first transfer transistor 102 transfers the charge photoelectrically converted by the PD 101 to the memory 104 by switching the electrical connection between the PD 101 and the memory 104. The first transfer transistor 102 is controlled by inputting a first charge transfer signal TX1 to the gate of the first transfer transistor 102 from a first charge transfer line 201 included in the horizontal control line 22.

[0022] The second transfer section can transfer the charge stored in the first charge storage section to the second charge storage section, and can transfer the charge stored in the second charge storage section to the first charge storage section. An example of the second transfer section is the second transfer transistor 103. The second transfer transistor 103 has a gate. The gate of the second transfer transistor 103 can electrically connect the memory 104 and the FD 105. The second transfer transistor 103 is controlled by inputting a second charge transfer signal TX2 to the gate of the second transfer transistor 103 from a second charge transfer line 202 included in the horizontal control line 22. The potential of the channel under the gate electrode of the second transfer transistor 103 by inputting the second charge transfer signal TX2 can be Vtx2Ha lower than the FD and Vtx2Hb higher than the FD. Hereinafter, the potential of the channel of the gate electrode of the transistor will be simply referred to as the potential of the transistor. The second transfer transistor 103 can transfer the charge accumulated in the memory 104 to the FD 105 by switching the electrical connection between the memory 104 and the FD 105. In addition, the second transfer transistor 103 can transfer the charge accumulated in the FD 105 to the memory 104 by switching the electrical connection between the memory 104 and the FD 105.

[0023] The second charge accumulation unit accumulates the charge transferred from the photoelectric conversion unit and the charge transferred from the first charge accumulation unit. An example of the second charge accumulation unit is the memory 104. The memory 104 has a structure of a transistor having a gate. The memory 104 is electrically connected to the first transfer transistor 102 and the second transfer transistor 103. The memory 104 is controlled by inputting a memory voltage signal Vmem from a memory voltage application line 203 included in the horizontal control line 22. The potential of the memory 104 by inputting the memory voltage signal Vmem can be Vma, which is lower than the potential of the FD and lower than the potential Vtx2Ha of the second transfer transistor 103, and Vmb, which is higher than the potential of the FD and higher than the potential Vtx2Hb of the second transfer transistor 103. The memory 104 accumulates the charge transferred from the PD 101 and the charge transferred from the FD 105. For example, the memory 104 accumulates the charge transferred from the PD 101 and the charge transferred from the memory 104 to the FD 105 and then transferred from the FD 105 to the memory 104. The memory 104 may have a structure of a transistor having a gate, but may have another structure.

[0024] The first charge accumulation unit accumulates the charge generated in the photoelectric conversion unit and transferred via the second charge accumulation unit. An example of the first charge accumulation unit is the FD 105. The FD 105 accumulates the charge transferred from the PD 101 via the memory 104. The FD 105 also accumulates the charge transferred from the FD 105 via the memory 104 and the charge transferred from the PD 101 via the memory 104.

[0025] The amplifier outputs a voltage signal based on the charge accumulated in the first charge accumulation unit. The amplifier is, for example, an amplifier transistor (AMP106). The AMP106 outputs a voltage signal based on the charge accumulated in the FD105. The AMP106 has a gate. The gate of the AMP106 can electrically connect the reset power supply Vrst and the selection transistor 107. The AMP106 outputs a signal based on the charge transferred from the PD101 to the FD105 via the memory 104. The AMP106 also outputs a signal based on the charge transferred from the FD105 to the memory 104 and then transferred again to the FD105, and the charge transferred from the PD101 to the FD105 via the memory 104.

[0026] The selection unit outputs a signal input from the amplification unit to the vertical signal line by switching an electrical connection between the amplification unit and the vertical signal line. The selection unit is, for example, a selection transistor 107. The selection transistor 107 has a gate. The selection transistor 107 can electrically connect the AMP 106 and the vertical signal line 24. The selection transistor 107 is controlled by inputting a row read signal RSEL to the gate from a row selection line 205 included in the horizontal control line 22. The source terminal of the selection transistor 107 is connected to a load current source (not shown). The load current source is connected to the vertical signal line 24 and supplies a current for reading out a signal from the pixel 30. This makes it possible to stabilize the operation of the AMP 106.

[0027] The reset unit discharges the charge stored in the first charge storage unit to a power supply wiring to which a reset voltage is supplied. The reset unit resets the potential of the first charge storage unit by the reset voltage. The reset unit is, for example, a reset transistor 108. The reset transistor 108 has a gate. The gate of the reset transistor 108 can electrically connect the FD 105 and a reset power supply Vrst. In response to a reset control signal RST being input to the gate of the reset transistor 108 from a reset line 204 included in the horizontal control line 22, the reset transistor 108 applies a reset voltage from the reset power supply Vrst to the FD 105 to reset the FD 105. Note that, although the reset unit has been described as discharging the charge to a power supply wiring to which a reset voltage is supplied, the reset unit may discharge the charge to a power supply wiring to which a power supply voltage different from the reset voltage is supplied.

[0028] The first charge storage unit and the output unit may be shared by a plurality of photoelectric conversion units. For example, a plurality of PDs 101 arranged in a row or column direction may share the FD 105, the AMP 106, and the selection transistor 107. Also, the pixel 30 may be composed of a plurality of photoelectric conversion units.

[0029] (Exposure Processing in Pixels According to the Embodiment) FIG. 4 is a timing chart showing the exposure process in the pixel 30. In FIG. LV is a period in which a signal for forming an image for live view is output, and Pexp is an exposure period. In the timing chart shown in FIG. 4, the exposure period Pexp is LV 4 is executed in a calculation section of the control section 4 mainly by the control section 4 in cooperation with each element of the imaging device 1 based on a program stored in advance in a storage section of the control section 4.

[0030] At time T0, the control unit 4 outputs the first charge transfer signal TX1, the second charge transfer signal TX2, and the reset control signal RST as pulse signals to the gates of the first transfer transistor 102, the second transfer transistor 103, and the reset transistor 108, respectively. FIG. 5(a) shows the potential distribution in the reset process. The control unit 4 outputs the first charge transfer signal TX1 as a pulse signal to the first transfer transistor 102 by changing the voltage level of the first charge transfer signal TX1 from a low voltage level Vtx1L' to a high voltage level Vtx1H'. In this way, the first charge transfer signal TX1 is input to the gate of the first transfer transistor 102, so that the potential of the first transfer transistor 102 changes from Vtx1L to Vtx1H. Similarly, when the second charge transfer signal TX2 is input to the gate of the second transfer transistor 103, the potential of the second transfer transistor 103 changes from Vtx2L to Vtx2Ha, and when the reset control signal RST is input to the gate of the reset transistor 108, the potential of the reset transistor 108 changes from RSTL to RSTH. As a result, as shown in FIG. 5(a), the potential Vtx1H of the first transfer transistor 102 becomes higher than the potential of the PD101 and lower than the potential Vma of the memory 104. The potential Vtx1Ha of the second transfer transistor 103 becomes higher than the potential Vma of the memory 104 and lower than the potential of the FD105. The potential RSTH of the reset transistor 108 becomes higher than the potential of the FD105 and the potential of the reset power supply Vrst. As a result, at time T0, the charges of the PD101, the memory 104, and the FD105 are discharged to the power supply wiring of the reset power supply Vrst.

[0031] Next, in the charge accumulation process during the charge accumulation period from time T1 to T2 in Fig. 4, the PD 101 converts the light incident on the PD 101 into charge and accumulates it. Fig. 5(b) shows the potential distribution during the accumulation process. The gray shaded area in Fig. 5(b) shows that charge is accumulated in the PD 101.

[0032] Next, in the first charge transfer process at time T2 in Fig. 4, the control unit 4 outputs the first charge transfer signal TX1 as a pulse signal to the first transfer transistor 102. Fig. 5(c) shows the potential distribution in the first charge transfer process. When the first charge transfer signal TX1 is input to the gate of the first transfer transistor 102, the potential of the first transfer transistor 102 changes from Vtx1L to Vtx1H. The potential Vtx1H of the first transfer transistor 102 becomes higher than the potential of the PD 101 and lower than the potential Vma of the memory 104. As a result, the charge accumulated in the accumulation process is transferred to the memory 104.

[0033] Next, in the FD reset process at time T4 in Fig. 4, the control unit 4 outputs a reset control signal RST as a pulse signal to the reset transistor 108. Fig. 6(a) shows the potential distribution in the FD reset process. The reset control signal RST is input to the gate of the reset transistor 108, thereby changing the potential of the reset transistor 108 from VrL to VrH. The potential VrH of the reset transistor 108 becomes higher than the potential of the FD 105 and the potential of the reset power supply Vrst. As a result, the charge of the FD 105 is discharged to the power supply wiring of the reset power supply Vrst.

[0034] 4, in a reset signal readout process at time T5, the control unit 4 outputs a row readout signal RSEL to the selection transistor 107. When the row readout signal RSEL is input to the gate of the selection transistor 107, the potential of the selection transistor 107 changes from L to H. As a result, a reset signal indicating the potential of the reset FD 105 is output to the column signal processing circuit 23 via the vertical signal line 24.

[0035] Next, in the second charge transfer process at time T6 in FIG. 4, the control unit 4 outputs the second charge transfer signal TX2 to the second transfer transistor 103 as a pulse signal. FIG. 6(b) shows the potential distribution in the second charge transfer process. The control unit 4 outputs the second charge transfer signal TX2 to the first transfer transistor 102 as a pulse signal by changing the voltage level of the second charge transfer signal TX2 from a low voltage level Vtx2L' to a high voltage level Vtx2Ha'. By inputting the second charge transfer signal TX2 to the gate of the second transfer transistor 103, the potential of the second transfer transistor 103 changes from Vtx2L to Vtx2Ha. The potential Vtx1Ha of the second transfer transistor 103 becomes higher than the potential Vma of the memory 104 and lower than the potential of the FD 105. As a result, the charge transferred to the memory 104 in the first charge transfer process is transferred to the FD 105.

[0036] 4, in the signal readout process at time T7, the control unit 4 outputs the row readout signal RSEL as a pulse signal to the selection transistor 107. When the row readout signal RSEL is input to the gate of the selection transistor 107, the potential of the selection transistor 107 changes from L to H. As a result, the selection transistor 107 outputs a signal based on the charge accumulated in the PD 101 between times T1 and T2 to the column signal processing circuit 23 via the vertical signal line 24.

[0037] The reset signal read out in the reset signal readout process at time T5 contains fixed pattern noise and reset noise generated at the time of FD reset at time T4. The signal based on the charge accumulated in the PD 101 between times T1 and T2, read out in the signal readout process at time T7, also contains fixed pattern noise and reset noise. The CDS circuit included in the column signal processing circuit 23 subtracts the reset signal from the signal based on the charge accumulated in the PD 101 between times T1 and T2, thereby obtaining a pixel signal from which the fixed pattern noise and reset noise have been removed. The control unit 4 generates an image signal from the pixel signal from which the fixed pattern noise and reset noise have been removed, and displays the image on the display unit 6 as an LV image.

[0038] Next, in the reverse transfer process at time T8 in FIG. 4, the control unit 4 outputs the memory voltage signal Vmem to the memory 104. By inputting the memory voltage signal Vmem to the memory 104, the potential of the memory 104 changes from Vma to Vmb, which is higher than Vma. At time T9 while the memory voltage signal Vmem is being output to the memory 104, the control unit 4 outputs the second charge transfer signal TX2 to the second transfer transistor 103 as a pulse signal. The control unit 4 outputs the second charge transfer signal TX2 to the second transfer transistor 103 by changing the voltage level of the second charge transfer signal TX2 from a low voltage level Vtx2L' to a high voltage level Vtx2Hb'. By inputting the second charge transfer signal TX2 to the gate of the second transfer transistor 103, the potential of the second transfer transistor 103 changes from Vtx2L to Vtx2Hb. FIG. 7(a) shows the potential distribution in the reverse transfer process. The potential Vmb of the memory 104 becomes higher than the potential Vtx2Hb of the second transfer transistor 103 and the potential of the FD105, and the potential Vtx2Hb of the second transfer transistor 103 becomes higher than the potential of the FD105 and lower than the potential Vmb of the memory 104. As a result, the charge transferred to the FD105 is transferred back to the memory 104. After reading out a signal based on the charge accumulated in the FD105, the charge is transferred back to the memory 104, so that the FD105 can be brought into a state similar to a reset state without discharging the charge accumulated in the FD105. As a result, it is possible to output a pixel signal from which fixed pattern noise and reset noise have been removed during the long second exposure period.

[0039] Next, in the first charge transfer process at time T10 in FIG. 4, the control unit 4 outputs the first charge transfer signal TX1 to the first transfer transistor 102 as a pulse signal. FIG. 7(b) shows the potential distribution in the first charge transfer process. In response to the first charge transfer signal TX1 being input to the gate of the first transfer transistor 102, the potential of the first transfer transistor 102 changes from Vtx1L to Vtx1H, and the charge accumulated between time T3 and time T10 after the previous first charge transfer process is transferred to the memory 104. At this time, the charge accumulated between time T1 and time T2, which has been transferred in reverse from the FD 105, is held in the memory 104. The memory 104 holds both the charge accumulated between time T1 and time T2 and the charge accumulated between time T3 and time T10. Then, the FD reset process at time T12 to the reverse transfer process at time T16 are repeated. Each process is similar to the above-mentioned process, so a description thereof will be omitted.

[0040] While the processes from the first charge transfer process to the reverse transfer process are repeated in sequence, the reset signal and the signal read out by the signal read out process are sequentially output to a CDS circuit included in the column signal processing circuit 23. The CDS circuit uses the reset signal to remove fixed pattern noise and reset noise from the signal read out by the signal read out process. The pixel signal from which the fixed pattern noise and reset noise have been removed by the CDS circuit is input to the control unit 4 via the output terminal 27 and stored in the memory unit of the control unit 4. The control unit 4 generates an image signal from the pixel signal and displays it on the display unit 6 as an LV image.

[0041] Here, the signal read out at time T15 is a signal based on the charges accumulated between time T1 and time T2 and the charges accumulated between time T3 and time T10. To obtain a signal based on the charges accumulated between time T3 and time T10, the pixel signal read out at time T7 and from which the fixed pattern noise and the reset noise have been subtracted is subtracted from the pixel signal read out at time T15 and from which the fixed pattern noise and the reset noise have been subtracted. The control unit 4 generates an image signal based on the charges accumulated between time T3 and time T10 from the pixel signal obtained by the subtraction, and can display the image on the display unit 6 as an LV image. In the above, to obtain an image signal based on charges accumulated between time T3 and time T10, a pixel signal read out at time T7 and having fixed pattern noise and reset noise subtracted therefrom is subtracted from a pixel signal read out at time T15 and having fixed pattern noise and reset noise subtracted therefrom, but the image signal may be generated by subtracting an image signal generated by a signal based on charges accumulated between time T1 and time T2 from an image signal generated by a signal based on charges accumulated between time T1 and time T2 and charges accumulated between time T3 and time T10. When the exposure period Pexp has elapsed, the control unit 4 executes a reset process without executing a reverse transfer process, and starts the next exposure process.

[0042] The control unit 4 generates image data from a signal based on the charges transferred from the FD 105 to the memory 104 and the charges transferred from the PD 101 to the memory 104, and outputs the generated image data to the display unit 6. In response to the input of the image data, the display unit 6 displays an image generated from a signal based on the charges transferred from the FD 105 to the memory 104 and the charges transferred from the PD 101 to the memory 104 storage unit.

[0043] In the above, the image signal generated by the signal based on the charge accumulated between time T1 and time T2 and the image signal generated by the signal based on the charge accumulated between time T3 and time T10 are displayed as LV images, respectively. However, the image signal based on the pixel signal output during each LV period may be output as an LV image. That is, after the image signal generated by the signal based on the charge accumulated between time T1 and time T2 is displayed as an LV image, the image signal generated by the charge accumulated between time T1 and time T2 and the signal based on the charge accumulated between time T3 and time T10 are displayed as an LV image, and similarly, the image signal generated by the signal based on the charge accumulated after time T1 is displayed as an LV image until the exposure period Pexp has elapsed. This allows the image obtained by the long-second exposure to be confirmed in the LV image. In addition, at this time, the long-second exposure may be terminated at any timing of the user's choice. This allows the user to confirm (monitor) the image obtained by the long-second exposure in the LV image and terminate the shooting when the user's desired image is obtained.

[0044] LV period P LV The pixels 30 whose signals are read out every LV image may be all the pixels 30 that the image sensor 3 has and that are used for imaging, or may be only the pixels 30 included in a portion of pixel rows allocated for the LV image. This allows the LV image to be displayed quickly. In this case, the reverse transfer process may be performed only on the pixels 30 included in a portion of pixel rows allocated for the LV image. Also, the reverse transfer process may be performed on all pixels. By performing the reverse transfer process on all pixels 30, the difference with other rows can be reduced. Also, the pixels 30 having a configuration capable of performing the reverse transfer process in the image sensor 3 may be only a portion of the pixels allocated for the LV image. Also, the image sensor 3 may be provided with pixels for phase difference AF (phase difference pixels). At this time, readout from the phase difference pixels may be performed in a period shorter than the exposure period Pexp for phase difference AF. For example, the LV period P LVThe LV period P during the period until the exposure period Pexp has elapsed is LV By performing readout and reverse transfer in the phase difference pixel for each image, the charge accumulated in the phase difference pixel increases, thereby improving the accuracy of AF in dark scenes. In addition, the reverse transfer process may be performed on the pixels 30 that are assigned for the LV image and phase difference AF among the pixels 30 that configure the image sensor 3, but reverse transfer may be performed on all the pixels 30. In addition, the pixels 30 that have a configuration that allows reverse transfer process in the image sensor 3 may be pixels for the LV image and pixels for the phase difference pixels.

[0045] Furthermore, reset noise occurs in the FD reset process. In this embodiment, in the reverse transfer process, charges including the reset noise generated in the FD reset process are reverse transferred. Therefore, the reset noise is superimposed on the charges each time the reverse transfer is repeated. However, because the reset noise is random noise, the noise is averaged by repeating the reverse transfer, and the effect of the reset noise on the image obtained by the long-second exposure of the exposure period Pexp is reduced. Also, a memory is provided within the image sensor, and the LV period P LV The reset signal read out in the reset signal readout process may be stored for each pixel 30. The stored reset signal may be used to correct pixel signals or image signals corresponding to the second or subsequent charge accumulation periods in the exposure period Pexp. Also, the pixel signals or image signals obtained by long-second exposure in the exposure period Pexp may be corrected. The memory for storing the reset signal may be provided outside the image sensor.

[0046] The effects of this embodiment are as follows. The image sensor 3 can output pixel signals from which fixed pattern noise and reset noise have been removed, based on charges converted by the PD 101 during a period shorter than the long-second exposure period, while retaining the charges converted by the PD 101 during the long-second exposure period in the pixels 30 by transferring the charges accumulated in the FD 105 back to the memory 104 and storing them therein. That is, in the image sensor 3, the second transfer transistor 103 can transfer the charges accumulated in the memory 104 to the FD 105, and can also transfer the charges accumulated in the FD 105 to the memory 104, so that the FD 105 can be reset after the charges are transferred from the FD 105 to the memory 104. Since the FD reset process is performed after the charges are transferred from the FD 105 to the memory 104, a signal based on fixed pattern noise and reset noise is sent to the column signal processing circuit 23 in the LV period P in the FD reset process without resetting (non-destructively) the charges converted by the PD 101 during the long-second exposure period. LV It can be output every LV period P LV Since a pixel signal from which fixed pattern noise and reset noise have been removed can be obtained by the signal output every time, an LV image with good image quality can be obtained.

[0047] In addition, since the charge converted by PD 101 during the long-second exposure period is not reset (non-destructive), it is possible to obtain a long-second exposure image with good quality while obtaining a pixel signal for an LV image during the long-second exposure period.

[0048] Also, since the charges converted by PD 101 during the long second exposure period are not reset (non-destructive), the pixels 30 read out to obtain an LV image may be some of the pixels 30 for LV (e.g. some pixel rows) rather than all of the pixels 30 for imaging in the image sensor 3. The LV image can be displayed at high speed compared to the case where the charges converted by PD 101 during the long second exposure period are reset (destroyed) to obtain a signal for an LV image. When the charges converted by PD 101 during the long second exposure period are reset (destroyed) to obtain a signal for an LV image, in order to obtain a long second exposure image, pixel signals output during the long second exposure period or image signals based on pixel signals output during the long second exposure period are added together, so that the LV period P LV This is because a readout process must be performed for all of the imaging pixels 30 of the imaging element 3 every time.

[0049] Second embodiment The second embodiment will be described with reference to Figs. 8 to 13. In the description of the second embodiment, the same components as those in the first embodiment are assigned the same numbers and the description will be omitted. Fig. 8 is a circuit diagram of a pixel 40. The pixel 40 according to the second embodiment includes a third transfer section, a third charge storage section that does not require resetting, and a second output section in addition to the components of the pixel 30. In the image sensor in the first embodiment, it was not possible to remove all reset noise from the image signal obtained by long-second exposure with an exposure period Pexp. In the image sensor in the second embodiment, the third transfer section, the third charge storage section that does not require resetting, and the second output section are provided as a circuit for outputting a pixel signal for an LV image. Therefore, reset noise does not occur in the process of outputting a pixel signal for an LV image. Since reset noise does not occur, reset noise is not included in the charge that is transferred in reverse.

[0050] In addition to the configuration of pixel 30, pixel 40 in the second embodiment includes a third transfer section, a third charge storage section, and a second output section. The second output section has a second amplifier section and a second selection section. The third transfer section, the second amplifier section, and the second selection section are configured by transistors having at least a gate terminal. The third transfer section, the second amplifier section, and the second selection section may have a gate terminal, a source terminal, and a drain terminal.

[0051] 8, the pixel 40 further includes a third transfer transistor 109, a floating gate (FG) 110, a second amplification transistor (second AMAP) 111, and a second selection transistor 112 in addition to the configuration of the pixel 30. The horizontal control line 22 of the pixel 40 further includes a third charge transfer line 206 and a second row selection line 207. In response to various signals being input to the third charge transfer line 206 and the second row selection line 207 included in the horizontal control line 22, a signal based on the charge accumulated in the PD 101 is output to the column signal processing circuit 23 via the vertical signal line 24. The third transfer transistor 109, the second AMAP 111, and the second selection transistor 112 are, for example, nMOS transistors, but the type of the transistor is not limited thereto.

[0052] The third transfer section can transfer the charge stored in the second charge storage section to the third charge storage section, and can transfer the charge stored in the third charge storage section to the second charge storage section. An example of the third transfer section is a third transfer transistor 109. The third transfer transistor 109 has a gate. The gate of the third transfer transistor 109 can electrically connect the memory 104 and the FG 110. The third transfer transistor 109 is controlled by inputting a third charge transfer signal TX3 to the gate of the third transfer transistor 109 from a third charge transfer line 206 included in the horizontal control line 22. The potential of the third transfer transistor 109 by inputting the third charge transfer signal TX3 can be Vtx3Ha lower than the FG 110 and Vtx3Hb higher than the FG 110. The third transfer transistor 109 can transfer the charge stored in the memory 104 to the FG 110 by switching the electrical connection between the memory 104 and the FG 110. In addition, the third transfer transistor 109 can transfer the charge stored in the FG 110 to the memory 104 by switching the electrical connection between the memory 104 and the FG 110.

[0053] The third charge accumulation section accumulates the charge generated in the photoelectric conversion section and transferred via the second charge accumulation section. An example of the third charge accumulation section is FG110. FG110 accumulates the charge transferred from PD101 via memory 104. It also accumulates the charge transferred from FG110 to memory 104 and the charge transferred from PD101 to memory 104. FG110 is a floating gate that does not need to be reset.

[0054] The second amplifier outputs a voltage signal based on the charge accumulated in the third charge accumulation section. The second amplifier is, for example, a second amplification transistor (second AMP111). The second AMP111 outputs a voltage signal based on the charge accumulated in the FG110. The second AMP111 has a gate. The gate of the second AMP111 can electrically connect the power supply voltage Vdd and the second selection transistor 112. The second AMP111 outputs a signal based on the charge transferred from the PD101 to the FG110 via the memory 104. The second AMP111 also outputs a signal based on the charge transferred from the FG110 to the memory 104 and then transferred again to the FG110 and the charge transferred from the PD101 to the FG110 via the memory 104.

[0055] The second selection unit outputs a signal input from the second amplification unit to the vertical signal line by switching an electrical connection between the second amplification unit and the vertical signal line. The second selection unit is, for example, a second selection transistor 112. The second selection transistor 112 has a gate. The second selection transistor 112 can electrically connect the second AMP 111 to the vertical signal line 24. The second selection transistor 112 is controlled by inputting a second row readout signal RSEL2 to the gate from a second row selection line 207 included in the horizontal control line 22. The source terminal of the second selection transistor 112 is connected to a load current source (not shown). The load current source is connected to the vertical signal line 24 and supplies a current for reading out a signal from the pixel 40. This makes it possible to stabilize the operation of the second AMP 111.

[0056] (Exposure Processing in Pixels According to the Embodiment) FIG. 9 is a timing chart showing the exposure process in the pixel 40. In FIG. LV is a period in which a signal for forming an image for live view is output, and Pexp is an exposure period. In the timing chart shown in FIG. 9, the exposure period Pexp is LV 9 is executed in a calculation section of the control section 4 mainly by the control section 4 in cooperation with each element of the imaging device 1 based on a program stored in advance in a storage section of the control section 4.

[0057] At time T0, the control unit 4 outputs the first charge transfer signal TX1, the second charge transfer signal TX2, the third charge transfer signal TX3, and the reset control signal RST as pulse signals to the gates of the first transfer transistor 102, the second transfer transistor 103, the third transfer transistor 109, and the reset transistor 108. The control unit 4 changes the voltage level of the first charge transfer signal TX1 from a low voltage level Vtx1L' to a high voltage level Vtx1H', thereby outputting the first charge transfer signal TX1 as a pulse signal to the first transfer transistor 102. In this manner, the first charge transfer signal TX1 is input to the gate of the first transfer transistor 102, whereby the potential of the first transfer transistor 102 changes from Vtx1L to Vtx1H. Similarly, when a second charge transfer signal TX2 is input to the gate of the second transfer transistor 103, the potential of the second transfer transistor 103 changes from Vtx2L to Vtx2H, when a third charge transfer signal TX3 is input to the gate of the third transfer transistor 109, the potential of the third transfer transistor 109 changes from Vtx3L to Vtx3Ha, and when a reset control signal RST is input to the gate of the reset transistor 108, the potential of the reset transistor 108 changes from VrL to VrH. As a result, at time T0, the charges in the PD 101, memory 104, FD 105, and FG 110 are discharged to the power supply wiring of the reset power supply Vrst.

[0058] Next, in the charge accumulation process during the charge accumulation period from time T1 to T2 in Fig. 9, the PD 101 converts the light incident on the PD 101 into charge and accumulates it. Fig. 10(a) shows the potential distribution during the accumulation process. The gray shaded area in Fig. 10(a) shows that charge is accumulated in the PD 101.

[0059] Next, in the first charge transfer process at time T2 in Fig. 9, the control unit 4 outputs the first charge transfer signal TX1 as a pulse signal to the first transfer transistor 102. Fig. 10(b) shows the potential distribution in the first charge transfer process. When the first charge transfer signal TX1 is input to the gate of the first transfer transistor 102, the potential of the first transfer transistor 102 changes from Vtx1L to Vtx1H. The potential Vtx1H of the first transfer transistor 102 becomes higher than the potential of the PD 101 and lower than the potential Vma of the memory 104. As a result, the charge accumulated in the accumulation process is transferred to the memory 104.

[0060] 9, in the FG signal readout process at time T4, the control unit 4 outputs the second row readout signal RSEL2 to the second selection transistor 112. When the second row readout signal RSEL2 is input to the gate of the second selection transistor 112, the potential of the second selection transistor 112 changes from L2 to H2. As a result, a signal indicating the potential of FG 110 is output to the column signal processing circuit 23 via the vertical signal line 24.

[0061] Next, in the third charge transfer process at time T5 in FIG. 9, the control unit 4 outputs the third charge transfer signal TX3 to the third transfer transistor 109 as a pulse signal. FIG. 11(a) shows the potential distribution in the third charge transfer process. The control unit 4 outputs the third charge transfer signal TX3 to the third transfer transistor 109 as a pulse signal by changing the voltage level of the third charge transfer signal TX3 from a low voltage level Vtx3L' to a high voltage level Vtx3Ha'. By inputting the third charge transfer signal TX3 to the gate of the third transfer transistor 109, the potential of the third transfer transistor 109 changes from Vtx3L to Vtx3Ha. The potential Vtx3Ha of the third transfer transistor 109 is higher than the potential Vma of the memory 104 and lower than the potential of the FG 110. As a result, the charge transferred to the memory 104 in the first charge transfer process is transferred to the FG 110.

[0062] 9, in the second signal readout process at time T6, the control unit 4 outputs the second row readout signal RSEL2 as a pulse signal to the second selection transistor 112. When the second row readout signal RSEL2 is input to the gate of the second selection transistor 112, the potential of the second selection transistor 112 changes from L2 to H2. As a result, the second selection transistor 112 outputs a signal based on the charge accumulated in the PD 101 between times T1 and T2 to the column signal processing circuit 23 via the vertical signal line 24.

[0063] The signal indicating the potential of FG110 read out in the FG signal readout process at time T4 contains fixed pattern noise. The signal based on the charge accumulated in PD101 between times T1 and T2 read out in the signal readout process at time T6 also contains fixed pattern noise. The CDS circuit included in the column signal processing circuit 23 subtracts the signal indicating the potential of FG110 from the signal based on the charge accumulated in PD101 between times T1 and T2 to obtain a pixel signal from which the fixed pattern noise has been removed. The control unit 4 generates an image signal from the pixel signal from which the fixed pattern noise has been removed, and displays the image on the display unit 6 as an LV image.

[0064] 9, in the reverse transfer process at time T7, the control unit 4 outputs the memory voltage signal Vmem to the memory 104. By inputting the memory voltage signal Vmem to the memory 104, the potential of the memory 104 changes from Vma to Vmb, which is higher than Vma. At time T8, the control unit 4 outputs the third charge transfer signal TX3 to the third transfer transistor 109 as a pulse signal. The control unit 4 changes the voltage level of the third charge transfer signal TX3 from a low voltage level Vtx3L' to a high voltage level Vtx3Hb', thereby outputting the third charge transfer signal TX3 to the third transfer transistor 109 as a pulse signal. When the third charge transfer signal TX3 is input to the gate of the third transfer transistor 109, the potential of the third transfer transistor 109 changes from Vtx3L to Vtx3Hb. FIG. 11(b) shows the potential distribution in the reverse transfer process. The potential Vmb of the memory 104 becomes higher than the potential Vtx3Hb of the third transfer transistor 109 and the potential of the FG 110, and the potential Vtx3Hb of the third transfer transistor 109 becomes higher than the potential of the FG 110 and lower than the potential Vmb of the memory 104. As a result, the charge transferred to FG 110 is transferred back to the memory 104. After reading out the signal based on the charge accumulated in FG 110, the charge is transferred back to the memory 104, thereby making it possible to non-destructively read out the signal based on the charge accumulated in FG 110. As a result, it is possible to output pixel signals from which fixed pattern noise has been removed during the long second exposure period.

[0065] In the charge accumulation period from time T3 to time T9 after the first charge transfer process from time T2 to time T3, the charge accumulation process is performed. FIG. 12(a) shows the potential distribution in the charge accumulation process. In the first charge transfer process at time T9 in FIG. 4, the control unit 4 outputs the first charge transfer signal TX1 as a pulse signal to the first transfer transistor 102. FIG. 12(b) shows the potential distribution in the first charge transfer process. In response to the first charge transfer signal TX1 being input to the gate of the first transfer transistor 102, the potential of the first transfer transistor 102 changes from Vtx1L to Vtx1H, and the charge accumulated in the charge accumulation period from time T3 to time T9 is transferred to the memory 104. At this time, the charge accumulated between time T1 and time T2 and transferred back from the FG 110 is held in the memory 104. The memory 104 holds the charge accumulated between time T1 and time T2 and the charge accumulated between time T3 and time T9. Then, the read process from FG 110 at time T11 to the reverse transfer process at time T14 are repeated. Each process is similar to the above-mentioned process, so the description will be omitted.

[0066] While the processes from the first charge transfer process to the reverse transfer process are repeated in sequence, the signals read out by the FG signal readout process and the signals read out by the second signal readout process are sequentially output to a CDS circuit included in the column signal processing circuit 23. The CDS circuit uses the signals read out by the FG signal readout process to remove fixed pattern noise from the signals read out by the second signal readout process. The pixel signals from which the fixed pattern noise has been removed by the CDS circuit are input to the control unit 4 via the output terminal 27 and stored in the storage unit of the control unit 4.

[0067] Here, the signal read out at time T13 is a signal based on the charges accumulated between time T1 and time T2 and the charges accumulated between time T3 and time T9. To obtain a signal based on the charges accumulated between time T3 and time T9, the pixel signal read out at time T6 and from which the fixed pattern noise has been subtracted is subtracted from the pixel signal read out at time T13 and from which the fixed pattern noise has been subtracted. The control unit 4 can generate an image signal based on the charges accumulated between time T3 and time T9 from the pixel signal obtained by the subtraction, and display the image on the display unit 6 as an LV image. Alternatively, the image signal based on the charges accumulated between time T3 and time T9 may be generated by subtracting an image signal generated by a signal based on the charges accumulated between time T1 and time T2 from an image signal generated by a signal based on the charges accumulated between time T1 and time T2 and the charges accumulated between time T3 and time T9. The control unit 4 generates an image signal from the pixel signal, and displays the image signal on the display unit 6 as an LV image.

[0068] The control unit 4 generates image data from a signal based on the charges transferred from FG 110 to memory 104 and the charges transferred from PD 101 to memory 104 until time T16, and outputs the generated image data to the display unit 6. In response to the input of the image data, the display unit 6 displays an image generated from a signal based on the charges transferred from FG 110 to memory 104 and the charges transferred from PD 101 to the memory 104 accumulation unit.

[0069] Next, at time T16 in FIG. 9, the first charge transfer process is performed. FIG. 13(a) shows the potential distribution in the first charge transfer process. The first charge transfer process is similar to the process described above, so a description is omitted. Next, at time T18, the control unit 4 performs the FD reset process. The control unit 4 outputs the reset control signal RST to the reset transistor 108 as a pulse signal. The reset control signal RST is input to the gate of the reset transistor 108, thereby changing the potential of the reset transistor 108 from VrL to VrH. The potential VrH of the reset transistor 108 becomes higher than the potential of the FD 105 and the potential of the reset power supply Vrst. As a result, the charge of the FD 105 is discharged to the power supply wiring of the reset power supply Vrst.

[0070] 9, in a reset signal readout process at time T19, the control unit 4 outputs a row readout signal RSEL to the selection transistor 107. When the row readout signal RSEL is input to the gate of the selection transistor 107, the potential of the selection transistor 107 changes from L to H. As a result, a reset signal indicating the potential of the reset FD 105 is output to the column signal processing circuit 23 via the vertical signal line 24.

[0071] Next, in the second charge transfer process at time T20 in Fig. 9, the control unit 4 outputs the second charge transfer signal TX2 as a pulse signal to the second transfer transistor 103. Fig. 13(b) shows the potential distribution in the second charge transfer process. When the second charge transfer signal TX2 is input to the gate of the second transfer transistor 103, the potential of the second transfer transistor 103 changes from Vtx2L to Vtx2Ha. The potential Vtx2Ha of the second transfer transistor 103 becomes higher than the potential Vma of the memory 104 and lower than the potential of the FD 105. As a result, the charges transferred to the memory 104 in the first charge transfer process are transferred to the FD 105.

[0072] 9, in the signal readout process at time T21, the control unit 4 outputs the row readout signal RSEL as a pulse signal to the selection transistor 107. When the row readout signal RSEL is input to the gate of the selection transistor 107, the potential of the selection transistor 107 changes from L to H. As a result, the control unit 4 outputs a signal based on the charges accumulated in the PD 101 during each charge accumulation period from time T1 to time T16 to the column signal processing circuit 23 via the vertical signal line 24.

[0073] The reset signal read out in the reset signal readout process at time T19 includes fixed pattern noise and reset noise. The signal based on the charges accumulated in the PD 101 during each charge accumulation period from time T1 to T16, which is read out in the signal readout process at time T21, also includes fixed pattern noise and reset noise. The CDS circuit included in the column signal processing circuit 23 subtracts the reset signal from the signal based on the charges accumulated in the PD 101 during each charge accumulation period from time T1 to T16, thereby obtaining a pixel signal from which the fixed pattern noise and reset noise have been removed. The pixel signal from which the fixed pattern noise and reset noise have been removed by the CDS circuit is input to the control unit 4 via the output terminal 27 and stored in the storage unit of the control unit 4. The control unit 4 generates an image signal corresponding to the exposure period Pexp from the pixel signal.

[0074] At time T22 in FIG. 9, a reset process is performed, and thereafter, the next exposure process is started.

[0075] The effects of the second embodiment are as follows. By providing the FG 110 as the third charge storage unit, LV Since a reset process is not required before the signal readout process during the exposure period, no reset noise occurs. In other words, reset noise is not superimposed on the charges transferred in reverse transfer processes, so that an image signal with high accuracy corresponding to the exposure period Pexp can be obtained.

[0076] In each of the above-described embodiments, the photodiode (PD) is used as an example of the photoelectric conversion unit. However, a photoelectric conversion film may be used as the photoelectric conversion unit.

[0077] All or some of the above-described embodiments may be combined in any desired manner. [Explanation of symbols]

[0078] 3. Image sensor 30 pixels 24 CDS circuit 20 Imaging unit 101 Photodiode (PD) 102 first transfer transistor 103 Second transfer transistor 104 Memory 105 Floating Diffusion (FD) 106 Amplifying transistor (AMP) 107 Select transistor 108 Reset Transistor 40 pixels 109 Third transfer transistor 110 Floating Gate (FG) 111 Second amplifying transistor (second AMP) 112 Second selection transistor

Claims

1. a photoelectric conversion unit that converts light into an electric charge; an output section that outputs a first signal generated based on charges converted by the photoelectric conversion section during a first period and transferred from the photoelectric conversion section, and a second signal generated based on charges used to generate the first signal and charges converted by the photoelectric conversion section during a second period after the first period; An imaging element comprising:

2. 2. The imaging device according to claim 1, an image sensor including a holding unit that holds the charge used to generate the first signal and the charge converted by the photoelectric conversion unit during the second period;

3. 3. The imaging device according to claim 2, the holding unit holds the charge used to generate the first signal when the photoelectric conversion unit converts light into charge during the second period. Image sensor.

4. 3. The imaging device according to claim 2, the holding unit transfers charges from the photoelectric conversion unit in a first direction and a second direction different from the first direction; Image sensor.

5. 5. The imaging device according to claim 4, a floating diffusion to which the charges converted by the photoelectric conversion unit are transferred; the second direction is a direction in which charges are transferred from the floating diffusion to the holding unit; Image sensor.

6. 3. The imaging device according to claim 2, a floating diffusion to which the charges converted by the photoelectric conversion unit are transferred; The floating diffusion transfers electric charges via the holding portion. Image sensor.

7. 7. The imaging device according to claim 6, the holding unit holds the charges converted by the photoelectric conversion unit and transferred from the floating diffusion. Image sensor.

8. 8. The imaging device according to claim 7, the holding unit holds the charges transferred from the floating diffusion to the holding unit after the charges converted by the photoelectric conversion unit are transferred from the holding unit to the floating diffusion during the first period, and the charges converted by the photoelectric conversion unit during the second period. Image sensor.

9. 7. The imaging device according to claim 6, a first transfer unit that transfers the charges converted by the photoelectric conversion unit to the holding unit; a second transfer unit that transfers the charges held by the holding unit to the floating diffusion; An imaging element comprising:

10. 10. The imaging device according to claim 9, the second transfer unit transfers the charges transferred to the floating diffusion to the holding unit; Image sensor.

11. 10. The imaging device according to claim 9, the second transfer unit transfers the charges held in the holding unit to the floating diffusion, and then transfers the charges transferred to the floating diffusion to the holding unit. Image sensor.

12. 10. The imaging device according to claim 9, the first transfer unit transfers the charges converted by the photoelectric conversion unit to the holding unit when the holding unit holds the charges transferred from the floating diffusion; Image sensor.

13. 10. The imaging device according to claim 9, the second transfer unit transfers, to the floating diffusion, the charges transferred from the floating diffusion by the holding unit and the charges transferred from the photoelectric conversion unit when the holding unit holds the charges transferred from the floating diffusion; Image sensor.

14. 10. The imaging device according to claim 9, the first transfer unit transfers the charges converted by the photoelectric conversion unit to the holding unit; the second transfer unit transfers the charges transferred to the holding unit by the first transfer unit to the floating diffusion, and then transfers the charges held in the floating diffusion to the holding unit; Image sensor.

15. 3. The imaging device according to claim 2, The holding unit is supplied with a first holding voltage signal that controls the potential of the holding unit, and a second holding voltage signal that controls the potential of the holding unit and has a higher voltage than the first holding voltage signal. Image sensor.

16. 16. The imaging device according to claim 15, an imaging element including a voltage signal supply line that supplies the first hold voltage signal and the second hold voltage signal to the holding unit;

17. 16. The imaging device according to claim 15, When the first hold voltage signal is supplied to the holding unit, the potential of the holding unit becomes a first hold potential, and when the second hold voltage signal is supplied to the holding unit, the potential of the holding unit becomes a second hold potential higher than the first hold potential. Image sensor.

18. 18. The imaging device according to claim 17, the holding unit transfers electric charges from the photoelectric conversion unit to the holding unit when the photoelectric conversion unit is at the first holding potential; Image sensor.

19. 18. The imaging device according to claim 17, a floating diffusion to which the charges converted by the photoelectric conversion unit are transferred; The floating diffusion transfers the charges converted by the photoelectric conversion unit via the holding unit. Image sensor.

20. 20. The imaging device according to claim 19, When the holding unit is at the first holding potential, charges are transferred from the holding unit to the floating diffusion. Image sensor.

21. 20. The imaging device according to claim 19, When the holding unit is at the second holding potential, charges are transferred from the floating diffusion to the holding unit. Image sensor.

22. 20. The imaging device according to claim 19, the first holding potential is lower than the potential of the floating diffusion; Image sensor.

23. 20. The imaging device according to claim 19, the second holding potential is higher than the potential of the floating diffusion; Image sensor.

24. 10. The imaging device according to claim 9, the second transfer unit is supplied with a first transfer voltage signal that controls the potential of the second transfer unit, and a second transfer voltage signal that controls the potential of the second transfer unit and has a higher voltage than the first transfer voltage signal. Image sensor.

25. 25. The imaging device according to claim 24, an imaging element including a voltage signal supply line that supplies the first transfer voltage signal and the second transfer voltage signal to the second transfer unit;

26. 25. The imaging device according to claim 24, When the first transfer voltage signal is supplied to the second transfer section, the potential of the second transfer section becomes a first transfer potential, and when the second transfer voltage signal is supplied to the second transfer section, the potential of the second transfer section becomes a second transfer potential higher than the first transfer potential. Image sensor.

27. 27. The imaging device according to claim 26, the second transfer unit transfers charges from the holding unit to the floating diffusion when at the first transfer potential; Image sensor.

28. 27. The imaging device according to claim 26, the second transfer unit transfers charges from the floating diffusion to the holding unit when at the second transfer potential; Image sensor.

29. 27. The imaging device according to claim 26, the first transfer potential is lower than the potential of the floating diffusion; Image sensor.

30. 27. The imaging device according to claim 26, the second transfer potential is higher than the potential of the floating diffusion; Image sensor.

31. 27. The imaging device according to claim 26, The holding unit is supplied with a first holding voltage signal that sets the potential of the holding unit to a first holding potential, and a second holding voltage signal that sets the potential of the holding unit to a second holding potential and has a higher voltage than the first holding voltage signal. Image sensor.

32. 32. The imaging device according to claim 31, a first voltage signal supply line that supplies the first hold voltage signal and the second hold voltage signal to the holding unit; a second voltage signal supply line that supplies the first transfer voltage signal and the second transfer voltage signal to the second transfer unit; An imaging element comprising:

33. 32. The imaging device according to claim 31, When the holding unit is at the first holding potential and the second transfer unit is at the first transfer potential, charges are transferred from the holding unit to the floating diffusion. Image sensor.

34. 32. The imaging device according to claim 31, When the holding unit is at the second holding potential and the second transfer unit is at the second transfer potential, charges are transferred from the floating diffusion to the holding unit. Image sensor.

35. 32. The imaging device according to claim 31, the first transfer potential is higher than the first holding potential and lower than the potential of the floating diffusion; Image sensor.

36. 32. The imaging device according to claim 31, the second transfer potential is higher than the potential of the floating diffusion and lower than the second holding potential; Image sensor.

37. 2. The imaging device according to claim 1, the output unit includes an amplifier unit that outputs a signal based on the charge converted by the photoelectric conversion unit. Image sensor.

38. 38. The imaging device according to claim 37, the output unit includes a selection unit that controls a connection between the amplification unit and a signal line through which a signal based on the charge converted by the photoelectric conversion unit is output. Image sensor.

39. 2. The imaging device according to claim 1, the first signal is used for image display; Image sensor.

40. 2. The imaging device according to claim 1, the first signal is used to generate a live view image; Image sensor.

41. a photoelectric conversion unit that converts light into an electric charge; a first output unit that outputs a first signal generated based on the charges converted by the photoelectric conversion unit and transferred from the photoelectric conversion unit during a first period; a second output section that outputs a second signal generated based on the charges used to generate the first signal and the charges converted by the photoelectric conversion section in a second period that is later than the first period; An imaging element comprising:

42. 42. The imaging device according to claim 41, an imaging element including a first holding unit that holds the charge used to generate the first signal and the charge converted by the photoelectric conversion unit during the second period;

43. 43. The imaging device according to claim 42, the first holding unit holds the charge used to generate the first signal while the photoelectric conversion unit converts light into charge during the second period. Image sensor.

44. 43. The imaging device according to claim 42, the first holding unit transfers charges from the photoelectric conversion unit in a first direction and a second direction different from the first direction; Image sensor.

45. 45. The imaging device according to claim 44, a second holding unit to which the charges converted by the photoelectric conversion unit are transferred; The second direction is a direction in which charges are transferred from the second holding unit to the first holding unit. Image sensor.

46. 43. The imaging device according to claim 42, a second holding unit to which the charges converted by the photoelectric conversion unit are transferred; the first holding unit holds the charges converted by the photoelectric conversion unit and transferred from the second holding unit; Image sensor.

47. 47. The imaging device according to claim 46, the first holding unit holds the charges transferred from the second holding unit to the first holding unit after the charges converted by the photoelectric conversion unit during the first period are transferred from the first holding unit to the second holding unit, and the charges converted by the photoelectric conversion unit during the second period. Image sensor.

48. 47. The imaging device according to claim 46, An imaging element including a floating diffusion to which the charges converted by the photoelectric conversion unit are transferred.

49. 49. The imaging device according to claim 48, the floating diffusion transfers charges used for the first signal and charges converted by the photoelectric conversion unit in the second period; Image sensor.

50. 49. The imaging device according to claim 48, the first output unit outputs a signal based on the charge transferred to the second holding unit; the second output section outputs a signal based on the charge transferred to the floating diffusion. Image sensor.

51. 49. The imaging device according to claim 48, a first transfer unit that transfers the charges converted by the photoelectric conversion unit to the first holding unit; a second transfer unit that transfers the charges held in the first holding unit to the second holding unit; a third transfer unit that transfers the charges held in the first holding unit to the floating diffusion; An imaging element comprising:

52. 52. The imaging device according to claim 51, the second transfer unit transfers the charges transferred to the second holding unit to the first holding unit; Image sensor.

53. 52. The imaging device according to claim 51, the second transfer unit transfers the charges held in the first holding unit to the second holding unit, and then transfers the charges transferred to the second holding unit to the first holding unit; Image sensor.

54. 52. The imaging device according to claim 51, the third transfer unit transfers the charges held in the first holding unit to the floating diffusion after the charges held in the second holding unit are transferred to the first holding unit by the second transfer unit; Image sensor.

55. 43. The imaging device according to claim 42, the first holding unit is supplied with a first holding voltage signal that controls the potential of the first holding unit, and a second holding voltage signal that controls the potential of the first holding unit and has a higher voltage than the first holding voltage signal; Image sensor.

56. 56. The imaging device according to claim 55, an imaging element including a voltage signal supply line that supplies the first hold voltage signal and the second hold voltage signal to the first holding unit;

57. 56. The imaging device according to claim 55, When the first hold voltage signal is supplied to the first holding unit, the potential of the first holding unit becomes a first hold potential, and when the second hold voltage signal is supplied to the first holding unit, the potential of the first holding unit becomes a second hold potential higher than the first hold potential. Image sensor.

58. 58. The imaging device according to claim 57, When the first holding unit is at the first holding potential, charges are transferred from the photoelectric conversion unit to the first holding unit. Image sensor.

59. 58. The imaging device according to claim 57, a second holding unit to which the charges converted by the photoelectric conversion unit are transferred; The second holding unit transfers the charges converted by the photoelectric conversion unit via the first holding unit. Image sensor.

60. 60. The imaging device according to claim 59, When the first holding unit is at the first holding potential, charge is transferred from the first holding unit to the second holding unit. Image sensor.

61. 60. The imaging device according to claim 59, When the first holding unit is at the second holding potential, charges are transferred from the second holding unit to the first holding unit. Image sensor.

62. 60. The imaging device according to claim 59, the first holding potential is lower than the potential of the second holding unit; Image sensor.

63. 60. The imaging device according to claim 59, the second holding potential is higher than the potential of the second holding unit; Image sensor.

64. 52. The imaging device according to claim 51, the second transfer unit is supplied with a first transfer voltage signal that controls the potential of the second transfer unit, and a second transfer voltage signal that controls the potential of the second transfer unit and has a higher voltage than the first transfer voltage signal. Image sensor.

65. 65. The imaging device according to claim 64, an imaging element including a voltage signal supply line that supplies the first transfer voltage signal and the second transfer voltage signal to the second transfer unit;

66. 65. The imaging device according to claim 64, When the first transfer voltage signal is supplied to the second transfer section, the potential of the second transfer section becomes a first transfer potential, and when the second transfer voltage signal is supplied to the second transfer section, the potential of the second transfer section becomes a second transfer potential higher than the first transfer potential. Image sensor.

67. 67. The imaging device according to claim 66, the second transfer unit transfers charges from the first holding unit to the second holding unit when at the first transfer potential; Image sensor.

68. 67. The imaging device according to claim 66, the second transfer unit transfers charges from the second holding unit to the first holding unit when at the second transfer potential; Image sensor.

69. 67. The imaging device according to claim 66, the first transfer potential is lower than the potential of the second holding unit; Image sensor.

70. 67. The imaging device according to claim 66, the second transfer potential is higher than the potential of the second holding unit; Image sensor.

71. 67. The imaging device according to claim 66, the first holding unit is supplied with a first holding voltage signal that sets the potential of the first holding unit to a first holding potential, and a second holding voltage signal that sets the potential of the first holding unit to a second holding potential and is higher than the first holding voltage signal; Image sensor.

72. 72. The imaging device according to claim 71, a first voltage signal supply line that supplies the first hold voltage signal and the second hold voltage signal to the first holding unit; a second voltage signal supply line that supplies the first transfer voltage signal and the second transfer voltage signal to the second transfer unit; An imaging element comprising:

73. 72. The imaging device according to claim 71, When the first holding unit is at a first holding potential and the second transfer unit is at the first transfer potential, charges are transferred from the first holding unit to the second holding unit. Image sensor.

74. 72. The imaging device according to claim 71, When the first holding unit is at the second holding potential and the second transfer unit is at the second transfer potential, charges are transferred from the second holding unit to the first holding unit. Image sensor.

75. 72. The imaging device according to claim 71, the first transfer potential is higher than the first holding potential and lower than the potential of the second holding unit; Image sensor.

76. 72. The imaging device according to claim 71, the second transfer potential is higher than the potential of the second holding unit and lower than the second holding potential; Image sensor.

77. 42. The imaging device according to claim 41, the first output unit includes a first amplifier unit that outputs a signal based on the charge converted by the photoelectric conversion unit, the second output unit includes a second amplifier unit that outputs a signal based on the charge converted by the photoelectric conversion unit; Image sensor.

78. 78. The imaging device according to claim 77, the first output unit includes a first selection unit that controls a connection between the first amplification unit and a signal line to which a signal based on the charge converted by the photoelectric conversion unit is output, the second output unit includes a second selection unit that controls a connection between the second amplification unit and the signal line; Image sensor.

79. 42. The imaging device according to claim 41, the first signal is used for image display; Image sensor.

80. 42. The imaging device according to claim 41, the first signal is used to generate a live view image; Image sensor.

81. 46. ​​The imaging device according to claim 45, The second holding unit is a floating gate that does not require resetting. Image sensor.

82. An imaging device comprising the imaging element according to any one of claims 1 to 81.

83. 83. The imaging device of claim 82, An imaging device including a display unit that displays an image based on the first signal and an image based on the second signal.

Images