Reverse Conducting IGBT

Abstract

To provide a technique to suppress the increase of switching losses in a reverse-conduction IGBT with a boundary region between the IGBT region and the diode region.SOLUTION: A semiconductor substrate 10 of the reverse-conduction IGBTs 1,2,3 is provided in the boundary region 106 and has a first conductive type boundary layer 18 of the first conductive type located below a drift layer 13 and in contact with a bottom electrode 22, and a second conductive type boundary layer 19 of the second conductive type provided in the boundary region 106 and located between the first conductive type boundary layer 18 and the drift layer 13.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present specification relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] A type of semiconductor device called a reverse conducting insulated gate bipolar transistor (IGBT) is being developed. A semiconductor substrate of this type of semiconductor device has an IGBT region in which an IGBT structure is provided, and a diode region in which a diode structure is provided. The diode structure is connected in antiparallel to the IGBT structure, and can operate as a freewheeling diode during recovery operation.

[0003] In this type of semiconductor device, holes are injected obliquely from the p-type base layer of the IGBT region toward the n-type cathode layer of the diode region during recovery operation. When the amount of holes injected obliquely from the p-type base layer toward the n-type cathode layer increases, the recovery current increases and the recovery loss increases. For this reason, as disclosed in Patent Document 1, in this type of semiconductor device, a boundary region may be provided between the IGBT region and the diode region. In the boundary region, a p-type collector layer is formed extending from the IGBT region. As a result, a diode structure is not formed in the boundary region, and the amount of holes injected obliquely from the p-type base layer toward the n-type cathode layer during recovery operation is suppressed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2022-15194 Summary of the Invention [Problem to be solved by the invention]

[0005] If a p-type collector layer is provided in the boundary region, holes are injected from the p-type collector layer in the boundary region toward the n-type drift layer in the boundary region when the IGBT structure is on. The holes injected into the drift layer in the boundary region move diagonally toward the p-type base layer in the IGBT region when the IGBT structure is turned off, and are discharged through the p-type base layer. This increases the time it takes for the holes to be discharged, and there is a concern that the tail current will increase, resulting in increased switching losses.

[0006] The present specification provides a technique for suppressing an increase in switching loss in a reverse conducting IGBT having a boundary region between an IGBT region and a diode region. [Means for solving the problem]

[0007] The semiconductor device (1, 2, 3) disclosed in this specification is a type of semiconductor device called a reverse conducting IGBT, and may include a semiconductor substrate (10) having an IGBT region (102), a diode region (104), and a boundary region (106) located between the IGBT region and the diode region, a lower electrode (22) provided on a lower surface of the semiconductor substrate, and an upper electrode (24) provided on an upper surface of the semiconductor substrate. The semiconductor substrate includes a first conductivity type drift layer (13) provided across the IGBT region, the diode region, and the boundary region, a second conductivity type base layer (14) provided across the IGBT region, the diode region, and the boundary region and disposed above the drift layer, a first conductivity type emitter layer (15) provided in the IGBT region, disposed above the base layer, and in contact with the upper electrode, and a second conductivity type emitter layer (16) provided in the IGBT region and disposed below the drift layer, The semiconductor device may have a collector layer (11) of a second conductivity type in contact with the lower electrode, a cathode layer (17) of a first conductivity type provided in the diode region, disposed below the drift layer, and in contact with the lower electrode, a first conductivity type boundary layer (18) of a first conductivity type provided in the boundary region, disposed below the drift layer, and in contact with the lower electrode, and a second conductivity type boundary layer (19) of a second conductivity type provided in the boundary region and disposed between the first conductivity type boundary layer and the drift layer. Here, "disposed above" and "disposed below" specify only the positional relationship between the two semiconductor layers in the vertical direction of the semiconductor substrate, and for example, the two semiconductor layers may be disposed so as to be in contact with each other, or another semiconductor layer may be interposed between the two semiconductor layers.

[0008] In the above reverse conducting IGBT, the first conductivity type boundary layer and the second conductivity type boundary layer are provided in a lower layer portion of the boundary region of the semiconductor substrate. Since the second conductivity type boundary layer is provided in the boundary region, the amount of carriers injected in an oblique direction from the base layer of the IGBT region toward the cathode layer of the diode region during recovery operation is suppressed. Furthermore, since the first conductivity type boundary layer is provided in the boundary region, the amount of carriers injected into the drift layer of the boundary region when the IGBT structure of the IGBT region is on is suppressed. Therefore, in the above reverse conducting IGBT, an increase in switching loss is suppressed.

[0009] This specification discloses a method for manufacturing a reverse conducting IGBT (1, 2, 3) including a semiconductor substrate (10) having an IGBT region (102), a diode region (104), and a boundary region (106) located between the IGBT region and the diode region. The manufacturing method may include a first ion implantation step of ion implanting a second conductive type impurity into a lower portion of the semiconductor substrate corresponding to the IGBT region and the boundary region, and a second ion implantation step of ion implanting a first conductive type impurity into a lower portion of the semiconductor substrate corresponding to the diode region and the boundary region. The second conductive type impurity ion implanted in the first ion implantation step and the first conductive type impurity ion implanted in the second ion implantation step may be adjusted such that the concentration of the first conductive type impurity is higher than the concentration of the second conductive type impurity on a side closer to a lower surface of the semiconductor substrate, and the concentration of the second conductive type impurity is higher than the concentration of the first conductive type impurity on a side farther from the lower surface of the semiconductor substrate.

[0010] According to the above manufacturing method, by using two masks, that is, the first mask and the second mask, a collector layer containing a second conductivity type impurity can be formed in the IGBT region of the semiconductor substrate, a collector layer containing a first conductivity type impurity can be formed in the diode region of the semiconductor substrate, a first conductivity type boundary layer can be formed in the boundary region of the semiconductor substrate closer to the bottom surface, and a second conductivity type boundary layer can be formed in the boundary region of the semiconductor substrate farther from the bottom surface. The above manufacturing method can form a number of layers that is greater than the number of masks. [Brief description of the drawings]

[0011] [Figure 1] FIG. 2 is a plan view of the semiconductor device of the present embodiment, and is a schematic plan view for explaining the layout of an IGBT region, a diode region, and a boundary region. [Diagram 2] 2 is a cross-sectional view of a main portion including an IGBT region, a diode region, and a boundary region partitioned into an element region of the semiconductor device of the present embodiment, the cross-sectional view being taken along a position corresponding to line II-II in FIG. 1. [Diagram 3] 1 shows a flow of steps for forming a collector layer, a cathode layer, an n-type boundary layer, and a p-type boundary layer in the method for manufacturing a semiconductor device of this embodiment. [Figure 4] 2 is a cross-sectional view of a main portion including an IGBT region, a diode region, and a boundary region partitioned into an element region of a modified example of the semiconductor device of the present embodiment, the cross-sectional view being taken along a position corresponding to line II-II in FIG. [Diagram 5] 2 is a cross-sectional view of a main portion including an IGBT region, a diode region, and a boundary region partitioned into an element region of a modified example of the semiconductor device of the present embodiment, the cross-sectional view being taken along a position corresponding to line II-II in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the semiconductor device of the present embodiment will be described with reference to the drawings. For the purpose of clarity of illustration, when components are repeatedly arranged, only one of the components is designated by a reference symbol, and the other components are not designated by a reference symbol.

[0013] FIG. 1 is a schematic plan view of a semiconductor device 1 according to the present embodiment. The semiconductor device 1 is a type of semiconductor device called a reverse conducting IGBT, and is manufactured using a semiconductor substrate 10. The semiconductor substrate 10 has an element region 10A and a termination region 10B located around the element region 10A. The element region 10A of the semiconductor substrate 10 is partitioned into an IGBT region 102 having an IGBT structure, a diode region 104 having a diode structure, and a boundary region 106 located between the IGBT region 102 and the diode region 104. When viewed from a direction perpendicular to the upper surface of the semiconductor substrate 10 (hereinafter referred to as "when the semiconductor substrate 10 is viewed in plan"), the IGBT region 102 and the diode region 104 are alternately and repeatedly arranged in the element region 10A along the y direction. A termination breakdown structure such as a guard ring is formed within a range of the semiconductor substrate 10 corresponding to the termination region 10B. Furthermore, a plurality of small signal pads 26 are provided within a range of the upper surface of the semiconductor substrate 10 corresponding to the termination region 10B. The small signal pads 26 may be, for example, a gate pad for inputting a gate signal, a temperature sense pad for outputting a temperature sense signal, and a current sense pad for outputting a current sense signal.

[0014] Fig. 2 is a schematic cross-sectional view of a main part corresponding to the line II-II in Fig. 1. As shown in Fig. 2, the semiconductor device 1 includes a semiconductor substrate 10 which is a silicon substrate, a collector electrode 22 (an example of a lower electrode) provided so as to cover the lower surface of the semiconductor substrate 10, an emitter electrode 24 (an example of an upper electrode) provided so as to cover the upper surface of the semiconductor substrate 10, a plurality of trench gates 30 provided in an upper layer portion of the semiconductor substrate 10, and a plurality of dummy trench gates 40 provided in the upper layer portion of the semiconductor substrate 10.

[0015] The semiconductor substrate 10 includes a p-type collector layer 11, an n-type buffer layer 12, and a n - A p-type drift layer 13, a p-type base layer 14, and a plurality of n + A type emitter layer 15 and a plurality of p+ A contact layer 16 of n-type + The n-type boundary layer 18 has a cathode layer 17 for n-type, an n-type boundary layer 18 for n-type, and a p-type boundary layer 19 for p-type.

[0016] The collector layer 11 is provided in a range corresponding to the IGBT region 102 in the lower layer portion of the semiconductor substrate 10, and is provided at a position exposed on the lower surface of the semiconductor substrate 10. The collector layer 11 is in ohmic contact with a collector electrode 22 covering the lower surface of the semiconductor substrate 10. The collector layer 11 is formed by ion implanting p-type impurities toward the lower surface of the semiconductor substrate 10 using ion implantation technology. The collector layer 11 is formed by multi-stage ion implantation, and may have multiple peak concentrations in the thickness direction of the semiconductor substrate 10. The p-type impurity is not particularly limited, but may be, for example, boron. The peak concentration of the p-type impurity contained in the collector layer 11 is not particularly limited, but may be, for example, 1×10 16 cm -3 ~1×10 18 cm -3 may be also possible.

[0017] The buffer layer 12 is provided over the entire IGBT region 102, boundary region 106, and diode region 104 of the semiconductor substrate 10. The buffer layer 12 is provided between the collector layer 11 and the drift layer 13 in the IGBT region 102, separating the collector layer 11 and the drift layer 13, with a lower surface in contact with the collector layer 11 and an upper surface in contact with the drift layer 13. The buffer layer 12 is provided between the p-type boundary layer 19 and the drift layer 13 in the boundary region 106, separating the p-type boundary layer 19 and the drift layer 13, with a lower surface in contact with the p-type boundary layer 19 and an upper surface in contact with the drift layer 13. The buffer layer 12 is provided between the cathode layer 17 and the drift layer 13 in the diode region 104, separating the cathode layer 17 from the drift layer 13, with its lower surface in contact with the cathode layer 17 and its upper surface in contact with the drift layer 13. The buffer layer 12 is a layer having a higher concentration of n-type impurities than the drift layer 13. The buffer layer 12 is formed by ion implanting n-type impurities toward the lower surface of the semiconductor substrate 10 using an ion implantation technique. The n-type impurity is not particularly limited, but may be, for example, phosphorus. The peak concentration of the n-type impurity contained in the buffer layer 12 is not particularly limited, but may be, for example, 1×10 15 cm -3 ~1×10 18 cm -3 may be also possible.

[0018] The drift layer 13 is provided across the IGBT region 102, boundary region 106, and diode region 104 of the semiconductor substrate 10. The drift layer 13 is provided between the buffer layer 12 and the base layer 14, separating the buffer layer 12 from the base layer 14, with a lower surface in contact with the buffer layer 12 and an upper surface in contact with the base layer 14. The drift layer 13 is a remnant of other semiconductor layers formed within the semiconductor substrate 10. The peak concentration of n-type impurities contained in the drift layer 13 is not particularly limited, but may be, for example, 1×10 13 cm -3 ~1×10 15 cm -3 may be also possible.

[0019] The base layer 14 is provided over the entire IGBT region 102, boundary region 106, and diode region 104 of the semiconductor substrate 10. The base layer 14 is provided between the drift layer 13 and the emitter layer 15 and contact layer 16 in the IGBT region 102, separating the drift layer 13 from the emitter layer 15 and contact layer 16, with a lower surface in contact with the drift layer 13 and an upper surface in contact with the emitter layer 15 and contact layer 16. The base layer 14 is provided between the drift layer 13 and the contact layer 16 in the boundary region 106 and diode region 104, separating the drift layer 13 from the contact layer 16, with a lower surface in contact with the drift layer 13 and an upper surface in contact with the contact layer 16. The base layer 14 is formed by ion-implanting p-type impurities toward the upper surface of the semiconductor substrate 10 using an ion implantation technique. The p-type impurities are not particularly limited, and may be, for example, boron. The peak concentration of the p-type impurity contained in the base layer 14 is not particularly limited, but is, for example, 1×10 15 cm -3 ~1×10 17 cm -3 may be also possible.

[0020] In this example, the base layer 14 further includes a first base layer 14a and a second base layer 14b. The first base layer 14a is a portion of the base layer 14 provided in a range corresponding to the IGBT region 102 of the semiconductor substrate 10. The second base layer 14b is a portion of the base layer 14 provided in a range corresponding to the diode region 104 and the boundary region 106 of the semiconductor substrate 10. The concentration of p-type impurities in the first base layer 14a is adjusted so that the gate threshold voltage of the trench gate 30 becomes a desired value. The concentration of p-type impurities in the second base layer 14b is adjusted to control the amount of holes injected during recovery operation. Therefore, the concentration of p-type impurities in the second base layer 14b is smaller than the concentration of p-type impurities in the first base layer 14a.

[0021] Each of the plurality of emitter layers 15 is partially provided in a range corresponding to the IGBT region 102 in the upper layer portion of the semiconductor substrate 10, and is provided at a position exposed on the upper surface of the semiconductor substrate 10. Each of the plurality of emitter layers 15 is in contact with the side surface of the corresponding trench gate 30, and is in ohmic contact with the emitter electrode 24 covering the upper surface of the semiconductor substrate 10. Each of the plurality of emitter layers 15 is selectively formed in the IGBT region 102 of the semiconductor substrate 10, and is not formed in the diode region 104 and the boundary region 106 of the semiconductor substrate 10. In other words, the range of the semiconductor substrate 10 in which the plurality of emitter layers 15 are provided is the IGBT region 102. Each of the plurality of emitter layers 15 is formed by ion implanting n-type impurities toward the upper surface of the semiconductor substrate 10 using an ion implantation technique. The n-type impurity is not particularly limited, but may be, for example, phosphorus. The peak concentration of the n-type impurity contained in each of the plurality of emitter layers 15 is not particularly limited, but may be, for example, 1×10 18 cm -3 ~1×10 20 cm -3 In the technology disclosed in this specification, the layout of the multiple emitter layers 15 formed in the upper layer portion of the semiconductor substrate 10 is not particularly limited, and various layouts can be adopted.

[0022] Each of the multiple contact layers 16 is partially provided across the IGBT region 102, boundary region 106, and diode region 104 of the semiconductor substrate 10, and is provided at a position exposed on the upper surface of the semiconductor substrate 10. Each of the multiple contact layers 16 is in ohmic contact with the emitter electrode 24 covering the upper surface of the semiconductor substrate 10. Each of the multiple contact layers 16 is formed by ion-implanting p-type impurities toward the upper surface of the semiconductor substrate 10 using an ion implantation technique. The p-type impurity is not particularly limited, but may be, for example, boron. The peak concentration of the p-type impurity contained in each of the multiple contact layers 16 is not particularly limited, but may be, for example, 1×10 17 cm -3 ~1×10 20 cm-3 In the technology disclosed in this specification, the layout of the multiple contact layers 16 formed in the upper layer of the semiconductor substrate 10 is not particularly limited, and various layouts may be adopted.

[0023] The cathode layer 17 is provided in a range corresponding to the diode region 104 in the lower layer of the semiconductor substrate 10, and is provided at a position exposed on the lower surface of the semiconductor substrate 10. The cathode layer 17 is in ohmic contact with the collector electrode 22 covering the lower surface of the semiconductor substrate 10. The cathode layer 17 is selectively formed in the diode region 104 of the semiconductor substrate 10, and is not formed in the IGBT region 102 and the boundary region 106 of the semiconductor substrate 10. In other words, the range of the semiconductor substrate 10 where the cathode layer 17 is provided becomes the diode region 104. The cathode layer 17 is formed by ion implantation of n-type impurities toward the lower surface of the semiconductor substrate 10 using an ion implantation technique. The cathode layer 17 is formed by multi-stage ion implantation, and may have multiple peak concentrations in the thickness direction of the semiconductor substrate 10. The n-type impurity is not particularly limited, but may be, for example, phosphorus. The peak concentration of the n-type impurity contained in the cathode layer 17 is not particularly limited, but may be, for example, 1×10 18 cm -3 ~1×10 20 cm -3 may be also possible.

[0024] The n-type boundary layer 18 is provided in a range corresponding to the boundary region 106 in the lower layer of the semiconductor substrate 10, and is provided at a position exposed on the lower surface of the semiconductor substrate 10. The end of the n-type boundary layer 18 on the IGBT region 102 side is in contact with the collector layer 11, and the end on the diode region 104 side is in contact with the cathode layer 17. The n-type boundary layer 18 is provided between the collector electrode 22 and the p-type boundary layer 19, and separates the collector electrode 22 from the p-type boundary layer 19. The lower surface of the n-type boundary layer 18 is in contact with the collector electrode 22, and the upper surface of the n-type boundary layer 18 is in contact with the p-type boundary layer 19. The n-type boundary layer 18 is in ohmic contact with the collector electrode 22 that covers the lower surface of the semiconductor substrate 10. The n-type boundary layer 18 is formed by ion-implanting an n-type impurity toward the lower surface of the semiconductor substrate 10 using an ion implantation technique. The n-type impurity is not particularly limited, and may be, for example, phosphorus. The peak concentration of the n-type impurity contained in the n-type boundary layer 18 is not particularly limited, but is, for example, 1×10 18 cm -3 ~1×10 20 cm -3 may be also possible.

[0025] The p-type boundary layer 19 is provided in a range corresponding to the boundary region 106 in the lower layer of the semiconductor substrate 10. The end of the p-type boundary layer 19 on the IGBT region 102 side is in contact with the collector layer 11, and the end on the diode region 104 side is in contact with the cathode layer 17. The p-type boundary layer 19 is provided between the n-type boundary layer 18 and the buffer layer 12, and separates the n-type boundary layer 18 from the buffer layer 12. The lower surface of the p-type boundary layer 19 is in contact with the n-type boundary layer 18, and the upper surface of the p-type boundary layer 19 is in contact with the buffer layer 12. The p-type boundary layer 19 is formed by ion-implanting a p-type impurity toward the lower surface of the semiconductor substrate 10 using an ion implantation technique. The p-type impurity is not particularly limited, but may be, for example, boron. The peak concentration of the p-type impurity contained in the p-type boundary layer 19 is not particularly limited, but may be, for example, 1×10 16 cm -3 ~1×10 18 cm -3 may be also possible.

[0026] Each of the trench gates 30 is provided in a trench formed in a range corresponding to the IGBT region 102 in the upper layer of the semiconductor substrate 10, and has a gate electrode 32 and a gate insulating film 34. The gate electrode 32 is insulated from the semiconductor substrate 10 by the gate insulating film 34, and is insulated from the emitter electrode 24 by the interlayer insulating film. Each of the trench gates 30 penetrates the base layer 14 from the upper surface of the semiconductor substrate 10 to reach the drift layer 13. In this example, each of the trench gates 30 extends along the x direction when the semiconductor substrate 10 is viewed in a plan view, and is spaced apart from one another in the y direction. That is, the trench gates 30 are spaced apart from one another along the direction in which the IGBT region 102 and the diode region 104 are repeatedly arranged when the semiconductor substrate 10 is viewed in a plan view, and have a striped layout. Instead of this example, the trench gates 30 may have other types of layouts.

[0027] Each of the multiple dummy trench gates 40 is provided in a trench formed in an area corresponding to the diode region 104 and the boundary region 106 in the upper layer portion of the semiconductor substrate 10. The multiple dummy trench gates 40 are fabricated in the same manufacturing process as the multiple trench gates 30, and differ from the trench gate 30 in that the interlayer insulating film insulating the gate electrode 32 and the emitter electrode 24 is removed. The multiple dummy trench gates 40 have the same layout as the multiple trench gates 30. When such a dummy trench gate 40 is provided, electric field concentration in the diode region 104 and the boundary region 106 can be alleviated.

[0028] The semiconductor device 1 can control the on / off of a current flowing through the IGBT region 102 from the collector electrode 22 to the emitter electrode 24 based on a gate voltage applied to the gate electrode 32 of the trench gate 30. Furthermore, in the semiconductor device 1, the diode structure formed in the diode region 104 can operate as a freewheeling diode during recovery operation.

[0029] During recovery operation in which the diode structure operates, if the number of holes injected obliquely from the p-type base layer 14 of the IGBT region 102 toward the n-type cathode layer 17 of the diode region 104 increases, the recovery current increases and the recovery loss increases. In the semiconductor device 1, the p-type boundary layer 19 is provided in the boundary region 106, so the distance between the p-type base layer 14 of the IGBT region 102 and the n-type cathode layer 17 of the diode region 104 becomes longer. Therefore, the number of holes injected obliquely during recovery operation is suppressed, and the recovery current is suppressed. Therefore, the semiconductor device 1 can have low recovery loss characteristics.

[0030] The width of the boundary region 106 measured along the direction connecting the IGBT region 102 and the diode region 104 is adjusted to a size necessary to suppress the amount of holes injected in an oblique direction. The width of the boundary region 106 is not particularly limited, but may be, for example, 0.5 μm or more, preferably 1.0 μm or more. The width of the boundary region 106 may be larger than the width between adjacent dummy trench gates 40 (i.e., the pitch width of the dummy trench gates 40). Alternatively, the width of the boundary region 106 may be larger than the substrate thickness of the semiconductor substrate 10. The width of the boundary region 106 may be smaller than twice the substrate thickness of the semiconductor substrate 10 in order to suppress area consumption.

[0031] Here, consider a case where the n-type boundary layer 18 is not provided in the boundary region 106, and only the p-type boundary layer 19 is provided. In this case, when the IGBT structure is on, holes are injected from the p-type boundary layer 19 in the boundary region 106 toward the n-type drift layer 13 in the boundary region 106. When the IGBT structure is turned off, the holes injected into the drift layer 13 move in an oblique direction toward the p-type base layer 14 in the IGBT region 102, and are discharged through the p-type base layer 14. For this reason, it takes longer for the holes to be discharged, and the switching loss increases due to an increase in the tail current.

[0032] In the semiconductor device 1, an n-type boundary layer 18 is provided in the boundary region 106. The n-type boundary layer 18 is provided between the collector electrode 22 and the p-type boundary layer 19, and separates the collector electrode 22 from the p-type boundary layer 19. Therefore, when the IGBT structure is on, the amount of holes injected from the p-type boundary layer 19 in the boundary region 106 toward the n-type drift layer 13 is suppressed. Therefore, the semiconductor device 1 can have low switching loss characteristics.

[0033] 3, the steps of forming the collector layer 11, the cathode layer 17, the n-type boundary layer 18, and the p-type boundary layer 19 in the method for manufacturing the semiconductor device 1 will be described. For the steps in the method for manufacturing the semiconductor device 1 other than the steps described below, known steps can be used.

[0034] First, a first mask is formed by photolithography on the lower surface of the semiconductor substrate 10 (see step S1). The first mask covers the diode region 104 on the lower surface of the semiconductor substrate 10 and has openings to expose the IGBT region 102 and the boundary region 106.

[0035] Next, using an ion implantation technique, p-type impurities are ion-implanted through the openings in the first mask into the lower portion of the semiconductor substrate 10 in an area corresponding to the IGBT region 102 and the boundary region 106 (see step S2). The p-type impurities are implanted to a first depth from the lower surface of the semiconductor substrate 10. The first mask is removed after the ion implantation.

[0036] Next, a second mask is formed on the lower surface of the semiconductor substrate 10 using photolithography (see step S3). The second mask covers the IGBT region 102 on the lower surface of the semiconductor substrate 10 and has openings to expose the diode region 104 and the boundary region 106.

[0037] Next, using an ion implantation technique, n-type impurities are ion-implanted through the openings in the second mask into the lower portion of the semiconductor substrate 10 in an area corresponding to the diode region 104 and the boundary region 106 (see step S4). The n-type impurities are implanted to a second depth from the lower surface of the semiconductor substrate 10. Here, comparing the first depth in step S2 with the second depth in step S4, the second depth is shallower than the first depth. The second mask is removed after the ion implantation.

[0038] Next, laser annealing is performed by irradiating the lower surface of the semiconductor substrate 10 with a laser (see step S5). This activates the p-type impurities and n-type impurities introduced into the lower layer of the semiconductor substrate 10. Through these steps, the collector layer 11, the cathode layer 17, the n-type boundary layer 18, and the p-type boundary layer 19 can be formed in the lower layer of the semiconductor substrate 10. Note that steps S1 and S2 may be performed after steps S3 and S4.

[0039] According to this manufacturing method, both n-type impurities and p-type impurities are implanted into the range corresponding to the boundary region 106 in the lower layer of the semiconductor substrate 10. The p-type impurities are implanted into a relatively deep first depth, and the n-type impurities are implanted into a relatively shallow second depth. The peak concentration of the p-type impurities at the first depth is greater than the concentration of the n-type impurities at the first depth. The peak concentration of the n-type impurities at the second depth is greater than the concentration of the p-type impurities at the second depth. Laser annealing can activate the implanted impurities without causing significant diffusion. Therefore, the n-type impurities and p-type impurities after activation can maintain the above concentration distribution. As a result, in the boundary region 106 of the semiconductor substrate 10, an n-type boundary layer 18 is formed on the side closer to the bottom surface of the semiconductor substrate 10, and a p-type boundary layer 19 is formed on the side farther from the bottom surface of the semiconductor substrate 10.

[0040] According to the above manufacturing method, by using two masks, a first mask and a second mask, a collector layer 11 containing p-type impurities can be formed in the IGBT region 102 of the semiconductor substrate 10, a cathode layer 17 containing n-type impurities can be formed in the diode region 104 of the semiconductor substrate 10, and a stack of an n-type boundary layer 18 and a p-type boundary layer 19 can be formed in the boundary region 106 of the semiconductor substrate 10. The above manufacturing method makes it possible to form a number of layers that is greater than the number of masks.

[0041] In the above manufacturing method, p-type impurities are ion-implanted simultaneously through a first mask into the IGBT region 102 and the boundary region 106 in the lower layer of the semiconductor substrate 10. Therefore, the distribution of p-type impurities in the thickness direction of the semiconductor substrate 10 is the same in the part where the n-type boundary layer 18 and the p-type boundary layer 19 are laminated and in the collector layer 11. Similarly, in the above manufacturing method, n-type impurities are ion-implanted simultaneously through a second mask into the diode region 104 and the boundary region 106 in the lower layer of the semiconductor substrate 10. Therefore, the distribution of n-type impurities in the thickness direction of the semiconductor substrate 10 is the same in the part where the n-type boundary layer 18 and the p-type boundary layer 19 are laminated and in the cathode layer 17. Such a concentration distribution is one feature of the application of the above manufacturing method.

[0042] In the above manufacturing method, n-type impurities and p-type impurities are injected into the boundary region 106 of the lower layer of the semiconductor substrate 10, and the part with a relatively high concentration of p-type impurities becomes the p-type boundary layer 19, and the part with a relatively high concentration of n-type impurities becomes the n-type boundary layer 18. Therefore, the effective peak concentration of n-type impurities in the n-type boundary layer 18 is smaller than the effective peak concentration of n-type impurities in the cathode layer 17. Similarly, the effective peak concentration of p-type impurities in the p-type boundary layer 19 is smaller than the effective peak concentration of p-type impurities in the collector layer 11. Such a relationship between the effective peak concentrations of impurities is one feature of the application of the above manufacturing method. In addition, in the above manufacturing method, the depth of the upper surface of the collector layer 11 coincides with the depth of the upper surface of the p-type boundary layer 19. Such a positional relationship is also one feature of the application of the above manufacturing method.

[0043] In the above manufacturing method, the p-type impurity and the n-type impurity are each introduced into the lower layer of the semiconductor substrate 10 by one ion implantation. Instead of this example, the p-type impurity and the n-type impurity may each be introduced into the lower layer of the semiconductor substrate 10 by multiple ion implantations, and the layer into which the p-type impurity is introduced and the layer into which the n-type impurity is introduced may each be formed as a multi-stage diffusion layer. In this case, the concentration of the p-type impurity may be adjusted to be higher than the concentration of the n-type impurity in the step farther from the lower surface of the semiconductor substrate 10 in the layer into which the p-type impurity is introduced, and the concentration of the n-type impurity may be adjusted to be higher than the concentration of the p-type impurity in the step closer to the lower surface of the semiconductor substrate 10 in the layer into which the n-type impurity is introduced. This manufacturing method also allows the stack of the n-type boundary layer 18 and the p-type boundary layer 19 to be formed in the boundary region 106 of the semiconductor substrate 10.

[0044] The semiconductor device 1 described above can be modified as follows. In the semiconductor device 2 shown in FIG. 4, the lamination of the n-type boundary layer 18 and the p-type boundary layer 19 is formed by intruding into the IGBT region 102 side from the boundary between the IGBT region 102 and the boundary region 106. The length of the lamination of the n-type boundary layer 18 and the p-type boundary layer 19 extending from the boundary between the IGBT region 102 and the boundary region 106 to the IGBT region 102 side may be a length that allows for manufacturing variations. Similarly, the lamination of the n-type boundary layer 18 and the p-type boundary layer 19 may be formed by retreating from the boundary between the IGBT region 102 and the boundary region 106 to the boundary region 106 side. In either case, the semiconductor device 2 can achieve the same effects as the semiconductor device 1.

[0045] The semiconductor device 3 shown in FIG. 5 is characterized in that an n-type barrier layer 21 is provided in the semiconductor substrate 10. The barrier layer 21 is provided over the entire IGBT region 102, the boundary region 106, and the diode region 104 of the semiconductor substrate 10. The barrier layer 21 is provided buried in the base layer 14 and divides the base layer 14 into upper and lower parts. The barrier layer 21 is formed by ion-implanting n-type impurities toward the upper surface of the semiconductor substrate 10 using an ion implantation technique. The n-type impurity is not particularly limited, but may be, for example, phosphorus. The effective peak concentration of the n-type impurity in the barrier layer 21 may be smaller than the effective peak concentration of the p-type impurity in the second base layer 14b. When such a barrier layer 21 is provided, hole injection from the base layer 14 can be suppressed during recovery operation. Therefore, the semiconductor device 3 can have low recovery loss characteristics.

[0046] The features of the technology disclosed in this specification are summarized below. Note that the technical elements described below are independent technical elements that exhibit technical usefulness alone or in various combinations.

[0047] (Feature 1) A reverse conducting IGBT (1, 2, 3), a semiconductor substrate (10) having an IGBT region (102), a diode region (104), and a boundary region (106) located between the IGBT region and the diode region; a lower electrode (22) provided on the lower surface of the semiconductor substrate; and an upper electrode (24) provided on an upper surface of the semiconductor substrate, The semiconductor substrate is a drift layer (13) of a first conductivity type provided across the IGBT region, the diode region, and the boundary region; a second conductivity type base layer (14) provided across the IGBT region, the diode region, and the boundary region and disposed above the drift layer; a first conductivity type emitter layer (15) provided in the IGBT region, disposed above the base layer, and in contact with the upper electrode; a collector layer (11) of a second conductivity type provided in the IGBT region, disposed below the drift layer, and in contact with the lower electrode; a cathode layer (17) of a first conductivity type provided in the diode region, disposed below the drift layer, and in contact with the lower electrode; a first conductivity type boundary layer (18) of a first conductivity type provided in the boundary region, disposed below the drift layer, and in contact with the lower electrode; a second conductivity type boundary layer (19) of a second conductivity type provided in the boundary region and disposed between the first conductivity type boundary layer and the drift layer.

[0048] (Feature 2) a distribution of the first-conductivity-type impurity in a thickness direction of the semiconductor substrate is the same in a portion where the first-conductivity-type boundary layer and the second-conductivity-type boundary layer are stacked and in the cathode layer; 2. The reverse conducting IGBT according to feature 1, wherein a distribution of the second conductive type impurity in a thickness direction of the semiconductor substrate is the same in a portion where the first conductive type boundary layer and the second conductive type boundary layer are stacked and in the collector layer.

[0049] (Feature 3) The base layer is a first base layer (14a) provided in the IGBT region; a second base layer (14b) provided in the diode region and the boundary region, 3. The reverse conducting IGBT according to feature 1 or 2, wherein a concentration of the second conductive type impurity in the second base layer is lower than a concentration of the second conductive type impurity in the first base layer.

[0050] (Feature 4) The semiconductor substrate is The reverse conducting IGBT according to any one of Features 1 to 3, further comprising a barrier layer (21) of a first conductivity type provided across the IGBT region, the diode region, and the boundary region and embedded in the base layer.

[0051] (Feature 5) The semiconductor substrate is a buffer layer (12) of a first conductivity type provided across the IGBT region, the diode region, and the boundary region, and disposed between the drift layer and each of the collector layer, the cathode layer, and the second conductivity type boundary layer, 5. The reverse conducting IGBT according to any one of Features 1 to 4, wherein a concentration of the first conductivity type impurity in the buffer layer is higher than a concentration of the first conductivity type impurity in the drift layer.

[0052] (Feature 6) The reverse conducting IGBT according to any one of Features 1 to 5, further comprising a trench gate (30) provided in the IGBT region, the trench extending from an upper surface of the semiconductor substrate through the base layer to the drift layer.

[0053] (Feature 7) The reverse conducting IGBT according to any one of features 1 to 6, further comprising: a dummy trench gate (40) provided in the diode region and the boundary region, and in a trench extending from an upper surface of the semiconductor substrate through the base layer to the drift layer.

[0054] (Feature 8) A method for manufacturing a reverse conducting IGBT (1, 2, 3) comprising a semiconductor substrate (10) having an IGBT region (102), a diode region (104), and a boundary region (106) located between the IGBT region and the diode region, comprising the steps of: a first ion implantation step of ion-implanting a second conductive type impurity into a lower layer portion of the semiconductor substrate corresponding to the IGBT region and the boundary region; a second ion implantation step of ion-implanting a first conductive type impurity into a lower layer portion of the semiconductor substrate corresponding to the diode region and the boundary region, a second conductivity type impurity ion-implanted in the first ion implantation step and a first conductivity type impurity ion-implanted in the second ion implantation step are adjusted so that a concentration of the first conductivity type impurity is higher than a concentration of the second conductivity type impurity on a side closer to a bottom surface of the semiconductor substrate, and a concentration of the second conductivity type impurity is higher than a concentration of the first conductivity type impurity on a side farther from the bottom surface of the semiconductor substrate.

[0055] (Feature 9) In the first ion implantation step, a second conductivity type impurity is ion-implanted to a first depth from a lower surface of the semiconductor substrate, In the second ion implantation step, a first conductivity type impurity is ion-implanted to a second depth from a lower surface of the semiconductor substrate; 9. The method of claim 8, wherein the second depth is shallower than the first depth.

[0056] Although specific examples of the present invention have been described above in detail, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of the objectives itself has technical utility. [Explanation of symbols]

[0057] 10: semiconductor substrate, 11: collector layer, 12: buffer layer, 13: drift layer, 14: base layer, 14a: first base layer, 14b: second base layer, 15: emitter layer, 16: contact layer, 17: cathode layer, 18: n-type boundary layer, 19: p-type boundary layer, 22: collector electrode, 24: emitter electrode, 30: trench gate, 32: gate electrode, 34: gate insulating film, 40: dummy trench gate, 102: IGBT region, 104: diode region, 106: boundary region

Claims

1. A reverse conducting IGBT (1, 2, 3), a semiconductor substrate (10) having an IGBT region (102), a diode region (104), and a boundary region (106) located between the IGBT region and the diode region; A lower electrode (22) provided on the lower surface of the semiconductor substrate; and an upper electrode (24) provided on an upper surface of the semiconductor substrate, The semiconductor substrate is a drift layer (13) of a first conductivity type provided across the IGBT region, the diode region, and the boundary region; a second conductivity type base layer (14) provided across the IGBT region, the diode region, and the boundary region and disposed above the drift layer; a first conductive type emitter layer (15) provided in the IGBT region, disposed above the base layer, and in contact with the upper electrode; a collector layer (11) of a second conductivity type provided in the IGBT region, disposed below the drift layer, and in contact with the lower electrode; a cathode layer (17) of a first conductivity type provided in the diode region, disposed below the drift layer, and in contact with the lower electrode; a first conductivity type boundary layer (18) provided in the boundary region, disposed below the drift layer, and in contact with the lower electrode; a second conductivity type boundary layer (19) of a second conductivity type provided in the boundary region and disposed between the first conductivity type boundary layer and the drift layer, a distribution of the first conductivity type impurity in a thickness direction of the semiconductor substrate is the same in a portion where the first conductivity type boundary layer and the second conductivity type boundary layer are stacked and in the cathode layer; a distribution of the second conductivity type impurity in a thickness direction of the semiconductor substrate is the same in a portion where the first conductivity type boundary layer and the second conductivity type boundary layer are stacked and in the collector layer; The base layer is A first base layer (14a) provided in the IGBT region; a second base layer (14b) provided in the diode region and the boundary region, a second base layer having a lower concentration of second-conductivity-type impurities than a first base layer having a lower concentration of second-conductivity-type impurities;

2. The semiconductor substrate is 2. The reverse conducting IGBT according to claim 1, further comprising a barrier layer (21) of a first conductivity type provided across the IGBT region, the diode region and the boundary region and embedded in the base layer.

3. The semiconductor substrate is a buffer layer (12) of a first conductivity type provided across the IGBT region, the diode region, and the boundary region, and disposed between the drift layer and each of the collector layer, the cathode layer, and the second conductivity type boundary layer, 2. The reverse conducting IGBT according to claim 1, wherein a concentration of the first conductivity type impurity in said buffer layer is higher than a concentration of the first conductivity type impurity in said drift layer.

4. 2. The reverse conducting IGBT according to claim 1, further comprising a trench gate (30) provided in the IGBT region and in a trench extending from an upper surface of the semiconductor substrate through the base layer to the drift layer.

5. 2. The reverse conducting IGBT according to claim 1, further comprising a dummy trench gate (40) provided in the diode region and the boundary region, the dummy trench gate being provided in a trench extending from the upper surface of the semiconductor substrate through the base layer to reach the drift layer.

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