Reverse conducting IGBT and its manufacturing method

Abstract

To provide a technique to suppress the increase of switching losses in a reverse-conduction IGBT with a boundary region between the IGBT region and the diode region.SOLUTION: A semiconductor substrate 10 of the reverse-conduction IGBTs 1, 2 is provided in the IGBT region 102 and the boundary region 104 and has a p-type collector layer 11 in contact with a collector electrode 22. The collector layer 11 has a first collector layer 11a in the IGBT region 102 and a second collector layer 11b in the boundary region 104. The concentration of p-type impurities in the second collector layer 11b is lower than the concentration of p-type impurities in the first collector layer 11a.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present specification relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] A type of semiconductor device called a reverse conducting insulated gate bipolar transistor (IGBT) is being developed. A semiconductor substrate of this type of semiconductor device has an IGBT region in which an IGBT structure is provided, and a diode region in which a diode structure is provided. The diode structure is connected in antiparallel to the IGBT structure, and can operate as a freewheeling diode during recovery operation.

[0003] In this type of semiconductor device, holes are injected obliquely from the p-type base layer of the IGBT region toward the n-type cathode layer of the diode region during recovery operation. When the amount of holes injected obliquely from the p-type base layer toward the n-type cathode layer increases, the recovery current increases and the recovery loss increases. For this reason, as disclosed in Patent Document 1, in this type of semiconductor device, a boundary region may be provided between the IGBT region and the diode region. In the boundary region, a p-type collector layer is formed extending from the IGBT region. As a result, a diode structure is not formed in the boundary region, and the amount of holes injected obliquely from the p-type base layer toward the n-type cathode layer during recovery operation is suppressed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2022-15194 Summary of the Invention [Problem to be solved by the invention]

[0005] If a p-type collector layer is provided in the boundary region, holes are injected from the p-type collector layer in the boundary region toward the n-type drift layer in the boundary region when the IGBT structure is on. The holes injected into the drift layer in the boundary region move diagonally toward the p-type base layer in the IGBT region when the IGBT structure is turned off, and are discharged through the p-type base layer. This increases the time it takes for the holes to be discharged, and there is a concern that the tail current will increase, resulting in increased switching losses.

[0006] The present specification provides a technique for suppressing an increase in switching loss in a reverse conducting IGBT having a boundary region between an IGBT region and a diode region. [Means for solving the problem]

[0007] The semiconductor device (1, 2) disclosed in this specification is a type of semiconductor device called a reverse conducting IGBT, and may include a semiconductor substrate (10) having an IGBT region (102), a diode region (104), and a boundary region (106) located between the IGBT region and the diode region, a lower electrode (22) provided on a lower surface of the semiconductor substrate, and an upper electrode (24) provided on a upper surface of the semiconductor substrate. The semiconductor substrate may have a first conductivity type drift layer (13) provided across the IGBT region, the diode region, and the boundary region, a second conductivity type base layer (14) provided across the IGBT region, the diode region, and the boundary region and disposed above the drift layer, an emitter layer (15) of the first conductivity type provided in the IGBT region, disposed above the base layer, and in contact with the upper electrode, a collector layer (11) of the second conductivity type provided between the IGBT region and the boundary region, disposed below the drift layer, and in contact with the lower electrode, and a cathode layer (17) of the first conductivity type provided in the diode region, disposed below the drift layer, and in contact with the lower electrode. The collector layer may have a first collector layer (11a) provided in the IGBT region and a second collector layer (11b) provided in the boundary region. The second collector layer may have a lower concentration of the second conductive type impurity than the first collector layer. Here, "disposed above" and "disposed below" specify only the positional relationship between the two semiconductor layers in the vertical direction of the semiconductor substrate, and for example, the two semiconductor layers may be disposed in contact with each other, or another semiconductor layer may be interposed between the two semiconductor layers.

[0008] In the reverse conducting IGBT, the collector layer is provided in the boundary region of the semiconductor substrate, so that the amount of carriers injected in an oblique direction from the base layer of the IGBT region toward the cathode layer of the diode region during recovery operation is suppressed. Furthermore, in the reverse conducting IGBT, the concentration of the second conductive type impurity in the portion of the collector layer corresponding to the boundary region is adjusted to be low. In this way, since the second collector layer in which the concentration of the second conductive type impurity is adjusted to be low is provided in the boundary region, the amount of carriers injected into the drift layer in the boundary region is suppressed when the IGBT structure in the IGBT region is on. Therefore, in the reverse conducting IGBT, an increase in switching loss is suppressed.

[0009] This specification discloses a method for manufacturing a reverse conducting IGBT (1, 2) including a semiconductor substrate (10) having an IGBT region (102), a diode region (104), and a boundary region (106) located between the IGBT region and the diode region. The manufacturing method may include the steps of forming a mask on the underside of the semiconductor substrate, the mask covering the diode region and a portion of the boundary region on the underside of the semiconductor substrate and exposing another portion of the IGBT region and the boundary region, ion-implanting a dopant into the underside of the semiconductor substrate through an opening in the mask, and activating the dopant by annealing.

[0010] In the above manufacturing method, by utilizing the mask, a portion of the collector layer containing the dopant at a relatively high concentration can be formed in the IGBT region of the semiconductor substrate, and a portion of the collector layer containing the dopant at a relatively low concentration can be formed in the boundary region of the semiconductor substrate. [Brief description of the drawings]

[0011] [Figure 1] FIG. 2 is a plan view of the semiconductor device of the present embodiment, and is a schematic plan view for explaining the layout of an IGBT region, a diode region, and a boundary region. [Diagram 2]2 is a cross-sectional view of a main portion including an IGBT region, a diode region, and a boundary region partitioned into an element region of the semiconductor device of the present embodiment, the cross-sectional view being taken along a position corresponding to line II-II in FIG. 1. [Diagram 3] 1 shows a flow of a process for forming a collector layer and a cathode layer in the method for manufacturing a semiconductor device according to the present embodiment. [Figure 4] 1 shows an example of a mask pattern formed on the lower surface of a semiconductor substrate in an ion implantation step for forming a collector layer in the method for manufacturing a semiconductor device according to the present embodiment. [Diagram 5] 13 shows another example of a mask pattern formed on the lower surface of the semiconductor substrate in the ion implantation step for forming a collector layer in the method for manufacturing a semiconductor device according to the present embodiment. [Figure 6] 13 shows another example of a mask pattern formed on the lower surface of the semiconductor substrate in the ion implantation step for forming a collector layer in the method for manufacturing a semiconductor device according to the present embodiment. [Figure 7] FIG. 2 is a cross-sectional view of a main portion including an IGBT region, a diode region, and a boundary region partitioned into an element region of a modified example of the semiconductor device of the present embodiment, the cross-sectional view being taken along a position corresponding to line II-II in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the semiconductor device of the present embodiment will be described with reference to the drawings. For the purpose of clarity of illustration, when components are repeatedly arranged, only one of the components is designated by a reference symbol, and the other components are not designated by a reference symbol.

[0013] FIG. 1 is a schematic plan view of a semiconductor device 1 according to the present embodiment. The semiconductor device 1 is a type of semiconductor device called a reverse conducting IGBT, and is manufactured using a semiconductor substrate 10. The semiconductor substrate 10 has an element region 10A and a termination region 10B located around the element region 10A. The element region 10A of the semiconductor substrate 10 is partitioned into an IGBT region 102 having an IGBT structure, a diode region 104 having a diode structure, and a boundary region 106 located between the IGBT region 102 and the diode region 104. When viewed from a direction perpendicular to the upper surface of the semiconductor substrate 10 (hereinafter referred to as "when the semiconductor substrate 10 is viewed in plan"), the IGBT region 102 and the diode region 104 are alternately and repeatedly arranged in the element region 10A along the y direction. A termination breakdown structure such as a guard ring is formed within a range of the semiconductor substrate 10 corresponding to the termination region 10B. Furthermore, a plurality of small signal pads 26 are provided within a range of the upper surface of the semiconductor substrate 10 corresponding to the termination region 10B. The small signal pads 26 may be, for example, a gate pad for inputting a gate signal, a temperature sense pad for outputting a temperature sense signal, and a current sense pad for outputting a current sense signal.

[0014] Fig. 2 is a schematic cross-sectional view of a main part corresponding to the line II-II in Fig. 1. As shown in Fig. 2, the semiconductor device 1 includes a semiconductor substrate 10 which is a silicon substrate, a collector electrode 22 (an example of a lower electrode) provided so as to cover the lower surface of the semiconductor substrate 10, an emitter electrode 24 (an example of an upper electrode) provided so as to cover the upper surface of the semiconductor substrate 10, a plurality of trench gates 30 provided in an upper layer portion of the semiconductor substrate 10, and a plurality of dummy trench gates 40 provided in the upper layer portion of the semiconductor substrate 10.

[0015] The semiconductor substrate 10 includes a p-type collector layer 11, an n-type buffer layer 12, and a n - A p-type drift layer 13, a p-type base layer 14, and a plurality of n + A type emitter layer 15 and a plurality of p + A contact layer 16 of n-type +and a cathode layer 17 of the same type.

[0016] The collector layer 11 is provided in a range corresponding to the IGBT region 102 and the boundary region 106 in the lower layer of the semiconductor substrate 10, and is provided at a position exposed on the lower surface of the semiconductor substrate 10. The collector layer 11 is in ohmic contact with a collector electrode 22 covering the lower surface of the semiconductor substrate 10. The collector layer 11 is formed by ion implanting p-type impurities toward the lower surface of the semiconductor substrate 10 using an ion implantation technique. The collector layer 11 is formed by multi-stage ion implantation, and may have multiple peak concentrations in the thickness direction of the semiconductor substrate 10. The p-type impurity is not particularly limited, but may be, for example, boron. The peak concentration of the p-type impurity contained in the collector layer 11 is not particularly limited, but may be, for example, 1×10 16 cm -3 ~1×10 18 cm -3 may be also possible.

[0017] In this example, the collector layer 11 further includes a first collector layer 11a and a second collector layer 11b. The first collector layer 11a is a portion of the collector layer 11 provided in a range corresponding to the IGBT region 102 of the semiconductor substrate 10. The second collector layer 11b is a portion of the collector layer 11 provided in a range corresponding to the boundary region 106 of the semiconductor substrate 10. The concentration of p-type impurities in the second collector layer 11b is smaller than the concentration of p-type impurities in the first collector layer 11a. The concentration of p-type impurities in the second collector layer 11b may be constant in the surface direction of the semiconductor substrate 10. Alternatively, the concentration of p-type impurities in the second collector layer 11b may decrease from the boundary between the IGBT region 102 and the boundary region 106 toward the diode region 104. In this case, the concentration of p-type impurities in the second collector layer 11b may decrease continuously or in multiple steps. In this way, since the concentration of p-type impurities in the second collector layer 11b decreases from the boundary between the IGBT region 102 and boundary region 106 toward the diode region 104, a sudden change in the p-type impurity at the boundary between the IGBT region 102 and boundary region 106 is suppressed, and electric field concentration at the boundary between the IGBT region 102 and boundary region 106 is suppressed.

[0018] The buffer layer 12 is provided over the entire IGBT region 102, the boundary region 106, and the diode region 104 of the semiconductor substrate 10. The buffer layer 12 is provided between the collector layer 11 and the drift layer 13 in the IGBT region 102 and the boundary region 106, separating the collector layer 11 and the drift layer 13, with a lower surface in contact with the collector layer 11 and an upper surface in contact with the drift layer 13. The buffer layer 12 is provided between the cathode layer 17 and the drift layer 13 in the diode region 104, separating the cathode layer 17 and the drift layer 13, with a lower surface in contact with the cathode layer 17 and an upper surface in contact with the drift layer 13. The buffer layer 12 is a layer having a higher concentration of n-type impurities than the drift layer 13. The buffer layer 12 is formed by ion-implanting n-type impurities toward the lower surface of the semiconductor substrate 10 using an ion implantation technique. The n-type impurity is not particularly limited, but may be, for example, phosphorus. The peak concentration of the n-type impurity contained in the buffer layer 12 is not particularly limited, but may be, for example, 1×10 15 cm -3 ~1×10 18 cm -3 may be also possible.

[0019] The drift layer 13 is provided across the IGBT region 102, boundary region 106, and diode region 104 of the semiconductor substrate 10. The drift layer 13 is provided between the buffer layer 12 and the base layer 14, separating the buffer layer 12 from the base layer 14, with a lower surface in contact with the buffer layer 12 and an upper surface in contact with the base layer 14. The drift layer 13 is a remnant of other semiconductor layers formed within the semiconductor substrate 10. The peak concentration of n-type impurities contained in the drift layer 13 is not particularly limited, but may be, for example, 1×10 13 cm -3 ~1×10 15 cm -3 may be also possible.

[0020] The base layer 14 is provided over the entire IGBT region 102, boundary region 106, and diode region 104 of the semiconductor substrate 10. The base layer 14 is provided between the drift layer 13 and the emitter layer 15 and contact layer 16 in the IGBT region 102, separating the drift layer 13 from the emitter layer 15 and contact layer 16, with a lower surface in contact with the drift layer 13 and an upper surface in contact with the emitter layer 15 and contact layer 16. The base layer 14 is provided between the drift layer 13 and the contact layer 16 in the boundary region 106 and diode region 104, separating the drift layer 13 from the contact layer 16, with a lower surface in contact with the drift layer 13 and an upper surface in contact with the contact layer 16. The base layer 14 is formed by ion-implanting p-type impurities toward the upper surface of the semiconductor substrate 10 using an ion implantation technique. The p-type impurities are not particularly limited, and may be, for example, boron. The peak concentration of the p-type impurity contained in the base layer 14 is not particularly limited, but is, for example, 1×10 15 cm -3 ~1×10 17 cm -3 may be also possible.

[0021] In this example, the base layer 14 further includes a first base layer 14a and a second base layer 14b. The first base layer 14a is a portion of the base layer 14 provided in a range corresponding to the IGBT region 102 of the semiconductor substrate 10. The second base layer 14b is a portion of the base layer 14 provided in a range corresponding to the diode region 104 and the boundary region 106 of the semiconductor substrate 10. The concentration of p-type impurities in the first base layer 14a is adjusted so that the gate threshold voltage of the trench gate 30 becomes a desired value. The concentration of p-type impurities in the second base layer 14b is adjusted to control the amount of holes injected during recovery operation. Therefore, the concentration of p-type impurities in the second base layer 14b is smaller than the concentration of p-type impurities in the first base layer 14a.

[0022] Each of the plurality of emitter layers 15 is partially provided in a range corresponding to the IGBT region 102 in the upper layer portion of the semiconductor substrate 10, and is provided at a position exposed on the upper surface of the semiconductor substrate 10. Each of the plurality of emitter layers 15 is in contact with the side surface of the corresponding trench gate 30, and is in ohmic contact with the emitter electrode 24 covering the upper surface of the semiconductor substrate 10. Each of the plurality of emitter layers 15 is selectively formed in the IGBT region 102 of the semiconductor substrate 10, and is not formed in the diode region 104 and the boundary region 106 of the semiconductor substrate 10. In other words, the range of the semiconductor substrate 10 in which the plurality of emitter layers 15 are provided is the IGBT region 102. Each of the plurality of emitter layers 15 is formed by ion implanting n-type impurities toward the upper surface of the semiconductor substrate 10 using an ion implantation technique. The n-type impurity is not particularly limited, but may be, for example, phosphorus. The peak concentration of the n-type impurity contained in each of the plurality of emitter layers 15 is not particularly limited, but may be, for example, 1×10 18 cm -3 ~1×10 20 cm -3 In the technology disclosed in this specification, the layout of the multiple emitter layers 15 formed in the upper layer portion of the semiconductor substrate 10 is not particularly limited, and various layouts can be adopted.

[0023] Each of the multiple contact layers 16 is partially provided across the IGBT region 102, boundary region 106, and diode region 104 of the semiconductor substrate 10, and is provided at a position exposed on the upper surface of the semiconductor substrate 10. Each of the multiple contact layers 16 is in ohmic contact with the emitter electrode 24 covering the upper surface of the semiconductor substrate 10. Each of the multiple contact layers 16 is formed by ion-implanting p-type impurities toward the upper surface of the semiconductor substrate 10 using an ion implantation technique. The p-type impurity is not particularly limited, but may be, for example, boron. The peak concentration of the p-type impurity contained in each of the multiple contact layers 16 is not particularly limited, but may be, for example, 1×10 17 cm -3 ~1×10 20 cm-3 In the technology disclosed in this specification, the layout of the multiple contact layers 16 formed in the upper layer of the semiconductor substrate 10 is not particularly limited, and various layouts may be adopted.

[0024] The cathode layer 17 is provided in a range corresponding to the diode region 104 in the lower layer of the semiconductor substrate 10, and is provided at a position exposed on the lower surface of the semiconductor substrate 10. The cathode layer 17 is in ohmic contact with the collector electrode 22 covering the lower surface of the semiconductor substrate 10. The cathode layer 17 is selectively formed in the diode region 104 of the semiconductor substrate 10, and is not formed in the IGBT region 102 and the boundary region 106 of the semiconductor substrate 10. In other words, the range of the semiconductor substrate 10 where the cathode layer 17 is provided becomes the diode region 104. The cathode layer 17 is formed by ion implantation of n-type impurities toward the lower surface of the semiconductor substrate 10 using an ion implantation technique. The cathode layer 17 is formed by multi-stage ion implantation, and may have multiple peak concentrations in the thickness direction of the semiconductor substrate 10. The n-type impurity is not particularly limited, but may be, for example, phosphorus. The peak concentration of the n-type impurity contained in the cathode layer 17 is not particularly limited, but may be, for example, 1×10 18 cm -3 ~1×10 20 cm -3 may be also possible.

[0025] Each of the trench gates 30 is provided in a trench formed in a range corresponding to the IGBT region 102 in the upper layer of the semiconductor substrate 10, and has a gate electrode 32 and a gate insulating film 34. The gate electrode 32 is insulated from the semiconductor substrate 10 by the gate insulating film 34, and is insulated from the emitter electrode 24 by the interlayer insulating film. Each of the trench gates 30 penetrates the base layer 14 from the upper surface of the semiconductor substrate 10 to reach the drift layer 13. In this example, each of the trench gates 30 extends along the x direction when the semiconductor substrate 10 is viewed in a plan view, and is spaced apart from one another in the y direction. That is, the trench gates 30 are spaced apart from one another along the direction in which the IGBT region 102 and the diode region 104 are repeatedly arranged when the semiconductor substrate 10 is viewed in a plan view, and have a striped layout. Instead of this example, the trench gates 30 may have other types of layouts.

[0026] Each of the multiple dummy trench gates 40 is provided in a trench formed in an area corresponding to the diode region 104 and the boundary region 106 in the upper layer portion of the semiconductor substrate 10. The multiple dummy trench gates 40 are fabricated in the same manufacturing process as the multiple trench gates 30, and differ from the trench gate 30 in that the interlayer insulating film insulating the gate electrode 32 and the emitter electrode 24 is removed. The multiple dummy trench gates 40 have the same layout as the multiple trench gates 30. When such a dummy trench gate 40 is provided, electric field concentration in the diode region 104 and the boundary region 106 can be alleviated.

[0027] The semiconductor device 1 can control the on / off of a current flowing through the IGBT region 102 from the collector electrode 22 to the emitter electrode 24 based on a gate voltage applied to the gate electrode 32 of the trench gate 30. Furthermore, in the semiconductor device 1, the diode structure formed in the diode region 104 can operate as a freewheeling diode during recovery operation.

[0028] During recovery operation in which the diode structure operates, if the number of holes injected obliquely from the p-type base layer 14 of the IGBT region 102 toward the n-type cathode layer 17 of the diode region 104 increases, the recovery current increases and the recovery loss increases. In the semiconductor device 1, the collector layer 11 is provided in the boundary region 106, so the distance between the p-type base layer 14 of the IGBT region 102 and the n-type cathode layer 17 of the diode region 104 becomes long. Therefore, the number of holes injected obliquely during recovery operation is suppressed, and the recovery current is suppressed. Therefore, the semiconductor device 1 can have low recovery loss characteristics.

[0029] The width of the boundary region 106 measured along the direction connecting the IGBT region 102 and the diode region 104 is adjusted to a size necessary to suppress the amount of holes injected in an oblique direction. The width of the boundary region 106 is not particularly limited, but may be, for example, 0.5 μm or more, preferably 1.0 μm or more. The width of the boundary region 106 may be larger than the width between adjacent dummy trench gates 40 (i.e., the pitch width of the dummy trench gates 40). Alternatively, the width of the boundary region 106 may be larger than the substrate thickness of the semiconductor substrate 10. The width of the boundary region 106 may be smaller than twice the substrate thickness of the semiconductor substrate 10 in order to suppress area consumption.

[0030] Here, consider a case where the concentration of p-type impurities in the collector layer 11 is constant across the IGBT region 102 and the boundary region 106, that is, the concentration of p-type impurities in the second collector layer 11b in the boundary region 106 is as high as the concentration of p-type impurities in the first collector layer 11a in the IGBT region 102. In this case, when the IGBT structure is on, holes are injected from the collector layer 11 in the boundary region 106 toward the n-type drift layer 13 in the boundary region 106. When the IGBT structure is turned off, the holes injected into the drift layer 13 move obliquely toward the p-type base layer 14 in the IGBT region 102 and are discharged through the p-type base layer 14. For this reason, it takes a longer time for the holes to be discharged, and the switching loss increases due to an increase in the tail current.

[0031] In the semiconductor device 1, the concentration of p-type impurities in the portion of the collector layer 11 corresponding to the boundary region 106, i.e., the second collector layer 11b, is adjusted to be low. Since the second collector layer 11b, in which the concentration of p-type impurities is adjusted to be low, is provided in the boundary region 106, the amount of holes injected into the drift layer 13 in the boundary region 106 is suppressed when the IGBT structure in the IGBT region 102 is on. As a result, in the semiconductor device 1, an increase in switching loss is suppressed.

[0032] 3, a process for forming the collector layer 11 and the cathode layer 17 in the method for manufacturing the semiconductor device 1 will be described. For the processes in the method for manufacturing the semiconductor device 1 other than the processes described below, known processes can be used.

[0033] First, a first mask is formed on the lower surface of the semiconductor substrate 10 by using a photolithography technique (see step S1). FIG. 4 shows an example of a pattern of the first mask 52 formed on the lower surface of the semiconductor substrate 10. The first mask 52 covers the diode region 104 and a part of the boundary region 106 on the lower surface of the semiconductor substrate 10, and has an opening so as to expose the IGBT region 102 and another part of the boundary region 106. Here, the opening area of ​​the first mask 52 per unit area is defined as the aperture ratio of the first mask 52. In this example, the aperture ratio of the first mask 52 is constant across the boundary region 106. Instead of this example, as shown in FIG. 5 and FIG. 6, the aperture ratio of the first mask 52 may decrease from the boundary between the IGBT region 102 and the boundary region 106 toward the diode region 104.

[0034] Next, using an ion implantation technique, p-type impurities are ion-implanted through the openings in the first mask 52 into the lower portion of the semiconductor substrate 10 in an area corresponding to the IGBT region 102 and the boundary region 106 (see step S2). The first mask 52 is removed after the ion implantation.

[0035] Next, a second mask is formed on the lower surface of the semiconductor substrate 10 using photolithography (see step S3). The second mask covers the IGBT region 102 and the boundary region 106 on the lower surface of the semiconductor substrate 10, and has an opening to expose the diode region 104.

[0036] Next, using an ion implantation technique, n-type impurities are ion-implanted through the openings in the second mask into the lower portion of the semiconductor substrate 10 in an area corresponding to the diode region 104 (see step S4). The second mask is removed after the ion implantation.

[0037] Next, laser annealing is performed by irradiating the lower surface of the semiconductor substrate 10 with a laser (see step S5). This activates the p-type impurities and n-type impurities introduced into the lower layer of the semiconductor substrate 10. Through these steps, the collector layer 11 and the cathode layer 17 can be formed in the lower layer of the semiconductor substrate 10. Note that steps S1 and S2 may be performed after steps S3 and S4.

[0038] According to this manufacturing method, the amount of p-type impurity introduced into the lower layer portion of the semiconductor substrate 10 is relatively lower in the range corresponding to the boundary region 106 than in the range corresponding to the IGBT region 102. Therefore, the concentration of the p-type impurity diffused by the laser annealing process is relatively lower in the boundary region 106. In particular, as shown in Figures 5 and 6, if the aperture ratio of the first mask 52 decreases from the boundary between the IGBT region 102 and the boundary region 106 toward the diode region 104, the concentration of the p-type impurity decreases from the boundary between the IGBT region 102 and the boundary region 106 toward the diode region 104.

[0039] In the above-described manufacturing method, by utilizing the first mask, a first collector layer 11a containing a relatively high concentration of p-type impurities can be formed in the IGBT region 102 of the semiconductor substrate 10, and a second collector layer 11b containing a relatively low concentration of p-type impurities can be formed in the boundary region 106 of the semiconductor substrate 10.

[0040] The semiconductor device 1 described above can be modified as follows. The semiconductor device 2 shown in FIG. 7 is characterized in that an n-type barrier layer 21 is provided in the semiconductor substrate 10. The barrier layer 21 is provided over the entire IGBT region 102, the boundary region 106, and the diode region 104 of the semiconductor substrate 10. The barrier layer 21 is provided buried in the base layer 14 and divides the base layer 14 into upper and lower parts. The barrier layer 21 is formed by ion-implanting n-type impurities toward the upper surface of the semiconductor substrate 10 using an ion implantation technique. The n-type impurity is not particularly limited, but may be, for example, phosphorus. The effective peak concentration of the n-type impurity in the barrier layer 21 may be smaller than the effective peak concentration of the p-type impurity in the second base layer 14b. When such a barrier layer 21 is provided, hole injection from the base layer 14 can be suppressed during recovery operation. Therefore, the semiconductor device 2 can have low recovery loss characteristics.

[0041] The features of the technology disclosed in this specification are summarized below. Note that the technical elements described below are independent technical elements that exhibit technical usefulness alone or in various combinations.

[0042] (Feature 1) A reverse conducting IGBT (1, 2), a semiconductor substrate (10) having an IGBT region (102), a diode region (104), and a boundary region (106) located between the IGBT region and the diode region; a lower electrode (22) provided on the lower surface of the semiconductor substrate; and an upper electrode (24) provided on an upper surface of the semiconductor substrate, The semiconductor substrate is a drift layer (13) of a first conductivity type provided across the IGBT region, the diode region, and the boundary region; a second conductivity type base layer (14) provided across the IGBT region, the diode region, and the boundary region and disposed above the drift layer; a first conductivity type emitter layer (15) provided in the IGBT region, disposed above the base layer, and in contact with the upper electrode; a collector layer (11) of a second conductivity type provided in the IGBT region and the boundary region, disposed below the drift layer, and in contact with the lower electrode; a cathode layer (17) of a first conductivity type provided in the diode region, disposed below the drift layer, and in contact with the lower electrode; The collector layer is A first collector layer (11a) provided in the IGBT region; and a second collector layer (11b) provided in the boundary region, a reverse conducting IGBT, wherein the second collector layer has a lower concentration of second conductivity type impurities than the first collector layer;

[0043] (Feature 2) 2. The reverse conducting IGBT according to feature 1, wherein a concentration of the second conductive type impurity in the second collector layer decreases from a boundary between the IGBT region and the boundary region toward the diode region.

[0044] (Feature 3) The base layer is a first base layer (14a) provided in the IGBT region; a second base layer (14b) provided in the diode region and the boundary region, 3. The reverse conducting IGBT according to feature 1 or 2, wherein a concentration of the second conductive type impurity in the second base layer is lower than a concentration of the second conductive type impurity in the first base layer.

[0045] (Feature 4) The semiconductor substrate is The reverse conducting IGBT according to any one of Features 1 to 3, further comprising a barrier layer (21) of a first conductivity type provided across the IGBT region, the diode region, and the boundary region and embedded in the base layer.

[0046] (Feature 5) 5. The reverse conducting IGBT according to any one of Features 1 to 4, further comprising: a trench gate (30) provided in the IGBT region, the trench extending from an upper surface of the semiconductor substrate through the base layer to the drift layer.

[0047] (Feature 6) The reverse conducting IGBT according to any one of features 1 to 5, further comprising a dummy trench gate (40) provided in the diode region and the boundary region, and in a trench extending from an upper surface of the semiconductor substrate through the base layer to reach the drift layer.

[0048] (Feature 7) A method for manufacturing a reverse conducting IGBT (1, 2) comprising a semiconductor substrate (10) having an IGBT region (102), a diode region (104), and a boundary region (106) located between the IGBT region and the diode region, comprising the steps of: forming a mask on the lower surface of the semiconductor substrate, the mask covering the diode region and a portion of the boundary region of the lower surface of the semiconductor substrate and exposing the IGBT region and another portion of the boundary region; implanting dopants into the underside of the semiconductor substrate through the openings in the mask; and activating the dopant by annealing.

[0049] (Feature 8) 8. The method for manufacturing a reverse conducting IGBT according to claim 7, wherein an aperture ratio of the mask decreases from a boundary between the IGBT region and the boundary region toward the diode region.

[0050] (Feature 9) 9. The method for manufacturing a reverse conducting IGBT according to feature 7 or 8, wherein the step of activating the dopant includes a laser annealing process of irradiating a lower surface of the semiconductor substrate with a laser.

[0051] Although specific examples of the present invention have been described above in detail, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of the objectives itself has technical utility. [Explanation of symbols]

[0052] 10: semiconductor substrate, 11: collector layer, 11a: first collector layer, 11b: second collector layer, 12: buffer layer, 13: drift layer, 14: base layer, 14a: first base layer, 14b: second base layer, 15: emitter layer, 16: contact layer, 17: cathode layer, 22: collector electrode, 24: emitter electrode, 30: trench gate, 32: gate electrode, 34: gate insulating film, 40: dummy trench gate, 102: IGBT region, 104: diode region, 106: boundary region

Claims

1. A reverse conducting IGBT (1, 2), a semiconductor substrate (10) having an IGBT region (102), a diode region (104), and a boundary region (106) located between the IGBT region and the diode region; A lower electrode (22) provided on the lower surface of the semiconductor substrate; and an upper electrode (24) provided on an upper surface of the semiconductor substrate, The semiconductor substrate is a drift layer (13) of a first conductivity type provided across the IGBT region, the diode region, and the boundary region; a second conductivity type base layer (14) provided across the IGBT region, the diode region, and the boundary region and disposed above the drift layer; a first conductive type emitter layer (15) provided in the IGBT region, disposed above the base layer, and in contact with the upper electrode; a collector layer (11) of a second conductivity type provided in the IGBT region and the boundary region, disposed below the drift layer, and in contact with the lower electrode; a cathode layer (17) of a first conductivity type provided in the diode region, disposed below the drift layer, and in contact with the lower electrode; The collector layer is A first collector layer (11a) provided in the IGBT region; a second collector layer (11b) provided in the boundary region, a concentration of the second conductive type impurity in the second collector layer is lower than a concentration of the second conductive type impurity in the first collector layer; a concentration of the second conductivity type impurity in the second collector layer decreases from a boundary between the IGBT region and the boundary region toward the diode region.

2. The base layer is A first base layer (14a) provided in the IGBT region; a second base layer (14b) provided in the diode region and the boundary region, 2. The reverse conducting IGBT according to claim 1, wherein a concentration of the second conductive type impurity in said second base layer is lower than a concentration of the second conductive type impurity in said first base layer.

3. The semiconductor substrate is 2. The reverse conducting IGBT according to claim 1, further comprising a barrier layer (21) of a first conductivity type provided across the IGBT region, the diode region and the boundary region and embedded in the base layer.

4. 2. The reverse conducting IGBT according to claim 1, further comprising a trench gate (30) provided in the IGBT region and in a trench extending from an upper surface of the semiconductor substrate through the base layer to the drift layer.

5. 2. The reverse conducting IGBT according to claim 1, further comprising a dummy trench gate (40) provided in the diode region and the boundary region, the dummy trench gate being provided in a trench extending from the upper surface of the semiconductor substrate through the base layer to reach the drift layer.

6. A method for manufacturing a reverse conducting IGBT (1, 2) comprising a semiconductor substrate (10) having an IGBT region (102), a diode region (104), and a boundary region (106) located between the IGBT region and the diode region, the method comprising the steps of: forming a mask on the lower surface of the semiconductor substrate, the mask covering the diode region and a portion of the boundary region on the lower surface of the semiconductor substrate and exposing the IGBT region and another portion of the boundary region; implanting dopants into the underside of the semiconductor substrate through the openings in the mask; and activating the dopant by annealing. an aperture ratio of the mask decreases from a boundary between the IGBT region and the boundary region toward the diode region.

7. The method for manufacturing a reverse conducting IGBT according to claim 6 , wherein the step of activating the dopant includes a laser annealing process of irradiating a lower surface of the semiconductor substrate with a laser.

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