Semiconductor device

Abstract

To provide a semiconductor device capable of obtaining a good service life even at a high operation temperature.SOLUTION: A semiconductor device comprises a semiconductor substrate, a semiconductor chip including a main electrode provided on the semiconductor substrate, a buffer plate, and a buffer joining material provided between the main electrode and the buffer plate. The buffer plate is a laminated material or an alloy material where a Curie point is higher than or equal to 300°C. The laminated material includes a first copper layer in contact with the buffer joining material, an alloy layer where the Curie point provided on the first copper layer is higher than or equal to 300°C, and a second copper layer provided on the alloy layer.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] As an example of a semiconductor device suitable for a power module, a semiconductor device has been proposed in which a buffer plate is bonded to a main electrode of a semiconductor chip, and bonding wires are bonded to the buffer plate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-186220 A [Patent Document 2] JP 2017-005037 A [Patent Document 3] JP 2019-057663 A Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, there has been an increasing demand for semiconductor devices that can be used at higher temperatures, and therefore a good life span at higher temperatures is desired.

[0005] An object of the present disclosure is to provide a semiconductor device that has a good life even at high operating temperatures. [Means for solving the problem]

[0006] The semiconductor device disclosed herein comprises a semiconductor chip having a semiconductor substrate and a main electrode provided on the semiconductor substrate, a buffer plate, and a buffer bonding material provided between the main electrode and the buffer plate, the buffer plate being a laminate material or an alloy material having a Curie point of 300°C or higher, the laminate material having a first copper layer in contact with the buffer bonding material, an alloy layer having a Curie point of 300°C or higher provided on the first copper layer, and a second copper layer provided on the alloy layer. Effect of the Invention

[0007] The present disclosure provides good life even at high operating temperatures. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a top view showing the semiconductor device according to the first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view showing the semiconductor device according to the first embodiment. [Diagram 3] FIG. 3 is a top view showing the semiconductor device according to the second embodiment. [Figure 4] FIG. 4 is a cross-sectional view showing the semiconductor device according to the second embodiment. [Diagram 5] FIG. 5 is a diagram showing an example of the results of a power cycle test. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The embodiments for carrying out the invention are described below.

[0010] [Description of the embodiments of the present disclosure] First, the embodiments of the present disclosure will be described. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description thereof will not be repeated.

[0011] [1] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor chip having a semiconductor substrate and a main electrode provided on the semiconductor substrate, a buffer plate, and a buffer bonding material provided between the main electrode and the buffer plate, the buffer plate being a laminate material or an alloy material having a Curie point of 300° C. or higher, the laminate material having a first copper layer in contact with the buffer bonding material, an alloy layer having a Curie point of 300° C. or higher provided on the first copper layer, and a second copper layer provided on the alloy layer.

[0012] In ferromagnetic materials, at temperatures below the Curie point, the volume change due to magnetostriction and the thermal expansion due to normal lattice vibration cancel each other out, resulting in small thermal expansion. Since the buffer plate is an alloy material with a Curie point of 300°C or higher, or a laminated material having an alloy layer with a Curie point of 300°C or higher, the thermal expansion of the buffer plate is small at temperatures below 300°C. This also suppresses the thermal deformation of the main electrode joined to the buffer plate by the buffer joining material. Therefore, even when used at high temperatures, the internal destruction of the main electrode is suppressed, resulting in a good lifespan.

[0013] The internal destruction of the main electrode occurs when grain boundary sliding and cracks occurring at the grain boundaries of the crystals that compose the main electrode are superimposed due to repeated thermal deformation. The internal destruction of the main electrode is confirmed, for example, as a decrease in the density of the main electrode or an increase in the thickness of the main electrode. Furthermore, when the internal destruction of the main electrode occurs, the effective bonding area between the main electrode and the members sandwiching it is reduced. Therefore, the internal destruction can also be confirmed as an increase in electrical or thermal series resistance.

[0014] The internal destruction of the main electrode may also occur in a power cycle test. That is, in a power cycle test, the temperature rises and falls repeatedly, so that the occurrence of grain boundary sliding and cracks may overlap, and the internal destruction may occur. For example, in the later stage of the power cycle test, the internal destruction of the main electrode may be confirmed as a break or peeling of the main electrode, a sudden increase in electrical resistance or a disconnection, or a sudden increase in thermal resistance or the occurrence of thermal runaway. These phenomena become particularly noticeable immediately before the end of the life.

[0015] [2] In [1], the buffer bonding material may have a sintered body with a porosity of 5% to 40%. By having the buffer bonding material have a sintered body with a porosity of 5% to 40%, the thermal stress acting on the buffer bonding material is reduced, and the thermal deformation of the main electrode is suppressed. Therefore, it is easy to obtain a good life.

[0016] [3] In [1] or [2], the alloy material and the alloy layer may contain iron and nickel, and the proportion of nickel in the alloy material and the alloy layer may be 40 mass% or more. In this case, the alloy material and the alloy layer are likely to have a Curie point of 300°C or more.

[0017] [4] In [1] or [2], the alloy material and the alloy layer may contain iron, nickel and cobalt, and the total proportion of nickel and cobalt in the alloy material and the alloy layer may be 40 mass% or more. In this case, the alloy material and the alloy layer are likely to have a Curie point of 300°C or more.

[0018] [5] A semiconductor device according to another aspect of the present disclosure includes a semiconductor chip having a semiconductor substrate and a main electrode provided on the semiconductor substrate, a buffer plate, and a buffer bonding material provided between the main electrode and the buffer plate, the buffer bonding material having a sintered body with a porosity of 5% or more and 40% or less.

[0019] By using a sintered body with a porosity of 5% to 40%, the thermal stress acting on the buffer bonding material is reduced, and the thermal deformation of the main electrode is suppressed. Therefore, even when used at high temperatures, internal destruction of the main electrode is suppressed, and a good life is achieved.

[0020] [6] In any one of [1] to [5], the main electrode may include an aluminum or aluminum alloy layer, and the first linear expansion coefficient of the semiconductor substrate and the second linear expansion coefficient of the buffer plate may be smaller than the third linear expansion coefficient of the main electrode, and the second linear expansion coefficient may be smaller than the first linear expansion coefficient. In this case, it is easy to obtain good electrical conductivity in the main electrode. On the other hand, since the third linear expansion coefficient is larger than the first linear expansion coefficient, the main electrode tends to thermally deform more than the semiconductor substrate. However, since the second linear expansion coefficient is smaller than the first linear expansion coefficient, the thermal deformation of the main electrode can be effectively suppressed by the buffer bonding material. Therefore, the thermal stress generated in the main electrode due to thermal deformation can be suppressed, and the internal destruction of the aluminum or aluminum alloy layer contained in the main electrode can be suppressed.

[0021] In general, aluminum or aluminum alloy layers are weaker than other metal parts that compose semiconductor devices in terms of strength and heat resistance. The grain boundary sliding that causes internal destruction of the main electrode is called creep, and the creep phenomenon onset temperature can be indexed to a temperature 0.4 times the melting point (Tm). This index shows that creep begins at a lower temperature in the aluminum or aluminum alloy layer compared to other parts. For example, the values ​​of "Tm x 0.4" for aluminum, copper, and nickel are 100°C, 270°C, and 418°C, respectively.

[0022] In particular, when the aluminum or aluminum alloy layer included in the main electrode is formed by sputtering, the grain size of the crystals constituting the aluminum or aluminum alloy layer is small, at only a few μm, and therefore, when the aluminum or aluminum alloy layer has a high density of crystal grain boundaries and thermal distortion occurs between the layers sandwiching the main electrode due to temperature rise and fall cycles during a power cycle test, grain boundary sliding is likely to occur.

[0023] In contrast, when the second linear expansion coefficient is smaller than the first linear expansion coefficient, the thermal deformation of the main electrode can be effectively suppressed by the buffer bonding material, and internal destruction of the aluminum or aluminum alloy layer contained in the main electrode can be suppressed.

[0024] [Details of the embodiment of the present disclosure] Hereinafter, the embodiments of the present disclosure will be described in detail, but the present embodiment is not limited thereto. In this specification and drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to avoid redundant description. In this specification and drawings, the X1-X2 direction, the Y1-Y2 direction, and the Z1-Z2 direction are defined as mutually orthogonal directions. The plane including the X1-X2 direction and the Y1-Y2 direction is defined as the XY plane, the plane including the Y1-Y2 direction and the Z1-Z2 direction is defined as the YZ plane, and the plane including the Z1-Z2 direction and the X1-X2 direction is defined as the ZX plane. For convenience, the Z1 direction is defined as the upward direction, and the Z2 direction is defined as the downward direction. In this disclosure, planar view refers to viewing an object from the Z1 side.

[0025] (First embodiment) A first embodiment will be described. The first embodiment relates to a semiconductor device. Fig. 1 is a top view showing the semiconductor device according to the first embodiment. Fig. 2 is a cross-sectional view showing the semiconductor device according to the first embodiment. Fig. 2 corresponds to a cross-sectional view taken along line II-II in Fig. 1.

[0026] As shown in FIGS. 1 and 2, the semiconductor device 1 according to the first embodiment mainly includes a heat sink 120, a substrate 110, a terminal 102, a terminal 103, a case 190, a diode 300, and a buffer plate 500.

[0027] The heat sink 120 is, for example, a rectangular plate-like body with a uniform thickness in a plan view. The material of the heat sink 120 is a metal with high thermal conductivity, such as copper (Cu), a copper alloy, aluminum (Al), an aluminum-silicon-carbon alloy (Al-Si-C alloy), etc. The heat sink 120 is fixed to a cooler or the like using a thermal interface material (TIM) or the like.

[0028] The case 190 is formed, for example, in a frame shape in a plan view, and the outer shape of the case 190 is the same as the outer shape of the heat sink 120. The material of the case 190 is an insulating material such as resin. The case 190 has a pair of side walls 191 and 192 facing each other, and a pair of end walls 193 and 194 connecting both ends of the side walls 191 and 192. The side walls 191 and 192 are arranged parallel to the ZX plane, and the end walls 193 and 194 are arranged parallel to the YZ plane. The side wall 191 is arranged on the Y1 side of the side wall 192, and the end wall 193 is arranged on the X2 side of the end wall 194.

[0029] Terminal 102 is disposed on the upper surface (surface on the Z1 side) of end wall portion 193, and terminal 103 is disposed on the upper surface (surface on the Z1 side) of end wall portion 194. Terminals 102 and 103 are each made of a metal plate.

[0030] Inside the case 190, the substrate 110 is disposed on the Z1 side of the heat sink 120. The substrate 110 has an insulating substrate 119, a second conductive pattern 112, a third conductive pattern 113, and a conductive layer 115. The first conductive pattern 111, the second conductive pattern 112, the third conductive pattern 113, the fourth conductive pattern 114, and the conductive layer 115 are made of Cu.

[0031] The second conductive pattern 112 and the third conductive pattern 113 are provided on the Z1 side surface of the insulating substrate 119. The conductive layer 115 is provided on the Z2 side surface of the insulating substrate 119. The conductive layer 115 is bonded to the heat sink 120 by a bonding material 131. The bonding material 131 may be a solder material or a sintered bonding material. When the bonding material 131 is a sintered bonding material, operation at a higher temperature, near the melting point of the solder or higher, is possible.

[0032] As shown in FIG. 2, the diode 300 mainly includes a silicon carbide substrate 310 , an anode electrode 332 , and a cathode electrode 333 .

[0033] The silicon carbide substrate 310 has a main surface 310A and a main surface 310B opposite to the main surface 310A. The main surface 310A is on the Z1 side of the main surface 310B. The silicon carbide substrate 310 has a shape of, for example, a rectangular parallelepiped. The main surfaces 310A and 310B are parallel to the XY plane. The anode electrode 332 is provided on the main surface 310A, and the cathode electrode 333 is provided on the main surface 310B. The diode 300 is provided on the third conductive pattern 113. The anode electrode 332 includes, for example, an aluminum layer. The anode electrode 332 may include an aluminum alloy layer such as an aluminum-silicon alloy (Al-Si alloy) or an Al-Si-Cu alloy instead of the aluminum layer. The cathode electrode 333 has an ohmic layer and a junction layer provided on the ohmic layer. The ohmic layer includes, for example, nickel or a nickel alloy. Nickel or a nickel alloy has good contact resistance with silicon carbide. The bonding layer includes a nickel layer. The bonding layer may further include a gold layer or a silver layer provided on the nickel layer. The cathode electrode 333 has a bonding layer, so that good bonding is obtained between the cathode electrode 333 and the third conductive pattern 113. The cathode electrode 333 is bonded to the third conductive pattern 113 using a bonding material 133 such as a silver sintered body or a copper sintered body. The diode 300 is an example of a semiconductor chip. The silicon carbide substrate 310 is an example of a semiconductor substrate. The anode electrode 332 is an example of a main electrode.

[0034] The buffer plate 500 is, for example, a laminated material having a first copper layer 510, an alloy layer 520, and a second copper layer 530. The alloy layer 520 is provided on the Z1 side of the first copper layer 510, and the second copper layer 530 is provided on the Z1 side of the alloy layer 520. That is, the alloy layer 520 is provided on the first copper layer 510, and the second copper layer 530 is provided on the alloy layer 520. The alloy layer 520 is an alloy material having a Curie point of 300° C. or higher. The alloy layer 520 includes, for example, iron (Fe) and nickel (Ni), and the proportion of Ni in the alloy layer 520 is 40% by mass or higher. The alloy layer 520 may include, for example, Fe, Ni, and cobalt (Co), and the total proportion of Ni and Co in the alloy layer 520 may be 40% by mass or higher. The alloy layer 520 may include 29% by mass of Ni and 17% by mass of Co. In either case, the alloy layer 520 may contain Fe at a ratio of 45% by mass or more, or may contain Fe at a ratio of 48% by mass or more. The alloy layer 520 may contain manganese at about 0.7% by mass. The material of the alloy layer 520 may be Kovar (registered trademark). The thickness T2 of the buffer plate 500 is, for example, 0.05 mm or more and 0.5 mm or less. The thickness T2 of the buffer plate 500 may be 0.05 mm or more and 0.25 mm or less. For example, the thickness T2 of the buffer plate 500 is smaller than the thickness T1 of the diode 300. The buffer plate 500 is provided on the anode electrode 332. The first copper layer 510 is bonded to the anode electrode 332 using a buffer bonding material 135 such as a silver sintered body or a copper sintered body. The buffer bonding material 135 has a sintered body with a porosity of 5% or more and 40% or less.

[0035] The silicon carbide substrate 310 has a first linear expansion coefficient ρ1, the buffer plate 500 has a second linear expansion coefficient ρ2, and the anode electrode 332 has a third linear expansion coefficient ρ3. The linear expansion coefficient in this disclosure is the linear expansion coefficient in a direction parallel to the main surface 310A at 25° C., unless otherwise specified. In addition, the linear expansion coefficient in this disclosure is the linear expansion coefficient when the silicon carbide substrate 310, the buffer plate 500, and the anode electrode 332 are separated from each other and are taken as a single body, unless otherwise specified. The first linear expansion coefficient ρ1 and the second linear expansion coefficient ρ2 are smaller than the third linear expansion coefficient ρ3. The second linear expansion coefficient ρ2 may be larger or smaller than the first linear expansion coefficient ρ1, but when the difference between the first linear expansion coefficient ρ1 and the second linear expansion coefficient ρ2 is small, the thermal stress applied to the anode electrode 332 is easily suppressed. When the second linear expansion coefficient ρ2 is smaller than the first linear expansion coefficient ρ1, the life is more likely to be extended than when the second linear expansion coefficient ρ2 is larger than the first linear expansion coefficient ρ1. For example, when the first linear expansion coefficient ρ1 is 4.0×10 -6 / ℃, while the second linear expansion coefficient ρ2 is 1.2×10 -6 / ℃ or more 3.9×10 -6 / ℃ or less. In this case, the value of "ρ2-ρ1" is -2.8×10 -6 / ℃ or more -0.1×10 -6 / ℃ or less, it is easier to obtain a longer life than when the value of "ρ2-ρ1" is positive. The linear expansion coefficient of iron-nickel alloys is 1.2×10 -6 / ℃, and the linear expansion coefficient of copper is 16.5×10 -6 / ℃, and the linear expansion coefficient of aluminum is 23.1×10 -6 / ℃.

[0036] The semiconductor device 1 further includes wires 162, 165, and 166. The number of each of the wires 162, 165, and 166 is not limited, and may be one, or may be two or more.

[0037] The wire 162 connects the second copper layer 530 of the buffer plate 500 and the second conductive pattern 112 to each other. The wire 165 connects the second conductive pattern 112 and the terminal 102 to each other. The wire 166 connects the third conductive pattern 113 and the terminal 103 to each other. The wires 162, 165, and 166 are, for example, copper wires. The diameter of each of the wires 162, 165, and 166 is, for example, not less than 100 μm and not more than 400 μm. The wires 162, 165, and 166 are bonded, for example, by ultrasonic bonding.

[0038] Generally, the lifespan of semiconductor devices used in power modules at their operating temperatures is evaluated by a power cycle test. In the power cycle test, a semiconductor device sample is repeatedly energized and cut off. At this time, the maximum junction temperature (Tjmax) is set as the operating temperature for which the lifespan is to be evaluated. Then, based on the difference (ΔT) between the maximum junction temperature (Tjmax) and the minimum junction temperature (Tjmin), it is determined that the sample has reached the end of its lifespan when the junction temperature (Tj) reaches Tjmax+ΔT×20%.

[0039] For example, if the maximum junction temperature (Tjmax) is 250°C and the minimum junction temperature (Tjmin) is 65°C, the difference (ΔT) is 185°C, so it is determined that the sample has reached its life when the junction temperature (Tj) reaches 287°C. Also, if the maximum junction temperature (Tjmax) is 250°C and the minimum junction temperature (Tjmin) is 25°C, the difference (ΔT) is 225°C, so it is determined that the sample has reached its life when the junction temperature (Tj) reaches 295°C.

[0040] In addition, in ferromagnetic materials such as Invar (registered trademark) and Kovar, the volume change due to magnetostriction and the thermal expansion due to normal lattice vibration cancel each other out at temperatures below the Curie point, so that the thermal expansion is small. As described above, in this embodiment, the alloy layer 520 is an alloy material with a Curie point of 300°C or higher. In other words, at temperatures below 300°C, the thermal expansion of the alloy layer 520 is small. Therefore, in this embodiment, the thermal deformation of the alloy layer 520 and the buffer plate 500 is suppressed in a power cycle test with a maximum junction temperature (Tjmax) of 250°C.

[0041] Furthermore, since the thermal deformation of the buffer plate 500 is suppressed, the thermal deformation of the anode electrode 332 joined to the buffer plate 400 by the buffer bonding material 135 is also suppressed. Therefore, according to this embodiment, even when used at high temperatures, it is possible to suppress the thermal stress generated in the anode electrode 332 due to the thermal deformation, and to suppress internal destruction of the anode electrode 332.

[0042] In this embodiment, the buffer bonding material 135 has a sintered body with a porosity of 5% or more and 40% or less. The higher the porosity, the lower the thermal stress acting on the buffer bonding material 135 during heating, and as a result, the thermal stress occurring in the anode electrode 332 can be suppressed. According to a stress analysis using the finite element method, when the temperature of the buffer bonding material 135 made of a copper sintered body is 200° C., the thermal stress occurring in the anode electrode 332 is 54 MPa when the porosity is 0%, 36 MPa when the porosity is 5%, and 10 MPa when the porosity is 30%. That is, when the porosity is 5%, the thermal stress is 34% lower than when the porosity is 0%, and when the porosity is 30%, the thermal stress is 72% lower than when the porosity is 5%. According to a stress analysis using the finite element method, it has been confirmed that even when the temperature of the buffer bonding material 135 made of a copper sintered body is 250° C., the thermal stress occurring in the anode electrode 332 is reduced when the porosity is 5% or more and 40% or less.

[0043] The effect of reducing thermal stress due to the increase in the porosity of the sintered body becomes more pronounced when the sintered body is used at high temperatures. This is because, in the case of bulk Cu, the Young's modulus obtained from the stress-strain curve does not usually have temperature dependence. On the other hand, the stress-strain curve of a Cu sintered body has temperature dependence, and the Young's modulus from the stress-strain curve becomes smaller in the high temperature range. It has been confirmed by the stress analysis using the above-mentioned finite element method that this phenomenon acts in a favorable direction to suppress the thermal deformation of the anode electrode 332. Moreover, the same temperature dependence has been confirmed not only for Cu sintered bodies but also for Ag sintered bodies.

[0044] If the porosity is less than 5%, it is difficult to reduce the thermal stress generated in the anode electrode 332. If the porosity is more than 40%, the buffer bonding material 135 is likely to become brittle. The porosity of the sintered body included in the buffer bonding material 135 may be 5% or more and 30% or less, or may be 5% or more and 20% or less.

[0045] In this manner, in this embodiment, the thermal stress acting on the buffer bonding material 135 is reduced, thereby suppressing thermal deformation of the anode electrode 332. Therefore, according to this embodiment, even when used at high temperatures, the thermal stress generated in the anode electrode 332 due to thermal deformation can be suppressed, and internal destruction of the anode electrode 332 can be suppressed.

[0046] According to this embodiment, the effect of the alloy layer 520 being an alloy material having a Curie point of 300°C or higher and the effect of the buffer bonding material 135 being a sintered body having a porosity of 5% or more and 40% or less can be obtained, and the effect of a combination of these can also be obtained as described below.

[0047] There are mainly two factors that can be considered as factors of thermal stress occurring in the anode electrode 332. The first factor is thermal distortion due to the difference between the second linear expansion coefficient ρ2 of the buffer plate 500 and the first linear expansion coefficient ρ1 of the silicon carbide substrate 310, and the second factor is the temperature dependency of the Young's modulus of the buffer bonding material 135. Regarding the first factor, by reducing the difference between the second linear expansion coefficient ρ2 and the first linear expansion coefficient ρ1, it is possible to suppress thermal distortion in a wide temperature range from the minimum bonding temperature, which is the operating temperature, to the maximum bonding temperature. Regarding the second factor, since the Young's modulus of the buffer bonding material 135 decreases with increasing temperature, it is possible to maintain the effect of suppressing thermal distortion in a wide temperature range. In contrast, when a bonding material made of a bulk material of copper is used instead of the buffer bonding material 135, the effect of suppressing thermal distortion may be reduced because the bulk material of copper does not have the temperature dependency of the Young's modulus.

[0048] Since the anode electrode 332 includes an aluminum layer or an aluminum alloy layer, it is easy to obtain good electrical conductivity in the anode electrode 332. On the other hand, the first linear expansion coefficient ρ1 of the silicon carbide substrate 310 and the second linear expansion coefficient ρ2 of the buffer plate 500 are smaller than the third linear expansion coefficient ρ3 of the anode electrode 332, and the second linear expansion coefficient ρ2 is smaller than the first linear expansion coefficient ρ1. In this case, the anode electrode 332 tends to thermally deform more than the silicon carbide substrate 310. However, since the second linear expansion coefficient ρ2 is smaller than the first linear expansion coefficient ρ1, the thermal deformation of the anode electrode 332 can be effectively suppressed by the buffer bonding material 135. Therefore, the thermal stress generated in the anode electrode 332 due to the thermal deformation can be suppressed, and the internal destruction of the anode electrode 332 can be suppressed.

[0049] In this embodiment, by bonding the wire 162 to the buffer plate 500, the wire 162 can be electrically connected to the anode electrode 332 via the buffer plate 500. Therefore, even if ultrasonic bonding is used to bond the wire 162, damage to the diode 300 can be suppressed. If the wire 162 is a copper wire, the wire 162 can be easily bonded to the second copper layer 530 of the buffer plate 500, and low electrical resistance can be easily obtained for the wire 162.

[0050] The buffer plate 500 may not include the first copper layer 510 and the second copper layer 530. In other words, the buffer plate 500 may be composed of an alloy layer 520 such as Kovar having a Curie point of 300° C. or higher.

[0051] When alloy layer 520 contains Fe and Ni, and the proportion of Ni in alloy layer 520 is 40 mass% or more, it is easy to obtain a Curie point of 300° C. or more in alloy layer 520. When alloy layer 520 contains Fe, Ni, and Co, and the total proportion of Ni and Co in alloy layer 520 is 40 mass% or more, it is also easy to obtain a Curie point of 300° C. or more in alloy layer 520.

[0052] If the Curie point of the alloy layer 520 is 300° C. or higher, the porosity of the sintered body included in the buffer bonding material 135 does not have to be 5% or higher and 40% or lower. Also, if the porosity of the sintered body included in the buffer bonding material 135 is 5% or higher and 40% or lower, the Curie point of the alloy layer 520 does not have to be 300° C. or higher.

[0053] A plurality of diodes 300 may be provided on the third conductive pattern 113. In this case, the plurality of diodes 300 are electrically connected in parallel to each other.

[0054] Second embodiment Next, a second embodiment will be described. The second embodiment differs from the first embodiment mainly in that a transistor is included. Fig. 3 is a top view showing the semiconductor device according to the second embodiment. Fig. 4 is a cross-sectional view showing the semiconductor device according to the second embodiment. Fig. 4 corresponds to a cross-sectional view taken along line IV-IV in Fig. 3.

[0055] As shown in Figures 3 and 4, the semiconductor device 2 of the second embodiment mainly has a heat sink 120, a substrate 110, a terminal 101, a terminal 102, a terminal 103, a case 190, a transistor 200, a diode 300, a buffer plate 400, and a buffer plate 500.

[0056] Terminals 101 and 102 are disposed on the upper surface (surface on the Z1 side) of end wall portion 193, and terminal 103 is disposed on the upper surface (surface on the Z1 side) of end wall portion 194. For example, terminal 102 is disposed on the Y2 side of terminal 101. Terminals 101, 102, and 103 are each made of a metal plate.

[0057] The substrate 110 has an insulating substrate 119, a first conductive pattern 111, a second conductive pattern 112, a third conductive pattern 113, a fourth conductive pattern 114, and a conductive layer 115. The first conductive pattern 111, the second conductive pattern 112, the third conductive pattern 113, the fourth conductive pattern 114, and the conductive layer 115 are made of Cu.

[0058] The first conductive pattern 111, the second conductive pattern 112, the third conductive pattern 113 and the fourth conductive pattern 114 are provided on the Z1 side surface of the insulating substrate 119. The conductive layer 115 is provided on the Z2 side surface of the insulating substrate 119.

[0059] As shown in FIG. 4, the transistor 200 mainly includes a silicon carbide substrate 210, a gate electrode 231, a source electrode 232, and a drain electrode 233.

[0060] The silicon carbide substrate 210 has a principal surface 210A and a principal surface 210B opposite to the principal surface 210A. The principal surface 210A is on the Z1 side of the principal surface 210B. The shape of the silicon carbide substrate 210 is, for example, a rectangular parallelepiped. The principal surfaces 210A and 210B are parallel to the XY plane. The gate electrode 231 and the source electrode 232 are provided on the principal surface 210A, and the drain electrode 233 is provided on the principal surface 210B. The transistor 200 is provided on the fourth conductive pattern 114. The gate electrode 231 and the source electrode 232 include, for example, an aluminum layer. The gate electrode 231 and the source electrode 232 may include an aluminum alloy layer such as an Al-Si alloy or an Al-Si-Cu alloy instead of the aluminum layer. The drain electrode 233 has an ohmic layer and a junction layer provided on the ohmic layer. The ohmic layer includes, for example, nickel or a nickel alloy. Nickel or a nickel alloy has good contact resistance with silicon carbide. The bonding layer includes a nickel layer. The bonding layer may further include a gold layer or a silver layer provided on the nickel layer. The drain electrode 233 includes a bonding layer, so that good bonding is obtained between the drain electrode 233 and the fourth conductive pattern 114. The drain electrode 233 is bonded to the fourth conductive pattern 114 using a bonding material 132 such as a silver sintered body or a copper sintered body. The transistor 200 is an example of a semiconductor chip. The silicon carbide substrate 210 is an example of a semiconductor substrate. The source electrode 232 is an example of a main electrode.

[0061] The buffer plate 400 is, for example, a laminated material having a first copper layer 410, an alloy layer 420, and a second copper layer 430. The alloy layer 420 is provided on the Z1 side of the first copper layer 410, and the second copper layer 430 is provided on the Z1 side of the alloy layer 420. That is, the alloy layer 420 is provided on the first copper layer 410, and the second copper layer 430 is provided on the alloy layer 420. The alloy layer 420 is an alloy material having a Curie point of 300° C. or higher. The alloy layer 420 includes, for example, Fe and Ni, and the proportion of Ni in the alloy layer 420 is 40% by mass or higher. The alloy layer 420 may include, for example, Fe, Ni, and Co, and the total proportion of Ni and Co in the alloy layer 420 may be 40% by mass or higher. The alloy layer 420 may include 29% by mass of Ni and 17% by mass of Co. In either case, the alloy layer 420 may contain Fe at a ratio of 45% by mass or more, or may contain Fe at a ratio of 48% by mass or more. The alloy layer 420 may contain manganese at about 0.7% by mass. The material of the alloy layer 420 may be Kovar. The thickness T4 of the buffer plate 400 is, for example, 0.05 mm or more and 0.5 mm or less. The thickness T4 of the buffer plate 400 may be 0.05 mm or more and 0.25 mm or less. For example, the thickness T4 of the buffer plate 400 is smaller than the thickness T3 of the transistor 200. The buffer plate 400 is provided on the source electrode 232. The first copper layer 410 is bonded to the source electrode 232 using a buffer bonding material 134 such as a silver sintered body or a copper sintered body. The buffer bonding material 134 has a sintered body with a porosity of 5% or more and 40% or less.

[0062] The silicon carbide substrate 210 has a first linear expansion coefficient ρ1', the buffer plate 400 has a second linear expansion coefficient ρ2', and the source electrode 232 has a third linear expansion coefficient ρ3'. In this disclosure, the linear expansion coefficient is the linear expansion coefficient in a direction parallel to the main surface 210A at 25°C, unless otherwise specified. In this disclosure, the linear expansion coefficient is the linear expansion coefficient when the silicon carbide substrate 210, the buffer plate 400, and the source electrode 232 are released from the bonded state and are taken as a single body, unless otherwise specified. The first linear expansion coefficient ρ1' and the second linear expansion coefficient ρ2' are smaller than the third linear expansion coefficient ρ3', and the second linear expansion coefficient ρ2' is smaller than the first linear expansion coefficient ρ1'. For example, when the first linear expansion coefficient ρ1' is 4.0×10 -6 / ℃, while the second linear expansion coefficient ρ2' is 1.2×10 -6 / ℃ or more 3.9×10 -6 / ℃ or less. In this case, the value of "ρ2´-ρ1´" is -2.8×10 -6 / ℃ or more -0.1×10 -6 / ℃ or less.

[0063] The semiconductor device 2 further includes wires 161, 162, 163, 164, 165, and 166. The number of each of the wires 161, 162, 163, 164, 165, and 166 is not limited, and may be one, or may be two or more.

[0064] The wire 161 connects the gate electrode 231 of the transistor 200 to the first conductive pattern 111. The wire 162 connects the second copper layer 430 of the buffer plate 400 to the second conductive pattern 112. The wire 163 connects the third conductive pattern 113 to the fourth conductive pattern 114. The wire 164 connects the first conductive pattern 111 to the terminal 101. The wire 165 connects the second conductive pattern 112 to the terminal 102. The wire 166 connects the anode electrode 332 of the diode 300 to the terminal 103. The wires 161, 162, 163, 164, 165, and 166 are, for example, copper wires. The diameter of each of the wires 161, 162, 163, 164, 165, and 166 is, for example, 100 μm or more and 400 μm or less. The bonding of the wires 161, 162, 163, 164, 165 and 166 is performed, for example, by ultrasonic bonding.

[0065] Other configurations of the second embodiment, such as the configurations of the diode 300 and the buffer plate 500, are the same as those of the first embodiment.

[0066] As described above, in this embodiment, the alloy layer 420 is an alloy material having a Curie point of 300° C. or higher. In other words, the thermal expansion of the alloy layer 420 is small at temperatures below 300° C. Therefore, in this embodiment, thermal deformation of the alloy layer 420 and the buffer plate 400 is suppressed in a power cycle test in which the maximum bonding temperature (Tjmax) is set to 250° C.

[0067] Furthermore, since the thermal deformation of the buffer plate 400 is suppressed, the thermal deformation of the source electrode 232 joined to the buffer plate 400 by the buffer bonding material 134 is also suppressed. Therefore, according to this embodiment, even when used at high temperatures, it is possible to suppress the thermal stress generated in the source electrode 232 due to the thermal deformation, and to suppress internal destruction of the source electrode 232.

[0068] In this embodiment, the buffer bonding material 134 has a sintered body with a porosity of 5% or more and 40% or less. Therefore, as in the diode 300, the thermal stress acting on the buffer bonding material 134 is reduced, and the thermal deformation of the source electrode 232 is suppressed. Therefore, according to this embodiment, even when used at high temperatures, the thermal stress generated in the source electrode 232 due to thermal deformation can be suppressed, and internal destruction of the source electrode 232 can be suppressed. The porosity of the sintered body included in the buffer bonding material 134 may be 5% or more and 30% or less, or 5% or more and 20% or less.

[0069] Since the source electrode 232 includes an aluminum layer or an aluminum alloy layer, good electrical conductivity is easily obtained in the source electrode 232. On the other hand, the first linear expansion coefficient ρ1' of the silicon carbide substrate 210 and the second linear expansion coefficient ρ2' of the buffer plate 400 are smaller than the third linear expansion coefficient ρ3' of the source electrode 232, and the second linear expansion coefficient ρ2' is smaller than the first linear expansion coefficient ρ1'. In this case, the source electrode 232 tends to thermally deform more than the silicon carbide substrate 210. However, since the second linear expansion coefficient ρ2' is smaller than the first linear expansion coefficient ρ1', the thermal deformation of the source electrode 232 can be effectively suppressed by the buffer bonding material 134. Therefore, the thermal stress generated in the source electrode 232 due to the thermal deformation can be suppressed, and the internal destruction of the source electrode 232 can be suppressed.

[0070] In this embodiment, by bonding the wire 162 to the buffer plate 400, the wire 162 can be electrically connected to the source electrode 232 via the buffer plate 400. Therefore, even if ultrasonic bonding is used to bond the wire 162, damage to the transistor 200 can be suppressed. If the wire 162 is a copper wire, the wire 162 can be easily bonded to the second copper layer 430 of the buffer plate 400, and low electrical resistance can be easily obtained for the wire 162.

[0071] The buffer plate 400 may not include the first copper layer 410 and the second copper layer 430. In other words, the buffer plate 400 may be composed of an alloy layer 420 such as Kovar having a Curie point of 300° C. or higher.

[0072] When alloy layer 420 contains Fe and Ni, and the proportion of Ni in alloy layer 420 is 40 mass% or more, it is easy to obtain a Curie point of 300° C. or more in alloy layer 420. When alloy layer 420 contains Fe, Ni, and Co, and the total proportion of Ni and Co in alloy layer 420 is 40 mass% or more, it is also easy to obtain a Curie point of 300° C. or more in alloy layer 420.

[0073] If the Curie point of the alloy layer 420 is 300° C. or higher, the porosity of the buffer bonding material 134 does not have to be 5% or more and 40% or less. Also, if the porosity of the buffer bonding material 134 is 5% or more and 40% or less, the Curie point of the alloy layer 420 does not have to be 300° C. or higher.

[0074] A plurality of transistors 200 may be provided on the fourth conductive pattern 114. In this case, the plurality of transistors 200 are electrically connected in parallel to each other.

[0075] (Characteristics test) Next, an example of the result of a power cycle test on the semiconductor device according to the embodiment of the present disclosure will be described. The power cycle test is performed as follows in accordance with IEC60749.

[0076] In the power cycle test, the temperature of the sample was raised from room temperature (25°C) to 65°C, and then a current of 125A was repeatedly applied and cut off. The current was applied for 1 second, and cut off for 13 seconds. The maximum junction temperature (Tjmax), which is the maximum value of the junction temperature (Tj) in each cycle, was set to 250°C, and the difference (ΔT) between the maximum junction temperature and the minimum junction temperature (65°C) in each cycle was set to 185°C.

[0077] The voltage at which current starts flowing when a low current of about 100mA is applied to the sample corresponds to the junction temperature (Tj) of the sample. Therefore, if a low current of 100mA, which is sufficiently smaller than the current that flows immediately after current is applied, is applied to the sample for each cycle of current application and interruption, and the voltage at which current starts is measured, the temperature at which current starts flowing in each cycle can be converted to the maximum junction temperature (Tjmax). As the power cycle test progresses, the sample gradually deteriorates and the maximum junction temperature (Tjmax) gradually increases, so the life in this test is defined as the state where the difference (ΔT) has increased by 20% from the start of current application. As mentioned above, if the minimum junction temperature is 65°C and the maximum junction temperature is 250°C, the difference (ΔT) is 185°C, so the life is defined as the state where the maximum junction temperature (Tjmax) reaches 287°C. This test is conducted in accordance with the inspection standard IEC60749 established by the International Organization for Standardization, so the life obtained can be compared using the same standard even for power module samples with different structures and manufacturing methods.

[0078] Figure 5 shows an example of the results of the power cycle test. Figure 5 shows the results of the power cycle test for a total of four types of samples (samples No. 1, No. 2, No. 3, and No. 4). In this power cycle test, diodes were used as samples. The horizontal axis of Figure 5 shows the number of times that the current was turned on and off, and the vertical axis shows the maximum junction temperature (Tjmax). The configurations of the buffer plate and buffer bonding material were different among the four types of samples, while the other conditions were the same. Table 1 shows an overview of the buffer plate and buffer bonding material of the four types of samples. Table 1 also shows the proportions of Ni and Co that make up the alloy layer. In addition, Table 1 also shows the number of cycles at which the difference (ΔT) increases by 20% (life).

[0079] [Table 1]

[0080] As shown in Figure 5 and Table 1, in sample No. 1, the material of the alloy layer was Invar, the Curie point was 280°C, and the porosity of the sintered body included in the buffer bonding material was 3%. The life was 19,700 cycles.

[0081] In sample No. 2, the material of the alloy layer was Kovar, the Curie point was 435°C, and the porosity of the sintered body included in the buffer bonding material was 3%. The lifespan was 45,400 times. The lifespan of sample No. 2 was 2.3 times that of sample No. 1.

[0082] In sample No. 3, the material of the alloy layer was Invar, the Curie point was 280°C, and the porosity of the sintered body included in the buffer bonding material was 30%. The lifespan was 49,900 times. The lifespan of sample No. 3 was 2.5 times that of sample No. 1.

[0083] In sample No. 4, the material of the alloy layer was Kovar, the Curie point was 435°C, and the porosity of the sintered body included in the buffer bonding material was 30%. The lifespan of sample No. 4 was 135,100 times. The lifespan of sample No. 4 was 6.8 times that of sample No. 1.

[0084] Thus, in samples No. 2, No. 3, and No. 4, in which the Curie point of the alloy layer is 300°C or higher or the sintered body contained in the buffer bonding material accounts for 5% to 40% at least, excellent life was obtained even under conditions in which the operating temperature was as high as 250°C.

[0085] Moreover, the life of sample No. 2 was 2.3 times that of sample No. 1, and the life of sample No. 3 was 2.5 times that of sample No. 1. By multiplying these results, it can be inferred that the life of sample No. 4 would be 5.75 times that of sample No. 1, but in reality it was 6.8 times, which was even longer. This demonstrates that the combination of an alloy layer Curie point of 300°C or higher and a sintered body with a porosity of 5% to 40% provides a greater effect than the combination of the effects of each.

[0086] In the present disclosure, the Curie point of the alloy layer or alloy material may be 350° C. or higher, or 400° C. or higher.

[0087] The porosity of a sintered body is defined as the ratio of the total area of ​​pores to the area of ​​the cross section of the buffer plate observed by an electron microscope. When observing the cross section, the cross section of the sample is usually mechanically polished, but great care must be taken not to block the pores. After mechanical polishing, surface damage can be removed by sputtering, or the accelerating voltage of the electron beam can be increased during observation by an electron microscope to eliminate the effects of the surface layer, making it easier to determine the porosity more accurately.

[0088] The porosity of the sintered body can be adjusted according to the applied pressure during the heat treatment in hydrogen gas to form the buffer bonding material. For example, when the applied pressure is 20 MPa, the porosity is about 3%, and when the applied pressure is 3 MPa, the porosity is about 30%.

[0089] In the present disclosure, an aluminum alloy layer may be used instead of the aluminum layer. The material used for the buffer bonding material is not limited. For example, the buffer bonding material may be made of a sintered body of an intermetallic compound containing copper, silver, nickel, or copper and tin. The sintered body of the intermetallic compound containing copper and tin is obtained by, for example, a transient liquid phase sintering method.

[0090] In the present disclosure, the semiconductor chip may be a silicon carbide chip. The silicon carbide chip has excellent high temperature resistance and is unlikely to break down even when used at high temperatures. The silicon carbide chip also has high mechanical properties. Furthermore, since internal destruction of the main electrode is suppressed, the semiconductor device as a whole is likely to have an excellent life even at high temperatures.

[0091] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0092] 1, 2 Semiconductor device 101, 102, 103 terminals 110 Substrate 111 First conductive pattern 112 Second conductive pattern 113 Third conductive pattern 114 Fourth conductive pattern 115 Conductive Layer 119 Insulating Substrate 120 Heat sink 131, 132, 133 Bonding material 134, 135 Buffer bonding material 161, 162, 163, 164, 165, 166: Wire 190 cases 191, 192 Side wall 193, 194 End wall 200 Transistors (Semiconductor Chips) 210 Silicon carbide substrate (semiconductor substrate) 210A, 210B main surface 231 Gate electrode 232 Source electrode (main electrode) 233 Drain electrode 300 Diode (semiconductor chip) 310 Silicon carbide substrate (semiconductor substrate) 310A, 310B main surface 332 Anode electrode (main electrode) 333 Cathode Electrode 400, 500 buffer plate 410, 510 First copper layer 420, 520 alloy layer 430, 530 Second copper layer

Claims

1. A semiconductor chip comprising a semiconductor substrate and a main electrode provided on the semiconductor substrate, Cushioning plate and A buffer bonding material provided between the main electrode and the buffer plate, A wire connected to the buffer plate, It has, The buffer plate is made of a laminated material or an alloy material with a Curie point of 300°C or higher. The aforementioned laminated material is The first copper layer in contact with the buffer bonding material, An alloy layer having a Curie point of 300°C or higher is provided on the first copper layer, A second copper layer provided on the alloy layer, A semiconductor device having

2. The semiconductor device according to claim 1, wherein the buffer bonding material has a sintered body with a porosity of 5% or more and 40% or less.

3. A semiconductor chip comprising a semiconductor substrate and a main electrode provided on the semiconductor substrate, Cushioning plate and A buffer bonding material provided between the main electrode and the buffer plate, It has, The buffer plate is made of a laminated material or an alloy material with a Curie point of 300°C or higher. The aforementioned laminated material is The first copper layer in contact with the buffer bonding material, An alloy layer having a Curie point of 300°C or higher is provided on the first copper layer, A second copper layer provided on the alloy layer, It has, The alloy material and the alloy layer contain iron and nickel. A semiconductor device wherein the proportion of nickel in the alloy material and the alloy layer is 40% by mass or more.

4. The alloy material and the alloy layer contain iron, nickel, and cobalt. The semiconductor device according to claim 1 or claim 2, wherein the total proportion of nickel and cobalt in the alloy material and the alloy layer is 40% by mass or more.

5. The buffer plate is the laminated material, The semiconductor device according to claim 1 or claim 2, wherein the wire is a copper wire and is connected to the second copper layer of the buffer plate.

6. The main electrode comprises an aluminum or aluminum alloy layer. The first linear expansion coefficient of the semiconductor substrate and the second linear expansion coefficient of the buffer plate are smaller than the third linear expansion coefficient of the main electrode. The semiconductor device according to claim 1 or claim 2, wherein the second coefficient of thermal expansion is smaller than the first coefficient of thermal expansion.

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