Semiconductor device

Abstract

To provide a semiconductor device with a novel structure.SOLUTION: A semiconductor device includes a CPU and an accelerator. The accelerator includes a first memory circuit, a driver circuit, and a product-sum operation circuit. The first memory circuit includes a first data retention portion, a second data retention portion, and a data reading portion. The first data retention portion, the second data retention portion, and the data reading portion each include a first transistor. The first transistor includes a first semiconductor layer containing a metal oxide in a channel formation region. First data retained in the first data retention portion and second data retained in the second data retention portion are each weight data input to the product-sum operation circuit. The product-sum operation circuit has a function of performing product-sum operation of the weight data and input data input through the driver circuit. The product-sum operation circuit and the driver circuit each include a second transistor. The second transistor includes a second semiconductor layer containing silicon in a channel formation region. The first transistor and the second transistor are stacked.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] This specification describes semiconductor devices and the like.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, an imaging device, a display device, a light-emitting device, a power storage device, a memory device, a display system, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. [Background technology]

[0003] Electronic devices having semiconductor devices including a CPU (Central Processing Unit) and the like are in widespread use. In order to process a large amount of data at high speed in such electronic devices, there has been active technological development to improve the performance of the semiconductor devices. One technology that achieves high performance is, for example, the so-called SoC (System on Chip) in which an accelerator such as a GPU (Graphics Processing Unit) is tightly coupled with a CPU. In a semiconductor device with high performance due to the SoC, heat generation and increased power consumption become problems.

[0004] In AI (Artificial Intelligence) technology, the amount of calculations and the number of parameters become enormous, so the amount of calculations increases. Since the increase in the amount of calculations leads to an increase in heat generation and power consumption, architectures for reducing the amount of calculations have been actively proposed. Representative architectures include the Binary Neural Network (BNN) and the Ternary Neural Network (TNN), which are particularly effective in reducing circuit scale and power consumption (see, for example, Patent Document 1).

[0005] For example, in a TNN, data originally expressed with 32-bit or 16-bit precision is compressed into three values, "+1," "0," or "-1," which can significantly reduce the amount of calculations and the number of parameters. In a BNN, data originally expressed with 32-bit or 16-bit precision is compressed into two values, "+1" or "-1," which can significantly reduce the amount of calculations and the number of parameters. BNNs and TNNs are effective in reducing circuit scale and power consumption, so they are considered to be compatible with applications that require low power consumption with limited hardware resources. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] International Publication No. 2019 / 078924 Summary of the Invention [Problem to be solved by the invention]

[0007] TNN uses ternary data for calculations. When ternary data is stored in a static RAM (SRAM), the number of transistors in a memory cell increases. This may make it difficult to miniaturize the semiconductor device. In addition, as transistors become more miniaturized, the power consumption associated with the leakage current of the transistors increases, which may contribute significantly to the power consumption of the entire semiconductor device.

[0008] In addition, in the multiplication and accumulation calculation of a fully connected neural network, data is read from memory frequently during calculation, so how to reduce the charge and discharge energy of the bit line is important in order to reduce power consumption. If the bit line is shortened to reduce the charge and discharge energy of the bit line, the area of ​​the memory cell array increases, which may significantly increase the area of ​​the peripheral circuits. In addition, if a technology for integrating the memory cell array in three dimensions using a bonding technique or the like is used to shorten the bit line, the spacing between the electrical connections is large, so parasitic capacitance may increase, making it impossible to reduce the charge and discharge energy.

[0009] An object of one embodiment of the present invention is to provide a miniaturized semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device with a novel structure.

[0010] Note that one embodiment of the present invention does not necessarily have to solve all of the above problems, but only needs to solve at least one of the problems. Furthermore, the description of the above problems does not preclude the existence of other problems. Problems other than these will become apparent from the description in the specification, claims, drawings, etc., and other problems can be extracted from the description in the specification, claims, drawings, etc. [Means for solving the problem]

[0011] One embodiment of the present invention is a semiconductor device including a CPU and an accelerator. The accelerator includes a first memory circuit, a driver circuit, and a product-sum operation circuit. The first memory circuit includes a first data retention unit, a second data retention unit, and a data reading unit. The first data retention unit, the second data retention unit, and the data reading unit each include a first transistor. The first transistor includes a first semiconductor layer having a metal oxide in a channel formation region. The first data held in the first data retention unit and the second data held in the second data retention unit are weight data input to a product-sum operation circuit. The product-sum operation circuit has a function of performing a product-sum operation on the weight data and input data input via the driver circuit. The product-sum operation circuit and the driver circuit each include a second transistor. The second transistor includes a second semiconductor layer having silicon in a channel formation region. The first transistor and the second transistor are stacked.

[0012] One embodiment of the present invention is a semiconductor device including a CPU and an accelerator. The accelerator includes a first memory circuit, a driver circuit, and a product-sum operation circuit. The first memory circuit includes a first data retention unit, a second data retention unit, and a data reading unit. Each of the first data retention unit, the second data retention unit, and the data reading unit includes a first transistor. The first transistor includes a first semiconductor layer having a metal oxide in a channel formation region. The first data held in the first data retention unit and the second data held in the second data retention unit are weight data input to a product-sum operation circuit. The product-sum operation circuit has a function of performing a product-sum operation on the weight data and input data input via the driver circuit. Each of the product-sum operation circuit and the driver circuit includes a second transistor. The second transistor includes a second semiconductor layer having silicon in a channel formation region, a well region having an impurity element that imparts conductivity, and an oxide layer provided in contact with the well region and the second semiconductor layer. The first transistor and the second transistor are stacked.

[0013] One embodiment of the present invention includes a CPU and an accelerator, the accelerator including a first memory circuit, a driver circuit, and a product-sum calculation circuit, the first memory circuit including a first data holding unit, a second data holding unit, and a data reading unit, the first data holding unit, the second data holding unit, and the data reading unit each including a first transistor, the first transistor including a first semiconductor layer having a metal oxide in a channel formation region, the first data held in the first data holding unit and the second data held in the second data holding unit being weight data input to the product-sum calculation circuit, and the product-sum calculation circuit including: The semiconductor device has a function of performing a multiplication and accumulation operation between weight data and input data input via a driving circuit, the multiplication and accumulation operation circuit and the driving circuit each having a second transistor, the second transistor having a second semiconductor layer having silicon in a channel formation region, the CPU has a CPU core having a flip-flop provided with a backup circuit, the backup circuit has a third transistor, the third transistor has a third semiconductor layer having a metal oxide in a channel formation region, and the first transistor, the third transistor, and the second transistor are stacked.

[0014] One embodiment of the present invention includes a CPU and an accelerator, the accelerator including a first memory circuit, a driver circuit, and a product-sum calculation circuit, the first memory circuit including a first data holding unit, a second data holding unit, and a data reading unit, the first data holding unit, the second data holding unit, and the data reading unit each including a first transistor, the first transistor including a first semiconductor layer having a metal oxide in a channel formation region, the first data held in the first data holding unit and the second data held in the second data holding unit being weight data input to the product-sum calculation circuit, the product-sum calculation circuit including the weight data, input data input via the driver circuit, a multiply-and-accumulate circuit and a drive circuit each having a second transistor, the second transistor having a second semiconductor layer having silicon in a channel formation region, a well region having an impurity element that imparts conductivity, and an oxide layer provided in contact with the well region and the second semiconductor layer, the CPU has a CPU core having a flip-flop provided with a backup circuit, the backup circuit has a third transistor, the third transistor has a third semiconductor layer having a metal oxide in a channel formation region, and the first transistor, the third transistor, and the second transistor are stacked.

[0015] In one embodiment of the present invention, the backup circuit is preferably a semiconductor device having a function of holding data held in a flip-flop in a state in which the supply of power supply voltage is stopped while the CPU is not operating.

[0016] In one aspect of the present invention, the semiconductor device is preferably such that the first data retention unit and the second data retention unit have a function of retaining the first data and the second data by making the first transistor non-conductive.

[0017] In one aspect of the present invention, a semiconductor device is preferred in which the first memory circuit is electrically connected to a first bit line for reading out the first data and a second bit line for reading out the second data, and the first bit line and the second bit line are electrically connected to a product-sum operation circuit via a first wiring provided perpendicular or approximately perpendicular to a substrate surface on which the second transistor is provided.

[0018] In one embodiment of the present invention, the metal oxide preferably contains In, Ga, and Zn.

[0019] Other aspects of the present invention will be described in the following embodiment and in the drawings. Effect of the Invention

[0020] According to one embodiment of the present invention, a miniaturized semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, a semiconductor device with a novel structure can be provided.

[0021] The description of multiple effects does not preclude the existence of other effects. In addition, one embodiment of the present invention does not necessarily have all of the exemplified effects. In addition, problems, effects, and novel features other than those described above regarding one embodiment of the present invention will become apparent from the description and drawings in this specification. [Brief description of the drawings]

[0022] [Figure 1] 1A and 1B are diagrams illustrating a configuration example of a semiconductor device. [Diagram 2] 2A and 2B are diagrams illustrating a configuration example of a semiconductor device. [Diagram 3] 3A, 3B, and 3C are diagrams for explaining configuration examples of a semiconductor device. [Figure 4] FIG. 4 is a diagram illustrating a configuration example of a semiconductor device. [Diagram 5]5A, 5B, and 5C are diagrams for explaining configuration examples of a semiconductor device. [Figure 6] 6A and 6B are diagrams illustrating a configuration example of a semiconductor device. [Figure 7] 7A and 7B are diagrams illustrating a configuration example of a semiconductor device. [Figure 8] 8A and 8B are diagrams illustrating a configuration example of a semiconductor device. [Figure 9] 9A and 9B are diagrams illustrating a configuration example of a semiconductor device. [Figure 10] 10A and 10B are diagrams illustrating a configuration example of a semiconductor device. [Figure 11] FIG. 11 is a diagram illustrating a configuration example of a semiconductor device. [Figure 12] FIG. 12 is a diagram illustrating an example of the configuration of the CPU. [Figure 13] 13A and 13B are diagrams for explaining an example of the configuration of a CPU. [Figure 14] FIG. 14 is a diagram illustrating an example of the configuration of the CPU. [Figure 15] FIG. 15 is a diagram illustrating a configuration example of a semiconductor device. [Figure 16] 16A and 16B are diagrams showing configuration examples of transistors. [Figure 17] 17A to 17C are diagrams showing configuration examples of transistors. [Figure 18] 18A to 18C are diagrams showing configuration examples of transistors. [Figure 19] Fig. 19A is a diagram for explaining the classification of IGZO crystal structures, Fig. 19B is a diagram for explaining the XRD spectrum of a CAAC-IGZO film, and Fig. 19C is a diagram for explaining the ultrafine electron beam diffraction pattern of a CAAC-IGZO film. [Figure 20] FIG. 20 is a diagram for explaining a configuration example of an integrated circuit. [Figure 21] 21A and 21B are diagrams for explaining a configuration example of an integrated circuit. [Figure 22]22A and 22B are diagrams for explaining an application example of an integrated circuit. [Diagram 23] 23A and 23B are diagrams for explaining an application example of an integrated circuit. [Figure 24] 24A, 24B, and 24C are diagrams for explaining an application example of an integrated circuit. [Diagram 25] FIG. 25 is a diagram for explaining an application example of an integrated circuit. [Figure 26] FIG. 26 is a diagram for explaining an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] The following describes an embodiment of the present invention. However, one embodiment of the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the embodiment and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention should not be interpreted as being limited to the description of the embodiment shown below.

[0024] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0025] In the drawings, the same elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same reference numerals, and repeated description thereof may be omitted.

[0026] In this specification, for example, the power supply potential VDD may be abbreviated to potential VDD, VDD, etc. This also applies to other components (for example, signals, voltages, circuits, elements, electrodes, wiring, etc.).

[0027] Furthermore, when the same reference symbol is used for multiple elements, particularly when it is necessary to distinguish between them, identification symbols such as “_1”, “_2”, "[n]”, "[m,n]”, etc. may be added to the reference symbol. For example, the second wiring GL is written as wiring GL[0].

[0028] (Embodiment 1) The structure, operation, and the like of a semiconductor device according to one embodiment of the present invention will be described.

[0029] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0030] 1A and 1B are diagrams for explaining a semiconductor device 100 according to an embodiment of the present invention. In the semiconductor device 100 in FIG. 1A and FIG. 1B, a CPU 10, an accelerator 20, and a bus 30 are illustrated as an example. The CPU 10 has a CPU core 11 and a backup circuit 12. The accelerator 20 has a drive circuit 15, an arithmetic processing unit 21, and memory units 22_1 to 22_N (N is a natural number). The drive circuit 15 is a circuit for driving the memory unit 22. The arithmetic processing unit 21 has arithmetic circuits 23_1 to 23_N. The drive circuit 15 is a circuit for driving the memory units 22_1 to 22_N and the arithmetic processing unit 21. The memory units 22_1 to 22_N each have a memory circuit 24. The memory units 22_1 to 22_N may be referred to as device memories or shared memories. The memory circuit 24 has a transistor 25 having a semiconductor layer 29 having a channel formation region.

[0031] The CPU 10 has a function of performing general-purpose processing such as executing an operating system, controlling data, and executing various calculations and programs. The CPU 10 has a CPU core 11. The CPU core 11 corresponds to one or more CPU cores. The CPU 10 also has a backup circuit 12 that can hold data in the CPU core 11 even if the supply of power voltage is stopped. The supply of power voltage can be controlled by electrically disconnecting it from the power domain using a power switch or the like. The power voltage may also be called a drive voltage. As the backup circuit 12, for example, a memory having a transistor (OS transistor) having an oxide semiconductor in its channel formation region is suitable.

[0032] The backup circuit 12, which is made up of OS transistors, can be stacked with the CPU core 11, which can be made up of Si CMOS. Since the area of ​​the backup circuit 12 is smaller than the area of ​​the CPU core 11, the backup circuit 12 can be placed on the CPU core without increasing the circuit area. The backup circuit 12 has a function of retaining data in the registers of the CPU core 11. The backup circuit 12 is also called a data retention circuit.

[0033] The details of the configuration of CPU core 11 including backup circuit 12 having OS transistors will also be described in the third embodiment.

[0034] The accelerator 20 has a function of executing a program (also called a kernel or a kernel program) called from a host program. The accelerator 20 can perform, for example, parallel processing of matrix operations in graphic processing, parallel processing of product-sum operations in neural networks, and parallel processing of floating-point operations in scientific and technological calculations.

[0035] The memory units 22_1 to 22_N have a function of storing data to be processed by the accelerator 20. Specifically, weight data W1 to W2 used for parallel processing of product-sum operations of a neural network are stored in the memory units 22_1 to 22_N. N The weight data W1 to W N is data expressed by three values, "+1", "0" or "-1", used in TNN. The memory circuit 24 of the memory units 22_1 to 22_N has a function of holding three-value data by holding two voltage values ​​in two data holding units. Note that the data is not limited to three values, and four or more values ​​are also possible.

[0036] The arithmetic processing unit 21 and the memory units 22_1 to 22_N are connected via bit lines PBL and bit lines NBL. Any one of the memory units 22_1 to 22_N has a memory circuit 24 connected to a pair of bit lines PBL and NBL. Note that the pair of bit lines PBL and NBL may be abbreviated to bit lines BL. Each pair of bit lines PBL and NBL is connected to any one of the arithmetic circuits 23_1 to 23_N. The pair of bit lines PBL and NBL transmits weight data W1 to W2. N from the memory unit 22 (any one of the memory units 22_1 to 22_N is referred to as the memory unit 22) to the arithmetic circuit 23 (any one of the arithmetic circuits 23_1 to 23_N is referred to as the arithmetic circuit 23).

[0037] The driving circuit 15 and the arithmetic processing unit 21 are connected to a data input line A IN Any one of the arithmetic circuits 23_1 to 23_N is connected via a data input line A IN Input data A1 to A N Any one of the input data A1 to A N is the binary data used in TNN, either "+1" or "-1". Data input line A IN The input data A1 to A N This configuration allows the arithmetic processing unit 21 to efficiently perform arithmetic processing based on an architecture such as a Ternary Neural Network (TNN).

[0038] In the memory circuit 24, the semiconductor layer 29 of the transistor 25 is an oxide semiconductor. That is, the transistor 25 is an OS transistor. The memory circuit 24 is preferably a memory including an OS transistor (hereinafter also referred to as an OS memory). The OS memory has a function of holding charge according to a voltage value by turning off the OS transistor.

[0039] Since the band gap of metal oxide is 2.5 eV or more, OS transistors have extremely small off-state current. For example, when the voltage between the source and drain is 3.5 V and the temperature is at room temperature (25 °C), the off-state current per 1 μm of channel width is 1 × 10 -20 Less than A, 1×10 -22 Less than A or 1×10 -24 A or less. That is, the on / off current ratio of the drain current can be set to 20 to 150 digits. Therefore, the amount of charge leaked from the retention node through the OS transistor is extremely small. Therefore, the OS memory can function as a non-volatile memory circuit, which enables power gating of the accelerator.

[0040] High-density integrated semiconductor devices may generate heat due to the operation of the circuits. This heat increases the temperature of the transistor, which may change the characteristics of the transistor, causing a change in field-effect mobility and a decrease in operating frequency. OS transistors have higher heat resistance than Si transistors, so that the field-effect mobility is less likely to change due to temperature changes and the operating frequency is less likely to decrease. Furthermore, OS transistors tend to maintain the characteristic that the drain current increases exponentially with respect to the gate-source voltage, even when the temperature rises. Therefore, the use of OS transistors allows stable operation in high temperature environments.

[0041] Metal oxides applicable to OS transistors include Zn oxide, Zn-Sn oxide, Ga-Sn oxide, In-Ga oxide, In-Zn oxide, and In-M-Zn oxide (M is one or more selected from Ti, Ga, Y, Zr, La, Ce, Nd, Sn, and Hf). In particular, metal oxides using Ga as M are preferably used for OS transistors because they can be made into transistors with excellent electrical characteristics such as field-effect mobility by adjusting the ratio of elements. In addition, the oxide containing indium and zinc may contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0042] In order to improve the reliability and electrical characteristics of an OS transistor, the metal oxide applied to the semiconductor layer is preferably a metal oxide having a crystalline part, such as CAAC-OS, CAC-OS, or nc-OS. CAAC-OS is an abbreviation for c-axis-aligned crystalline oxide semiconductor. CAC-OS is an abbreviation for cloud-aligned composite oxide semiconductor. nc-OS is an abbreviation for nanocrystalline oxide semiconductor.

[0043] CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distortion refers to a location where the lattice orientation changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple nanocrystals are connected.

[0044] CAC-OS has the function of flowing electrons (or holes) that act as carriers, and the function of not flowing electrons that act as carriers. By separating the function of flowing electrons from the function of not flowing electrons, it is possible to maximize both functions. In other words, by using CAC-OS in the channel formation region of an OS transistor, it is possible to achieve both a high on-current and an extremely low off-current.

[0045] Metal oxides have a large band gap, electrons are less likely to be excited, and the effective mass of holes is large, so that OS transistors are less likely to experience avalanche breakdown and the like compared to general Si transistors. Therefore, for example, hot carrier degradation caused by avalanche breakdown can be suppressed. Suppressing hot carrier degradation allows OS transistors to be driven at a high drain voltage.

[0046] OS transistors are accumulation-type transistors that use electrons as majority carriers. Therefore, they are less susceptible to drain-induced barrier lowering (DIBL), which is one of the short-channel effects, compared to inversion-type transistors (typically, Si transistors) that have a pn junction. In other words, OS transistors have higher resistance to short-channel effects than Si transistors.

[0047] Because OS transistors have high resistance to short channel effects, their channel length can be reduced without degrading their reliability, and so their use can increase the degree of circuit integration. As the channel length is reduced, the drain electric field becomes stronger, but as mentioned above, OS transistors are less susceptible to avalanche breakdown than Si transistors.

[0048] In addition, because OS transistors have high resistance to short channel effects, it is possible to make the gate insulating film thicker than that of Si transistors. For example, even in a minute transistor with a channel length and width of 50 nm or less, it may be possible to provide a thick gate insulating film of about 10 nm. By making the gate insulating film thicker, the parasitic capacitance can be reduced, thereby improving the operating speed of the circuit. Furthermore, by making the gate insulating film thicker, the leakage current through the gate insulating film is reduced, which leads to a reduction in static current consumption.

[0049] As described above, the accelerator 20 can retain data even when the supply of power supply voltage is stopped by having the memory circuit 24, which is an OS memory. This enables power gating of the accelerator 20, and allows a significant reduction in power consumption.

[0050] The memory circuit 24 configured with OS transistors can be stacked with the arithmetic circuit 23 that can be configured with Si CMOS, and therefore can be arranged without increasing the circuit area.

[0051] The memory circuit 24 preferably has a circuit configuration of NOSRAM. "NOSRAM (registered trademark)" is an abbreviation of "Nonvolatile Oxide Semiconductor RAM". NOSRAM refers to a memory in which the memory cell is a two-transistor type (2T) or three-transistor type (3T) gain cell, and the access transistor is an OS transistor. The current that flows between the source and drain in the off state, that is, the leakage current, is extremely small. NOSRAM can be used as a nonvolatile memory by retaining a charge according to data in the memory circuit using the characteristic of extremely small leakage current. In particular, NOSRAM can read the retained data without destroying it (nondestructive read), so it is suitable for parallel processing of product-sum operations of neural networks, which repeats a large amount of data read operations only.

[0052] The arithmetic processing unit 21 has a function of performing arithmetic processing using digital values. Digital values ​​are not easily affected by noise. Therefore, the accelerator 20 is suitable for performing arithmetic processing that requires highly accurate arithmetic results. The arithmetic processing unit 21 is preferably configured with a Si CMOS, that is, a transistor having silicon in a channel formation region (Si transistor). With this configuration, it can be stacked with an OS transistor.

[0053] The driving circuit 15 has a function of storing weight data in the memory units 22_1 to 22_N, and also has a function of providing input data to the arithmetic circuits 23_1 to 23_N to execute product-sum operations of the neural network, etc.

[0054] The memory circuit 24, which is made up of OS transistors, and the arithmetic circuits 23_1 to 23_N are electrically connected via bit lines NBL and PBL, which are provided extending in a direction approximately perpendicular to the substrate surface on which the driving circuit 15 and the arithmetic circuits 23_1 to 23_N are provided. Note that "approximately perpendicular" refers to a state in which they are arranged at an angle of 85 degrees or more and 95 degrees or less. Note that in this specification, the X direction, Y direction, and Z direction illustrated in FIG. 1B and the like are directions that are orthogonal to or intersect with each other. Also, the X direction and the Y direction are parallel or approximately parallel to the substrate surface, and the Z direction is perpendicular or approximately perpendicular to the substrate surface.

[0055] The arithmetic circuits 23_1 to 23_N receive input data A1 to A N and weight data W1 to W N The arithmetic circuit 23 has a function of repeatedly executing the same process such as a multiply-and-accumulate operation.

[0056] The arithmetic circuits 23_1 to 23_N are configured to provide one arithmetic circuit 23 for each bit line NBL and bit line PBL of the memory circuit 24, that is, for each column (Column-Parallel Calculation). This configuration allows data for one row (maximum all bit lines) of the memory circuit 24 to be arithmetically processed in parallel. Compared with the multiply-and-accumulate operation using the CPU 10, Column-Parallel Calculation is not limited by the data bus size (32 bits, etc.) between the CPU and the memory, so that the degree of parallelism of the operation can be significantly increased, and the efficiency of calculations related to massive calculation processing such as learning (deep learning) of deep neural networks, which is an AI technology, and scientific and technological calculations that perform floating-point calculations can be improved. In addition, since the calculation of data output from the memory circuit 24 can be completed and read out, the power generated by memory access (data transfer between the CPU and memory and calculations by the CPU) can be reduced, and the increase in heat generation and power consumption can be suppressed. Furthermore, by shortening the physical distance between one arithmetic circuit 23 and memory circuit 24, for example by stacking the circuits, the wiring distance can be shortened, thereby reducing the parasitic capacitance generated in the signal lines, and thus reducing power consumption.

[0057] In the arithmetic circuits 23_1 to 23_N, the semiconductor layers of the transistors constituting the circuits are silicon. A transistor having silicon as a semiconductor layer is called a Si transistor. The Si transistor is preferably formed using an SOI substrate having an insulating layer (also called a BOX layer) formed in a silicon substrate by buried oxidation (Burried oxide) and single crystal silicon on the insulating layer. The silicon substrate is, for example, a p-type single crystal silicon substrate.

[0058] A well region to which an impurity element that imparts conductivity is added can be provided on the silicon substrate in the region where the Si transistor is provided. The well region can function as a bottom gate electrode by independently changing the potential of the well region. Therefore, the threshold voltage of the Si transistor can be controlled. In particular, by applying a negative potential to the well region, the threshold voltage of the Si transistor can be increased and the off-current can be reduced. Therefore, by applying a negative potential to the well region, the drain current when the potential applied to the gate electrode of the Si transistor is 0 V can be reduced. In addition, since it is not necessary to add an impurity element to the channel formation region for the purpose of controlling the threshold voltage, the variation in the threshold voltage can be reduced and the power supply voltage can be lowered. As a result, the power consumption in the arithmetic circuits 23_1 to 23_N can be reduced and the arithmetic efficiency can be improved.

[0059] The bus 30 electrically connects the CPU 10 and the accelerator 20. That is, the CPU 10 and the accelerator 20 can transmit data via the bus 30.

[0060] Next, advantages of the configurations of Figures 1A and 1B will be described. Figure 2A is a schematic diagram of a plan view of the schematic diagram of Figure 1B seen from the z direction. In Figure 2A, six arithmetic circuits 23_1 to 23_6 are arranged in the y direction, and six memory units 22_1 to 22_6 are illustrated so as to overlap in the z direction. Also, in Figure 2A, the data input line A IN 1 shows a driver circuit 15 which supplies input data A1 to A6 to six arithmetic circuits 23_1 to 23_6 via the driver circuits 15a to 15c.

[0061] In the arithmetic circuits 23_1 to 23_6 in FIG. 2A, data W (W1 to W6) expressed by three values ​​based on data of a pair of bit lines NBL and PBL, and data input line A IN Then, output signals Y1 to Y6 corresponding to the product (=W×A) of input data A (A1 to A6) and are obtained.

[0062] In addition, in FIG. 2A, the arithmetic circuits 23_1 to 23_6 are connected to the memory units 22_1 to 22_6 by bit lines NBL and PBL (illustrated as one opening in FIG. 2A), respectively. That is, they are illustrated as being connected via wiring extending in the z direction. That is, the arithmetic circuits 23_1 to 23_6 and the memory units 22_1 to 22_6 can be arranged at a short distance by the bit lines NBL and PBL. Therefore, the parasitic capacitance between the bit lines NBL and PBL and other elements can be reduced. Therefore, the charge due to charging and discharging of the bit lines can be reduced, and it is possible to achieve low power consumption and improved arithmetic efficiency.

[0063] In addition, in the configuration of FIG. 2A, all the transistors of the memory units 22_1 to 22_6 are OS transistors, so they can be stacked on the arithmetic circuits 23_1 to 23_6 that are configured with Si transistors. Therefore, the arithmetic circuits and the memory units can be arranged so as to overlap each other, so that the circuit area that is increased by arranging the memory units can be reduced. Therefore, the semiconductor device can be made smaller. In addition, the data input line A extending from the driver circuit 15 IN can be shortened.

[0064] 2B shows a schematic diagram of the case where the arithmetic circuits 23_1 to 23_6 and the memory units 22_1 to 22_6 are arranged alternately in the y direction in the same manner as in FIG. 2A. The example of FIG. 2B shows a case where the memory circuit is configured with Si transistors so that the data retention circuit of the memory circuit is an SRAM (Static RAM). Therefore, the arithmetic processing unit and the memory unit are not arranged overlapping each other as in FIG. 2A, but are arranged side by side on a plane.

[0065] In FIG. 2B, the arithmetic circuits 23_1 to 23_6 are connected to each other by bit lines NBL and PBL (illustrated as one wiring in FIG. 2A) extending from the memory units 22_1 to 22_6 adjacent to each other. That is, the arithmetic circuits 23_1 to 23_6 are illustrated as being connected to each other via wiring extending in the y direction. That is, the bit lines NBL and PBL enable the arithmetic circuits 23_1 to 23_6 and the memory units 22_1 to 22_6 to be arranged at a longer distance than in the z direction. Therefore, the parasitic capacitance between the bit lines NBL and PBL and other elements increases. Therefore, the charge due to charging and discharging of the bit lines increases. Therefore, the configuration of one embodiment of the present invention illustrated in FIG. 2A can be said to be excellent in terms of miniaturization and low power consumption.

[0066] One embodiment of the present invention can provide a miniaturized semiconductor device including an accelerator and a CPU. Alternatively, one embodiment of the present invention can provide a semiconductor device including an accelerator and a CPU with reduced power consumption. Alternatively, one embodiment of the present invention can provide a semiconductor device in which the number of data transfers in the CPU is reduced. Alternatively, a semiconductor device having a novel structure can be provided. The semiconductor device of one embodiment of the present invention has a non-von Neumann architecture and can perform parallel processing with extremely low power consumption compared to a von Neumann architecture in which power consumption increases as the processing speed increases.

[0067] Fig. 3A is a diagram explaining the relationship between processing power (OPS: Operations Per Second) and power consumption (W). In Fig. 3A, the vertical axis represents processing power, and the horizontal axis represents power consumption. Fig. 3A also indicates 0.1 TOPS / W (Tera Operations Per Second / W), 1 TOPS / W, 10 TOPS / W, 100 TOPS / W, and 1 POPS / W (Pera Operations Per Second / W) with dashed lines as indexes of computing efficiency.

[0068] 3A , a region 910 includes a conventional general-purpose AI accelerator (von Neumann type), and a region 912 includes a semiconductor device of one embodiment of the present invention. Note that the region 910 includes, for example, a central processing unit (CPU), a graphics processing unit (GPU), a field-programmable gate array (FPGA), and the like.

[0069] 3A, by applying the semiconductor device of one embodiment of the present invention, power consumption can be reduced by about two orders of magnitude and processing performance can be improved significantly (for example, 1000 times or more) as compared to a conventional general-purpose AI accelerator (von Neumann type). Note that by applying the semiconductor device of one embodiment of the present invention, computing efficiency of 100 TOPS / W or more can be expected.

[0070] Here, specific examples of a conventional configuration and a configuration to which a semiconductor device of one embodiment of the present invention is applied will be described with reference to Fig. 3B and Fig. 3C. Fig. 3B illustrates an image of power consumption in image recognition by a semiconductor device having a conventional configuration, and Fig. 3C illustrates an image of power consumption in image recognition by a semiconductor device using the configuration of one embodiment of the present invention.

[0071] In Figures 3B and 3C, the vertical axis represents power and the horizontal axis represents time. In Figure 3B, power 914 represents leakage power, power 916 represents CPU power (power consumption of the CPU), and power 918 represents memory power. In Figure 3C, power 914 represents leakage power, power 920 represents CPU power, and power 922 represents accelerator power (power consumption of the accelerator). Power 922 includes power used in the arithmetic circuit and memory circuit.

[0072] 3B and 3C, arrows a, b, and c respectively represent signals in image recognition. It is assumed that when the signals of arrows a, b, and c are input, arithmetic processing such as image recognition is started in the semiconductor device.

[0073] As shown in FIG. 3B, in the case of a semiconductor device having a conventional configuration, a constant leakage power (power 914) occurs over time. On the other hand, as shown in FIG. 3C, in the case of a configuration in which a semiconductor device according to one embodiment of the present invention is applied, leakage power (power 914) occurs while CPU power (power 920) and accelerator power (power 922) are being used, but during a period in which CPU power (power 920) and accelerator power (power 922) are not being used, normally-off drive (period t1 shown in FIG. 3C) in which leakage power (power 914) does not occur can be achieved. This makes it possible to significantly reduce power consumption. In other words, a semiconductor device with extremely low power consumption can be provided.

[0074] FIG. 4 shows a graph comparing the read energy and the relative cost per 1 Gbit (1 Gbit / cost) in the NOSRAM, DRAM (Dynamic RAM), SRAM (Static RAM), and flash memory (flash) included in a NOSRAM, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an FPGA (Field-Programmable Gate Array), etc. included in a semiconductor device according to one embodiment of the present invention described in FIG. 3A.

[0075] Flash memory has a high relative cost per Gbit, but a high read energy of 100 pJ. DRAM has a lower relative cost per Gbit than flash memory, but a low read energy. SRAM has a significantly lower relative cost per Gbit than DRAM and flash memory, but a significantly low read energy. Compared to flash memory, DRAM, and SRAM, the NOSRAM included in the semiconductor device of one embodiment of the present invention has an extremely low read energy and is also superior to SRAM in relative cost per Gbit. Therefore, when aiming for a computing efficiency exceeding 100 TOPS / W as described with reference to FIG. 3A, a semiconductor device including NOSRAM is suitable.

[0076] Fig. 5A is a diagram for explaining an example of a circuit configuration applicable to memory units 22_1 to 22_N included in the semiconductor device 100 of the present invention. Fig. 5A illustrates bit lines PBL_1 to PBL_N, bit lines NBL_1 to NBL_N, and word lines WL_1 to WL_M (M is a natural number) arranged in a matrix direction of M rows and N columns (M and N are natural numbers of 2 or more). Also illustrated is a memory circuit 24 connected to each word line and bit line.

[0077] 5B is a diagram illustrating an example of a circuit configuration applicable to the memory circuit 24. The memory circuit 24 has a data retention circuit 31_P, a data retention circuit 31_N, a transistor 32_P, a transistor 32_N, a transistor 33_P, and a transistor 33_N.

[0078] Each transistor in the memory circuit 24 may have a backgate. In this case, the backgate may be connected to the gate, or may be given a potential different from that of the gate to control the electrical characteristics of the transistor.

[0079] The data retention circuit 31_P is connected to a node MN_P of a wiring connected to a gate of the transistor 32_P. One of the source or drain of the transistor 32_P is connected to a fixed potential such as GND. One of the source or drain of the transistor 33_P is connected to the other of the source or drain of the transistor 32_P. One of the source or drain of the transistor 33_P is connected to a bit line PBL. The gate of the transistor 33_P is connected to a word line WL.

[0080] The data retention circuit 31_N is connected to a node MN_N of a wiring connected to a gate of the transistor 32_N. One of the source or drain of the transistor 32_N is connected to a fixed potential such as GND. One of the source or drain of the transistor 33_N is connected to the other of the source or drain of the transistor 32_N. One of the source or drain of the transistor 33_N is connected to a bit line NBL. The gate of the transistor 33_N is connected to a word line WL.

[0081] Data retention circuit 31_P and data retention circuit 31_N each have a function of retaining a signal corresponding to a voltage of H level or L level. Fig. 5C illustrates a circuit configuration of data retention circuit 31 applicable to data retention circuit 31_P and data retention circuit 31_N in Fig. 5B.

[0082] The data retention circuit 31, including the transistor 32 applicable to the transistors 32_P and 32_N and the transistor 33 applicable to the transistors 33_P and 33_N, corresponds to a NOSRAM of a three-transistor type (3T) gain cell. That is, the data retention circuit 31 has a transistor 34 and a capacitance element 35 as shown in FIG. 5C. Each transistor shown in FIG. 5C is an OS transistor. In the off state, the current flowing between the source and drain, that is, the leakage current, is extremely small. The NOSRAM can be used as a non-volatile memory by using the characteristic of extremely small leakage current to hold a charge corresponding to data in the node MN in the memory circuit 24. The voltage of the node MN is a voltage held by the data retention circuit 31. The voltage held by the data retention circuit 31 is given by a signal MBL. The signal MBL may be configured to be written to the node MN at the timing controlled by the signal MWL given to the gate of the transistor 34. In addition, NOSRAM with a three-transistor (3T) gain cell is capable of holding two or more voltage values, such as five or seven values.

[0083] FIG. 6A shows the circuit configuration of the memory circuit 24 in which the circuit configuration of the data retention circuit 31 in FIG. 5C is applied to FIG. 5B. The truth table of each signal shown in FIG. 6A is as shown in Table 1. In Table 1, the H level and L level voltages are expressed as logic "1" and "0". "Cell P" corresponds to the logic corresponding to the voltage held by node MN_P, that is, data retention circuit 31_P. "Cell N" corresponds to the logic corresponding to the voltage held by node MN_N, that is, data retention circuit 31_N. "W" is data determined by the logic of bit lines NBL and PBL, and is data expressed as three values ​​of "0", "+1" or "-1" used for TNN. Prohibition is expressed by "x".

[0084] [Table 1]

[0085] In the configuration of Fig. 6A, if the voltage of the H level of the node MN_P is held, and the fixed potential of either the source or the drain of the node MN_N is set to the ground potential (voltage of the L level), the voltage read out to the bit line PBL becomes the L level, and the held voltage and the read voltage are inverted. Therefore, it is preferable to have a configuration in which the node MN_P and the gate of the transistor 32_N, and the node MN_N and the gate of the transistor 32_P are connected as shown in Fig. 6B. The truth table of each signal shown in Fig. 6B is as shown in Table 2.

[0086] [Table 2]

[0087] Note that Fig. 6A can be modified to the circuit configuration of Fig. 7A. As shown in Fig. 7A, transistors 33_P and 33_N are replaced with transistor 34, and the connections between the wiring and the transistors are changed. In the circuit configuration of Fig. 7A, the data of the truth table shown in Table 1 can be obtained.

[0088] Similarly, Fig. 6B can be modified to the circuit configuration of Fig. 7B. As shown in Fig. 7B, transistors 33_P and 33_N are replaced with transistor 34, and the connections between the wiring and the transistors are changed. In the circuit configuration of Fig. 7B, the data of the truth table shown in Table 2 can be obtained.

[0089] 8A is a diagram for explaining an example of a circuit configuration applicable to the arithmetic processing unit 21 included in the semiconductor device 100 of the present invention. The arithmetic processing unit 21 has arithmetic circuits 23_1 to 23_N. Each of the N arithmetic circuits 23_1 to 23_N is connected to any one of the N bit lines PBL_1 to PBL_N, any one of the N bit lines NBL_1 to NBL_N, and a data input line A IN Input data A1 to A N The output signals Q_1 to Q_N are the data held in the memory circuit 24 and the data input line A. IN This corresponds to data obtained by performing a product-sum operation using data input from the driver circuit 15 via the .

[0090] FIG. 8B is a diagram for explaining a circuit configuration example of the arithmetic circuit 23 applicable to the arithmetic circuits 23_1 to 23_N. FIG. 8B is a circuit for executing arithmetic processing based on the architecture of the TNN. The arithmetic circuit 23 has a logic circuit 42 for performing product-sum operations, an accumulator 43, a latch circuit 44, and an encoding circuit 45 for outputting an output signal Q. The logic circuit 42 is connected to any one of N bit lines PBL_1 to PBL_N (data PBL in the figure), any one of N bit lines NBL_1 to NBL_N (data NBL in the figure), and a data input line A. IN Input data A1 to A N The signal of either one of the above (data A in the figure) is input. From the data PBL and data NBL, data W expressed as ternary values ​​of "0", "+1" or "-1" is output, along with data A expressed as binary values ​​of "+1" or "-1", which is the product (=W x A) of the two, data Y.

[0091] The truth table for each signal in the logic circuit in Figure 8A is shown in Table 3. In Table 3, "+1" in data A is represented as "(0)", and "-1" in data A is represented as "(1)", a 1-bit digital signal. In Table 3, "0" in data Y is represented as "(00)", "+1" in data Y is represented as "(01)", and "-1" in data Y is represented as "(11)", a 2-bit digital signal. Prohibition is represented as "x".

[0092] [Table 3]

[0093] In Figures 8A and 8B, memory access selects one row per clock, so M (=1 bit x M rows) products and their sums are executed in M ​​clocks. In the arithmetic circuit of Figures 8A and 8B, the same M products and their sums can be executed in N parallel x 1 bit x M / N rows, so M / N clocks are required. Therefore, the configurations of Figures 8A and 8B can reduce the calculation time by executing product-sum operations in parallel, thereby improving calculation efficiency.

[0094] FIG. 9A illustrates a hierarchical neural network. FIG. 9A illustrates a fully connected neural network consisting of a neuron 50, one input layer (I1), three intermediate layers (M1 to M3), and one output layer (O1). If the number of neurons in the input layer I1 is 786, the number of neurons in the intermediate layers M1 to M3 is 256, and the number of neurons in the output layer O1 is 10, the number of connections in each layer (layer 51, layer 52, layer 53, and layer 54) is (786×256)+(256×256)+(256×256)+(256×10), which is a total of 334336. In other words, the weight parameters required for neural network calculations are about 330K bits in total, so that the memory capacity can be sufficiently implemented even in a small-scale system.

[0095] Next, FIG. 9B shows a detailed block diagram of a semiconductor device 100 capable of performing the neural network calculations shown in FIG. 9A.

[0096] Figure 9B illustrates an example configuration of the driving circuit 15 illustrated in Figures 1A and 1B, in addition to the arithmetic processing unit 21, the arithmetic circuit 23 corresponding to the arithmetic circuits 23_1 to 23_N, the memory unit 22 corresponding to the memory units 22_1 to 22_N, the memory circuit 24, and the bit lines NBL and PBL, all of which are described in Figures 1A and 1B.

[0097] FIG. 9B illustrates a controller 61, a row decoder 62, a word line driver 63, a column decoder 64, a write driver 65, a precharge circuit 66, an input buffer 71, and an arithmetic control circuit 72 as components corresponding to the drive circuit 15 described in FIG. 1A and FIG. 1B.

[0098] Fig. 10A is a diagram in which blocks that control the memory unit 22 are extracted from each configuration shown in Fig. 9B. In Fig. 10A, a controller 61, a row decoder 62, a word line driver 63, a column decoder 64, a write driver 65, and a precharge circuit 66 are extracted and illustrated.

[0099] The controller 61 processes an external input signal to generate control signals for the row decoder 62 and the column decoder 64. The external input signal is a control signal for controlling the memory unit 22, such as a write enable signal or a read enable signal. The controller 61 also inputs and outputs data to be written to the memory unit 22 or data to be read from the memory unit 22, between the controller 61 and the CPU 10 via a bus.

[0100] The row decoder 62 generates signals for driving the word line driver 63. The word line driver 63 generates signals for the word lines WL as well as signals MWL for the data hold circuits 31_P and 31_N. The column decoder 64 generates signals for driving the write driver 65. The write driver 65 generates signals MBL for the data hold circuits 31_P and 31_N as well as signals ABL for the data input lines ABL. IN Input data A1 to A N The precharge circuit 66 has a function of precharging the bit lines NBL, PBL, etc. A signal read from the memory circuit 24 of the memory unit 22 is input to the arithmetic circuit 23 via the bit lines NBL, PBL.

[0101] FIG. 10B is a diagram illustrating blocks that control the arithmetic processing unit 21 in each configuration illustrated in FIG. 9B.

[0102] The controller 61 processes an input signal from the outside and generates a control signal for the arithmetic control circuit 72. The controller 61 also generates various signals such as a clock signal for controlling the arithmetic circuit 23 of the arithmetic processing unit 21. The arithmetic control circuit 72 controls the data input line A in response to the control of the controller 61 and the output of the input buffer 71. IN Input data A1 to A N The calculation processing unit 21 re-inputs data related to the calculation result to the calculation processing unit 21 via the input buffer 71 and the calculation control circuit 72. The calculation processing unit 21 processes data according to the calculation result using the buffer memory in the input buffer 71, thereby enabling parallel calculation of a number of bits greater than the data bus width of the CPU without reading data during the calculation to a main memory outside the accelerator. In addition, the number of times a huge number of weight parameters are transferred between the accelerator 10 and the calculation processing unit 21 can be reduced, thereby achieving low power consumption.

[0103] As described above, one embodiment of the present invention can provide a semiconductor device including an accelerator and a CPU that is miniaturized. Alternatively, one embodiment of the present invention can provide a semiconductor device including an accelerator and a CPU that consumes less power. Alternatively, one embodiment of the present invention can provide a semiconductor device in which the number of data transfers in the CPU is reduced. Alternatively, a semiconductor device with a novel structure can be provided.

[0104] (Embodiment 2) In this embodiment, an example of an operation in the case where part of the calculations of the program executed by the CPU 10 described in the above embodiment is executed by the accelerator 20 will be described.

[0105] FIG. 11 is a diagram for explaining an example of an operation when part of the calculations of a program executed by a CPU is executed by an accelerator.

[0106] The host program is executed by the CPU (step S1).

[0107] When the CPU confirms an instruction to reserve a data area required for performing a calculation using the accelerator in the memory section (step S2), the CPU reserves the data area in the memory section (step S3).

[0108] Next, the CPU transmits input data from the main memory to the memory unit (step S4). The memory unit receives the input data and stores the input data in the area secured in step S2 (step S5).

[0109] When the CPU confirms an instruction to start the kernel program (step S6), the accelerator starts executing the kernel program (step S7).

[0110] Immediately after the accelerator starts executing the kernel program, the CPU may be switched from a state in which it performs calculations to a PG state (step S8). In this case, the CPU is switched from the PG state to a state in which it performs calculations immediately before the accelerator finishes executing the kernel program (step S9). By keeping the CPU in the PG state during the period from step S8 to step S9, it is possible to suppress power consumption and heat generation in the semiconductor device as a whole.

[0111] When the accelerator finishes the execution of the kernel program, the output data is stored in the memory unit (step S10).

[0112] After the execution of the kernel program is completed, if the CPU confirms an instruction to transmit output data stored in the memory unit to the main memory (step S11), the output data is transmitted to the main memory and stored in the main memory (step S12).

[0113] When the CPU confirms an instruction to release the data area secured on the memory unit (step S13), the area secured on the memory unit is released (step S14).

[0114] By repeating the above operations from step S1 to step S14, it is possible to suppress the power consumption and heat generation of the CPU and accelerator, while allowing the accelerator to execute part of the calculations executed by the CPU.

[0115] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0116] (Embodiment 3) In this embodiment, an example of a CPU having a CPU core capable of power gating will be described.

[0117] 12 shows an example of the configuration of the CPU 10. The CPU 10 has a CPU core (CPU Core) 200, an L1 (level 1) cache memory device (L1 Cache) 202, an L2 cache memory device (L2 Cache) 203, a bus interface unit (Bus I / F) 205, power switches 210 to 212, and a level shifter (LS) 214. The CPU core 200 has a flip-flop 220.

[0118] The CPU core 200 , the L1 cache memory device 202 , and the L2 cache memory device 203 are interconnected via a bus interface unit 205 .

[0119] The PMU 193 generates a clock signal GCLK1 and various PG (power gating) control signals in response to interrupt signals (Interrupts) input from the outside and signals such as a signal SLEEP1 issued by the CPU 10. The clock signal GCLK1 and the PG control signals are input to the CPU 10. The PG control signals control the power switches 210 to 212 and the flip-flop 220.

[0120] The power switches 210 and 211 respectively control the supply of voltages VDDD and VDD1 to a virtual power line V_VDD (hereinafter referred to as a V_VDD line). The power switch 212 controls the supply of voltage VDDH to a virtual power line V_VDH (hereinafter referred to as a V_VDH line). The voltage VSSS is input to the CPU 10 and the PMU 193 without passing through a power switch. The voltage VDDD is input to the PMU 193 without passing through a power switch.

[0121] The voltages VDDD and VDD1 are drive voltages for the CMOS circuits. The voltage VDD1 is lower than the voltage VDDD and is the drive voltage in the sleep state. The voltage VDDH is a drive voltage for the OS transistors and is higher than the voltage VDDD.

[0122] Each of the L1 cache memory device 202, the L2 cache memory device 203, and the bus interface unit 205 has at least one power domain that can be power-gated. The power domain that can be power-gated is provided with one or more power switches. These power switches are controlled by a PG control signal.

[0123] The flip-flop 220 is used as a register. A backup circuit is provided in the flip-flop 220. The flip-flop 220 will be described below.

[0124] 13A shows an example of the circuit configuration of the flip-flop 220. The flip-flop 220 includes a scan flip-flop 221 and a backup circuit 222.

[0125] The scan flip-flop 221 has nodes D1, Q1, SD, SE, RT, CK, and a clock buffer circuit 221A.

[0126] Node D1 is a data input node, node Q1 is a data output node, and node SD is an input node for scan test data. Node SE is an input node for signal SCE. Node CK is an input node for clock signal GCLK1. Clock signal GCLK1 is input to clock buffer circuit 221A. Analog switches of scan flip-flop 221 are connected to nodes CK1 and CKB1 of clock buffer circuit 221A. Node RT is an input node for a reset signal.

[0127] A signal SCE is a scan enable signal, and is generated by the PMU 193. The PMU 193 generates signals BK and RC. A level shifter 214 shifts the levels of the signals BK and RC to generate signals BKH and RCH. The signals BK and RC are a backup signal and a recovery signal.

[0128] The circuit configuration of the scan flip-flop 221 is not limited to that shown in Fig. 13. Flip-flops available in a standard circuit library can be applied.

[0129] The backup circuit 222 includes nodes SD_IN and SN11, transistors M11 to M13, and a capacitive element C11.

[0130] The node SD_IN is an input node for scan test data, and is connected to the node Q1 of the scan flip-flop 221. The node SN11 is a storage node of the backup circuit 222. The capacitive element C11 is a storage capacitor for storing the voltage of the node SN11.

[0131] The transistor M11 controls the conduction state between the node Q1 and the node SN11. The transistor M12 controls the conduction state between the node SN11 and the node SD. The transistor M13 controls the conduction state between the node SD_IN and the node SD. The on / off of the transistors M11 and M13 is controlled by a signal BKH, and the on / off of the transistor M12 is controlled by a signal RCH.

[0132] The transistors M11 to M13 are OS transistors, similar to the transistors in the data retention circuits 31_N and 31_P in the memory circuit 24, and the transistors 32_P, 32_N, 33_P, and 33_N. The transistors M11 to M13 are illustrated as having back gates. The back gates of the transistors M11 to M13 are connected to a power supply line that supplies a voltage VBG1.

[0133] At least the transistors M11 and M12 are preferably OS transistors. OS transistors have an extremely small off-state current, which can suppress a voltage drop at the node SN11 and consume almost no power to retain data, so that the backup circuit 222 has nonvolatile characteristics. Since data is rewritten by charging and discharging the capacitive element C11, the backup circuit 222 is theoretically capable of writing and reading data without any restrictions on the number of times it can be rewritten, and can write and read data with low energy.

[0134] It is highly preferable that all the transistors in the backup circuit 222 are OS transistors. As shown in Fig. 13B, the backup circuit 222 can be stacked on a scan flip-flop 221 that is configured with a silicon CMOS circuit.

[0135] Since the backup circuit 222 has a very small number of elements compared to the scan flip-flop 221, there is no need to change the circuit configuration and layout of the scan flip-flop 221 in order to stack the backup circuit 222. In other words, the backup circuit 222 is a highly versatile backup circuit. In addition, since the backup circuit 222 can be provided in the region in which the scan flip-flop 221 is formed, the area overhead of the flip-flop 220 can be reduced to zero even if the backup circuit 222 is incorporated. Therefore, by providing the backup circuit 222 in the flip-flop 220, power gating of the CPU core 200 becomes possible. Since little energy is required for power gating, the CPU core 200 can be power gated with high efficiency.

[0136] By providing the backup circuit 222, a parasitic capacitance due to the transistor M11 is added to the node Q1, but since it is small compared to the parasitic capacitance due to the logic circuit connected to the node Q1, it does not affect the operation of the scan flip-flop 221. In other words, even if the backup circuit 222 is provided, the performance of the flip-flop 220 does not substantially deteriorate.

[0137] For example, a clock gating state, a power gating state, or a pause state can be set as the low power consumption state of the CPU core 200. The PMU 193 selects the low power consumption mode of the CPU core 200 based on an interrupt signal, a signal SLEEP1, etc. For example, when transitioning from a normal operation state to a clock gating state, the PMU 193 stops generating the clock signal GCLK1.

[0138] For example, when transitioning from a normal operation state to a hibernation state, the PMU 193 performs voltage and / or frequency scaling. For example, when performing voltage scaling, the PMU 193 turns off the power switch 210 and turns on the power switch 211 to input the voltage VDD1 to the CPU core 200. The voltage VDD1 is a voltage that does not cause data to be lost in the scan flip-flop 221. When performing frequency scaling, the PMU 193 reduces the frequency of the clock signal GCLK1.

[0139] When the CPU core 200 is transitioned from a normal operation state to a power gating state, an operation is performed to back up the data of the scan flip-flop 221 in the backup circuit 222. When the CPU core 200 is returned from the power gating state to the normal operation state, an operation is performed to recover the data of the backup circuit 222 to the scan flip-flop 221.

[0140] Fig. 14 shows an example of a power gating sequence of the CPU core 200. In Fig. 14, t1 to t7 represent time. Signals PSE0 to PSE2 are control signals for the power switches 210 to 212, and are generated by the PMU 193. When the signal PSE0 is "H" / "L", the power switch 210 is on / off. The same applies to the signals PSE1 and PSE2.

[0141] Before time t1, the state is normal operation. The power switch 210 is on, and the voltage VDDD is input to the CPU core 200. The scan flip-flop 221 performs normal operation. At this time, since the level shifter 214 does not need to operate, the power switch 212 is off, and the signals SCE, BK, and RC are "L". Since the node SE is "L", the scan flip-flop 221 stores the data of the node D1. In the example of FIG. 14, at time t1, the node SN11 of the backup circuit 222 is "L".

[0142] The operation during backup will be described. At operation time t1, the PMU 193 stops the clock signal GCLK1 and sets the signals PSE2 and BK to "H." The level shifter 214 becomes active and outputs the signal BKH at "H" to the backup circuit 222.

[0143] The transistor M11 of the backup circuit 222 turns on, and the data of the node Q1 of the scan flip-flop 221 is written to the node SN11 of the backup circuit 222. If the node Q1 of the scan flip-flop 221 is "L", the node SN11 remains "L", and if the node Q1 is "H", the node SN11 becomes "H".

[0144] The PMU 193 sets signals PSE2 and BK to "L" at time t2, and sets signal PSE0 to "L" at time t3. At time t3, the state of the CPU core 200 transitions to a power gating state. Note that signal PSE0 may also fall at the same timing as signal BK falls.

[0145] The operation during power gating will be described. When the signal PSE0 goes to "L", the voltage of the V_VDD line drops, and the data at the node Q1 is lost. The node SN11 continues to hold the data at the node Q1 at time t3.

[0146] The operation during recovery will be explained below. At time t4, the PMU 193 changes the signal PSE0 to "H", transitioning from the power gating state to the recovery state. Charging of the V_VDD line begins, and when the voltage of the V_VDD line reaches VDDD (time t5), the PMU 193 changes the signals PSE2, RC, and SCE to "H".

[0147] The transistor M12 turns on, and the charge of the capacitive element C11 is distributed to the nodes SN11 and SD. If the node SN11 is "H", the voltage of the node SD rises. Since the node SE is "H", the data of the node SD is written to the input side latch circuit of the scan flip-flop 221. When the clock signal GCLK1 is input to the node CK at time t6, the data of the input side latch circuit is written to the node Q1. In other words, the data of the node SN11 is written to the node Q1.

[0148] At time t7, the PMU 193 sets the signals PSE2, SCE, and RC to "L," and the recovery operation ends.

[0149] The backup circuit 222 using OS transistors is very suitable for normally-off computing because it consumes small amounts of power both dynamically and statically. The CPU 10 including the CPU core 200 having the backup circuit 222 using OS transistors can be called an NoffCPU (registered trademark). The NoffCPU has a non-volatile memory, and can stop the power supply when operation is not required. Even if the flip-flop 220 is installed, it is possible to prevent almost no performance degradation of the CPU core 200 and almost no increase in dynamic power.

[0150] The CPU core 200 may have multiple power domains that can be power-gated. The multiple power domains are provided with one or more power switches for controlling the input of voltage. The CPU core 200 may also have one or more power domains in which power gating is not performed. For example, a power gating control circuit for controlling the flip-flop 220 and the power switches 210 to 212 may be provided in the power domain in which power gating is not performed.

[0151] The application of the flip-flop 220 is not limited to the CPU 10. In a computing device, the flip-flop 220 can be applied to a register provided in a power domain capable of power gating.

[0152] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0153] (Embodiment 4) In this embodiment, a configuration of a transistor applicable to the semiconductor device 100, the CPU 10, and the accelerator 20 described in the above embodiment will be described. As an example, a configuration in which transistors having different electrical characteristics are stacked will be described. By using this configuration, the design freedom of the semiconductor device can be increased. In addition, by stacking transistors having different electrical characteristics, the integration degree of the semiconductor device can be increased.

[0154] Part of a cross-sectional structure of the semiconductor device is shown in Fig. 15. The semiconductor device shown in Fig. 15 includes a transistor 550, a transistor 500, and a capacitor 600. Fig. 16A is a cross-sectional view of the transistor 500 in the channel length direction, and Fig. 16B is a cross-sectional view of the transistor 500 in the channel width direction. For example, the transistor 500 corresponds to the transistors 32 to 34 described in the above embodiment, and the transistor 550 corresponds to a Si transistor included in the arithmetic circuit 23. The capacitor 600 corresponds to the capacitor 35.

[0155] The transistor 500 is an OS transistor. An OS transistor has an extremely small off-state current. Therefore, a data voltage or charge written to a storage node through the transistor 500 can be held for a long period of time. That is, the frequency of a refresh operation of the storage node (node ​​MN) can be reduced or the refresh operation is not required, thereby reducing the power consumption of the semiconductor device.

[0156] In FIG. 15, the transistor 500 is provided above the transistor 550 , and the capacitor 600 is provided above the transistor 550 and the transistor 500 .

[0157] The transistor 550 is provided on a substrate 311. The substrate 311 is, for example, a p-type silicon substrate. The substrate 311 may be an n-type silicon substrate. The oxide layer 314 is preferably an insulating layer (also referred to as a BOX layer) formed by buried oxide in the substrate 311, for example, silicon oxide. The transistor 550 is provided on single crystal silicon provided on the substrate 311 via the oxide layer 314, that is, a so-called SOI (Silicon On Insulator) substrate.

[0158] A substrate 311 in the SOI substrate is provided with an insulator 313 functioning as an element isolation layer. The substrate 311 also has a well region 312. The well region 312 is a region to which n-type or p-type conductivity is imparted according to the conductivity type of the transistor 550. A semiconductor region 315, and low-resistance regions 316a and 316b functioning as source and drain regions are provided in the single crystal silicon in the SOI substrate. Also, a low-resistance region 316c is provided on the well layer 312.

[0159] The transistor 550 can be provided overlapping the well region 312 to which an impurity element that imparts conductivity is added. The well region 312 can function as a bottom gate electrode of the transistor 550 by independently changing the potential through the low-resistance region 316c. Therefore, the threshold voltage of the transistor 550 can be controlled. In particular, by applying a negative potential to the well region 312, the threshold voltage of the transistor 550 can be increased and the off-current can be reduced. Therefore, by applying a negative potential to the well region 312, the drain current when the potential applied to the gate electrode of the Si transistor is 0 V can be reduced. As a result, the power consumption due to the through current or the like in the arithmetic circuit 23 including the transistor 550 can be reduced, and the arithmetic efficiency can be improved.

[0160] The transistor 550 is preferably a so-called fin type in which a top surface of a semiconductor layer and side surfaces in a channel width direction are covered with a conductor 318 via an insulator 317. By making the transistor 550 a fin type, the effective channel width is increased, and thus the on characteristics of the transistor 550 can be improved. In addition, the contribution of the electric field of the gate electrode can be increased, and thus the off characteristics of the transistor 550 can be improved.

[0161] Note that the transistor 550 may be either a p-channel transistor or an n-channel transistor.

[0162] The conductor 318 may function as a first gate (also called a top gate) electrode. The well region 312 may function as a second gate (also called a bottom gate) electrode. In this case, the potential applied to the well region 312 can be controlled via the low resistance region 316c.

[0163] The region where the channel of the semiconductor region 315 is formed, the region nearby the region, the low resistance region 316a which becomes the source region or drain region, the low resistance region 316b, the low resistance region 316c which is connected to the electrode which controls the potential of the well region 312, and the like preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single crystal silicon. Alternatively, they may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 550 may be a HEMT by using GaAs and GaAlAs, or the like.

[0164] Well region 312, low resistance region 316a, low resistance region 316b, and low resistance region 316c include the semiconductor material applied to semiconductor region 315 as well as an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0165] The conductor 318 functioning as the gate electrode can be a conductive material such as a semiconductor material such as silicon containing an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron, a metal material, an alloy material, or a metal oxide material. The conductor 318 can also be a silicide such as nickel silicide.

[0166] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Furthermore, in order to achieve both electrical conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as the conductor in a laminated state, and in particular, it is preferable to use tungsten in terms of heat resistance.

[0167] The low-resistance region 316a, the low-resistance region 316b, and the low-resistance region 316c may be configured to be provided by stacking another conductor, for example, a silicide such as nickel silicide. With this configuration, the conductivity of the region functioning as an electrode can be increased. In addition, in this case, an insulator functioning as a sidewall spacer (also called a sidewall insulating layer) may be provided on the side surface of the conductor 318 functioning as the gate electrode and the side surface of the insulator functioning as the gate insulating film. With this configuration, it is possible to prevent the conductor 318 from being electrically connected to the low-resistance region 316a and the low-resistance region 316b.

[0168] An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order over the transistor 550.

[0169] As the insulators 320, 322, 324, and 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like can be used.

[0170] In this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen, silicon nitride oxide refers to a material having a higher nitrogen content than oxygen, aluminum oxynitride refers to a material having a higher oxygen content than nitrogen, and aluminum nitride oxide refers to a material having a higher nitrogen content than oxygen.

[0171] The insulator 322 may function as a planarizing film that planarizes steps caused by the transistor 550 or the like provided thereunder. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0172] The insulator 324 is preferably a film having a barrier property that prevents hydrogen or impurities from diffusing from the substrate 311, the transistor 550, or the like to a region where the transistor 500 is provided.

[0173] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 550. Specifically, the film that suppresses the diffusion of hydrogen is a film that releases a small amount of hydrogen.

[0174] The amount of desorption of hydrogen can be analyzed, for example, by using thermal desorption spectrometry (TDS). For example, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in the TDS analysis. 15 atoms / cm 2 Less than or equal to 5×10 15 atoms / cm 2 The following is acceptable.

[0175] The insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. For example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0176] Conductors 328 and 330, which connect to the capacitor 600 or the transistor 500, are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as plugs or wiring. A plurality of conductors that function as plugs or wiring may be collectively assigned the same reference numeral. In this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, a part of the conductor may function as the wiring, and a part of the conductor may function as the plug.

[0177] As the material for each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used in a single layer or a laminated layer. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferably used. Alternatively, it is preferable to form the plug and wiring from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be reduced.

[0178] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 15 , an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring connected to the transistor 550. Note that the conductor 356 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0179] Note that, for example, the insulator 350 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0180] Note that, for example, tantalum nitride or the like may be used as a conductor having a barrier property against hydrogen. By stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 550 can be suppressed while maintaining the conductivity of the wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.

[0181] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. 15, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. A conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. The conductor 366 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0182] Note that, for example, the insulator 360 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0183] A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 15, an insulator 370, an insulator 372, and an insulator 374 are stacked in this order. A conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 functions as a plug or a wiring. The conductor 376 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0184] Note that, for example, the insulator 370 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0185] A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 15, an insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. A conductor 386 is formed in the insulator 380, the insulator 382, ​​and the insulator 384. The conductor 386 functions as a plug or a wiring. The conductor 386 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0186] Note that, for example, the insulator 380 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0187] In the above, a wiring layer including the conductor 356, a wiring layer including the conductor 366, a wiring layer including the conductor 376, and a wiring layer including the conductor 386 have been described, but the semiconductor device of this embodiment is not limited to this. There may be three or fewer wiring layers similar to the wiring layer including the conductor 356, or there may be five or more wiring layers similar to the wiring layer including the conductor 356.

[0188] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are stacked in this order on the insulator 384. Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably made of a substance that has a barrier property against oxygen or hydrogen.

[0189] For example, the insulator 510 and the insulator 514 are preferably formed using a film having a barrier property against hydrogen and impurities in a region where the transistor 500 is provided, such as the substrate 311 or a region where the transistor 550 is provided. Therefore, a material similar to that of the insulator 324 can be used.

[0190] As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, a film that suppresses the diffusion of hydrogen is preferably used between the transistor 500 and the transistor 550.

[0191] As a film having a barrier property against hydrogen, for example, the insulator 510 and the insulator 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0192] In particular, aluminum oxide has a high blocking effect of preventing the film from permeating both oxygen and impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. In addition, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0193] For example, the insulator 512 and the insulator 516 can be made of a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, the parasitic capacitance generated between wirings can be reduced. For example, the insulator 512 and the insulator 516 can be made of a silicon oxide film, a silicon oxynitride film, or the like.

[0194] A conductor 518, a conductor constituting the transistor 500 (for example, the conductor 503), and the like are embedded in the insulator 510, the insulator 512, the insulator 514, and the insulator 516. Note that the conductor 518 functions as a plug or a wiring connected to the capacitor 600 or the transistor 550. The conductor 518 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0195] In particular, the insulator 510 and the conductor 518 in the region in contact with the insulator 514 are preferably conductors having barrier properties against oxygen, hydrogen, and water. With this structure, the transistor 550 and the transistor 500 can be separated by a layer having barrier properties against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0196] Above the insulator 516 is a transistor 500 .

[0197] As shown in Figures 16A and 16B, transistor 500 has a conductor 503 arranged so as to be embedded in insulator 514 and insulator 516, an insulator 520 arranged on insulator 516 and conductor 503, an insulator 522 arranged on insulator 520, an insulator 524 arranged on insulator 522, an oxide 530a arranged on insulator 524, an oxide 530b arranged on oxide 530a, conductors 542a and 542b arranged apart from each other on oxide 530b, an insulator 580 arranged on conductor 542a and conductor 542b and having an opening formed therebetween overlapping with conductor 542a and conductor 542b, an insulator 545 arranged on the bottom and side surfaces of the opening, and a conductor 560 arranged on the formation surface of insulator 545.

[0198] 16A and 16B, it is preferable that an insulator 544 is disposed between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b and the insulator 580. It is preferable that the conductor 560 has a conductor 560a provided inside the insulator 545 and a conductor 560b provided so as to be embedded inside the conductor 560a, as shown in FIG. 16A and 16B. It is preferable that an insulator 574 is disposed on the insulator 580, the conductor 560, and the insulator 545, as shown in FIG. 16A and 16B.

[0199] In this specification and other documents, oxide 530a and oxide 530b may be collectively referred to as oxide 530.

[0200] Note that, in the transistor 500, a two-layer structure of the oxide 530a and the oxide 530b is shown in the region where the channel is formed and in the vicinity thereof, but the present invention is not limited to this structure. For example, a single layer of the oxide 530b or a stacked structure of three or more layers may be used.

[0201] Although the conductor 560 in the transistor 500 has a two-layer structure, the present invention is not limited to this. For example, the conductor 560 may have a single-layer structure or a three-or-more-layer structure. The transistor 500 shown in FIGS. 15, 16A, and 16B is merely an example and is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration, driving method, and the like.

[0202] Here, the conductor 560 functions as a gate electrode of the transistor, and the conductors 542a and 542b function as a source electrode and a drain electrode, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangement of the conductors 560, 542a, and 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. Therefore, the conductor 560 can be formed without providing a margin for alignment, so that the area occupied by the transistor 500 can be reduced. This allows the semiconductor device to be miniaturized and highly integrated.

[0203] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. This makes it possible to reduce the parasitic capacitance formed between the conductor 560 and the conductor 542a and between the conductor 560 and the conductor 542b. This makes it possible to improve the switching speed of the transistor 500 and provide high frequency characteristics.

[0204] The conductor 560 may function as a first gate (also referred to as a top gate) electrode. The conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 503, the threshold voltage of the transistor 500 can be increased and the off-current can be reduced. Therefore, the drain current when the potential applied to the conductor 560 is 0 V can be reduced by applying a negative potential to the conductor 503 compared to the case where a negative potential is not applied.

[0205] The conductor 503 is disposed so as to overlap the oxide 530 and the conductor 560. In this manner, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and a channel formation region formed in the oxide 530 can be covered.

[0206] In this specification and the like, a transistor configuration in which a channel formation region is electrically surrounded by the electric field of a pair of gate electrodes (a first gate electrode and a second gate electrode) is called a surrounded channel (S-channel) configuration. The S-channel configuration disclosed in this specification and the like is different from a fin type configuration and a planar type configuration. By adopting the S-channel configuration, it is possible to obtain a transistor that is more resistant to the short channel effect, in other words, in which the short channel effect is less likely to occur.

[0207] The conductor 503 has a structure similar to that of the conductor 518, and the conductor 503a is formed in contact with the inner walls of the openings of the insulator 514 and the insulator 516, and the conductor 503b is formed further inside. Note that, although the transistor 500 shows a structure in which the conductor 503a and the conductor 503b are stacked, the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0208] Here, the conductor 503a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the impurities are less likely to permeate through). Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate through). Note that in this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities and oxygen.

[0209] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503b can be prevented from being oxidized and the conductivity from decreasing.

[0210] In addition, when the conductor 503 also functions as a wiring, it is preferable that the conductor 503b is made of a highly conductive material containing tungsten, copper, or aluminum as a main component. Note that, although the conductor 503 is illustrated in this embodiment as a stack of the conductors 503a and 503b, the conductor 503 may have a single layer structure.

[0211] The insulators 520, 522, and 524 function as a second gate insulating film.

[0212] Here, it is preferable that the insulator 524 in contact with the oxide 530 is an insulator containing more oxygen than the oxygen that satisfies the stoichiometric composition. The oxygen is easily released from the film by heating. In this specification and the like, oxygen released by heating may be called "excess oxygen." In other words, it is preferable that the insulator 524 has a region containing excess oxygen (also called "excess oxygen region"). By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies (V O In addition, when hydrogen enters an oxygen vacancy in the oxide 530, the defect (hereinafter, V OH.) may function as a donor and generate electrons as carriers. Some of the hydrogen may bond with oxygen that is bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily moved by stress such as heat or an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be deteriorated. In one embodiment of the present invention, V in the oxide 530 O It is preferable to reduce H as much as possible and make it high-purity intrinsic or substantially high-purity intrinsic. O In order to obtain an oxide semiconductor in which H is sufficiently reduced, it is important to remove impurities such as moisture and hydrogen from the oxide semiconductor (also called "dehydration" or "dehydrogenation treatment") and to supply oxygen to the oxide semiconductor to compensate for oxygen vacancies (also called "oxygenation treatment"). O By using an oxide semiconductor in which impurities such as H are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0213] Specifically, it is preferable to use an oxide material from which some oxygen is released by heating as an insulator having an excess oxygen region. An oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen converted into oxygen atoms is 1.0×10 18 atoms / cm 3 More than 1.0×10 19 atoms / cm 3 More preferably, 2.0×10 19 atoms / cm 3 or more, or 3.0×10 20 atoms / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or more and 700° C. or less, or 100° C. or more and 400° C. or less.

[0214] In addition, the oxide 530 may be brought into contact with the insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By carrying out such treatment, water or hydrogen in the oxide 530 can be removed. For example, a reaction occurs in the oxide 530 that breaks the bond of VoH, in other words, "V O The reaction "H → Vo + H" occurs, and dehydrogenation can be achieved. Some of the hydrogen generated at this time may combine with oxygen to become H2O, which may be removed from the oxide 530 or the insulator near the oxide 530.

[0215] In addition, the microwave treatment is preferably performed using, for example, a device having a power source that generates high-density plasma or a device having a power source that applies RF to the substrate side. For example, high-density oxygen radicals can be generated by using a gas containing oxygen and high-density plasma, and the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator near the oxide 530 by applying RF to the substrate side. In addition, the pressure of the microwave treatment may be set to 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. In addition, for example, oxygen and argon are used as gases to be introduced into the microwave treatment device, and the oxygen flow rate ratio (O2 / (O2+Ar)) is 50% or less, preferably 10% or more and 30% or less.

[0216] In addition, in a manufacturing process of the transistor 500, it is preferable to perform heat treatment while the surface of the oxide 530 is exposed. The heat treatment may be performed, for example, at a temperature of 100° C. or higher and 450° C. or lower, more preferably 350° C. or higher and 400° C. or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. In this way, oxygen is supplied to the oxide 530 to reduce oxygen deficiencies (V O) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for the desorbed oxygen after the heat treatment in a nitrogen gas or inert gas atmosphere. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in succession to a heat treatment in a nitrogen gas or inert gas atmosphere.

[0217] By subjecting the oxide 530 to oxygen addition treatment, the oxygen vacancies in the oxide 530 can be repaired by the supplied oxygen, in other words, the reaction of "Vo+O→null" can be promoted. Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide 530, and the hydrogen can be removed as H2O (dehydrated). As a result, the hydrogen remaining in the oxide 530 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0218] When the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (eg, oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate).

[0219] The insulator 522 preferably has a function of suppressing diffusion of oxygen and impurities, so that oxygen contained in the oxide 530 does not diffuse toward the insulator 520. Furthermore, reaction of the conductor 503 with the insulator 524 or oxygen contained in the oxide 530 can be suppressed.

[0220] The insulator 522 is preferably a single layer or a multilayer insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0221] In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials having a function of suppressing the diffusion of impurities and oxygen (the oxygen is unlikely to permeate through them). As an insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530 and the intrusion of impurities such as hydrogen into the oxide 530 from the periphery of the transistor 500.

[0222] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0223] In addition, the insulator 520 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In addition, by combining a high-k material insulator with silicon oxide or silicon oxynitride, it is possible to obtain the insulator 520 or the insulator 526 having a thermally stable laminated structure with a high relative dielectric constant.

[0224] 16A and 16B, the second gate insulating film has a three-layer stack structure, which includes the insulators 520, 522, and 524. However, the second gate insulating film may have a single layer, two layers, or four or more layers. In this case, the second gate insulating film is not limited to a stack structure made of the same material, and may have a stack structure made of different materials.

[0225] In the transistor 500, a metal oxide functioning as an oxide semiconductor is used for the oxide 530 including the channel formation region. For example, a metal oxide such as In-M-Zn oxide (wherein the element M is one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like) may be used for the oxide 530.

[0226] The metal oxide functioning as an oxide semiconductor may be formed by a sputtering method or an ALD (Atomic Layer Deposition) method. Note that the metal oxide functioning as an oxide semiconductor will be described in detail in another embodiment.

[0227] The metal oxide that functions as a channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. In this manner, by using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0228] The oxide 530 has the oxide 530a below the oxide 530b, and thus can suppress the diffusion of impurities from components formed below the oxide 530a to the oxide 530b.

[0229] The oxide 530 preferably has a laminated structure of a plurality of oxide layers having different atomic ratios of metal atoms. Specifically, the atomic ratio of element M among the constituent elements in the metal oxide used for the oxide 530a is preferably larger than the atomic ratio of element M among the constituent elements in the metal oxide used for the oxide 530b. In addition, the atomic ratio of element M to In in the metal oxide used for the oxide 530a is preferably larger than the atomic ratio of element M to In in the metal oxide used for the oxide 530b. In addition, the atomic ratio of In to element M in the metal oxide used for the oxide 530b is preferably larger than the atomic ratio of In to element M in the metal oxide used for the oxide 530a.

[0230] In addition, it is preferable that the energy of the conduction band minimum of the oxide 530a is higher than that of the oxide 530b, or, in other words, it is preferable that the electron affinity of the oxide 530a is smaller than that of the oxide 530b.

[0231] Here, at the junction between the oxide 530a and the oxide 530b, the energy level of the conduction band minimum changes gradually. In other words, it can be said that the energy level of the conduction band minimum at the junction between the oxide 530a and the oxide 530b changes continuously or is a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b.

[0232] Specifically, the oxide 530a and the oxide 530b have a common element other than oxygen (as a main component), so that a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxide 530a may be an In-Ga-Zn oxide, a Ga-Zn oxide, or a gallium oxide.

[0233] At this time, the main carrier path is the oxide 530b. By configuring the oxide 530a as described above, the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced. Therefore, the effect of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-state current.

[0234] Conductors 542a and 542b functioning as a source electrode and a drain electrode are provided on the oxide 530b. As the conductors 542a and 542b, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed, and are therefore preferable.Furthermore, metal nitride films such as tantalum nitride are preferable because they have barrier properties against hydrogen or oxygen.

[0235] 16A, the conductor 542a and the conductor 542b are shown as a single layer, but may be a laminated structure of two or more layers. For example, a tantalum nitride film and a tungsten film may be laminated. A titanium film and an aluminum film may be laminated. A two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, or a two-layer structure in which a copper film is laminated on a tungsten film may be used.

[0236] In addition, there are three-layer structures in which a titanium film or titanium nitride film is laminated with an aluminum film or copper film on the titanium film or titanium nitride film, and a titanium film or titanium nitride film is further formed thereon, and a three-layer structure in which a molybdenum film or molybdenum nitride film is laminated with an aluminum film or copper film on the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further formed thereon, etc. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0237] 16A, regions 543a and 543b may be formed as low-resistance regions at and near the interface of the oxide 530 with the conductor 542a (conductor 542b). In this case, the region 543a functions as one of the source region and the drain region, and the region 543b functions as the other of the source region and the drain region. A channel formation region is formed in a region sandwiched between the regions 543a and 543b.

[0238] By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, the oxygen concentration in the region 543a (region 543b) may be reduced. Also, a metal compound layer containing a metal contained in the conductor 542a (conductor 542b) and a component of the oxide 530 may be formed in the region 543a (region 543b). In such a case, the carrier density in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.

[0239] The insulator 544 is provided to cover the conductor 542a and the conductor 542b and suppresses oxidation of the conductor 542a and the conductor 542b. In this case, the insulator 544 may be provided to cover the side surface of the oxide 530 and to be in contact with the insulator 524.

[0240] The insulator 544 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. Alternatively, the insulator 544 can be silicon nitride oxide, silicon nitride, or the like.

[0241] In particular, it is preferable to use, as the insulator 544, an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize in a heat treatment in a later process. Note that the insulator 544 is not an essential component when the conductors 542a and 542b are made of a material having oxidation resistance or when the conductivity does not decrease significantly even when oxygen is absorbed. It may be designed appropriately depending on the desired transistor characteristics.

[0242] The insulator 544 can prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing to the oxide 530b through the insulator 545. The insulator 580 can also prevent the conductor 560 from being oxidized by excess oxygen contained in the insulator 580.

[0243] The insulator 545 functions as a first gate insulating film. Like the insulator 524 described above, the insulator 545 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating.

[0244] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having vacancies can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0245] By providing an insulator containing excess oxygen as the insulator 545, oxygen can be effectively supplied from the insulator 545 to the channel formation region of the oxide 530b. Similarly to the insulator 524, the concentration of impurities such as water or hydrogen in the insulator 545 is preferably reduced. The thickness of the insulator 545 is preferably 1 nm or more and 20 nm or less. The microwave treatment described above may be performed before and / or after the formation of the insulator 545.

[0246] Furthermore, in order to efficiently supply excess oxygen contained in the insulator 545 to the oxide 530, a metal oxide may be provided between the insulator 545 and the conductor 560. The metal oxide preferably suppresses oxygen diffusion from the insulator 545 to the conductor 560. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of excess oxygen from the insulator 545 to the conductor 560 can be suppressed. That is, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to the excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 can be used.

[0247] The insulator 545 may have a layered structure, similar to the second gate insulating film. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. Therefore, by making the insulator that functions as the gate insulating film have a layered structure of a high-k material and a thermally stable material, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, a layered structure that is thermally stable and has a high relative dielectric constant can be obtained.

[0248] Although the conductor 560 functioning as the first gate electrode is shown as having a two-layer structure in FIGS. 16A and 16B, it may have a single-layer structure or a laminated structure of three or more layers.

[0249] The conductor 560a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferably made of a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). The conductor 560a has a function of suppressing the diffusion of oxygen, so that it is possible to suppress the conductor 560b from being oxidized by the oxygen contained in the insulator 545 and its conductivity from decreasing. As a conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. In addition, an oxide semiconductor applicable to the oxide 530 can be used as the conductor 560a. In that case, the conductor 560b can be formed by a sputtering method to reduce the electrical resistance value of the conductor 560a and make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0250] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 560b also functions as wiring, so it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above conductive material.

[0251] The insulator 580 is provided on the conductor 542a and the conductor 542b via the insulator 544. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably has silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having voids, or a resin. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having voids are preferable because they can easily form an excess oxygen region in a later step.

[0252] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580 from which oxygen is released by heating, oxygen in the insulator 580 can be efficiently supplied to the oxide 530. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.

[0253] The opening of insulator 580 is formed to overlap the region between conductor 542a and conductor 542b, so that conductor 560 is formed so as to be embedded in the opening of insulator 580 and the region sandwiched between conductor 542a and conductor 542b.

[0254] In miniaturizing a semiconductor device, it is necessary to shorten the gate length, but it is also necessary to prevent the conductivity of the conductor 560 from decreasing. If the film thickness of the conductor 560 is increased for that purpose, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided so as to be embedded in the opening of the insulator 580, so that even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 can be formed without collapsing during the process.

[0255] The insulator 574 is preferably provided in contact with a top surface of the insulator 580, a top surface of the conductor 560, and a top surface of the insulator 545. By forming the insulator 574 by a sputtering method, an excess oxygen region can be provided in the insulator 545 and the insulator 580. This allows oxygen to be supplied from the excess oxygen region into the oxide 530.

[0256] For example, the insulator 574 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like.

[0257] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even in a thin film with a thickness of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can function as a barrier film against impurities such as hydrogen as well as an oxygen source.

[0258] An insulator 581 functioning as an interlayer film is preferably provided over the insulator 574. Like the insulator 524, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen.

[0259] Conductor 540a and conductor 540b are arranged in openings formed in insulator 581, insulator 574, insulator 580, and insulator 544. Conductor 540a and conductor 540b are provided facing each other with conductor 560 interposed therebetween. Conductor 540a and conductor 540b have the same configuration as conductor 546 and conductor 548, which will be described later.

[0260] An insulator 582 is provided over the insulator 581. The insulator 582 is preferably made of a substance that has a barrier property against oxygen and hydrogen. Therefore, the insulator 582 can be made of a material similar to that of the insulator 514. For example, the insulator 582 is preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0261] In particular, aluminum oxide has a high blocking effect of preventing the film from permeating both oxygen and impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. In addition, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0262] An insulator 586 is provided over the insulator 582. The insulator 586 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 586.

[0263] In addition, conductors 546, 548, etc. are embedded in insulators 520, 522, 524, 544, 580, 574, 581, 582, and 586.

[0264] The conductor 546 and the conductor 548 function as a plug or a wiring that connects to the capacitor 600, the transistor 500, or the transistor 550. The conductor 546 and the conductor 548 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0265] After the transistor 500 is formed, an opening may be formed to surround the transistor 500, and an insulator having a high barrier property against hydrogen or water may be formed to cover the opening. By surrounding the transistor 500 with the insulator having a high barrier property, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, a plurality of transistors 500 may be collectively surrounded by an insulator having a high barrier property against hydrogen or water. When an opening is formed to surround the transistor 500, for example, an opening reaching the insulator 522 or the insulator 514 is formed, and the insulator having a high barrier property is formed in contact with the insulator 522 or the insulator 514, which is preferable because it serves as part of the manufacturing process of the transistor 500. Note that the insulator having a high barrier property against hydrogen or water may be made of a material similar to that of the insulator 522 or the insulator 514, for example.

[0266] Next, a capacitor 600 is provided above the transistor 500. The capacitor 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0267] A conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 functions as a plug or a wiring connected to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. Note that the conductor 612 and the conductor 610 can be formed at the same time.

[0268] A metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-mentioned element (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used for the conductor 612 and the conductor 610. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide with added silicon oxide can also be used.

[0269] In this embodiment, the conductor 612 and the conductor 610 have a single-layer structure, but the present invention is not limited to this structure and may have a stacked structure of two or more layers. For example, a conductor having a barrier property and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having a barrier property and a conductor having high conductivity.

[0270] The conductor 620 is provided so as to overlap with the conductor 610 with the insulator 630 interposed therebetween. Note that the conductor 620 can be made of a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. When the conductor 620 is formed simultaneously with other components such as a conductor, a low resistance metal material such as Cu (copper) or Al (aluminum) may be used.

[0271] An insulator 640 is provided over the conductor 620 and the insulator 630. The insulator 640 can be provided using a material similar to that of the insulator 320. The insulator 640 may also function as a planarizing film that covers the uneven shape underneath.

[0272] With this structure, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor.

[0273] <Transistor modification 1> A transistor 500A shown in FIGS. 17A, 17B, and 17C is a modification of the transistor 500 having the structure shown in FIGS. 16A and 16B. FIG. 17A is a top view of the transistor 500A, FIG. 17B is a cross-sectional view of the transistor 500A in the channel length direction, and FIG. 17C is a cross-sectional view of the transistor 500A in the channel width direction. Note that some elements are omitted in the top view of FIG. 17A for clarity. The structures shown in FIGS. 17A, 17B, and 17C can also be applied to other transistors included in the semiconductor device of one embodiment of the present invention, such as the transistor 550.

[0274] 17A, 17B, and 17C differs from transistor 500 shown in FIGS. 16A and 16B in that transistor 500A includes insulator 552, insulator 513, and insulator 404. Transistor 500A also differs from transistor 500 shown in FIGS. 16A and 16B in that insulator 552 is provided in contact with a side surface of conductor 540a and insulator 552 is provided in contact with a side surface of conductor 540b. Transistor 500A also differs from transistor 500 shown in FIGS. 16A and 16B in that insulator 520 is not provided.

[0275] 17A, 17B, and 17C, an insulator 513 is provided over an insulator 512. Furthermore, an insulator 404 is provided over the insulator 574 and the insulator 513.

[0276] 17A, 17B, and 17C, the insulator 514, the insulator 516, the insulator 522, the insulator 524, the insulator 544, the insulator 580, and the insulator 574 are patterned, and the insulator 404 covers them. That is, the insulator 404 contacts the top surface of the insulator 574, the side surface of the insulator 574, the side surface of the insulator 580, the side surface of the insulator 544, the side surface of the insulator 524, the side surface of the insulator 522, the side surface of the insulator 516, the side surface of the insulator 514, and the top surface of the insulator 513. As a result, the oxide 530 and the like are isolated from the outside by the insulator 404 and the insulator 513.

[0277] The insulator 513 and the insulator 404 preferably have a high function of suppressing diffusion of hydrogen (for example, at least one of hydrogen atoms, hydrogen molecules, and the like) or water molecules. For example, the insulator 513 and the insulator 404 are preferably made of silicon nitride or silicon nitride oxide, which are materials with high hydrogen barrier properties. This can suppress diffusion of hydrogen and the like into the oxide 530, thereby suppressing deterioration in the characteristics of the transistor 500A. Therefore, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0278] The insulator 552 is provided in contact with the insulator 581, the insulator 404, the insulator 574, the insulator 580, and the insulator 544. The insulator 552 preferably has a function of suppressing diffusion of hydrogen or water molecules. For example, the insulator 552 is preferably made of an insulator having a high hydrogen barrier property, such as silicon nitride, aluminum oxide, or silicon nitride oxide. In particular, silicon nitride is preferably used as the insulator 552 because it has a high hydrogen barrier property. By using a material having a high hydrogen barrier property as the insulator 552, impurities such as water or hydrogen can be suppressed from diffusing from the insulator 580 or the like to the oxide 530 through the conductor 540a and the conductor 540b. Furthermore, oxygen contained in the insulator 580 can be suppressed from being absorbed by the conductor 540a and the conductor 540b. As described above, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0279] <Transistor modification 2> A configuration example of a transistor 500B will be described with reference to Figures 18A, 18B, and 18C. Figure 18A is a top view of the transistor 500B. Figure 18B is a cross-sectional view of the L1-L2 portion shown by the dashed line in Figure 18A. Figure 18C is a cross-sectional view of the W1-W2 portion shown by the dashed line in Figure 18A. Note that in the top view of Figure 18A, some elements are omitted for clarity.

[0280] The transistor 500B is a modified example of the transistor 500 and can be substituted for the transistor 500. Therefore, in order to avoid repetition of the description, the following description will mainly focus on the differences between the transistor 500B and the transistor 500.

[0281] The conductor 560 functioning as the first gate electrode has a conductor 560a and a conductor 560b on the conductor 560a. The conductor 560a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Alternatively, it is preferably made of a conductive material having a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like).

[0282] The conductor 560a has a function of suppressing the diffusion of oxygen, which improves the material selectivity of the conductor 560b. In other words, the presence of the conductor 560a suppresses oxidation of the conductor 560b, thereby preventing a decrease in electrical conductivity.

[0283] It is preferable to provide an insulator 544 so as to cover the top surface and side surfaces of the conductor 560 and the side surfaces of the insulator 545. Note that the insulator 544 may be made of an insulating material having a function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen. For example, it is preferable to use aluminum oxide or hafnium oxide. In addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride oxide, or silicon nitride may also be used.

[0284] Providing the insulator 544 can suppress oxidation of the conductor 560. Furthermore, providing the insulator 544 can suppress diffusion of impurities such as water and hydrogen contained in the insulator 580 to the transistor 500B.

[0285] In the transistor 500B, the conductor 560 overlaps with part of the conductor 542a and part of the conductor 542b, and thus the parasitic capacitance of the transistor 500B is likely to be larger than that of the transistor 500. Thus, the operating frequency of the transistor 500B tends to be lower than that of the transistor 500. However, the productivity of the transistor 500B is higher than that of the transistor 500 because a step of forming an opening in the insulator 580 or the like and filling the conductor 560 and the insulator 545 is not required.

[0286] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiment modes and examples.

[0287] (Embodiment 5) In this embodiment, the crystal structure of an oxide semiconductor will be described in detail.

[0288] [Classification of crystal structures] First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 19A. Fig. 19A is a diagram for explaining classification of crystal structures of oxide semiconductors, typically IGZO (metal oxide containing In, Ga, and Zn).

[0289] As shown in FIG. 19A, oxide semiconductors are broadly classified into "Amorphous", "Crystalline", and "Crystal". "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC). "Crystalline" excludes single crystal, poly crystal, and completely amorphous. "Crystal" includes single crystal and poly crystal.

[0290] The structure in the bold frame shown in Fig. 19A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure is completely different from the energetically unstable "Amorphous" and "Crystal".

[0291] The crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. FIG. 19B shows an XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of the CAAC-IGZO film classified as "Crystalline". The GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in FIG. 19B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in FIG. 19B is in the vicinity of In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in FIG. 19B is 500 nm.

[0292] As shown in Figure 19B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ=31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 19B, the peak near 2θ=31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0293] The crystal structure of the film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 19C. FIG. 19C is a diffraction pattern observed by NBED, which causes an electron beam to be incident parallel to the substrate. The composition of the CAAC-IGZO film shown in FIG. 19C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0294] As shown in FIG. 19C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0295] [Structure of oxide semiconductor] In addition, when focusing on the crystal structure, oxide semiconductors may be classified differently from that shown in FIG. 19A. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. In addition, non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OS), amorphous oxide semiconductors, and the like.

[0296] Next, the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be explained.

[0297] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystalline regions, each of which has a c-axis aligned in a specific direction. The specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. The crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, the crystalline region is also a region with a uniform lattice arrangement. CAAC-OS has a region in which a plurality of crystalline regions are connected in the ab-plane direction, and the region may have distortion. The distortion refers to a portion in which the direction of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in the region in which the plurality of crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor having a c-axis aligned and no clear orientation in the ab-plane direction.

[0298] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be about several tens of nm.

[0299] In addition, in an In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer) are stacked. Note that indium and element M are mutually substituted. Thus, the (M, Zn) layer may contain indium. Also, the In layer may contain element M. Note that the In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0300] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD device, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0301] For example, a plurality of bright points (spots) are observed in the electron diffraction pattern of the CAAC-OS film, and the two spots are observed at positions symmetrical to each other with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0302] When the crystal region is observed from the specific direction, the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The above distortion may have a pentagonal or heptagonal lattice arrangement. In addition, no clear grain boundary can be confirmed in the CAAC-OS even in the vicinity of the distortion. That is, it is found that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is considered to be because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction and the bond distance between atoms changes due to the substitution of metal atoms.

[0303] A crystal structure in which clear grain boundaries are observed is called a polycrystal. The grain boundaries are likely to become recombination centers and capture carriers, causing a decrease in the on-current of a transistor and a decrease in field effect mobility. Therefore, CAAC-OS in which clear grain boundaries are not observed is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. In order to form a CAAC-OS, a structure containing Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the occurrence of grain boundaries more than In oxide.

[0304] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. In addition, since the crystallinity of an oxide semiconductor can be decreased by the inclusion of impurities or the generation of defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of an oxide semiconductor having the CAAC-OS are stable. Therefore, an oxide semiconductor having the CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, the use of the CAAC-OS in an OS transistor can increase the degree of freedom in the manufacturing process.

[0305] [nc-OS] The nc-OS has periodic atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has minute crystals. Note that the size of the minute crystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the minute crystals are also called nanocrystals. In addition, the nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is seen in the entire film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structure analysis is performed on an nc-OS film using an XRD device, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scan. In addition, when an nc-OS film is subjected to electron diffraction (also called selected area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystals (for example, 50 nm or more), a diffraction pattern like a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter (e.g., 1 nm to 30 nm) that is close to the size of a nanocrystal or smaller than the nanocrystal, an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on the direct spot may be obtained.

[0306] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Moreover, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0307] [Oxide semiconductor composition] Next, the above-mentioned CAC-OS will be described in detail, with reference to its material composition.

[0308] [CAC-OS] CAC-OS is, for example, a material configuration in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide and the regions having the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0309] Furthermore, CAC-OS is a composite metal oxide in which the material is separated into a first region and a second region, forming a mosaic structure, and the first region is distributed throughout the film (hereinafter, also referred to as a cloud structure). In other words, CAC-OS is a composite metal oxide in which the first region and the second region are mixed together.

[0310] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are represented as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0311] Specifically, the first region is a region mainly composed of indium oxide, indium zinc oxide, etc., and the second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region mainly composed of In, and the second region can be rephrased as a region mainly composed of Ga.

[0312] In addition, there are cases where a clear boundary between the first region and the second region cannot be observed.

[0313] For example, in the case of a CAC-OS of an In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) has confirmed that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0314] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, giving the CAC-OS a switching function (On / Off function). In other words, CAC-OS has a conductive function in part of the material and an insulating function in other parts of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, it is possible to maximize both functions. Therefore, by using CAC-OS in a transistor, it is possible to achieve a high on-current (I on ), high field effect mobility (μ), and good switching behavior can be achieved.

[0315] Oxide semiconductors have a variety of structures and each structure has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0316] [Transistor Having Oxide Semiconductor] Next, the case where the oxide semiconductor is used for a transistor will be described.

[0317] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0318] It is preferable to use an oxide semiconductor having a low carrier concentration for a channel formation region of a transistor. For example, the carrier concentration of the channel formation region of an oxide semiconductor is 1×10 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm-3 It is more preferable that the carrier concentration in the oxide semiconductor film is less than 100%. In order to reduce the carrier concentration in the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. An oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0319] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states might also be low.

[0320] In addition, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave as if they are fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0321] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0322] 〔impurities〕 Here, the influence of each impurity in an oxide semiconductor will be described.

[0323] When an oxide semiconductor contains silicon or carbon, which is one of the group 14 elements, defect levels are formed in the oxide semiconductor. For this reason, the concentrations of silicon and carbon in the channel formation region of the oxide semiconductor and the vicinity of the interface with the channel formation region of the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 18 atoms / cm 3Less than or equal to 2×10 17 atoms / cm 3 The following applies.

[0324] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed and carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 Less than or equal to 2×10 16 atoms / cm 3 To the following:

[0325] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 To the following:

[0326] Furthermore, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. In addition, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration measured by SIMS in the channel formation region of the oxide semiconductor is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0327] When an oxide semiconductor in which impurities are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0328] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiment modes and examples.

[0329] (Embodiment 6) In this embodiment, the configuration of an integrated circuit including the configuration of the semiconductor device 100 described in the above embodiment will be described with reference to FIGS.

[0330] FIG. 20 is an example of a block diagram for explaining an example of the configuration of an integrated circuit including the configuration of the semiconductor device 100. As shown in FIG.

[0331] The integrated circuit 390 shown in FIG. 20 includes a CPU 10, an accelerator 20, an on-chip memory 131, a DMAC (Direct Memory Access Controller) 141, a power supply circuit 160, a power management unit (PMU) 142, a security circuit 147, a memory controller 143, a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) controller 144, a USB (Universal Serial Bus) interface circuit 145, a display interface circuit 146, a bridge circuit 150, an interrupt control circuit 151, an interface circuit 152, a battery control circuit 153, and an ADC (Analog-to-digital converter) / DAC (Digital-to-analog converter) interface circuit 154.

[0332] The CPU 10 includes, for example, a CPU core 111, an instruction cache 112, a data cache 113, and a bus interface circuit 114. The accelerator 20 includes a memory circuit 121, an arithmetic circuit 122, and a drive circuit 123.

[0333] The CPU core 111 has multiple CPU cores. The instruction cache 112 may be a circuit configuration that temporarily stores instructions to be executed by the CPU core 111. The data cache 113 may be a circuit configuration that temporarily stores data to be processed by the CPU core 111 or data obtained by the processing. The bus interface circuit 114 may be a circuit configuration that can transmit and receive signals such as data and addresses to and from a bus that connects the CPU 10 to other circuits in the semiconductor device.

[0334] The memory circuit 121 corresponds to the memory circuit 24 described in the first embodiment. The memory circuit 121 may have a circuit configuration for storing data to be processed by the accelerator 20. The arithmetic circuit 122 corresponds to the arithmetic circuit 23 described in the first embodiment. The arithmetic circuit 122 may have a circuit configuration for performing arithmetic processing of data held in the memory circuit 121. The drive circuit 123 corresponds to a configuration including the drive circuit 15 described in the first embodiment. The drive circuit 123 may have a circuit configuration for controlling each circuit in the accelerator 20, as shown in FIG. 9B.

[0335] The high-speed bus 140A is a bus for transmitting and receiving various signals at high speed between the CPU 10, the accelerator 20, the on-chip memory 131, the DMAC 141, the power management unit 142, the security circuit 147, the memory controller 143, the DDR SDRAM controller 144, the USB interface circuit 145, and the display interface circuit 146. As an example, an AMBA (Advanced Microcontroller Bus Architecture)-AHB (Advanced High-performance Bus) can be used as the bus.

[0336] The on-chip memory 131 has a circuit configuration for storing data or programs to be input / output to / from the circuitry included in the integrated circuit 390, such as the CPU 10 or the accelerator 20.

[0337] The DMAC 141 is a direct memory access controller. By including the DMAC 141, peripheral devices other than the CPU 10 can access the on-chip memory 131 without going through the CPU 10.

[0338] The power management unit 142 has a circuit configuration for controlling power gating of circuits such as a CPU core included in the integrated circuit 390.

[0339] The security circuit 147 has a circuit configuration for enhancing the confidentiality of signals, such as by encrypting signals before transmitting and receiving signals between the integrated circuit 390 and an external circuit.

[0340] The memory controller 143 has circuitry for writing or reading a program to be executed by the CPU 10 or the accelerator 20 from a program memory external to the integrated circuit 390 .

[0341] The DDR SDRAM controller 144 includes circuitry for reading and writing data to and from a main memory, such as a DRAM, external to the integrated circuit 390 .

[0342] The USB interface circuit 145 has a circuit configuration for transmitting and receiving data to and from a circuit external to the integrated circuit 390 via a USB terminal.

[0343] The display interface circuit 146 comprises circuitry for sending and receiving data to and from a display device external to the integrated circuit 390 .

[0344] The power supply circuit 160 is a circuit for generating a voltage used in the integrated circuit 390. For example, it is a circuit for generating a negative voltage to be applied to the back gate of an OS transistor in order to stabilize the electrical characteristics.

[0345] The low-speed bus 140B is a bus for transmitting and receiving various signals at low speed between the interrupt control circuit 151, the interface circuit 152, the battery control circuit 153, and the ADC / DAC interface circuit 154. As an example, an AMBA-APB (Advanced Peripheral Bus) can be used as the bus. Various signals are transmitted and received between the high-speed bus 140A and the low-speed bus 140B via a bridge circuit 150.

[0346] The interrupt control circuit 151 has a circuit configuration for carrying out interrupt processing in response to a request received from a peripheral device.

[0347] The interface circuit 152 has a circuit configuration for operating interfaces such as a universal asynchronous receiver / transmitter (UART), an inter-integrated circuit (I2C), or a serial peripheral interface (SPI).

[0348] The battery control circuit 153 has circuitry for transmitting and receiving data relating to charging and discharging of a battery external to the integrated circuit 390 .

[0349] The ADC / DAC interface circuit 154 has a circuit configuration for transmitting and receiving data to and from a device that outputs an analog signal, such as a MEMS (Micro Electro Mechanical Systems) device, located outside the integrated circuit 390 .

[0350] 21A and 21B are diagrams showing an example of the layout of circuit blocks when implemented as an SoC. As in the integrated circuit 390 shown in FIG. 21A, each configuration shown in the block diagram of FIG. 20 can be arranged in separate regions on a chip.

[0351] 20 can be configured with a memory circuit configured with OS transistors, such as NOSRAM. That is, the on-chip memory 131 and the memory circuit 121 have the same circuit configuration. Therefore, when fabricated into an SoC, the on-chip memory 131 and the memory circuit 121 can be integrated and arranged in the same area, as in the integrated circuit 390E illustrated in FIG. 21B.

[0352] According to the above-described embodiment of the present invention, a novel semiconductor device and electronic device can be provided. According to another embodiment of the present invention, a semiconductor device and electronic device with low power consumption can be provided. According to another embodiment of the present invention, a semiconductor device and electronic device in which heat generation can be suppressed can be provided.

[0353] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0354] (Embodiment 7) In this embodiment mode, an electronic device, a mobile object, and a computing system to which the integrated circuit 390 described in the above embodiment mode can be applied will be described with reference to FIGS.

[0355] Fig. 22A shows an external view of an automobile as an example of a moving body. Fig. 22B shows a simplified diagram of data exchange within the automobile. The automobile 590 has a plurality of cameras 591 and the like. The automobile 590 also includes various sensors (not shown) such as an infrared radar, a millimeter wave radar, and a laser radar.

[0356] In an automobile 590, the above-mentioned integrated circuit 390 can be used for a camera 591, etc. In the automobile 590, a plurality of images obtained by a camera 591 in a plurality of imaging directions 592 are processed by the integrated circuit 390 described in the above embodiment, and the plurality of images are collectively analyzed by a host controller 594, etc. via a bus 593, etc., so that the automobile 590 can determine the surrounding traffic conditions, such as the presence or absence of guardrails or pedestrians, and perform automatic driving. The automobile 590 can also be used in a system that performs road guidance, hazard prediction, etc.

[0357] In the integrated circuit 390, the obtained image data can be subjected to arithmetic processing such as a neural network, thereby enabling processes such as increasing the image resolution, reducing image noise, facial recognition (for crime prevention purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reducing reflected glare.

[0358] Although an automobile is described above as an example of a moving object, the moving object is not limited to an automobile. For example, the moving object may be a train, a monorail, a ship, or an aircraft (helicopter, unmanned aerial vehicle (drone), airplane, or rocket). A semiconductor device according to one embodiment of the present invention may be applied to these moving objects to provide them with a system using artificial intelligence.

[0359] Fig. 23A is an external view showing an example of a portable electronic device. Fig. 23B is a simplified diagram showing data exchange within the portable electronic device. Portable electronic device 595 has a printed wiring board 596, a speaker 597, a camera 598, a microphone 599, and the like.

[0360] In portable electronic device 595, the integrated circuit 390 can be provided on printed circuit board 596. Portable electronic device 595 can improve user convenience by processing and analyzing a plurality of pieces of data obtained by speaker 597, camera 598, microphone 599, etc., using integrated circuit 390 described in the above embodiment. Also, the portable electronic device can be used in a system that performs voice guidance, image search, etc.

[0361] In the integrated circuit 390, the obtained image data can be subjected to arithmetic processing such as a neural network, thereby enabling processes such as increasing the image resolution, reducing image noise, facial recognition (for crime prevention purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reducing reflected glare.

[0362] A portable game machine 1100 shown in FIG. 24A includes a housing 1101, a housing 1102, a housing 1103, a display unit 1104, a connection unit 1105, an operation key 1107, and the like. The housings 1101, 1102, and 1103 are removable. By attaching the connection unit 1105 provided in the housing 1101 to the housing 1108, a video output to the display unit 1104 can be output to another video device. On the other hand, by attaching the housings 1102 and 1103 to the housing 1109, the housings 1102 and 1103 are integrated to function as an operation unit. The integrated circuit 390 described in the above embodiment can be incorporated in a chip provided on a substrate of the housings 1102 and 1103.

[0363] 24B shows a stick-type electronic device 1120 of a USB connection type. The electronic device 1120 has a housing 1121, a cap 1122, a USB connector 1123, and a board 1124. The board 1124 is housed in the housing 1121. For example, a memory chip 1125 and a controller chip 1126 are attached to the board 1124. The integrated circuit 390 shown in the previous embodiment can be incorporated in the controller chip 1126 of the board 1124, etc.

[0364] 24C shows a humanoid robot 1130. The robot 1130 has sensors 2101 to 2106 and a control circuit 2110. For example, the integrated circuit 390 shown in the previous embodiment can be incorporated into the control circuit 2110.

[0365] The integrated circuit 390 described in the above embodiment can be used in a server that communicates with the electronic device instead of being built into the electronic device. In this case, the electronic device and the server constitute a computing system. Figure 25 shows an example of the configuration of a system 3000.

[0366] The system 3000 is configured with an electronic device 3001 and a server 3002. Communication between the electronic device 3001 and the server 3002 can be performed via an Internet line 3003.

[0367] Server 3002 has a plurality of racks 3004. A plurality of boards 3005 are provided in the plurality of racks, and integrated circuits 390 described in the above embodiment can be mounted on the boards 3005. This forms a neural network in server 3002. Server 3002 can perform neural network calculations using data input from electronic device 3001 via internet line 3003. Results of calculations by server 3002 can be transmitted to electronic device 3001 via internet line 3003 as necessary. This can reduce the calculation load on electronic device 3001.

[0368] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes. EXAMPLES

[0369] In this embodiment, a simulation result for estimating the operation efficiency of the accelerator having the extremely excellent processing performance described in the first embodiment will be described.

[0370] The data used in the simulation assumes that the Si technology of the transistors that make up the accelerator is 55nm, and that the IGZO technology is 60nm. Parasitic capacitance was also added to each layout. The calculation efficiency was estimated assuming that all neurons (memory circuits) in the neural network are activated, that is, the multiplication and accumulation calculation by the neural network consumes more power. The number of memory circuits (memory cells) connected to one bit line was estimated at 16 cells, 32 cells, 64 cells, and 128 cells.

[0371] As a specific calculation example, in the case of 32 cells / bit line, it can be estimated as (2048 (PE) x 2 (two types of operations, multiply and add) x (50 MHz)) / (2048 (PE) x 20.2fJ x (50 MHz)) = 99 TOPS / W. Note that 2048 (PE) corresponds to the number of calculation circuits that can perform calculations at one time, in other words, the number of columns in the memory cell array. 20.2 fJ is the total energy obtained by adding the read energy from the memory cells (13.9 fJ) to the product-sum calculation energy (6.3 fJ) required for the product-sum calculation.

[0372] That is, in the circuit diagram shown in Fig. 26, the calculation efficiency was estimated when the number of columns of the memory circuit 24 (PE) is 2048. In the case of Fig. 26, the two bit lines, the bit lines PBL_1 to PBL_N and the bit lines NBL_1 to NBL_N, are charged and discharged, and the larger the number of memory cells connected to one bit line, the larger the read energy from the memory cells (corresponding to the memory unit 22) becomes. The product-sum calculation energy (corresponding to the calculation processing unit 21) can be estimated to be 6.3 fJ, regardless of the number of memory cells connected to one bit line.

[0373] 26 shows word lines WL_1 to WL_M as other components. In addition, in the arithmetic processing unit that performs the product-sum operation, a plurality of logic blocks that perform multiplication and a plurality of logic blocks that perform addition are shown. In the logic block that performs multiplication, signals from the bit lines PBL and NBL and input data A1 are input, and multiplied data Y1 to Y N The data Y1 to Y N The data Y is added together and multiplied and accumulated. AS The configuration for obtaining the above is illustrated.

[0374] The above is summarized in Table 4. As shown in Table 4, the calculation efficiency was obtained when the number of memory cells was estimated to be 16 cells, 32 cells, 64 cells, and 128 cells.

[0375] [Table 4]

[0376] As shown in Table 4, it was found that by using the semiconductor device of one embodiment of the present invention, a computing efficiency of 100 TOPS / W or more can be expected.

[0377] (Additional notes regarding the present specification, etc.) The above embodiment and each configuration in the embodiment will be described below with additional notes.

[0378] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments or examples to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0379] In addition, the content (or a part of the content) described in one embodiment can be applied to, combined with, or replaced by another content (or a part of the content) described in that embodiment, and / or the content (or a part of the content) described in one or more other embodiments.

[0380] The contents described in the embodiments refer to contents described in each embodiment using various figures or contents described using text in the specification.

[0381] In addition, a figure (or a part of it) described in one embodiment can be combined with another part of that figure, with another figure (or a part of it) described in that embodiment, and / or with a figure (or a part of it) described in one or more other embodiments to form even more figures.

[0382] In addition, in the present specification and the like, in the block diagrams, the components are classified by function and shown as mutually independent blocks. However, in actual circuits and the like, it is difficult to separate the components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, and may be rephrased appropriately according to the situation.

[0383] In addition, in the drawings, the size, layer thickness, or region are shown at an arbitrary size for convenience of explanation. Therefore, they are not necessarily limited to the scale. Note that the drawings are shown diagrammatically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0384] In addition, the positional relationship of components shown in the drawings is relative. Therefore, when describing components with reference to the drawings, terms such as "above" and "below" that indicate the positional relationship may be used for convenience. The positional relationship of components is not limited to the contents described in this specification, and can be rephrased appropriately depending on the situation.

[0385] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode, or first terminal) and "the other of the source or drain" (or second electrode, or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like depending on the situation.

[0386] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are formed integrally.

[0387] In addition, in this specification and the like, voltage and potential can be interchanged as appropriate. Voltage is a potential difference from a reference potential, and if the reference potential is a ground voltage (earth voltage), for example, voltage can be interchanged with potential. Ground potential does not necessarily mean 0V. Note that potential is relative, and the potential applied to wiring, etc. may be changed depending on the reference potential.

[0388] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on a circuit configuration, a device structure, etc. Also, a terminal, a wiring, etc. can be referred to as a node.

[0389] In this specification, A and B are connected means that A and B are electrically connected. Here, A and B are electrically connected means a connection in which an electrical signal between A and B can be transmitted when an object (an element such as a switch, a transistor element, or a diode, or a circuit including the element and wiring) exists between A and B. Note that when A and B are electrically connected, this includes a case in which A and B are directly connected. Here, A and B are directly connected means a connection in which an electrical signal between A and B can be transmitted through wiring (or electrodes) between A and B without passing through the object. In other words, a direct connection means a connection that can be regarded as the same circuit diagram when expressed as an equivalent circuit.

[0390] In this specification, a switch refers to a device that has a function of controlling whether a current flows or not by being in a conductive state (on state) or a non-conductive state (off state), or a device that has a function of selecting and switching a path for a current to flow.

[0391] In this specification, the channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between the source and drain in a region where a channel is formed.

[0392] In this specification, the channel width refers to, for example, the length of the region where a semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and a gate electrode overlap, or the length of the portion where a source and a drain face each other in a region in which a channel is formed.

[0393] In this specification and the like, the terms "film" and "layer" can be interchanged depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film". Or, for example, the term "insulating film" can be changed to the term "insulating layer". [Explanation of symbols]

[0394] : M11: transistor, M12: transistor, M13: transistor, 10: CPU, 11: CPU core, 12: backup circuit, 15: drive circuit, 20: accelerator, 21: arithmetic processing unit, 22: memory unit, 22_N: memory unit, 22_1: memory unit, 22_6: memory unit, 23: arithmetic circuit, 23_N: arithmetic circuit, 23_1: arithmetic circuit, 23_6: arithmetic circuit, 24: memory circuit, 25: transistor, 27: transistor, 29: semiconductor layer, 30: bus, 31: data retention circuit, 31_N: data retention circuit, 31_P: data retention circuit, 32: transistor, 32_N: transistor, 32_P: transistor, 33: transistor, 33_N: transistor, 33_P: transistor, 34: transistor, 35: capacitance element, 42: logic circuit, 43: accumulator, 44: latch circuit, 45: encoding circuit, 50: neuron, 51: layer, 52: layer, 53: layer, 54: layer, 61: controller, 62: row decoder, 63: word line driver, 64: column decoder, 65: write driver, 66: precharge circuit, 71: input buffer, 72: arithmetic control circuit, 100: semiconductor device, 111 : CPU core, 112: instruction cache, 113: data cache, 114: bus interface circuit, 121: memory circuit, 122: arithmetic circuit, 123: drive circuit, 131: on-chip memory, 140A: high-speed bus, 140B: low-speed bus, 141: DMAC, 142: power management unit, 143: memory controller, 144: controller, 145: interface circuit, 146: display interface circuit, 147: security circuit, 150: bridge circuit, 151: control circuit, 152: interface circuit, 15 3: battery control circuit, 154: interface circuit, 160: power supply circuit, 193: PMU, 200: CPU core, 202: cache memory device, 203: cache memory device, 205: bus interface unit, 210: power switch, 211: power switch, 212: power switch, 214: level shifter, 220: flip-flop, 221: scan flip-flop, 221A: clock buffer circuit, 222: backup circuit, 311: substrate, 312: well region, 313: insulator, 314: oxide layer, 315: semiconductor region,316a: low resistance region, 316b: low resistance region, 316c: low resistance region, 317: insulator, 318: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 350: insulator, 352: insulator, 354: insulator, 356: conductor, 360: insulator, 362: insulator, 364: insulator, 366: conductor, 370: insulator, 372: insulator, 374: insulator, 376: conductor, 380: insulator, 382: insulator, 384: insulator, 386: conductor, 390: integrated circuit, 390E: integrated circuit, 404: insulator body, 500: transistor, 500A: transistor, 500B: transistor, 503: conductor, 503a: conductor, 503b: conductor, 510: insulator, 512: insulator, 513: insulator, 514: insulator, 516: insulator, 518: conductor, 520: insulator, 522: insulator, 524: insulator, 526: insulator, 530: oxide, 530a: oxide, 530b: oxide, 540a: conductor, 540b: conductor, 542: conductor, 542a: conductor, 542b: conductor, 543a: region, 543b: region, 544: insulator, 545: insulator, 546: conductor conductor, 548: conductor, 550: transistor, 552: insulator, 560: conductor, 560a: conductor, 560b: conductor, 574: insulator, 580: insulator, 581: insulator, 582: insulator, 586: insulator, 590: automobile, 591: camera, 592: imaging direction, 593: bus, 594: host controller, 595: portable electronic device, 596: printed wiring board, 597: speaker, 598: camera, 599: microphone, 600: capacitive element, 610: conductor, 612: conductor, 620: conductor, 630: insulator, 640: insulator, 910: Area, 912: area, 914: power, 916: power, 918: power, 920: power, 922: power, 1100: portable game machine, 1101: housing, 1102: housing, 1103: housing, 1104: display unit, 1105: connection unit, 1107: operation key, 1108: housing, 1109: housing, 1120: electronic device, 1121: housing, 1122: cap, 1123: USB connector, 1124: board, 1125: memory chip, 1126: controller chip, 1130: robot, 2101: sensor, 2106: sensor, 2110: control circuit, 3000: system,3001: Electronic equipment, 3002: Server, 3003: Internet line, 3004: Rack, 3005: Circuit board,

Claims

[Claim 1] A CPU, an accelerator; the accelerator includes a first memory circuit, a drive circuit, and a multiply-accumulate circuit; the first memory circuit has a first data holding unit, a second data holding unit, and a data reading unit; the first data held in the first data holding unit and the second data held in the second data holding unit are weight data to be input to the product-sum calculation circuit, the sum-of-products calculation circuit has a function of performing a sum-of-products calculation of the weight data and input data input via the driving circuit, the first data holding unit includes a first transistor and a first capacitance element; the second data holding unit includes a second transistor and a second capacitance element; the data read unit includes third to sixth transistors, one of a source and a drain of the first transistor is electrically connected to one electrode of the first capacitance element and a gate of the fourth transistor; one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor; one of a source and a drain of the second transistor is electrically connected to one electrode of the second capacitance element and a gate of the fifth transistor; one of a source and a drain of the sixth transistor is electrically connected to one of a source and a drain of the fifth transistor; each of the first transistor to the sixth transistor has a channel formation region in a first semiconductor layer including a metal oxide; each of the multiply-accumulate circuit and the drive circuit includes a seventh transistor; the seventh transistor has a channel formation region in a second semiconductor layer containing silicon; Semiconductor device.

Images