Image sensor

Abstract

To provide an image sensor in which coupling between a floating diffusion region and a wiring is reduced and which therefore has an improved efficiency, and to provide a manufacturing method of the image sensor.SOLUTION: An image sensor includes: a first substrate 400 including a first surface 400a and a second surface 400b which are opposite to each other, and including a photoelectric conversion region 410; a transmission transistor TX which is positioned at the first surface of the first substrate; a second substrate 500 including a first surface 500a and a second surface 500b which are opposite to each other; a plurality of transistors which are positioned at the first surface of the second substrate, and are coupled to the transmission transistor; a plurality of wirings which are positioned at the second surface of the second substrate; and a dip node DN which penetrates through the second substrate. The first surface of the first substrate and the first surface of the second substrate are faced each other. One or more of the plurality of transistors positioned at the first surface of the second substrate and the plurality of wirings positioned at the second surface of the second substrate are coupled to each other via the dip node.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to an image sensor and a method for manufacturing an image sensor. [Background technology]

[0002] An image sensor is a semiconductor device that converts an optical image into an electrical signal. Image sensors are classified into CCD (Charge Coupled Device) type and CMOS (Complementary Metal Oxide Semiconductor) type. CMOS type image sensors are abbreviated as CIS (CMOS image sensor). CIS has multiple pixels arranged two-dimensionally. Each pixel includes a photodiode (PD). The photodiode converts incident light into an electrical signal.

[0003] In recent years, image sensors have been proposed in which a semiconductor wafer having a plurality of pixels and a semiconductor wafer including a transistor for reading signal charges in a charge storage portion are stacked. Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention provides an image sensor and a method for fabricating the same that has improved efficiency by reducing coupling between a floating diffusion region and wiring. [Means for solving the problem]

[0005] An image sensor according to one embodiment includes a first substrate including a photoelectric conversion region having a first surface and a second surface facing each other, a transfer transistor located on the first surface of the first substrate, a second substrate including a first surface and a second surface facing each other, a plurality of transistors located on the first surface of the second substrate and connected to the transfer transistor, a plurality of wirings located on the second surface of the second substrate, and a dip node penetrating the second substrate, wherein the first surface of the first substrate and the first surface of the second substrate face each other, and one or more of the plurality of transistors located on the first surface of the second substrate and the plurality of wirings located on the second surface of the second substrate are connected via the dip node.

[0006] According to another embodiment, an image sensor includes a first substrate including a first surface and a second surface facing each other and including a photoelectric conversion region, a light transmitting layer located on the second surface of the first substrate, a transfer transistor located on the first surface of the first substrate, a first wiring region located on the first surface of the first substrate, a second substrate including a first surface and a second surface facing each other, a plurality of transistors located on the first surface of the second substrate and connected to the transfer transistor, a second wiring region located on the first surface of the second substrate, a third wiring region located on the second surface of the second substrate, and a dip node penetrating the second substrate, wherein the first surface of the first substrate and the first surface of the second substrate face each other, and at least a portion of the wiring located in the second wiring region and the wiring located in the third wiring region are connected via the dip node.

[0007] A method for manufacturing an image sensor according to one embodiment includes the steps of: preparing a first substrate having a first surface and a second surface facing each other, the first substrate including a transfer transistor and a first wiring region located on the first surface; preparing a second substrate having a first surface and a second surface facing each other, the second substrate including a transfer transistor and a second wiring region located on the first surface; bonding the first substrate and the second substrate such that the first surface of the first substrate faces the first surface of the second substrate; forming a dip node on the second surface of the second substrate that penetrates the second substrate in a direction toward the first surface of the second substrate; and forming a third wiring region on the second surface of the second substrate, wherein at least a portion of the wiring located in the second wiring region and the wiring located in the third wiring region are connected via the dip node. Effect of the Invention

[0008] According to an embodiment, an image sensor having improved efficiency by reducing coupling between a floating diffusion region and wiring and a method for manufacturing the same are provided. [Brief description of the drawings]

[0009] [Figure 1] 1 is an exemplary block diagram of an image sensor according to an embodiment; [Diagram 2] 2 is a circuit diagram showing one pixel included in an image sensor according to an embodiment of the present invention; [Diagram 3] 1 is a plan view showing an image sensor according to an embodiment of the present invention; [Figure 4] 1 is a partial cross-sectional view of one pixel (PX) of an image sensor according to the present embodiment. [Diagram 5] 1 illustrates the planar arrangement of one pixel on a first substrate. [Figure 6] 1 illustrates the planar arrangement of one pixel on a first substrate. [Figure 7] 1 illustrates the planar arrangement of one pixel on a first substrate. [Figure 8]1 illustrates the planar arrangement of the first and second surfaces of the second substrate for one pixel. [Figure 9] 1 illustrates the planar arrangement of the first and second surfaces of the second substrate for one pixel. [Figure 10] 1 illustrates the planar arrangement of the first and second surfaces of the second substrate for one pixel. [Figure 11] 1 illustrates the planar arrangement of the first and second surfaces of the second substrate for one pixel. [Figure 12] 1 shows a manufacturing process of the image sensor according to the present embodiment. [Figure 13] 1 shows a manufacturing process of the image sensor according to the present embodiment. [Figure 14] 1 shows a manufacturing process of the image sensor according to the present embodiment. [Figure 15] 1 shows a manufacturing process of the image sensor according to the present embodiment. [Figure 16] 1 shows a manufacturing process of the image sensor according to the present embodiment. [Figure 17] 1 shows a manufacturing process of the image sensor according to the present embodiment. [Figure 18] 1 shows a manufacturing process of the image sensor according to the present embodiment. [Figure 19] 1 illustrates an image sensor according to another embodiment. [Figure 20] 10 is a circuit diagram similar to FIG. 2 for an image sensor according to another embodiment. [Figure 21] 5 shows a cross section similar to FIG. 4 for another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention may be embodied in various different forms and is not limited to the embodiments described herein.

[0011] In order to clearly describe the present invention, parts not necessary for the description will be omitted, and the same reference numerals will be used throughout the specification to refer to the same or similar components.

[0012] In addition, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, and the present invention is not necessarily limited to those shown in the drawings. In the drawings, thicknesses are enlarged to clearly express various layers and regions. In the drawings, thicknesses of some layers and regions are exaggerated for convenience of explanation.

[0013] Furthermore, when a part such as a layer, film, region, or plate is said to be "on" or "above" another part, this includes not only the case where it is "directly above" the other part, but also the case where there is another part in between. Conversely, when a part is said to be "directly above" another part, it means that there is no other part in between. Furthermore, being "on" or "above" a reference part means being located above or below the reference part, and does not necessarily mean being located "on" or "above" the side opposite to gravity.

[0014] Additionally, throughout the specification, when a part is said to "comprise" a certain element, this means that it may further include other elements, but not excluding other elements, unless specifically stated to the contrary.

[0015] Also, throughout the specification, "in a plane" means when the part is viewed from above, and "in cross section" means when the part is cut vertically and viewed from the side.

[0016] FIG. 1 is an exemplary block diagram of an image sensor according to an embodiment.

[0017] 1, an image sensor 100 according to an embodiment may include a controller 110, a timing generator 120, a row driver 130, a pixel array 140, a readout circuit 150, a ramp signal generator 160, a data buffer 170, and an image signal processor 180. In an embodiment, the image signal processor 180 may be located outside the image sensor 100.

[0018] The image sensor 100 may convert light received from the outside into an electrical signal to generate an image signal. The image signal (IMS) may be provided to an image signal processor 180.

[0019] The image sensor 100 is mounted in an electronic device having an image or light sensing function. For example, the image sensor 100 is mounted in electronic devices such as a camera, a smartphone, a wearable device, an Internet of Things (IoT) device, a home appliance, a tablet PC (Personal Computer), a PDA (Personal Digital Assistant), a PMP (Portable Multimedia Player), a navigation device, a drone, an advanced driver assistance system (ADAS), etc. Alternatively, the image sensor 100 is mounted in an electronic device provided as a component in a vehicle, furniture, manufacturing equipment, a door, various measuring instruments, etc.

[0020] The controller 110 may generally control each of the components 120, 130, 150, 160, and 170 included in the image sensor 100. The controller 110 may also control the operation timing of each of the components 120, 130, 150, 160, and 170 using a control signal. In one embodiment, the controller 110 may receive a mode signal indicating an imaging mode from an application processor and generally control the image sensor 100 based on the received mode signal. For example, the application processor may determine an imaging mode of the image sensor 100 according to various scenarios such as the illuminance of an imaging environment, a user's resolution setting, a sensed or learned state, and provide the determined result to the controller 110 as a mode signal. The controller 110 may control a plurality of pixels of the pixel array 140 to output pixel signals according to an imaging mode, the pixel array 140 may output pixel signals for each of the plurality of pixels or for a portion of the plurality of pixels, and the readout circuit 150 may sample and process the pixel signals transmitted from the pixel array 140. The timing generator 120 can generate a signal that is a reference for the operation timing of the components of the image sensor 100. The timing generator 120 can control the timing of the row driver 130, the readout circuit 150, and the ramp signal generator 160. The timing generator 120 can provide a control signal that controls the timing of the row driver 130, the readout circuit 150, and the ramp signal generator 160.

[0021] The pixel array 140 may include a plurality of pixels (PX), and a plurality of row lines (RL) and a plurality of column lines (LL) respectively connected to the plurality of pixels (PX). In one embodiment, each pixel (PX) may include at least one photoelectric conversion element. The photoelectric conversion element may sense incident light and convert the incident light into an electrical signal corresponding to the amount of light, that is, a plurality of analog pixel signals. The photoelectric conversion element may be a photodiode, a pin diode, or the like. The photoelectric conversion element may also be a SPAD (Single-Photon Avalanche Diode) applied to a 3D sensor pixel. The level of the analog pixel signal output from the photoelectric conversion element may be proportional to the amount of charge output from the photoelectric conversion element. That is, the level of the analog pixel signal output from the photoelectric conversion element is determined according to the amount of light received in the pixel array 140.

[0022] The row lines (RL) extend in a first direction and are connected to the pixels (PX) arranged along the first direction. For example, a control signal output from the row driver 130 to the row lines (RL) can be transmitted to gates of transistors of the pixels (PX) connected to the row lines (RL). The column lines (LL) extend in a second direction intersecting the first direction and are connected to the pixels (PX) arranged along the second direction. A plurality of pixel signals output from the pixels (PX) can be transmitted to the readout circuit 150 via the column lines (LL).

[0023] A color filter layer and a microlens layer may be located on the pixel array 140. The microlens layer may include a plurality of microlenses, and each of the plurality of microlenses may be located above at least one corresponding pixel (PX). The color filter layer may include color filters of red, green, blue, etc., and may additionally include a white filter. For one pixel (PX), a color filter of one color may be located between the pixel (PX) and the corresponding microlens. Specific structures of the color filter layer and the microlens layer will be described later with reference to FIG. 4.

[0024] The row driver 130 generates a control signal for driving the pixel array 140 in response to a control signal from the timing generator 120, and provides the control signal to a plurality of pixels (PX) of the pixel array 140 through a plurality of row lines (RL). In one embodiment, the row driver 130 controls the pixels (PX) to sense incident light in row line units. The row line unit may include at least one row line (RL). For example, the row driver 130 may provide a transmission signal (TS), a reset signal (RS), a selection signal (SEL), and the like to the pixel array 140 as described below.

[0025] The readout circuit 150 may convert a pixel signal (or an electrical signal) from a pixel (PX) connected to a row line (RL) selected from among a plurality of pixels (PX) into a pixel value indicating the amount of light in response to a control signal from the timing generator 120. The readout circuit 150 may convert a pixel signal outputted through a corresponding column line (LL) into a pixel value. For example, the readout circuit 150 may convert the pixel signal into a pixel value by comparing a ramp signal with the pixel signal. The pixel value may be image data having a plurality of bits. Specifically, the readout circuit 150 may include a selector, a plurality of comparators, a plurality of counter circuits, and the like.

[0026] The ramp signal generator 160 may generate and transmit a reference signal to the readout circuit 150 .

[0027] The ramp signal generator 160 may include a current source, a resistor, and a capacitor. The ramp signal generator 160 may generate a plurality of ramp signals that rise or fall at a slope determined by the magnitude of the current of the variable current source or the resistance value of the variable resistor by adjusting a ramp voltage, which is a voltage applied to the ramp resistor, by adjusting the magnitude of the current of the variable current source or the resistance value of the variable resistor.

[0028] The data buffer 170 can store pixel values ​​of a plurality of pixels (PX) connected to a selected column line (LL) transmitted from the readout circuit 150, and output the stored pixel values ​​in response to an enable signal from the controller 110.

[0029] The image signal processor 180 may perform image signal processing on the image signal received from the data buffer 170. For example, the image signal processor 180 may receive a plurality of image signals from the data buffer 170 and synthesize the received image signals to generate one image.

[0030] In one embodiment, a plurality of pixels may be grouped in an M*N (M and N are integers equal to or greater than 2) configuration to form one unit pixel group. The M*N configuration may be a configuration in which M pixels are arranged in the arrangement direction of the column lines (LL) and N pixels are arranged in the arrangement direction of the row lines (RL). For example, one unit pixel group includes a plurality of pixels arranged in a 2*2 configuration, and one unit pixel group can output one analog pixel signal. The following embodiment is not limited to one pixel, and may also be applied to a unit pixel group.

[0031] FIG. 2 is a circuit diagram of one pixel included in an image sensor according to an embodiment of the present invention.

[0032] Referring to FIG. 2, one pixel may include a plurality of photoelectric conversion elements (PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8). Each of the photoelectric conversion elements (PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8) may perform photoelectric conversion. As shown in FIG. 2, a plurality of photoelectric conversion elements (PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8) may be connected to one floating diffusion region (FD). Although FIG. 2 illustrates a configuration in which eight photoelectric conversion elements are connected to one floating diffusion region (FD), this is merely an example, and the number of photoelectric conversion elements connected to one floating diffusion region (FD) may vary depending on the embodiment.

[0033] The following description will focus on the first photoelectric conversion element (PD1), but the following description also applies to the other photoelectric conversion elements (PD2, PD3, PD4, PD5, PD6, PD7, and PD8).

[0034] The first photoelectric conversion element (PD1) can generate and accumulate electric charges according to the amount of light received. The first photoelectric conversion element (PD1) can include an anode connected to ground and a cathode connected to one end of the first transmission transistor (TX1). A first transmission signal (TS1) is supplied to a gate (TG1) of the first transmission transistor (TX1), and one end of the first transmission transistor (TX1) is connected to the floating diffusion region (FD). When the first transmission transistor (TX1) is turned on by the first transmission signal (TS1), the electric charges stored in the first photoelectric conversion element (PD1) are transferred to the floating diffusion region (FD). The floating diffusion region (FD) can hold the electric charges transferred from the photoelectric conversion element (PD).

[0035] Each of the plurality of transmission transistors (TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8) may include a gate electrode (TG1, TG2, TG3, TG4, TG5, TG6, TG7, TG8) connected between one of the plurality of photoelectric conversion elements (PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8) and the floating diffusion region (FD) and receiving a plurality of transmission signals (TS1, TS2, TS3, TS4, TS5, TS6, TS7, TS8). For example, the first transmission transistor (TX1) may include a gate electrode (TG1) connected between the first photoelectric conversion element (PD1) and the floating diffusion region (FD) and receiving a first transmission signal (TS1). The number of the multiple transmission transistors (TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8) may be the same as the number of the multiple photoelectric conversion elements (PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8).

[0036] The reset transistor RX is connected between a power supply voltage VDD and the floating diffusion region FD, and may include a gate electrode RG that receives a reset signal RS.

[0037] The reset transistor (RX) can periodically reset the charge accumulated in the floating diffusion region (FD). The drain electrode of the reset transistor (RX) is connected to the source electrode of the dual conversion transistor (DCX), and the source electrode is connected to the power supply voltage (VDD). When the reset transistor (RX) is turned on, the power supply voltage (VDD) connected to the source electrode of the reset transistor (RX) can be applied to the floating diffusion region (FD). Therefore, when the reset transistor (RX) is turned on, the charge accumulated in the floating diffusion region (FD) is discharged and the floating diffusion region (FD) is reset.

[0038] The dual conversion transistor (DCX) is located between the reset transistor (RX) and the floating diffusion region (FD) and may include a gate electrode (DCG) that receives a dual conversion signal (DCS). The dual conversion transistor (DCX) may reset the floating diffusion region (FD) together with the reset transistor (RX).

[0039] The drain electrode of the dual conversion transistor (DCX) is connected to the floating diffusion region (FD), and the source electrode of the dual conversion transistor (DCX) is connected to the drain electrode of the reset transistor (RX). When the reset transistor (RX) and the dual conversion transistor (DCX) are turned on, the power supply voltage (VDD) connected to the source electrode of the reset transistor (RX) is applied to the floating diffusion region (FD) through the dual conversion transistor (DCX). Therefore, the charge accumulated in the floating diffusion region (FD) is discharged and the floating diffusion region (FD) is reset.

[0040] The amplifying transistor (SX) can output a pixel signal according to the voltage of the floating diffusion region (FD). The gate (SF) of the amplifying transistor (SX) is connected to the floating diffusion region (FD), a power supply voltage (VDD) is supplied to the source electrode of the amplifying transistor (SX), and a drain electrode of the amplifying transistor (SX) is connected to one end of the selection transistor (AX). The amplifying transistor (SX) forms a source follower circuit and can output a voltage level corresponding to the charge accumulated in the floating diffusion region (FD) to the pixel signal.

[0041] When the selection transistor (AX) is turned on by the selection signal (SEL), the pixel signal from the amplification transistor (SX) is transmitted to the readout circuit. The selection signal (SEL) is applied to the gate electrode (AG) of the selection transistor (AX), and the drain electrode of the selection transistor (AX) is connected to the output wiring (Vout) that outputs a plurality of pixel signals.

[0042] The operation of the image sensor will be described with reference to FIG. 2. First, with light blocked, a power supply voltage (VDD) is applied to the drain electrode of the reset transistor (RX) and the drain electrode of the amplifying transistor (SX), turning on the reset transistor (RX) and the dual conversion transistor (DCX) to release the charge remaining in the floating diffusion region (FD). After that, the reset transistor (RX) is turned off, and when external light is incident on the photoelectric conversion elements (PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8), electron-hole pairs are generated in each of the photoelectric conversion elements (PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8). The holes move to the p-type impurity regions of the photoelectric conversion elements (PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8) and the electrons move to the n-type impurity regions and are stored there. When the transmission transistors (TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8) are turned on, these charges such as electrons and holes are transferred to the floating diffusion region (FD) and stored. The gate bias of the amplification transistor (SX) changes in proportion to the amount of stored charge, causing a change in the source potential of the amplification transistor (SX). At this time, when the selection transistor (AX) is turned on, the signal generated by the charge is read out of the output wiring (Vout).

[0043] The wiring may be electrically connected to at least one of the gate electrodes (TG1, TG2, TG3, TG4, TG5, TG6, TG7, TG8) of the transfer transistors (TX1, TX2, TX3, TX5, TX6, TX7, TX8), the gate electrode (SF) of the amplifying transistor (SX), the gate electrode (DCG) of the dual conversion transistor (DCX), the gate electrode (RG) of the reset transistor (RX), and the gate electrode (AG) of the selection transistor (AX). The wiring may include a power supply voltage transmission wiring that applies a power supply voltage (VDD) to the source electrode of the reset transistor (RX) or the source electrode of the amplifying transistor (SX). The wiring may include an output wiring (Vout) connected to the selection transistor (AX).

[0044] As will be described in detail below with reference to Fig. 4, the image sensor according to this embodiment may include a first chip 1000, a second chip 2000, and a third chip 3000. In this case, the portion marked with A in the circuit diagram of Fig. 2 may be located in the first chip 1000, and the region marked with B may be located in the second chip 2000. The floating diffusion region (FD) of the first chip 1000 is connected to the second chip 2000 via floating diffusion region connection nodes (FDCN_1, FDCN_2), and a specific connection structure will be described later.

[0045] In the region shown in B of FIG. 2, some wirings connected to transistors are shown in bold. Specifically, a power supply voltage transmission wiring for transmitting a power supply voltage (VDD) to the reset transistor (RX) and the amplification transistor (SX), a wiring connected to the gate electrode (RG) of the reset transistor (RX) and transmitting a reset signal (RS), a wiring connected to the gate electrode (DCG) of the dual conversion transistor (DCX) and transmitting a dual conversion signal (DCS), a wiring connected to the gate electrode (AG) of the selection transistor (AX) and transmitting a selection signal (SEL), an output wiring (Vout) connected to the drain electrode of the selection transistor (AX), etc. are shown in bold. One or more of the wirings shown in bold may be located on a different plane from the gate electrodes (RG, DCG, SF, SELG) of the respective transistors (RX, DCX, SX, AX). As will be described in detail with reference to FIG. 4, the transistors (RX, DCX, SX, AX) may be located on a first surface 500a of the second substrate 500 included in the second chip 2000, and one or more of the wirings connected to the transistors (RX, DCX, SX, AX) may be located on a second surface 500b of the second substrate 500. The transistors (RX, DCX, SX, AX) and the wirings are connected via a dip node (DN) penetrating the second substrate 500. The image sensor having this structure may increase the conversion gain (CG) by shortening the length of the connection of the floating diffusion region (FD) between the first chip 1000 and the second chip 2000, and may reduce coupling between the floating diffusion region (FD) and the wirings. Specific effects will be described separately below.

[0046] Fig. 3 is a plan view showing an image sensor according to an embodiment of the present invention. Fig. 4 is a partial cross-sectional view of one pixel (PX) of the image sensor according to the embodiment. However, the contents of Fig. 3 and Fig. 4 are merely examples and the present invention is not limited thereto.

[0047] 3 and 4, the image sensor according to this embodiment may include a first chip 1000, a second chip 2000, and a third chip 3000. The first chip 1000 may include a photoelectric conversion layer 10, a first wiring region 20, and a light transmission layer 30. The photoelectric conversion layer 10 may include a first substrate 400, a pixel isolation pattern 450, an element isolation pattern 403, and a photoelectric conversion region 410 located in the first substrate 400. Light incident from the outside is converted into an electrical signal in the photoelectric conversion region 410.

[0048] 3, the first substrate 400 may include a pixel array region (AR), an optical black region (OB) and a pad region (PAD) on a plane. The pixel array region (AR) may be located in a central region of the first substrate 400 on a plane. The pixel array region (AR) may include a plurality of pixels (PX). The pixels (PX) may output photoelectric signals from incident light. The pixels (PX) are arranged along rows aligned with a first direction (D1) and columns aligned with a second direction (D2).

[0049] The pad area (PAD) may be located at an edge portion of the first substrate 400 and surround the pixel array area (AR). A plurality of pad terminals 90 may be located in the pad area (PAD). The pad terminals 90 may output electrical signals generated in the pixels (PX) to the outside. Alternatively, an external electrical signal or voltage may be transmitted to the pixels (PX) via the pad terminals 90. Since the pad area (PAD) is located at the edge portion of the first substrate 400, the pad terminals 90 may be easily connected to the outside.

[0050] The optical black area (OB) is disposed between the pixel array area (AR) and the pad area (PAD) of the first substrate 400. The optical black area (OB) may surround the pixel array area (AR). The pixels located in the optical black area (OB) may include a dummy area instead of the photoelectric conversion area 410. The signal generated in the dummy area may be used as information for removing process noise.

[0051] Hereinafter, the stacked structure of the image sensor will be described in detail with reference to Fig. 4. The image sensor according to this embodiment may include a first chip 1000, a second chip 2000 and a third chip 3000.

[0052] The first chip 1000 includes a photoelectric conversion layer 10 and is a layer that generates a photoelectric signal, and the second chip 2000 may be a layer in which transistors such as a reset transistor (RX), a dual conversion transistor (DCX), an amplification transistor (SX) and a selection transistor (AX) and wiring connected to each transistor are located. A logic circuit may be located in the third chip 3000.

[0053] This embodiment is characterized in that at least one of the wirings connected to the reset transistor (RX), dual conversion transistor (DCX), amplifying transistor (SX) and selecting transistor (AX) of the second chip 2000 is located on the opposite side of the reset transistor (RX), dual conversion transistor (DCX), amplifying transistor (SX) and selecting transistor (AX). That is, the reset transistor (RX), dual conversion transistor (DCX), amplifying transistor (SX) and selecting transistor (AX) are connected to wirings through a dip node (DN) penetrating the second substrate 500 of the second chip 2000. Therefore, as will be described separately below, the length of the connection between the floating diffusion region (FD) in the first chip 1000 and the second chip 2000 is shortened, so that the conversion gain (CG) can be increased and the coupling between the floating diffusion region (FD) and the wiring can be reduced.

[0054] This will be described in detail below with reference to FIG.

[0055] The first chip 1000 includes a first substrate 400. The first substrate 400 may include a first surface 400a and a second surface 400b facing each other. Light may be incident on the second surface 400b of the first substrate 400. The first wiring region 20 may be located on the first surface 400a of the first substrate 400, and the light transmission layer 30 may be located on the second surface 400b of the first substrate 400. The first substrate 400 may be a semiconductor substrate or a silicon on insulator (SOI) substrate. For example, the semiconductor substrate may include a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The first substrate 400 may include a first conductive type impurity. For example, the first conductive type impurity may be a p-type impurity such as aluminum (Al), boron (B), indium (In), and gallium (Ga).

[0056] The first substrate 400 may include a pixel separation pattern 450. The pixel separation pattern 450 may define a plurality of unit pixels. In addition, when a pixel includes a plurality of photoelectric conversion regions, the pixel separation pattern 450 may be located between the photoelectric conversion regions. FIG. 4 illustrates a portion of a cross section of a pixel, and two photoelectric conversion regions are illustrated on the cross section. However, this is a fictitious cross section for convenience of explanation, and the present invention is not limited thereto. That is, as illustrated in FIG. 2, a pixel may include eight photoelectric conversion regions, and the number of photoelectric conversion regions included in a pixel may vary.

[0057] The first substrate 400 may include a photoelectric conversion region 410. The photoelectric conversion region 410 may have the same functions and roles as the photoelectric conversion elements (PD1, PD2, PD3, PD4, PD5, PD6, PD7, and PD8) illustrated in Fig. 2. A first photoelectric conversion element PD1 and a second photoelectric conversion element PD2 are illustrated in Fig. 4.

[0058] The photoelectric conversion region 410 may be a region doped with impurities of a second conductivity type in the first substrate 400. The impurities of the second conductivity type may have a conductivity type opposite to that of the impurities of the first conductivity type. The impurities of the second conductivity type may be n-type impurities such as phosphorus, arsenic, bismuth, and antimony. For example, each photoelectric conversion region 410 may include a first region adjacent to the first surface 400a and a second region adjacent to the second surface 400b. There may be an impurity concentration difference between the first and second regions of the photoelectric conversion region 410. Thus, the photoelectric conversion region 410 may have a potential gradient between the first surface 400a and the second surface 400b of the first substrate 400. However, as another example, the photoelectric conversion region 410 may not have a potential gradient between the first surface 400a and the second surface 400b of the first substrate 400.

[0059] The first substrate 400 and the photoelectric conversion region 410 can form a photodiode. That is, the photodiode is formed by a pn junction between the first substrate 400 of the first conductivity type and the photoelectric conversion region 410 of the second conductivity type. The photoelectric conversion region 410 constituting the photodiode can generate and accumulate photocharges in proportion to the intensity of incident light.

[0060] 4, a pixel separation pattern 450 may be disposed on the first substrate 400. The pixel separation pattern 450 may have a lattice structure on a plane. As will be described below with reference to FIG. 5, the pixel separation pattern 450 may be disposed between a plurality of photoelectric conversion elements (PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8) included in one pixel while defining each pixel on a plane.

[0061] Referring to FIG. 4, the pixel isolation pattern 450 may be located in a first trench TR1. The first trench TR1 may be recessed from a first surface 400a of the first substrate 400. The pixel isolation pattern 450 may extend from the first surface 400a to the second surface 400b of the first substrate 400. The pixel isolation pattern 450 may be a deep trench-isolation (DTI) film. The pixel isolation pattern 450 may penetrate the first substrate 400. The vertical height of the pixel isolation pattern 450 may be substantially the same as the vertical thickness of the first substrate 400. For example, the width of the pixel isolation pattern 450 may be gradually reduced from the first surface 400a to the second surface 400b of the first substrate 400. The width of pixel separating pattern 450 on first surface 400a may be a first width (W1), and the width of pixel separating pattern 450 on second surface 400b may be a second width (W2). In other words, the first width (W1) may be greater than the second width (W2).

[0062] The pixel isolation pattern 450 may include a first isolation pattern 451, a second isolation pattern 453, and a capping pattern 455. The first isolation pattern 451 may be located along a sidewall of the first trench (TR1). The first isolation pattern 451 may include, for example, a silicon-based insulating material (e.g., silicon nitride, silicon oxide, or silicon oxynitride) or a high dielectric material (e.g., hafnium oxide or aluminum oxide). As another example, the first isolation pattern 451 may include a plurality of layers, each of which may include a different material. The first isolation pattern 451 may have a lower refractive index than the first substrate 400. Thus, crosstalk between the pixels (PX) located on the first substrate 400 may be prevented or reduced.

[0063] The second isolated pattern 453 may be located within the first isolated pattern 451. For example, a sidewall of the second isolated pattern 453 is surrounded by the first isolated pattern 451. The first isolated pattern 451 may be located between the second isolated pattern 453 and the first substrate 400. The second isolated pattern 453 is separated from the first substrate 400 by the first isolated pattern 451. Thus, the second isolated pattern 453 may be electrically isolated from the first substrate 400 during operation of the image sensor. The second isolated pattern 453 may include a crystalline semiconductor material, for example, polycrystalline silicon. For example, the second isolated pattern 453 may further include a dopant, and the dopant may include a first conductive type impurity or a second conductive type impurity.

[0064] For example, the second isolated pattern 453 may include doped polycrystalline silicon. Or, the second isolated pattern 453 may include an undoped crystalline semiconductor material. For example, the second isolated pattern 453 may include undoped polycrystalline silicon. The term "undoped" means that no intentional doping process is performed. The dopant may include an n-type dopant and a p-type dopant.

[0065] The capping pattern 455 may be located on a lower surface of the second separation pattern 453. The capping pattern 455 is disposed adjacent to the first surface 400a of the first substrate 400. The lower surface of the capping pattern 455 may be coplanar with the first surface 400a of the first substrate 400. The upper surface of the capping pattern 455 may be substantially the same as the lower surface of the second separation pattern 453. The capping pattern 455 may include a non-conductive material. For example, the capping pattern 455 may include a silicon-based insulating material (e.g., silicon nitride, silicon oxide, or silicon oxynitride) or a high dielectric material (e.g., hafnium oxide or aluminum oxide). Thus, the pixel separation pattern 450 may prevent photocharges generated by incident light incident on a pixel (PX) from being incident on another adjacent pixel (PX) due to random drift. That is, the pixel separation pattern 450 may prevent crosstalk between the pixels (PX).

[0066] The device isolation pattern 403 may be located in the first substrate 400. For example, the device isolation pattern 403 may be located in a second trench (TR2). The second trench (TR2) may be recessed from a first surface 400a of the first substrate 400. The device isolation pattern 403 may be a shallow trench-isolation (STI) film. The device isolation pattern 403 may define an active pattern (ACT) (see FIG. 5). An upper surface of the device isolation pattern 403 may be located in the first substrate 400. A width of the device isolation pattern 403 gradually decreases from the first surface 400a to the second surface 400b of the first substrate 400. An upper surface of the device isolation pattern 403 is vertically separated from the photoelectric conversion region 410. The pixel isolation pattern 450 may overlap a portion of the device isolation pattern 403.

[0067] The image sensor may include an active pattern (ACT) defined by an isolation pattern 403. Referring to FIG 5, a plurality of active patterns (ACT1, ACT2, ACT3, ACT4) defined by an isolation pattern 403 are illustrated. Although FIG 5 illustrates a configuration in which a first active pattern (ACT1), a second active pattern (ACT2), a third active pattern (ACT3) and a fourth active pattern (ACT4) are included in one pixel (PX), this is merely an example and the present invention is not limited thereto. In other words, the number and arrangement of the active patterns arranged on a plane may vary.

[0068] Referring again to FIG. 4, the transfer transistor (TX) described in FIG. 2 may be located on the first surface 400a of the first substrate 400. The transfer transistor (TX) is electrically connected to the photoelectric conversion region 410. The transfer transistor (TX) may include a transfer gate (TG) and a floating diffusion region (FD) located on the active pattern (ACT). The transfer gate (TG) may include a first portion (TGa) located on the first surface 400a of the first substrate 400 and a second portion (TGb) extending from the first portion (TGa) into the first substrate 400. The maximum width of the first portion (TGa) in the second direction (D2) may be greater than the maximum width of the second portion (TGb) in the second direction (D2). The floating diffusion region (FD) may be adjacent to one side of the transfer gate (TG). The floating diffusion region (FD) may be located within the active pattern (ACT). The floating diffusion region (FD) may have a second conductivity type (eg, n-type) opposite to that of the first substrate 400.

[0069] A gate dielectric layer (GI) may be disposed between the transmission gate (TG) and the first substrate 400. A gate spacer (GS) may be disposed on a sidewall of the transmission gate (TG). The gate spacer (GS) may include silicon nitride, silicon carbonitride, or silicon oxynitride.

[0070] The first wiring region 20 is located on the first surface 400a of the first substrate 400 and may include multiple insulating layers (IL1, IL2, IL3, IL4), multiple wiring layers (CL1, CL2), a first floating diffusion region connecting node (FDCN_1) and multiple vias (VIA).

[0071] The insulating layer may include a first insulating layer (IL1), a second insulating layer (IL2), a third insulating layer (IL3) and a fourth insulating layer (IL4).

[0072] The first insulating layer (IL1) may cover the first surface 400a of the first substrate 400. The first insulating layer (IL1) may cover the gate electrode (TG). The second insulating layer (IL2) may be located on the first insulating layer (IL1). The third insulating layer (IL3) may be located on the second insulating layer (IL2). The fourth insulating layer (IL4) may be located on the third insulating layer (IL3).

[0073] The first to fourth insulating layers (IL1, IL2, IL3, IL4) may include a non-conductive material, for example, the first to fourth insulating layers (IL1, IL2, IL3, IL4) may include a silicon-based insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0074] The wiring layers (CL1, CL2) may include a first wiring layer (CL1) and a second wiring layer (CL2). The first wiring layer (CL1) may be located in a second insulating layer (IL2). The second wiring layer (CL2) may be located in a third insulating layer (IL3).

[0075] The wirings located in the first wiring layer (CL1) and the second wiring layer (CL2) are connected to the floating diffusion region (FD) through vias (VIA). The vias (VIA) may penetrate the insulating layers (IL1, IL2, IL3, IL4).

[0076] The wiring arrangement of the wiring layers (CL1, CL2) is arranged regardless of the arrangement of the photoelectric conversion regions 410, and is not limited to the illustrated arrangement and can be changed in various ways. Fig. 6 shows the planar arrangement of the first wiring layer (CL1), and Fig. 7 shows the planar arrangement of the second wiring layer (CL2). However, this is just an example, and the arrangement of each wiring layer (CL1, CL2) is not limited to this.

[0077] A first floating diffusion region connection node (FDCN_1) may be located in the fourth insulating layer (IL4). The first floating diffusion region connection node (FDCN_1) may include a main connection portion (FDCN_1A) and a shielding portion (FDCN_1B). The shielding portion (FDCN_1B) may be located at an edge of the main connection portion (FDCN_1A) and may have a smaller area than the main connection portion (FDCN_1A). The shielding portion (FDCN_1B) may prevent interference between floating diffusion region connection nodes of adjacent pixels (PX). The main connection part (FDCN_1A) of the first floating diffusion region connection node (FDCN_1) is connected to the wiring of the first wiring layer (CL1) and the second wiring layer (CL2), but the shielding part (FDCN_1B) of the first floating diffusion region connection node (FDCN_1) may not be connected to the wiring of the first wiring layer (CL1) and the wiring of the second wiring layer (CL2). In addition, the main connection part (FDCN_1A) of the first floating diffusion region connection node (FDCN_1) is located in an island shape separated for each pixel, but the shielding part (FDCN_1B) may be located connected to adjacent pixels. For example, the shielding part (FDCN_1B) may be located in a line shape extending in one direction on a plane. A separate voltage may be applied to the shielding part (FDCN_1B).

[0078] 4, one surface of the first floating diffusion region connection node (FDCN_1) is exposed and not covered by the fourth insulating layer (IL4), and can therefore contact a second floating diffusion region connection node (FDCN_2) located in the second chip 2000, as will be described below.

[0079] A plurality of vias (VIA) may be located in the first insulating layer (IL1), the second insulating layer (IL2), and the third insulating layer (IL3). The vias (VIA) may connect the floating diffusion region (FD), the first wiring layer (CL1), the second wiring layer (CL2), and the first floating diffusion region connection node (FDCN_1).

[0080] The first wiring layer (CL1), the second wiring layer (CL2), the first floating diffusion region connecting node (FDCN_1) and the via (VIA) may include a metal material. For example, the first wiring layer (CL1), the second wiring layer (CL2), the first floating diffusion region connecting node (FDCN_1) and the via (VIA) may include copper (Cu).

[0081] 5 to 7 show the planar arrangement of one pixel (PX) on the first substrate 400. For ease of explanation, Fig. 5 to Fig. 7 selectively show some of the components located on the first substrate 400. The planar shapes of Fig. 5 to Fig. 7 are merely examples, and the present invention is not limited thereto.

[0082] 5 illustrates a pixel isolation pattern 450, an element isolation pattern 403, a plurality of active patterns (ACT1, ACT2, ACT3, ACT4) and transmission gates (TG1, TG2, TG3, TG4, TG5, TG6, TG7, TG8). Each of the transmission gates (TG1, TG2, TG3, TG4, TG5, TG6, TG7, TG8) and adjacent active patterns (ACT1, ACT2, ACT3, ACT4) may include a floating diffusion region. The active patterns (ACT) may include a first active pattern (ACT1), a second active pattern (ACT2), a third active pattern (ACT3), and a fourth active pattern (ACT4).

[0083] In Fig. 5, contacts (CT) for connection with the first wiring layer (CL1) are also shown. Referring to Figs. 2 and 5 together, one pixel (PX) can include eight transmission gates (TG1, TG2, TG3, TG4, TG5, TG6, TG7, TG8) and a plurality of transmission transistors (TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8) that each transmission gate constitutes. However, this is merely an example and the present invention is not limited thereto.

[0084] FIG. 6 illustrates a plurality of active patterns (ACT1, ACT2, ACT3, ACT4), respective transmission gates (TG1, TG2, TG3, TG4, TG5, TG6, TG7, TG8), and a first wiring layer (CL1). The first wiring layer (CL1) may include a plurality of connection patterns (CP) connected to contacts (CT) and a first floating diffusion region connection pattern (FDCP_1C). Referring to FIG. 6, the floating diffusion regions adjacent to the respective transmission gates (TG1, TG2, TG3, TG4, TG5, TG6, TG7, TG8) are connected to the first floating diffusion region connection pattern (FDCP_1C). That is, the floating diffusion regions (FD) adjacent to the respective transmission gates (TG1, TG2, TG3, TG4, TG5, TG6, TG7, TG8) are connected together by the first floating diffusion region connection pattern (FDCP_1C).

[0085] FIG. 7 illustrates a plurality of active patterns (ACT1, ACT2, ACT3, ACT4), transmission gates (TG1, TG2, TG3, TG4, TG5, TG6, TG7, TG8), and a second wiring layer (CL2). The second wiring layer (CL2) may include a second floating diffusion region connection pattern (FDCP_2C), a plurality of transmission signal lines (TXL), and a ground line (VSS). Each of the transmission signal lines (TXL) may be connected to the transmission gates (TG1, TG2, TG3, TG4, TG5, TG6, TG7, TG8) to transmit a transmission signal. Referring to FIG. 2 as well, the ground line (VSS) may be connected to the photoelectric conversion elements (PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8) to transmit a ground voltage.

[0086] The second floating diffusion region connection pattern (FDCP_2C) of Fig. 7 may be connected to the first floating diffusion region connection pattern (FDCP_1C) of Fig. 6. As described in Fig. 4, the first floating diffusion region connection pattern (FDCP_1C) located in the first wiring layer (CL1) and the second floating diffusion region connection pattern (FDCP_2C) located in the second wiring layer (CL2) may be connected through a via (VIA).

[0087] Therefore, the floating diffusion regions adjacent to each transmission gate (TG1, TG2, TG3, TG4, TG5, TG6, TG7, TG8) can be connected to the second floating diffusion region connection pattern (FDCP_2C) through the first floating diffusion region connection pattern (FDCP_1C). Although not shown in FIG 7, referring to FIG 4, the second floating diffusion region connection pattern (FDCP_2C), which is the second wiring layer (CL2), can be connected to the first floating diffusion region connection node (FDCN_1) through a via (VIA).

[0088] 4 again, the first chip 1000 may include a light-transmitting layer 30. The light-transmitting layer 30 may include an insulating structure 329, a color filter 303, and a microlens unit 306. The light-transmitting layer 30 may collect and filter light incident from the outside and provide the light to the photoelectric conversion region 410.

[0089] The color filter 303 may be located on the second surface 400b of the first substrate 400. The color filter 303 may be disposed in each pixel (PX). In each pixel (PX), the color filter 303 may include a primary color filter. The color filter 303 may include a first color filter, a second color filter, and a third color filter having different colors. For example, the first color filter, the second color filter, and the third color filter may include green, red, and blue color filters, respectively. The first color filter, the second color filter, and the third color filter may be arranged in a Bayer pattern. As another example, the first color filter, the second color filter, and the third color filter may include colors such as cyan, magenta, or yellow.

[0090] An insulating structure 329 may be disposed between the second surface 400b of the first substrate 400 and the color filter 303. The insulating structure 329 may prevent reflection of light so that light incident on the second surface 400b of the first substrate 400 can smoothly reach the photoelectric conversion region 410. The insulating structure 329 may be called an anti-reflection structure.

[0091] The insulating structure 329 may include a first fixed charge film 321, a second fixed charge film 323, and a planarization film 325, which are sequentially stacked on the second surface 400b of the first substrate 400. The first fixed charge film 321, the second fixed charge film 323, and the planarization film 325 may each include different materials. The first fixed charge film 321 may include any one of aluminum oxide, tantalum oxide, titanium oxide, and hafnium oxide. The second fixed charge film 323 may include any other one of aluminum oxide, tantalum oxide, titanium oxide, and hafnium oxide. For example, the first fixed charge film 321 may include aluminum oxide, the second fixed charge film 323 may include hafnium oxide, and the planarization film 325 may include silicon oxide. Although not shown, in another embodiment, a silicon anti-reflection film (not shown) may be interposed between the second fixed charge film 323 and the planarization film 325. The anti-reflection film may include silicon nitride.

[0092] A microlens unit 306 may be located on the color filter 303. The microlens unit 306 may include a flat portion 305 in contact with the color filter 303 and a microlens 307 located on the flat portion 305. The flat portion 305 may include an organic material, for example. As another example, the flat portion 305 may include silicon oxide or silicon oxynitride. The microlens 307 may have a convex shape so as to condense light incident on the pixel (PX). Each microlens 307 may overlap the photoelectric conversion region 410 vertically. The lens may have various shapes. Although FIG. 4 illustrates one microlens 307 overlapping two photoelectric conversion regions 410 for convenience of explanation, one microlens 307 may be located in a shape overlapping eight photoelectric conversion regions 410. That is, one microlens 307 may be located on the plane of one pixel (PX) illustrated in FIGS. 5 to 7. However, this is just one example, and the number of microlenses 307 located in one pixel (PX) may vary.

[0093] The light transmission layer 30 may further include a low refraction pattern 311 and a protective film 316. The low refraction pattern 311 may be located between adjacent color filters 303 to separate them from each other. The low refraction pattern 311 may be located on an insulating structure 329. For example, the low refraction pattern 311 may have a lattice structure. The low refraction pattern 311 may include a material having a lower refractive index than the color filter 303. The low refraction pattern 311 may include an organic material. For example, the low refraction pattern 311 may be a polymer layer containing silica nanoparticles. Since the low refraction pattern 311 has a low refractive index, it may increase the amount of light incident on the photoelectric conversion region 410 and reduce crosstalk between pixels (PX). That is, the light receiving efficiency is increased in each photoelectric conversion region 410, and the SNR (Signal Noise Ratio) characteristic is improved.

[0094] The protective layer 316 may cover the surface of the low refraction pattern 311 with a substantially uniform thickness. The protective layer 316 may include, for example, at least one single layer or multiple layers of an aluminum oxide layer and a silicon oxycarbide layer. The protective layer 316 may protect the color filter 303 and perform a moisture absorbing function.

[0095] The following describes the second chip 2000. The second chip 2000 may include a second substrate 500, a second wiring region 40, and a third wiring region 50.

[0096] The second substrate 500 may include a first surface 500a and a second surface 500b facing each other. The second wiring region 40 may be located on the first surface 500a of the second substrate 500, and the third wiring region 50 may be located on the second surface 500b of the second substrate 500.

[0097] The second substrate 500 may be a semiconductor substrate or a silicon on insulator (SOI) substrate. The semiconductor substrate may include, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The second substrate 500 may include impurities of a first conductivity type. For example, the impurities of the first conductivity type may include p-type impurities such as aluminum (Al), boron (B), indium (In), and / or gallium (Ga).

[0098] The first surface 500 a of the second substrate 500 may be positioned opposite the first surface 400 a of the first substrate 400 .

[0099] 4 and 8, the second substrate 500 may include a fifth active pattern (ACT) and a sixth active pattern (ACT6) defined by an isolation pattern 503. The gate electrode (RG) of the reset transistor (RX), the gate electrode (DCG) of the dual conversion transistor (DCX), the gate electrode (SF) of the amplification transistor (SX), and the gate electrode (AG) of the selection transistor (AX) described in FIG. 2 may be located on a first surface 500a of the second substrate 500. The cross section of FIG. 4 is a virtual cross section for convenience of explanation, and the present invention is not limited thereto. That is, the cross section of FIG. 4 may not match the planar arrangements of FIGS. 5 to 7 and the planar arrangements of FIGS. 8 to 11. The cross section of FIG. 4 is a cross section for convenience of explanation of the stacked structure and the configuration of the dip node of the image sensor, and the planar arrangements of FIGS. 5 to 11 are also examples, and the planar arrangements may be changed.

[0100] A gate dielectric film (GI) is interposed between each of the selection gate (AG), amplification gate (SF), dual conversion gate (DCG), and reset gate (RG) and the second substrate 500. A gate spacer (GS) may be located on a sidewall of each of the gate electrodes (AG, SF, DCG, RG). The gate spacer (GS) may include silicon nitride, silicon carbonitride, or silicon oxynitride.

[0101] Although not shown in FIG. 4, a second floating diffusion region may be located in a fifth active pattern (ACT5) adjacent to the gate electrode (RG) of the reset transistor (RX), the gate electrode (DCG) of the dual conversion transistor (DCX), the gate electrode (SF) of the amplification transistor (SX), and the gate electrode (AG) of the selection transistor (AX).

[0102] A fifth insulating layer (IL5), a sixth insulating layer (IL6), a seventh insulating layer (IL7), a third wiring layer (CL3), a plurality of vias (VIA) and a second floating diffusion region connection node (FDCN_2) may be located on the first surface 500a of the second substrate 500.

[0103] The fifth insulating layer (IL5), the sixth insulating layer (IL6) and the seventh insulating layer (IL7) may include a non-conductive material. For example, the fifth insulating layer (IL5), the sixth insulating layer (IL6) and the seventh insulating layer (IL7) may include a silicon-based insulating material such as silicon oxide, silicon nitride or silicon oxynitride.

[0104] The third wiring layer (CL3), the via (VIA) and the second floating diffusion region connection node (FDCN_2) may include a metal material. For example, the third wiring layer (CL3), the via (VIA) and the second floating diffusion region connection node (FDCN_2) may include copper (Cu).

[0105] The third wiring layer (CL3) may be located in the sixth insulating layer (IL6). The wiring of the third wiring layer (CL3) and at least one of the gate electrode (RG) of the reset transistor (RX), the gate electrode (DCG) of the dual conversion transistor (DCX), the gate electrode (SF) of the amplification transistor (SX), and the gate electrode (AG) of the selection transistor (AX) are connected to the via (VIA). Also, the third wiring layer (CL3) and at least one of the electrodes of the reset transistor (RX), the dual conversion transistor (DCX), the amplification transistor (SX), and the selection transistor (AX) are connected to the via.

[0106] The second floating diffusion region connecting node (FDCN_2) may be located in the seventh insulating layer (IL7). The second floating diffusion region connecting node (FDCN_2) may include a main connecting portion (FDCN_2A) and a shielding portion (FDCN_2B). The shielding portion (FDCN_2B) may be located at an edge of the main connecting portion (FDCN_2A) and may be located in an area smaller than that of the main connecting portion (FDCN_2A). The shielding portion (FDCN_2B) may prevent interference between the floating diffusion region connecting nodes of adjacent pixels. The main connecting portion (FDCN_2A) of the second floating diffusion region connecting node (FDCN_2) is connected to a wiring of the third wiring layer (CL3), but the shielding portion (FDCN_2B) of the second floating diffusion region connecting node (FDCN_2) may not be connected to a wiring of the third wiring layer (CL3). The main connection portion (FDCN_2A) of the second floating diffusion region connection node (FDCN_2) is located in an island shape separated for each pixel, while the shielding portion (FDCN_2B) may be located connected to adjacent pixels. For example, the shielding portion (FDCN_2B) may be located in a line shape extending in one direction on a plane. A separate voltage may be applied to the shielding portion (FDCN_2B).

[0107] 4, one surface of the second floating diffusion region connection node (FDCN_2) is exposed and not covered by the seventh insulating layer (IL7), so that the first floating diffusion region connection node (FDCN_1) located in the first chip 1000 and the second floating diffusion region connection node (FDCN_2) located in the second chip 2000 can contact each other.

[0108] 4, the second chip 2000 includes a dipped node (DN) penetrating the second substrate 500. The dipped node (DN) may include a metal, for example, copper (Cu), but this material is merely an example and may include other metal materials.

[0109] The dip node (DN) is located through the second substrate 500, and one end of the dip node (DN) may be located on the first surface 500a, and the other end may be located on the second surface 500b. In this specification, the expression "located on a surface" is not limited to being located in contact with the surface, but includes being located in a non-contact form or in a protruding form on the surface. That is, as shown in FIG. 4, one end of the dip node (DN) may be located protruding from the first surface 500a, and the other end may be located protruding from the second surface 500b.

[0110] 4, one end of the dip node (DN) may contact the wiring of the third wiring layer (CL3), and the other end of the dip node (DN) may contact the fourth wiring layer (CL4) located on the second surface 500b of the second substrate 500.

[0111] On the second surface 500b of the second substrate 500, an eighth insulating layer (IL8), a ninth insulating layer (IL9), a tenth insulating layer (IL10), a fourth wiring layer (CL4), a fifth wiring layer (CL5) and vias (VIA) may be located.

[0112] The eighth insulating layer (IL8), the ninth insulating layer (IL9), and the tenth insulating layer (IL10) may include a non-conductive material. For example, the eighth insulating layer (IL8), the ninth insulating layer (IL9), and the tenth insulating layer (IL10) may include a silicon-based insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0113] The fourth wiring layer (CL4), the fifth wiring layer (CL5) and the vias (VIA) may include a metal material. For example, the fourth wiring layer (CL4), the fifth wiring layer (CL5) and the vias (VIA) may include copper (Cu). However, such a material is merely an example, and the present invention is not limited thereto.

[0114] The fourth wiring layer (CL4) may be located in the ninth insulating layer (IL9). The fifth wiring layer (CL5) may be located in the tenth insulating layer (IL10). The fourth wiring layer (CL4) and the fifth wiring layer (CL5) may be connected through a via (VIA).

[0115] The dip node (DN) may be located in the fifth insulating layer (IL5), the second substrate 500, and the eighth insulating layer (IL8). The dip node (DN) may be located through the second substrate 500, and may connect one or more of the reset transistor (RX), the dual conversion transistor (DCX), the amplification transistor (SX), and the selection transistor (AX) located on the first surface 500a of the second substrate 500 to the fourth wiring layer (CL4) and the fifth wiring layer (CL5) located on the second surface 500b of the second substrate 500.

[0116] That is, the wirings located in the fourth wiring layer (CL4) and the fifth wiring layer (CL5) can be connected to the gate electrode (RG) of the reset transistor (RX), the gate electrode (DCG) of the dual conversion transistor (DCX), and the gate electrode (AG) of the selection transistor (AX) to transmit a gate signal. Also, the wirings can be connected to the source electrodes of the reset transistor (RX) and the amplification transistor (SX) to apply a power supply voltage (VDD). Also, the output wiring (Vout) located in the fourth wiring layer (CL4) or the fifth wiring layer (CL5) can be connected to the drain electrode of the selection transistor (AX). Referring to FIG. 2, one or more of the wirings shown in bold in FIG. 2 can be located on the second surface 500b of the second substrate 500.

[0117] As described above, in the image sensor according to this embodiment, the reset transistor (RX), the dual conversion transistor (DCX), the amplifying transistor (SX) and the selection transistor (AX) are located on a first surface 500a of the second substrate 500, and one or more of the wirings connected to the reset transistor (RX), the dual conversion transistor (DCX), the amplifying transistor (SX) and the selection transistor (AX) may be located on a second surface 500b of the second substrate 500. The reset transistor (RX), the dual conversion transistor (DCX), the amplifying transistor (SX) and the selection transistor (AX) and the wirings are connected via a dip node (DN) penetrating the second substrate 500.

[0118] Since the transistors and the wiring are located on different surfaces, the length of the floating diffusion region between the first chip 1000 and the second chip 2000 can be shortened. In other words, in FIG. 4, when the fourth wiring layer (CL4) and the fifth wiring layer (CL5) are located on the first surface 500a of the second substrate 500, the distance between the first surface 400a of the first substrate 400 and the first surface 500a of the second substrate 500 is increased by the thickness of the fourth wiring layer (CL4), the fifth wiring layer (CL5) and the insulating layer for insulating them. However, in the image sensor according to the present embodiment, since the fourth wiring layer (CL4) and the fifth wiring layer (CL5) are located on the second surface 500b of the second substrate 500, the distance between the first surface 400a of the first substrate 400 and the first surface 500a of the second substrate 500 can be reduced. Therefore, the length of the connection between the floating diffusion regions (FD) of the first chip 1000 and the second chip 2000 is shortened, and the conversion gain (CG) can be improved.

[0119] In addition, since the floating diffusion region (FD) and the floating diffusion region connection nodes (FDCN_1, FDCN_2) and wiring connected thereto are located on different surfaces with the second substrate 500 in between, coupling between the floating diffusion region (FD) and wiring can be minimized. Referring to FIGS. 2 and 4 at the same time, for example, a wiring of the fourth wiring layer (CL4) connected to the gate electrode (RG) of the reset transistor (RX) and a wiring of the fourth wiring layer (CL4) connected to the gate electrode (DCG) of the dual conversion transistor (DCX) are located between the second floating diffusion region connection node (FDCN_2) and the second substrate 500. Therefore, coupling between the floating diffusion region connection node (FDCN_2) and wiring connected to each transistor can be minimized.

[0120] 2 and 4, the output wiring (Vout) located in the fourth wiring layer (CL4) is located between the second floating diffusion region connection node (FDCN_2) and the second substrate 500. Therefore, it is possible to minimize coupling between the floating diffusion region connection node (FDCN_2) and the output wiring (Vout).

[0121] 4, the second chip 2000 may be connected to the third chip 3000. The third chip 3000 may include a third substrate 700 and a fourth wiring region 60. A transistor (not shown) constituting a logic circuit may be located on a first surface 700a of the third substrate 700, and a plurality of wirings (LCL) may be located in the fourth wiring region 60. The fourth wiring region 60 includes an insulating film (LIL), and the plurality of wirings (LCL) are connected to wirings of the second chip 2000 through vias (not shown).

[0122] The third substrate 700 may be a semiconductor substrate or a silicon-on-insulator (SOI) substrate. The semiconductor substrate may include, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The third substrate 700 may include impurities of a first conductivity type. For example, the impurities of the first conductivity type may include p-type impurities such as aluminum (Al), boron (B), indium (In), and / or gallium (Ga).

[0123] 8 to 11 show the planar arrangement of the first surface 500a and the second surface 500b of the second substrate 500 in one pixel (PX). For ease of explanation, Figs. 8 to 11 selectively show some of the components located on the second substrate 500. The planar shapes in Figs. 8 to 11 are merely examples, and the present invention is not limited thereto.

[0124] 8 illustrates the first surface 500a of the second substrate 500, showing a fifth active pattern (ACT5), a sixth active pattern (ACT6) and a gate electrode. Referring to FIG. 8, the fifth active pattern (ACT5) is located, and the gate electrode (RG) of the reset transistor (RX), the gate electrode (DCG) of the dual conversion transistor (DCX), the gate electrode (SF) of the amplification transistor (SX) and the gate electrode (AG) of the selection transistor (AX) may be located on the fifth active pattern (ACT5). FIG. 9 also illustrates a contact (CT) for connection to the third wiring layer (CL3).

[0125] 9 illustrates the first surface 500a of the second substrate 500, and in addition to FIG. 9, a third wiring layer (CL3) and a dip node (DN) are illustrated. The third wiring layer (CL3) may include a plurality of connection patterns (CP). Each connection pattern (CP) may be connected to each gate electrode or the fifth active pattern (ACT5) and the sixth active pattern (ACT6) through a contact (CT). The connection pattern (CP) may include a third floating diffusion region connection pattern (FDCP_3C). The third floating diffusion region connection pattern (FDCP_3C) may be connected to the second floating diffusion region connection node (FDCN_2) illustrated in FIG. 4.

[0126] In FIG. 9, the dip nodes (DN) are illustrated as being arranged side by side, but this is merely an example, and the planar arrangement of the second substrate 500 is not limited thereto.

[0127] FIG. 10 illustrates the second surface 500b of the second substrate 500, and illustrates the fourth wiring layer (CL4) and the dip node (DN). The fourth wiring layer (CL4) is connected to the third wiring layer (CL3) located on the first surface 500a of the second substrate 500 via the dip node (DN). The fourth wiring layer (CL4) may include a plurality of signal wirings (SGL). In FIG. 10, the signals transmitted by each signal wiring (SGL) are written on the signal wiring (SGL), but this is an example and the present invention is not limited thereto. In FIG. 10, the signal wiring (SGL) with FD2 written thereon may be a wiring connected to the second substrate 500 when the second substrate 500 includes a second floating diffusion region.

[0128] FIG. 11 illustrates the second surface 500b of the second substrate 500, and shows the fifth wiring layer (CL5). The wiring located in the fifth wiring layer (CL5) can be connected to the wiring located in the fourth wiring layer (CL4) through the via (VIA) shown in FIG. 4. The fifth wiring layer (CL5) can include a plurality of signal wirings (SGL). The signal wirings (SGL) of the fifth wiring layer (CL5) can be positioned in a direction intersecting with the signal wirings (SGL) of the fourth wiring layer (CL4). However, this is an example, and the present invention is not limited thereto. In FIG. 11, the signals transmitted by each signal wiring (SGL) are written on the signal wirings (SGL), but this is an example, and the present invention is not limited thereto.

[0129] The planar arrangement of the first surface 500a and the second surface 500b of the second substrate 500 shown in FIGS. 8 to 11 is merely an example, and the present invention is not limited thereto.

[0130] A method for manufacturing an image sensor according to this embodiment will be described below with reference to Figures 12 to 18. The following mainly describes a process for forming a dip node (DN) and a process for forming a fourth wiring layer (CL4) and a fifth wiring layer (CL5) on the second surface 500b of the second substrate 500, and other components can be formed by a typical method for manufacturing an image sensor.

[0131] 12 to 18 show the manufacturing process of the image sensor according to this embodiment.

[0132] First, referring to Fig. 12, a first substrate 400 is prepared. The description of the first substrate 400 is the same as that of Fig. 4, and detailed descriptions of the same components will be omitted. That is, the first substrate 400 may include a photoelectric conversion layer 10 and a first wiring region 20. The photoelectric conversion layer 10 may include a photoelectric conversion region 410 and a plurality of transfer transistors (TX). The description of the photoelectric conversion layer 10 and the first wiring region 20 is the same as that described above, and detailed descriptions of the same components will be omitted.

[0133] Next, referring to FIG. 13, a second substrate 500 is prepared. The second substrate 500 may have a first surface 500a on which a second wiring region 40 is formed. The first surface 500a and the second wiring region 40 of the second substrate 500 are described in the same manner as in FIG. 4, and detailed description of the same components will be omitted. That is, referring to FIGS. 4, 8, and 13 at the same time, the first surface 500a of the second substrate 500 may include a gate electrode (RG) of the reset transistor (RX), a gate electrode (DCG) of the dual conversion transistor (DCX), a gate electrode (SF) of the amplification transistor (SX), and a gate electrode (AG) of the selection transistor (AX) located on a fifth active pattern (ACT5).

[0134] A fifth insulating layer (IL5), a sixth insulating layer (IL6), a seventh insulating layer (IL7), a third wiring layer (CL3), a plurality of vias (VIA) and a second floating diffusion region connection node (FDCN_2) may be located on the first surface 500a of the second substrate 500.

[0135] The third wiring layer (CL3) and at least one of the gate electrode (RG) of the reset transistor (RX), the gate electrode (DCG) of the dual conversion transistor (DCX), the gate electrode (SF) of the amplifying transistor (SX), and the gate electrode (Ag) of the selection transistor (AX) are connected to the via (VIA). Also, the second floating diffusion region connection node (FDCN_2) may be located in the seventh insulating layer (IL7).

[0136] Next, referring to Fig. 14, the first substrate 400 of Fig. 12 and the second substrate 500 of Fig. 13 are bonded together. At this time, the first surface 400a of the first substrate 400 and the first surface 500a of the second substrate 500 may be bonded together to face each other. During the bonding process, the first floating diffusion region connection node (FDCN_1) of the first substrate 400 and the second floating diffusion region connection node (FDCN_2) of the second substrate 500 may come into contact with each other. Therefore, the floating diffusion region (FD) located in the first substrate 400 is connected to the gate (SF) of the amplifying transistor (SX) located in the second substrate.

[0137] Next, referring to FIG. 15, a dip node (DN) is formed on the second substrate 500. At this time, the dip node may be formed in a direction from the second surface 500b of the second substrate 500 toward the first surface 500a. The dip node may be formed by forming an eighth insulating layer (IL8) on the second surface 500b of the second substrate 500, punching through the eighth insulating layer (IL8), the second substrate 500, and the fifth insulating layer (IL5), and then filling with a metal material. Depending on the embodiment, the eighth insulating layer (IL8) forming process may be omitted. The dip node (DN) may be formed to contact the third wiring layer (CL3) located on the first surface 500a of the second substrate 500. That is, in the etching process for forming the dip node (DN), the third wiring layer (CL3) may act as an etching stopper. After a hole is drilled through the eighth insulating layer (IL8), the second substrate 500 and the fifth insulating layer (IL5) so as to reach the third wiring layer (CL3), the hole can be filled with metal to form a dip node (DN).

[0138] Next, referring to FIG. 16, a ninth insulating layer (IL9), a tenth insulating layer (IL10), a fourth wiring layer (CL4), a fifth wiring layer (CL5) and vias (VIA) can be formed on the second surface 500b of the second substrate 500.

[0139] 17, the third chip 3000 including the third substrate 700 and the fourth wiring region 60 can be bonded to the second surface 500b of the second substrate 500. Next, referring to FIG. 18, the light-transmitting layer 30 can be formed on the second surface 400b of the first substrate 400. The description of the light-transmitting layer 30 is omitted since it is the same as that described above. The manufacturing method described above with reference to FIGS. 12 to 18 is an example, and the specific manufacturing order may be different except for the process in which the dip node (DN) is formed from the second surface 500b to the first surface 500a of the second substrate 500.

[0140] In the above embodiment, the third wiring layer (CL3) is located on the first surface 500a of the second substrate 500, and the fourth wiring layer (CL4) and the fifth wiring layer (CL5) are located on the second surface 500b, but the present invention is not limited thereto. In another embodiment, the third wiring layer (CL3) and the fourth wiring layer (CL4) can be located on the first surface 500a of the second substrate 500, and the fifth wiring layer (CL5) can be located on the second surface 500b.

[0141] FIG. 19 illustrates an image sensor according to another embodiment. Referring to FIG. 19, the image sensor according to this embodiment is similar to the embodiment of FIG. 4, except that the third wiring layer (CL3) and the fourth wiring layer (CL4) are located on the first surface 500a, and the fifth wiring layer (CL5) is located on the second surface 500b. A detailed description of the same components will be omitted. In the embodiment of FIG. 19, the fourth wiring layer (CL4) and the ninth insulating layer (IL9) may be located between the third wiring layer (CL3) and the first surface 500a of the second substrate 500. The wiring of the fourth wiring layer (CL4) may be connected to the third wiring layer (CL3) through a via (VIA). The dip node (DN) may connect the third wiring layer (CL3) and the fifth wiring layer (CL5). 19, the fifth wiring layer (CL5) is located on the second surface 500b, so the distance between the first surface 500a of the second substrate 500 and the first surface 400a of the first substrate 400 is shortened. Therefore, the conversion gain (CG) can be improved. In addition, the floating diffusion region (FD) and the fifth wiring layer (CL5) are located with the second substrate 500 therebetween, so coupling between the floating diffusion region (FD) and the wiring located in the fifth wiring layer (CL5) can be minimized.

[0142] In addition, some of the wirings connecting to the transistors located on the second surface 500b of the second substrate 500, i.e., the reset transistor (RX), the dual conversion transistor (DCX), the amplification transistor (SX) and the selection transistor (AX), may be located on the first surface 500a and some may be located on the second surface 500b.

[0143] FIG 20 illustrates the same circuit diagram as FIG 2 for an image sensor according to another embodiment. In FIG 20, the wiring located on the second surface 500b of the second substrate 500 is illustrated with a thick line. As illustrated in FIG 20, among the wirings connected to the transistors located on the second substrate 500, the output wiring (Vout) may be located on the second surface 500b, and the remaining wirings may be located on the first surface 500a. However, FIG 2 is only an example, and an embodiment in which one or more of the wirings illustrated with a thick line in the circuit diagram of FIG 2 are located on the second surface 500b of the second substrate 500, and the remaining wirings are located on the first surface 500a, is also included in the present invention.

[0144] Fig. 21 illustrates the same cross section as Fig. 4 for another embodiment. Referring to Fig. 21, in the image sensor according to this embodiment, a third wiring layer (CL3) and a 3-1 wiring layer (CL3-1) may be located on a first surface 500a, and a fourth wiring layer (CL4) and a fifth wiring layer (CL5) may be located on a second surface 500b. The 3-1 wiring layer (CL3-1) may be located within a 6-1 insulating layer (IL6-1).

[0145] In this embodiment, some of the wirings connected to the reset transistor (RX), dual conversion transistor (DCX), amplification transistor (SX) and selection transistor (AX) are located in the 3-1 wiring layer (CL3-1) located on the first surface 500a, and some of the wirings may be located in the 4th wiring layer (CL4) located on the second surface 500b. With reference to Figs. 20 and 21 at the same time, the wiring located in the 4th wiring layer (CL4) may be the output wiring (Vout) shown in bold in Fig. 20. This is a structure to solve the biggest coupling problem between the output wiring (Vout) and the floating diffusion region (FD).

[0146] However, this is merely an example, and the present invention is not limited thereto. The present invention includes any embodiment in which one or more of the wirings illustrated by the thick lines in FIG. 2 are located on the second surface 500b of the second substrate 500.

[0147] As described above, the image sensor and the manufacturing method thereof according to the present embodiment include a first substrate including a photoelectric conversion region and a second substrate including a transistor connected thereto, the transistor and the wiring are located with the second substrate in between, and the transistor and the wiring are connected to a dip node penetrating the second substrate. Therefore, the length of the floating diffusion region connected between the first substrate and the second substrate can be shortened to increase the conversion gain, and the floating diffusion region and the wiring are located with the second substrate in between, so that coupling can be reduced.

[0148] Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the present invention defined in the following claims also belong to the scope of the present invention.

Claims

1. a first substrate including a first surface and a second surface opposed to each other and including a photoelectric conversion region; a transfer transistor located on a first surface of the first substrate; a second substrate including a first surface and a second surface opposed to each other; a plurality of transistors disposed on a first surface of the second substrate and coupled to the transfer transistor; a plurality of traces located on a second surface of the second substrate; a dipped node through the second substrate; a first surface of the first substrate and a first surface of the second substrate face each other; an image sensor, wherein at least one of a plurality of transistors located on a first surface of the second substrate and a plurality of wirings located on a second surface of the second substrate are connected to each other via the dip node;

2. a floating diffusion region located on the first substrate and connecting the transfer transistor and the plurality of transistors; The plurality of transistors located on the second substrate include a reset transistor for initializing the floating diffusion region; an amplifying transistor having a gate coupled to the floating diffusion region; The image sensor of claim 1 , further comprising a selection transistor coupled to one end of the amplification transistor.

3. the plurality of wirings includes an output wiring connected to one end of the selection transistor, The image sensor of claim 2 , wherein the output wiring and the selection transistor are connected through the dip node.

4. the plurality of wirings includes a power supply voltage transmission wiring connected to one end of the reset transistor, The image sensor of claim 2 , wherein the power supply voltage transmission line and the reset transistor are connected to each other through the dip node.

5. the plurality of wirings includes a power supply voltage transmission wiring connected to one end of the amplification transistor, The image sensor of claim 2 , wherein the power supply voltage transmission line and the amplifying transistor are connected to each other through the dip node.

6. the plurality of wirings includes a wiring connected to a gate of the reset transistor, The image sensor of claim 2 , wherein the gate of the reset transistor and the wiring are connected through the dip node.

7. the plurality of wirings include a wiring connected to a gate of the selection transistor, The image sensor of claim 2 , wherein the gate of the selection transistor and the wiring are connected through the dip node.

8. a dual conversion transistor connecting the reset transistor and the floating diffusion region, the plurality of wirings include a wiring connected to a gate of the dual conversion transistor, The image sensor of claim 2 , wherein the dual conversion transistor and the wiring are connected through the dip node.

9. One end of the dip node is located protruding from the first surface of the second substrate, The image sensor of claim 1 , wherein the other end of the dip node is positioned to protrude from the second surface of the second substrate.

10. a first floating diffusion region connection node located on the first substrate; the image sensor includes a plurality of pixels; The pixel includes eight photoelectric conversion regions and eight transfer transistors, 2. The image sensor of claim 1, wherein the eight transfer transistors are connected to the same first floating diffusion region connection node.

Images