Image pickup device

Abstract

To provide an image pickup device capable of preventing reduction of a change gain when reading an electric charge generated in a photo diode.SOLUTION: An image pickup device includes: a first photoelectric conversion part PD-1; a second photoelectric conversion part PD-2 that is arranged to the adjacent of the first photoelectric conversion part PD-1 in a first direction; a third photoelectric conversion part PD-5; a fourth photoelectric conversion part PD-6 that is arranged to the adjacent of the third photoelectric conversion part PD-5 in the first direction; a first expansion part FD-1 in which the first photoelectric conversion part PD-1 and an electric charge converted by the third photoelectric conversion part PD-5 are transferred; a second expansion part FD-2 in which the second photoelectric conversion part PD-2 and the electric charge converted by the fourth photoelectric conversion part PD-6 are transferred. The first expansion part FD-1 is arranged to between the first photoelectric conversion part PD-1 and the third photoelectric conversion part PD-5 in a second direction, and the second expansion part FD-2 is arranged to between the second photoelectric conversion part PD-2 and the fourth photoelectric conversion part PD-6 in the second direction.SELECTED DRAWING: Figure 15

Description

[Technical field]

[0001] The present invention relates to an imaging device. [Background technology]

[0002] There is known an imaging element that can read out first and second signals from a pixel having first and second photoelectric conversion units individually, or can add and read out the first and second signals from the first and second photoelectric conversion units (see Patent Document 1). In the conventional technology, in the case of individual readout, the charges of the first and second photoelectric conversion units are transferred individually to the first and second FDs. In the case of added readout, the charges of the first and second photoelectric conversion units are transferred to the first and second FDs that are electrically connected to each other. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2013-90160 Summary of the Invention

[0004] According to a first aspect of the present invention, an imaging element includes a first photoelectric conversion unit that converts light transmitted through a first microlens into an electric charge, a second photoelectric conversion unit that converts light transmitted through the first microlens into an electric charge and is disposed adjacent to the first photoelectric conversion unit in a first direction, a third photoelectric conversion unit that converts light transmitted through the second microlens into an electric charge and is disposed adjacent to the first microlens in a second direction intersecting the first direction, a fourth photoelectric conversion unit that converts light transmitted through the second microlens into an electric charge and is disposed adjacent to the third photoelectric conversion unit in the first direction, and a first diffusion unit having one diffusion region to which the electric charge converted in the first photoelectric conversion unit and the electric charge converted in the third photoelectric conversion unit are transferred. the first diffusion section is disposed between the first photoelectric conversion section and the third photoelectric conversion section in the second direction, and the second diffusion section is disposed between the second photoelectric conversion section and the fourth photoelectric conversion section in the second direction, the first diffusion section having a first diffusion region to which charges converted in the second photoelectric conversion section and charges converted in the fourth photoelectric conversion section are transferred, a first transistor having a gate electrically connected to the first diffusion section and outputting a first signal, a second transistor having a gate electrically connected to the second diffusion section and outputting a second signal, a first signal line for reading out the first signal output from the first transistor, and a second signal line for reading out the second signal output from the second transistor, wherein the first diffusion section is disposed between the first photoelectric conversion section and the third photoelectric conversion section in the second direction, and the second diffusion section is disposed between the second photoelectric conversion section and the fourth photoelectric conversion section in the second direction. [Brief description of the drawings]

[0005] [Figure 1] 1 is a block diagram illustrating a camera according to a first embodiment. [Diagram 2] FIG. 2 is a diagram illustrating a schematic configuration of an imaging element. [Diagram 3] FIG. 2 is a circuit diagram illustrating a pixel arrangement of an imaging element. [Figure 4] 4 is a circuit diagram illustrating pixels arranged in M ​​columns in FIG. 3. [Diagram 5] FIG. 5 is a diagram for explaining the layout of the pixel in FIG. [Figure 6] 3A and 3B are diagrams illustrating various control signals supplied to an imaging element. [Figure 7] FIG. 2 is a diagram illustrating an example of a-series and b-series signals. [Figure 8] 10 is a circuit diagram illustrating pixels arranged in M ​​columns in a first modification of the first embodiment. FIG. [Figure 9] 3A and 3B are diagrams illustrating various control signals supplied to an imaging element. [Figure 10] 13 is a circuit diagram illustrating pixels arranged in M ​​columns in a second modification of the first embodiment. FIG. [Figure 11] FIG. 11 is a diagram for explaining the layout of the pixel in FIG. [Figure 12] 3A and 3B are diagrams illustrating various control signals supplied to an imaging element. [Figure 13] FIG. 11 is a circuit diagram illustrating pixels arranged in M ​​columns in the second embodiment. [Figure 14] FIG. 14 is a diagram for explaining the layout of the pixel in FIG. [Figure 15] The figure focuses on the pixel in the (N+1)th row, pixel 20G in the (N+2)th row, and pixel 20R in the (N+3)th row among the pixels arranged in M ​​columns in a second modification of the second embodiment. [Figure 16] 13A to 13C are diagrams illustrating various control signals supplied to an image sensor according to a second modification of the second embodiment. [Figure 17] Fig. 17(a) is a diagram illustrating a pixel circuit of an image sensor according to a third embodiment, and Fig. 17(b) is an enlarged view of a region U of a photoelectric conversion unit in Fig. 17(a). [Figure 18] 13A to 13C are diagrams illustrating various control signals supplied to an image sensor according to a third embodiment. [Figure 19] 13A to 13C are diagrams illustrating various control signals supplied to an image sensor according to a third embodiment at the time of readout for focus adjustment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] Hereinafter, an embodiment of the invention will be described with reference to the drawings. (First embodiment) FIG. 1 is a block diagram illustrating a digital camera 1 (hereinafter referred to as camera 1) equipped with a focus detection device using a solid-state image sensor 3 (hereinafter referred to as image sensor 3) according to the first embodiment. In the first embodiment, the camera 1 is described as an example of a lens-interchangeable camera such as a single-lens reflex or mirrorless type, but it does not have to be a lens-interchangeable camera. For example, it may be configured as an imaging device such as a camera with an integrated lens, or a camera mounted on a mobile terminal such as a smartphone. In addition, it may be configured as an imaging device such as a video camera that captures moving images, a mobile camera, etc., not limited to still images.

[0007] <Camera configuration> A photographing lens 2 is attached to the camera 1 as an imaging optical system. The photographing lens 2 has a focusing lens and an aperture. The focusing lens and aperture of the photographing lens 2 are controlled by a lens control unit 2a that receives instructions from a microprocessor 9. The photographing lens 2 forms an optical image (subject image) on the imaging surface of an image sensor 3. The photographing lens 2 is also called an imaging optical system.

[0008] The imaging element 3 has a plurality of pixels. As described later, each of the plurality of pixels has two photoelectric conversion units that perform photoelectric conversion on incident light to generate electric charges. The plurality of pixels each perform photoelectric conversion on light transmitted through the photographing lens 2. The plurality of pixels each output a signal based on the electric charges generated by photoelectric conversion. The imaging element 3 is controlled by an imaging control unit 4 that receives instructions from a microprocessor 9. Signals output from the plurality of pixels of the imaging element 3 are processed via a signal processing unit 5 and an A / D conversion unit 6, and then temporarily stored in a memory 7. The lens control unit 2a, the imaging control unit 4, the memory 7, the microprocessor 9, a focus calculation unit (focus detection processing unit) 10, a recording unit 11, an image compression unit 12, an image processing unit 13, and the like are connected to the bus 8. The imaging element 3 may be configured to include some or all of the signal processing unit 5, the A / D conversion unit 6, and the memory 7. The imaging element 3 may be configured to stack at least one of the signal processing unit 5, the A / D conversion unit 6, and the memory 7, and a plurality of pixels.

[0009] An operation signal is input from an operation unit 9a such as a release button to the microprocessor 9. The microprocessor 9 sends instructions to each block based on the operation signal from the operation unit 9a, and controls the camera 1.

[0010] The focus calculation unit 10 calculates the focus adjustment state of the photographing lens 2 by a pupil division type phase difference detection method based on signals from pixels of the image sensor 3. The focus calculation unit 10 calculates the focus position of the focus lens for focusing the image of the photographing lens 2 on the imaging surface of the image sensor 3 based on signals based on charges generated by first and second photodiodes PD-1 and PD-2 of the pixel 20 described later. Specifically, the focus calculation unit 10 detects the image shift amount of the image formed by a plurality of light beams passing through different regions of the pupil of the photographing lens 2, and calculates the defocus amount based on the detected image shift amount. The defocus amount is the amount of shift between the imaging surface on which the image of the photographing lens 2 is formed and the imaging surface of the image sensor 3. Since the calculation of the defocus amount by the phase difference detection method is publicly known, a detailed description will be omitted. The focus calculation unit 10 calculates the movement amount of the focus lens to the in-focus position based on the calculated defocus amount. The microprocessor 9 instructs the lens control unit 2a to move the focusing lens and sends the calculated movement amount of the focus lens to the lens control unit 2a. This causes the focus adjustment to be performed automatically. The focus calculation unit 10, the microprocessor 9, and the lens control unit 2a operate as a focus adjustment unit.

[0011] The image processing unit 13 performs a predetermined image processing on the signal from the imaging element 3 stored in the memory 7 to generate image data. The image processing unit 13 operates as an image generating unit. The image compression unit 12 compresses the image data after the image processing in a predetermined format. The recording unit 11 records the compressed image data in a predetermined file format on the recording medium 11a and reads out the image data recorded on the recording medium 11a. The recording medium 11a is composed of a memory card that is detachable from the recording unit 11, etc.

[0012] Moreover, the image processing unit 13 generates image data for displaying an image on the display unit 14. The display unit 14 displays an image based on the image data generated by the image processing unit 13. The images displayed by the display unit 14 include reproduced images (still images, moving images) based on image data recorded on the recording medium 11a, and monitor images (also called live view images) acquired by the imaging element 3 at a predetermined interval (for example, 60 fps).

[0013] <Image sensor overview> 2 is a diagram illustrating a schematic configuration of the image sensor 3. The image sensor 3 has a plurality of pixels 20 arranged in a matrix and a peripheral circuit for outputting a signal from each pixel 20. Generally, the smallest unit constituting an image is called a "pixel," but in this embodiment, a configuration for generating a signal of the smallest unit constituting an image is called a "pixel." The imaging region 31 indicates a region in which the pixels 20 are arranged in a matrix. In the example of Fig. 2, the imaging region 31 is illustrated as having a range of 16 pixels, 4 rows horizontally and 4 columns vertically, but the actual number of pixels is much greater than that illustrated in Fig. 2.

[0014] FIG. 3 is a diagram illustrating an example of a pixel arrangement of the imaging element 3. A microlens ML and a color filter (not shown) are provided in the pixel 20. For each pixel 20, one of three color filters having different spectral characteristics, for example, R (red), G (green), and B (blue), is provided. The R color filter mainly transmits light in the red wavelength range. The G color filter mainly transmits light in the green wavelength range. The B color filter mainly transmits light in the blue wavelength range. The G color filter transmits light in a wavelength range shorter than that of the R color filter. The B color filter transmits light in a wavelength range shorter than that of the G color filter. As a result, each pixel 20 has different spectral characteristics depending on the color filter provided.

[0015] In the imaging element 3, pixel rows in which pixels 20 having R and G color filters (hereinafter referred to as pixel 20R and pixel 20G, respectively) are alternately arranged and pixel rows in which pixels 20 having G and B color filters (hereinafter referred to as pixel 20G and pixel 20B, respectively) are alternately arranged are repeatedly arranged in a two-dimensional manner. In the first embodiment, the pixels 20R, 20G, and 20B are arranged according to a Bayer array. In the following description, when the pixel 20 is referred to without the R, G, or B designation, it includes all of the pixel 20R, the pixel 20G, and the pixel 20B.

[0016] Each pixel 20 is provided with two photoelectric conversion units. In general, when two photoelectric conversion units are provided per pixel, there are two cases where the two photoelectric conversion units are arranged in the horizontal direction, i.e., in the row direction (also called horizontal division), and two photoelectric conversion units are arranged in the vertical direction, i.e., in the column direction (also called vertical division). In the first embodiment, horizontally divided pixels 20 are arranged over the entire imaging region 31. However, in a predetermined region, vertically divided pixels 20 may be arranged instead of the horizontally divided pixels 20. Each pixel 20 performs photoelectric conversion in the two photoelectric conversion units in accordance with a control signal from a peripheral circuit, and outputs a signal based on the charge generated by the photoelectric conversion.

[0017] 3, one of the two photoelectric conversion units of each pixel 20 is shown hatched. The hatched photoelectric conversion unit indicates that a first signal (to be described later) is generated based on the charge generated in the photoelectric conversion unit. The non-hatched photoelectric conversion unit indicates that a second signal (to be described later) is generated based on the charge generated in the photoelectric conversion unit. Each pixel 20 performs photoelectric conversion in two photoelectric conversion units in accordance with a control signal from a peripheral circuit, and outputs a photoelectric conversion signal.

[0018] 2 again. The peripheral circuits are composed of, for example, a vertical scanning circuit 21, a horizontal scanning circuit 22, control signal lines 23 and 24 connected thereto, first to third vertical signal lines 25a, 25b, and 25c that receive signals from the pixels 20, a constant current source 26 connected to the first to third vertical signal lines 25a, 25b, and 25c, a correlated double sampling circuit (CDS circuit) 27, a horizontal signal line 28 that receives a signal output from the CDS circuit 27, and an output amplifier 29. In this embodiment, three vertical signal lines, that is, the first to third vertical signal lines 25a, 25b, and 25c, are provided for one pixel column consisting of a plurality of pixels 20 arranged in the column direction.

[0019] The vertical scanning circuit 21 and the horizontal scanning circuit 22 output predetermined control signals in response to instructions from the imaging control unit 4. Each pixel 20 is driven by a control signal output from the vertical scanning circuit 21, and outputs a signal based on the charge generated in the photoelectric conversion unit to first to third vertical signal lines 25a, 25b, and 25c. The signal output from the pixel 20 is subjected to noise removal in the CDS circuit 27, and is output to the outside via a horizontal signal line 28 and an output amplifier 29 in response to a control signal from the horizontal scanning circuit 22.

[0020] <1 pixel 2PD configuration> 4 is a circuit diagram illustrating pixels 20 arranged in M ​​columns (vertically arranged) in FIG. 3, i.e., for example, pixel 20G in the Nth row and pixel 20R in the N+1th row. Each pixel 20 has two photodiodes PD-1 and PD-2 as a photoelectric conversion unit inside (behind) the microlens ML and the color filter. That is, each pixel 20 has a first photodiode PD-1 arranged on the left side of the pixel 20 and a second photodiode PD-2 arranged on the right side of the pixel 20. Therefore, a light beam that has passed through a first region of the pupil of the photographing lens 2 is incident on the first photodiode PD-1 of each pixel 20, and a light beam that has passed through a second region of the pupil of the photographing lens 2 is incident on the second photodiode PD-2.

[0021] In this embodiment, for example, the first photodiode PD-1, the second photodiode PD-2, and a readout unit that reads out a signal based on the charge generated by the first and second photodiodes PD-1 and PD-2 are collectively referred to as a "pixel." An example will be described in which the readout unit includes a transfer transistor, an FD region, an amplification transistor, and a selection transistor, which will be described later, but the scope of the readout unit does not necessarily have to be as shown in this example.

[0022] As described above, in each pixel 20, light that has passed through different regions of the pupil of the photographing lens 2, i.e., the first and second regions, is incident on the first and second photodiodes PD-1 and PD-2. The first and second photodiodes PD-1 and PD-2 each photoelectrically convert the incident light to generate electric charges. The electric charges generated in the first photodiode PD-1 are transferred to a first FD (floating diffusion) region FD1 via a first transfer transistor Tx-1.

[0023] The first FD region FD1 accumulates the received charge and converts it into a voltage. A signal according to the potential of the first FD region FD1 is amplified by the first amplification transistor AMP1. The first FD region FD1 and the first amplification transistor AMP1 operate as a first signal generation unit. Then, the signal is read out via the first vertical signal line 25a (output unit) as a signal of a row selected by the first selection transistor SEL1 that selects a row. The first reset transistor RST1 operates as a reset unit that resets the potential of the first FD region FD1.

[0024] The charge generated in the second photodiode PD-2 is transferred to the second FD region FD2 via the second transfer transistor Tx-2. The second FD region FD2 accumulates the received charge and converts it into a voltage. A signal according to the potential of the second FD region FD2 is amplified by the second amplification transistor AMP2. The second FD region FD2 and the second amplification transistor AMP2 operate as a second signal generation unit. Then, the signal is read out via the second vertical signal line 25b (output unit) as a signal of a row selected by the second selection transistor SEL2 that selects a row. The second reset transistor RST2 operates as a reset unit that resets the potential of the second FD region FD2.

[0025] The image sensor 3 according to this embodiment can also transfer the charges generated in the first photodiode PD-1 and the charges generated in the second photodiode PD-2 together to the third FD region FD3 via the third transfer transistor unit Tx-3. The third transfer transistor unit Tx-3 has a transfer transistor Tx-3a that transfers the charges of the first photodiode PD-1 to the third FD region FD3, and a transfer transistor Tx-3b that transfers the charges of the second photodiode PD-2 to the third FD region FD3. The third FD region FD3 accumulates the charges from the first photodiodes PD-1 and PD-2 and converts them into a voltage. A signal according to the potential of the third FD region FD3 is amplified by the third amplification transistor AMP3. The third FD region FD3 and the third amplification transistor AMP3 operate as a third signal generation unit. Then, the signal is read out via the third vertical signal line 25c (output unit) as a signal of a row selected by the third selection transistor SEL3 that selects a row. The third reset transistor RST3 operates as a reset unit that resets the potential of the third FD region FD3.

[0026] In the first embodiment, for example, a signal (referred to as a first signal) based on a charge generated in a first photodiode PD-1 arranged on the left side of a horizontally divided pixel 20, a signal (referred to as a second signal) based on a charge generated in a second photodiode PD-2 arranged on the right side of the pixel 20, and a signal (referred to as a third signal) based on the sum of the charge generated in the first photodiode PD-1 and the charge generated in the second photodiode PD-2 are read out via different first to third vertical signal lines 25a, 25b, and 25c, respectively.

[0027] <Control signal> In the pixel 20, the first transfer transistor Tx-1 is turned on by the first control signal φTx1 when transferring the charge generated in the first photodiode PD-1 to the first FD region FD1. The second transfer transistor Tx-2 is turned on by the second control signal φTx2 when transferring the charge generated in the second photodiode PD-2 to the second FD region FD2. The third transfer transistor unit Tx-3 is turned on by the third control signal φTx3 when transferring the charge generated in the first photodiode PD-1 and the charge generated in the second photodiode PD-2 together to the third FD region FD3. That is, the transfer transistors Tx-3a and Tx-3b of the third transfer transistor unit Tx-3 are simultaneously turned on by the third control signal φTx3.

[0028] The first selection transistor SEL1 for row selection is turned on by a first control signal φSEL1 when a first signal is to be output to the first vertical signal line 25a (output section). The second selection transistor SEL2 for row selection is turned on by a second control signal φSEL2 when a second signal is to be output to the second vertical signal line 25b (output section). The third selection transistor SEL3 for row selection is turned on by a third control signal φSEL3 when a third signal is to be output to the third vertical signal line 25c (output section).

[0029] The first reset transistor RST1 is turned on by a first control signal φRST1 when resetting the potential of the first FD region FD1. The second reset transistor RST2 is turned on by a second control signal φRST2 when resetting the potential of the second FD region FD2. The third reset transistor RST3 is turned on by a third control signal φRST3 when resetting the potential of the third FD region FD3.

[0030] Fig. 5 is a schematic diagram illustrating the layout of the pixels 20G and 20R corresponding to the circuit diagram of Fig. 4. Note that wiring for the first to third control signals φTx1 to φTx3, the first to third control signals φRST1 to φRST3, and the first to third control signals φSEL1 to φSEL3 is omitted from the illustration. In FIG. 5, the first FD region FD1 is disposed on one end side of the first photodiode PD-1, and the second FD region FD2 is disposed on one end side of the second photodiode PD-2 so that the first and second FD regions FD1 and FD2 are arranged on the left and right sides of the pixel 20. The third FD region FD3 is disposed on the other end side of the first and second photodiodes PD-1 and PD-2. The areas of the first photodiode PD-1 and the second photodiode PD-2 disposed on the left and right sides of the pixel 20 are substantially the same. In the present embodiment, the area of ​​the gate oxide film of the first transfer transistor Tx-1 and the area of ​​the first FD region FD1, which are closely related to the electrostatic capacitance (hereinafter simply referred to as capacitance) in the first FD region FD1, are substantially the same as the area of ​​the gate oxide film of the second transfer transistor Tx-2 and the area of ​​the second FD region FD1, which are closely related to the capacitance in the second FD region FD2.

[0031] Furthermore, in this embodiment, the area of ​​the gate oxide film of the third transfer transistor portion Tx-3, which is closely related to the capacitance in the third FD region FD3, and the area of ​​the third FD region FD3 are approximately the same as the area of ​​the gate oxide film of the first transfer transistor Tx-1 and the area of ​​the first FD region FD1, or the area of ​​the gate oxide film of the second transfer transistor Tx-2 and the area of ​​the second FD region FD2, respectively. In this way, the three sets of transfer transistors and FD regions described above are formed through the same process, so that the capacitances of the three sets of FD regions FD1 to FD3 are approximately equal.

[0032] As described above, the areas of the first and second photodiodes PD-1 and PD-2 in the pixel 20 are configured to be substantially the same, so that the amount of charge (photoelectric conversion efficiency) generated per unit amount of incident light is substantially the same. For example, when the same amount of light is incident on the first and second photodiodes PD-1 and PD-2, the amount of charge Q generated by the first and second photodiodes PD-1 and PD-2 is substantially the same. Therefore, the amount of charge Q transferred from the first and second photodiodes PD-1 and PD-2 to the first FD region FD1 and the second FD region FD2 is substantially the same. Also, when different amounts of light are incident on the first and second photodiodes PD-1 and PD-2, different amounts of charge are generated based on the amount of light incident on the first and second photodiodes PD-1 and PD-2. Therefore, different amounts of charges generated in the first and second photodiodes PD-1 and PD-2 are transferred to the first FD region FD1 and the second FD region FD2, respectively. In addition, since the potential difference V=Q / C is established, the capacitance C of the first FD region FD1 and the capacitance C of the second FD region FD2 are made substantially equal, so that the conversion efficiency (signal generation efficiency) to the voltage (signal) converted per unit charge amount is substantially equal. For example, when substantially equal charge amounts Q are generated by the first and second photodiodes PD-1 and PD-2, the magnitudes of the signals generated by the first signal generation unit and the second signal generation unit are substantially equal. In addition, when different charge amounts are generated by the first and second photodiodes PD-1 and PD-2, the first signal generation unit and the second signal generation unit generate signals based on the different charge amounts. That is, the signal generation efficiency is substantially equal between the first signal generation unit and the second signal generation unit, and the variation in the signal generation efficiency is suppressed. The photoelectric conversion efficiencies of the first and second photodiodes PD-1 and PD-2 are approximately equal, and the signal generation efficiencies of the first and second signal generation units are approximately equal, which means that the conversion gains during photoelectric conversion are approximately equal.

[0033] Furthermore, in this embodiment, the capacitance C of the third FD region FD3 in the third signal generation unit is made approximately the same as the capacitance C of the first FD region FD1 in the first signal generation unit (the capacitance C of the second FD region FD2 in the second signal generation unit), so that the signal generation efficiency is approximately the same in the third signal generation unit and the first signal generation unit (second signal generation unit), and variation in the signal generation efficiency is suppressed. The photoelectric conversion efficiencies of the first and second photodiodes PD-1 and PD-2 are approximately equal, and the signal generation efficiencies between the third signal generation unit and the first signal generation unit are approximately equal, which means that the conversion gains during photoelectric conversion of the first signal generation unit to the third signal generation unit are approximately equal. Therefore, for example, when the same amount of light is incident on the first and second photodiodes PD-1 and PD-2 as described above, the magnitude of the signal generated by the third signal generating unit is approximately twice that of the signal generated by the first signal generating unit (the signal generated by the second signal generating unit).

[0034] Generally, as the area of ​​the FD region increases, the capacitance increases and the signal generation efficiency decreases (in other words, the conversion gain decreases). However, in this embodiment, the area of ​​the gate oxide film of the third transfer transistor unit Tx-3 and the area of ​​the third FD region FD3 are approximately the same as the area of ​​the gate oxide film of the first transfer transistor Tx-1 and the area of ​​the first FD region FD1, respectively, so that the conversion gain of the third signal generation unit is approximately equal to the conversion gain of the first signal generation unit. In addition, the conversion gain of the first signal generation unit is also approximately equal to the conversion gain of the second signal generation unit. From the above, it is possible to prevent the conversion gain when signals based on the charges generated by the first photodiode PD-1 and the second photodiode PD-2 are added and read out from being reduced compared to when the signals based on the charges generated by the first photodiode PD-1 or the second photodiode PD-2 are read out individually.

[0035] <Explanation of the time chart> FIG. 6 is a time chart for explaining various control signals supplied to the image sensor 3. In a period in which the first signal and the second signal are individually read out to perform focus adjustment (a readout period for focus adjustment in FIG. 6), the first and second control signals φSEL1 and φSEL2 at H level are simultaneously supplied to the first selection transistor SEL1 and the second selection transistor SEL2. As a result, the first selection transistor SEL1 that outputs the first signal and the second selection transistor SEL2 that outputs the second signal are simultaneously turned on. In addition, a reset pulse at H level is supplied as the first control signal φRST1, so that the first reset transistor RST1 is turned on and the potential of the first FD region FD1 is reset. Similarly, a reset pulse at H level is supplied as the second control signal φRST2, so that the second reset transistor RST2 is turned on and the potential of the second FD region FD2 is reset. At the time indicated by the dashed line t1, the first and second signals at the reset level are read out via the first and second vertical signal lines 25a and 25b, respectively.

[0036] Next, a transfer pulse of H level is supplied as the first control signal φTx1, so that the first transfer transistor Tx-1 is turned on and the charge generated in the first photodiode PD-1 is transferred to the first FD region FD1. At the same time as the supply of the first control signal φTx1, a transfer pulse of H level is supplied as the second control signal φTx2, so that the second transfer transistor Tx-2 is turned on and the charge generated in the second photodiode PD-2 is transferred to the second FD region FD2. As a result, at the time indicated by the dashed line t2, the first and second signals at the signal levels are read out via the first and second vertical signal lines 25a and 25b, respectively.

[0037] In order to generate image data, during a period in which signals based on charges generated by the first photodiode PD-1 and the second photodiode PD-2 are added together and read out (image readout period in FIG. 6), a third control signal φSEL3 of H level is supplied to the third selection transistor SEL3. This turns on the third selection transistor SEL3 that outputs the third signal. In addition, a reset pulse of H level is supplied as the third control signal φRST3, so that the third reset transistor RST3 turns on and the potential of the third FD region FD3 is reset. At the time indicated by the dashed line t3, the third signal of the reset level is read out via the third vertical signal line 25c.

[0038] Next, an H-level transfer pulse is supplied as the third control signal φTx3, turning on the third transfer transistor unit Tx-3 and transferring the charges generated in the first photodiode PD-1 and the second photodiode PD-2 to the third FD region FD3. As a result, at the time indicated by the dashed line t4, the third signal at the signal level is read out via the third vertical signal line 25c.

[0039] <Focus adjustment> The camera 1 of this embodiment generates a pair of focus detection signals used for focus detection based on, for example, a first signal and a second signal of the pixel 20G read out from a pixel row included in the focus area. The focus area is an area where the focus calculation unit 10 detects the amount of image shift as phase difference information, and is also called a focus detection area, a ranging point, or an autofocus (AF) point.

[0040] For example, when an operation signal indicating that the release button has been half-pressed is input from the operation unit 9a, the microprocessor 9 instructs the imaging control unit 4 to perform imaging for focus adjustment. In imaging for focus adjustment, a control signal for performing readout for focus adjustment is supplied from the vertical scanning circuit 21 and the horizontal scanning circuit 22 to a pixel row to be read out of the imaging element 3, thereby performing readout for focus adjustment. Readout for focus adjustment refers to supplying a first control signal φTx1, etc. to each pixel 20G in the pixel row to read out a first signal from the first photodiode PD-1 of the pixel 20G, and supplying a second control signal φTx2, etc. to each pixel 20G to read out a second signal from the second photodiode PD-2 of the pixel 20G.

[0041] By reading out for focus adjustment, the first signal and the second signal read out from each pixel 20G in the pixel row to which the first and second control signals φTx1, φTx2 are supplied are stored in the memory 7. The multiple first signals A1, A2, ..., An (referred to as a-series signals) stored in the memory 7 and the multiple second signals B1, B2, ..., Bn (referred to as b-series signals) stored in the memory 7 represent the intensity distribution of an image formed by multiple light beams that have passed through different regions of the pupil of the photographing lens 2.

[0042] 7 is a diagram illustrating an a-series signal consisting of a plurality of first signals and a b-series signal consisting of a plurality of second signals. In FIG. 7, n a-series signals are represented by hatched circles. Also, n b-series signals are represented by white circles. The a-series signals and b-series signals from the pixel 20G are read out from every other column in FIG. 3. The vertical dashed lines in FIG. 7 correspond to pixel columns. The focus calculation unit 10 calculates the image shift amount of multiple images by performing image shift detection calculation processing (correlation calculation processing, phase difference detection processing) based on the a-series signals and the b-series signals, and calculates the defocus amount by multiplying the image shift amount by a predetermined conversion coefficient.

[0043] Next, the microprocessor 9 judges whether the defocus amount calculated by the focus calculation unit 10 is within a tolerance. If the defocus amount exceeds the tolerance, the microprocessor 9 judges that the focus is not achieved, and sends a lens movement instruction to the lens control unit 2a. The lens control unit 2a moves the focusing lens to a position (focus position) that brings the defocus amount within the tolerance. On the other hand, if the defocus amount is within the tolerance, the microprocessor 9 judges that the focus is achieved, and does not send a lens movement instruction.

[0044] Furthermore, when focus adjustment is performed while a monitor image is displayed on the display unit 14, the imaging control unit 4 can cause the imaging element 3 to alternately perform readout for focus adjustment and readout for an image, which will be described later, for example, for each pixel row. In this case, the microprocessor 9 starts an image shift detection calculation process based on the a-series signals and the b-series signals stored in the memory 7, for example, after readout for focus adjustment has been performed from the pixel row that is the target of readout for focus adjustment.

[0045] On the other hand, in the image readout, the vertical scanning circuit 21 and the horizontal scanning circuit 22 supply control signals for image readout to the pixel row to be read out of the image sensor 3, thereby performing the image readout. The image readout refers to supplying a control signal φTx3 or the like to each pixel 20G in the pixel row to read out a third signal. As described above, the third signal is a signal for generating image data based on the sum of the charge generated in the first photodiode PD-1 and the charge generated in the second photodiode PD-2. The image processing unit 13 performs a predetermined image processing on the third signal stored in the memory 7 by the image readout, thereby generating image data for displaying an image for monitoring on the display unit 14. In this way, when the camera 1 displays an image for monitoring while performing focus adjustment, the imaging control unit 4 causes the above-mentioned readout for focus adjustment and readout for the image to be repeatedly performed.

[0046] In the above-described camera 1, image data used for focus adjustment is generated based on the first and second signals of pixel 20G read from a pixel row included in the focus area. The image data used for focus adjustment is not limited to the first and second signals of pixel 20G, and may be generated based on the first and second signals of pixel 20R or the first and second signals of pixel 20B.

[0047] <Image data generation> The camera 1 of this embodiment generates image data relating to a subject image based on a third signal read from each pixel 20 in the imaging area 31 (FIG. 2). When an operation signal indicating that the release button has been fully pressed is input from the operation unit 9a, for example, the microprocessor 9 instructs the imaging control unit 4 to capture an image for recording. In capturing an image for recording, control signals are supplied from the vertical scanning circuit 21 and the horizontal scanning circuit 22 to each pixel row of the imaging element 3, and image reading is performed. Specifically, a third control signal φTx3 or the like is supplied to each pixel 20 in the pixel row, and the third signal is read from the pixel 20.

[0048] As a result, the third signals read out from each pixel 20 by the image readout are stored in the memory 7. The image processing unit 13 performs gradation processing, color interpolation processing, and the like on the third signals stored in the memory 7 to generate image data for recording.

[0049] According to the first embodiment described above, the following advantageous effects can be obtained. (1) The image sensor 3 includes a first photodiode PD-1 that photoelectrically converts light transmitted through the microlens ML to generate an electric charge, a second photodiode PD-2 that photoelectrically converts light transmitted through the microlens ML to generate an electric charge, a first FD region FD1 that accumulates the electric charge generated by the first photodiode PD-1, a second FD region FD2 that accumulates the electric charge generated by the second photodiode PD-2, and a second FD region FD3 that accumulates the electric charge generated by the first photodiode PD-1 and the electric charge generated by the second photodiode PD-2. A plurality of pixels 20 are provided, each having a third FD region FD3 for accumulating charge, a first transfer transistor Tx-1 for transferring charge generated in a first photodiode PD-1 to the first FD region FD1, a second transfer transistor Tx-2 for transferring charge generated in a second photodiode PD-2 to the second FD region FD2, and a third transfer transistor section Tx-3 for transferring charge generated in the first photodiode PD-1 and charge generated in the second photodiode PD-2 to the third FD region FD3. This allows the first signal based on the charge generated in the first photodiode PD-1 and the second signal based on the charge generated in the second photodiode PD-2 to be appropriately read out individually or collectively from each pixel 20.

[0050] (2) The third FD region FD3 in (1) above accumulates the combined charges of the charges generated by the first photodiode PD-1 and the charges generated by the second photodiode PD-2, so that a third signal based on the sum of the charges generated by the first and second photodiodes PD-1 and PD-2 can be read out as a single signal.

[0051] (3) The difference between the capacity of the first FD region FD1 and the capacity of the second FD region FD2 in (1) above is smaller than a predetermined value, and the difference between the capacity of the first FD region FD1 or the second FD region FD2 and the capacity of the third FD region FD3 is smaller than a predetermined value. This makes the capacities of the three FD regions FD1 to FD3 described above approximately equal, making it possible to make the conversion gains during photoelectric conversion in the first to third signal generation units described above approximately equal. Making the conversion gains approximately equal prevents the accuracy of focus adjustment based on the generated signals from deteriorating. Also, it prevents the image quality of the image based on the generated image data from deteriorating.

[0052] (4) In the above-described imaging element 3, the pixel 20 has a first vertical signal line 25a that outputs a first signal based on the charges accumulated in the first FD region FD1, a second vertical signal line 25b that outputs a second signal based on the charges accumulated in the second FD region FD2, and a third vertical signal line 25c that outputs a third signal based on the charges accumulated in the third FD region FD3, so that the first to third signals generated by the above-described first to third signal generating units can be read out individually.

[0053] (5) In the image sensor 3 of (4) above, at least one of the pixels 20 outputs a first signal based on the charge accumulated in the first FD region FD1 from the first vertical signal line 25a, and outputs a second signal based on the charge accumulated in the second FD region FD2 from the second vertical signal line 25b, and at least one of the pixels 20 outputs a third signal based on the charge accumulated in the third FD region FD3 from the third vertical signal line 25c. This makes it possible to perform readout for focus adjustment and readout for images for each pixel row, for example.

[0054] (6) In the image sensor 3 of (4) or (5) above, the difference between the generation efficiency of the first signal by the first signal generating unit outputted from the first vertical signal line 25a and the generation efficiency of the second signal by the second signal generating unit outputted from the second vertical signal line 25b is smaller than a predetermined value, and the difference between the generation efficiency of the first signal by the first signal generating unit or the generation efficiency of the second signal by the second signal generating unit and the generation efficiency of the third signal by the third signal generating unit outputted from the third vertical signal line 25c is smaller than a predetermined value. This makes it possible to make the conversion gains during photoelectric conversion in the first to third signal generating units described above approximately equal. By making the conversion gains approximately equal, it is possible to prevent the accuracy of focus adjustment based on the generated signal from deteriorating. In addition, it is possible to prevent the image quality of the image based on the generated image data from deteriorating.

[0055] The following modifications are also within the scope of the present invention, and one or more of the modifications may be combined with the above-described embodiment. (First modification of the first embodiment) In the first modification of the first embodiment, a third signal based on the sum of the charge generated in the first photodiode PD-1 and the charge generated in the second photodiode PD-2 is read out via the first vertical signal line 25a or the second vertical signal line 25b. Fig. 8 is a circuit diagram for explaining pixels 20 arranged in M ​​columns (arranged vertically) in Fig. 3, i.e., for example, pixel 20G in the Nth row and pixel 20R in the N+1th row, in Modification 1 of the first embodiment. The same reference numerals are used for the same configurations as in Fig. 4 of the first embodiment, and explanations thereof will be omitted.

[0056] In FIG. 8, the third signal of the row selected by the third selection transistor SEL3 for selecting a row is read out via the second vertical signal line 25b (output section), which is different from the first embodiment (FIG. 4) in which the third signal is read out via the third vertical signal line 25c (output section). By reading out the third signal via the same second vertical signal line 25b (output section) as the second signal, the wiring can be reduced. This allows the areas of the first photodiode PD-1 and the second photodiode PD-2 to be increased. This allows the aperture ratio of the image sensor 3 to be increased. In the first modification of the first embodiment, an example is described in which the third signal is read out via the same second vertical signal line 25b (output section) as the second signal, but the third signal may be read out via the same first vertical signal line 25a (output section) as the first signal.

[0057] Alternatively, in the same pixel column, for example, in odd rows, the third signal may be read out through the same second vertical signal line 25b (output section) as the second signal, and in even rows, the third signal may be read out through the same first vertical signal line 25a (output section) as the first signal. For example, by making the output section different for each pixel row, the third signal can be read out simultaneously from pixels in even rows and pixels in odd rows. Furthermore, the bias in the number of third selection transistors SEL3 connected to the first vertical signal line 25a (output section) and the second vertical signal line 25b (output section) can be suppressed. This can prevent the parasitic capacitance of the first vertical signal line 25a (output section) and the parasitic capacitance of the second vertical signal line 25b (output section) from being biased, thereby preventing a decrease in the readout speed of the vertical signal line with the larger parasitic capacitance. As a specific example, one adjacent pixel 20 outputs a third signal based on the charge accumulated in the third FD region FD3 to the second vertical signal line 25b, and the other adjacent pixel 20 outputs a signal based on the charge accumulated in the third FD region FD3 to the first vertical signal line 25a.

[0058] <Explanation of the time chart> FIG. 9 is a time chart for explaining various control signals supplied to the image sensor 3 of the first modification of the first embodiment. As in the first embodiment (FIG. 6), in the period in which the focus adjustment readout is performed, the first and second control signals φSEL1 and φSEL2 of H level are supplied to the first selection transistor SEL1 and the second selection transistor SEL2, respectively. This turns on the first selection transistor SEL1 that outputs the first signal and the second selection transistor SEL2 that outputs the second signal. In addition, by supplying a reset pulse of H level as the first control signal φRST1, the first reset transistor RST1 is turned on and the potential of the first FD region FD1 is reset. Similarly, by supplying a reset pulse of H level as the second control signal φRST2, the second reset transistor RST2 is turned on and the potential of the second FD region FD2 is reset. At the time indicated by the dashed line t1, the first and second signals of the reset level are read out via the first and second vertical signal lines 25a and 25b, respectively.

[0059] Next, a transfer pulse of H level is supplied as the first control signal φTx1, so that the first transfer transistor Tx-1 is turned on and the charge generated in the first photodiode PD-1 is transferred to the first FD region FD1. Similarly, a transfer pulse of H level is supplied as the second control signal φTx2, so that the second transfer transistor Tx-2 is turned on and the charge generated in the second photodiode PD-2 is transferred to the second FD region FD2. As a result, at the time indicated by the dashed line t2, the first and second signals at the signal levels are read out via the first and second vertical signal lines 25a and 25b, respectively. The above-described read operation for focus adjustment is the same as the read operation for focus adjustment shown in FIG.

[0060] During the period when image readout is performed, the third selection transistor SEL3 that outputs the third signal is turned on by supplying the third control signal φSEL3 of H level. Also, the third reset transistor RST3 is turned on by supplying a reset pulse of H level as the third control signal φRST3, and the potential of the third FD region FD3 is reset. At the time indicated by the dashed line t3, the third signal of the reset level is read out via the second vertical signal line 25b.

[0061] Next, an H-level transfer pulse is supplied as the third control signal φTx3, turning on the third transfer transistor unit Tx-3 and transferring the charge generated in the first photodiode PD-1 and the charge generated in the second photodiode PD-2 to the third FD region FD3. As a result, at the time indicated by the dashed line t4, the third signal at the signal level is read out via the second vertical signal line 25b. In this manner, the third signal can be read out via the second vertical signal line 25b (output section) in the same manner as the second signal.

[0062] According to the first modification of the first embodiment described above, the following advantageous effects can be obtained. That is, in the image sensor 3, the third vertical signal line 25c is shared with the first or second vertical signal line 25a or 25b, so that the wiring can be reduced. This can increase the aperture ratio of the image sensor 3.

[0063] (Modification 2 of the first embodiment) In the second modification of the first embodiment, as shown in FIG. 10, a transistor SW is provided to electrically connect / disconnect the first FD region FD1 and the second FD region FD2. This is to read out a signal based on the sum of the charge generated in the first photodiode PD-1 and the charge generated in the second photodiode PD-2 in two ways. The first readout method is to keep the transistor SW off, turn on the third selection transistor SEL3 and the third transfer transistor Tx-3 as in the first modification of the first embodiment (FIG. 8), and read out the third signal from the second vertical signal line 25b. The second readout method is to keep the transistor SW on, turn on the second selection transistor SEL2 and the first and second transfer transistors Tx-1 and Tx-2, and read out the sum of the first signal and the second signal from the second vertical signal line 25b. Of course, as the second readout method described above, the transistor SW can be turned on to turn on the first selection transistor SEL1 and the first and second transfer transistors Tx-1 and Tx-2, thereby reading out the sum of the first and second signals from the first vertical signal line 25a. Fig. 10 is a circuit diagram for explaining pixels 20 arranged in M ​​columns (arranged vertically) in Fig. 3, i.e., for example, pixel 20G in the Nth row and pixel 20R in the N+1th row, in Modification 2 of the first embodiment. The same components as those in Modification 1 of the first embodiment (Fig. 8) are given the same reference numerals and will not be described.

[0064] As described above, the present embodiment differs from the modified example of the first embodiment (FIG. 8) in that a transistor SW is disposed to electrically connect and disconnect the first FD region FD1 and the second FD region FD2. FIG. 11 is a schematic diagram for explaining the layout of the pixels 20G and 20R corresponding to the circuit diagram of FIG. 10. Note that wiring for the control signal φSW, the first to third control signals φTx1 to φTx3, the first to third control signals φRST1 to φRST3, and the first to third control signals φSEL1 to φSEL3 that switch the transistor SW on and off are omitted from the drawing.

[0065] In Fig. 11, when the transistor SW is on, the first FD region FD1 and the second FD region FD2 are electrically connected, and the area of ​​the FD region is expanded by more than twice. Therefore, the capacitance in the FD region (first FD region FD1 + second FD region FD2) when the transistor SW is on is more than twice the capacitance of the first FD region FD1 (or the capacitance of the second FD region FD2, or the third FD region FD3). As a result, the conversion gain of the signal generating unit by the FD region (first FD region FD1 + second FD region FD2) when the transistor SW is on is lower than the conversion gain of the third signal generating unit by the third FD region FD3 (for example, 1 / 2 or less). In contrast, when the transistor SW is turned off, the first FD region FD1 and the second FD region FD2 are electrically isolated from each other. In this state, the same effects as those of the first modification of the first embodiment (FIG. 8) can be obtained.

[0066] For the above reasons, in the second modification of the first embodiment, the first readout method and the second readout method are switched depending on the shooting conditions. For example, when shooting in a dark environment or a dark subject, the transistor SW is turned off to switch to the first readout method. This makes it possible to read out a high-level third signal based on a high conversion gain. This makes it possible to obtain a bright image even when shooting in a dark environment or a dark subject. On the other hand, when shooting in an overly bright environment or when shooting a bright subject, the transistor SW is turned on to switch to the second readout method described above. This makes it possible to read out a third signal with a suppressed signal level based on a conversion gain lower than the conversion gain of the first readout method. This allows an image with appropriate brightness to be obtained even when shooting in an overly bright environment or when shooting a bright subject. Therefore, for example, the brightness of the subject image can be detected based on the output of the imaging element 3 or based on the output of a separately provided sensor for detecting the brightness of the subject, and the first readout method and the second readout method can be switched. Specifically, when the output of the imaging element 3 or the output of the sensor for detecting the brightness of the subject is less than a threshold, the first readout method can be used, and when the output of the imaging element 3 or the sensor for detecting the brightness of the subject is equal to or greater than the threshold, the second readout method can be used.

[0067] <Explanation of the time chart> FIG. 12 is a time chart for explaining the control signal supplied to the image sensor 3 in the second readout method in the second modification of the first embodiment. The period during which the focus adjustment readout is performed is the same as that in the first modification of the first embodiment (FIG. 9), so the description will be omitted. During the period during which the image readout is performed, the transistor SW is turned on by supplying an H-level control signal φSW, and the first FD region FD1 and the second FD region FD2 are electrically connected. In addition, the second control signal φSEL2 of the H level is supplied, and the second selection transistor SEL2 that outputs the sum of the first signal and the second signal is turned on. Then, the first and second reset transistors RST1 and RST2 are turned on by supplying H-level reset pulses as the first and second control signals φRST1 and φRST2, respectively, and the potentials of the first FD region FD1 and the second FD region FD2 are reset, respectively. At the time indicated by the dashed line t3, the sum of the first signal and the second signal at the reset level is read out via the second vertical signal line 25b.

[0068] Subsequently, H-level transfer pulses are supplied as the first and second control signals φTx1 and φTx2, respectively, to turn on the first and second transfer transistors Tx-1 and Tx-2, and the charges generated in the first photodiode PD-1 and the charges generated in the second photodiode PD-2 are transferred to the first FD region FD1 and the second FD region FD2, respectively. As a result, at the time indicated by the dashed line t4, the sum of the first and second signals of the signal levels is read out via the second vertical signal line 25b. In this way, the sum of the first signal and the second signal can be read out via the second vertical signal line 25b (output section) in the same manner as when the second signal is read out individually.

[0069] According to the second modification of the first embodiment described above, the following advantageous effects can be obtained in addition to the advantageous effects of the first embodiment. (1) In the image sensor 3, a transistor SW is provided that can electrically connect the first FD region FD1 and the second FD region FD2. This makes it possible to read out a signal based on the sum of the charges generated in the first photodiode PD-1 and the second photodiode PD-2 in two ways.

[0070] (2) The camera 1 as an imaging device comprises the imaging element 3 described above in (1) and an image processing unit 13 that generates image data based on at least one of the charges accumulated in the first FD region FD1 and the second FD region FD2 connected by a transistor SW and the charges accumulated in the third FD region FD3. Therefore, for example, by varying the conversion gain of the signal generation unit when reading out signals using the two methods described above, it becomes possible to generate images of different brightness.

[0071] (Second embodiment) In the second embodiment, a signal readout section is shared between pixels 20 adjacent to each other in the column direction. Note that the camera 1 in the second embodiment may or may not be of an interchangeable lens type, as in the first embodiment, and may be configured as an imaging device such as a smartphone or a video camera. Fig. 13 is a circuit diagram for explaining the pixels 20 arranged in M ​​columns (arranged vertically) in Fig. 3 in the second embodiment, i.e., for example, the pixel 20G in the Nth row, the pixel 20R in the N+1th row, the pixel 20G in the N+2th row, and the pixel 20R in the N+3th row. The same components as those in the first embodiment (Fig. 4) are given the same reference numerals and will not be described.

[0072] As described above, the second embodiment differs from the first embodiment (FIG. 4) in that the FD region, amplifying transistor, reset transistor, and selection transistor of the readout unit are shared between adjacent pixels 20 in the column direction.

[0073] Specifically, pixel 20G in the Nth row and pixel 20R in the N+1th row, which are adjacent to each other in the column direction, share the first and second FD regions FD1 and FD2, the first and second amplification transistors AMP1 and AMP2, the first and second reset transistors RST1 and RST2, and the first and second selection transistors SEL1 and SEL2 included in pixel 20R. The first and second FD regions, the first and second amplification transistors, the first and second reset transistors, and the first and second selection transistors shared by the Nth row pixel 20G and the N+1th row pixel 20R adjacent to each other in the column direction may be provided entirely or partially between the Nth row pixel 20G and the N+1th row pixel 20R. Furthermore, a part of the above may be provided in the pixel 20G.

[0074] In addition, the pixel 20R in the (N+1)th row and the pixel 20G in the (N+2)th row, which are adjacent to each other in the column direction, share the third FD region FD3, the third amplification transistor AMP3, the third reset transistor RST3, and the third selection transistor SEL3 included in the pixel 20G. The third FD region, the third amplification transistor, the third reset transistor, and the third selection transistor shared by the pixel 20R in the N+1th row and the pixel 20G in the N+2th row adjacent to each other in the column direction may be provided entirely or partially between the pixel 20R in the N+1th row and the pixel 20G in the N+2th row. Furthermore, a part of the above may be provided in the pixel 20R.

[0075] Similarly, the Nth row pixel 20G shares a third FD region FD3 (not shown), a third amplification transistor AMP3 (not shown), a third reset transistor RST3 (not shown), and a third selection transistor SEL3 (not shown) included in the N-1th row pixel 20R (not shown) adjacent to the opposite side of the N+1th row pixel 20R.

[0076] In this way, two adjacent pixels 20 in the column direction share the first and second FD regions FD1 and FD2, the first and second amplification transistors AMP1 and AMP2, the first and second reset transistors RST1 and RST2, and the first and second selection transistors SEL1 and SEL2 with one of the adjacent pixels 20 in the column direction. Furthermore, two adjacent pixels 20 in the column direction share the third FD region FD3, the third amplification transistor AMP3, the third reset transistor RST3, and the third selection transistor SEL3 with the other adjacent pixel 20 in the column direction.

[0077] Fig. 14 is a schematic diagram illustrating the layout of the pixels 20G and 20R corresponding to the circuit diagram of Fig. 13. Note that wiring for the first to third control signals φTx1 to φTx3, the first to third control signals φRST1 to φRST3, and the first to third control signals φSEL1 to φSEL3 is omitted from the illustration.

[0078] According to the example of Fig. 14, the first to third amplification transistors AMP1 to AMP3, the first to third reset transistors RST1 to RST3, and the first to third selection transistors SEL1 to SEL3 are shared between the pixels 20 adjacent to each other in the column direction, so that the space for nine transistors per two pixels can be reduced compared to the first embodiment (Fig. 5) in which they are not shared. That is, while there are 12 transistors per pixel (24 transistors per two pixels) in the example of Fig. 5, six transistors are required for pixel 20G and nine transistors are required for pixel 20R (15 transistors for two pixels) in the example of Fig. 14, so that the mounting efficiency can be improved.

[0079] In addition, in any pixel 20, the area of ​​the gate oxide film of the first transfer transistor Tx-1, which is closely related to the capacitance in the first FD region FD1, and the area of ​​the first FD region FD1 are approximately the same as the area of ​​the gate oxide film of the second transfer transistor Tx-2, which is closely related to the capacitance in the second FD region FD2, and the area of ​​the second FD region FD1.

[0080] Furthermore, in any pixel 20, the area of ​​the gate oxide film of the third transfer transistor Tx-3, which is closely related to the capacitance in the third FD region FD3, and the area of ​​the third FD region FD3 are approximately the same as the area of ​​the gate oxide film of the first transfer transistor Tx-1 and the first FD region FD1, or the area of ​​the gate oxide film of the second transfer transistor Tx-2 and the area of ​​the second FD region FD2. In this way, the three sets of transfer transistors and FD regions described above are formed through the same process, and therefore the capacitances of the three sets of FD regions FD1 to FD3 are approximately equal.

[0081] Since the areas of the first and second photodiodes PD-1 and PD-2 in the pixel 20 are configured to be substantially the same, the amount of charge (photoelectric conversion efficiency) generated per unit amount of incident light is substantially the same. For example, when the same amount of light is incident on the first and second photodiodes PD-1 and PD-2, the amount of charge Q generated by the first and second photodiodes PD-1 and PD-2 is substantially the same. Therefore, the amount of charge Q transferred from the first and second photodiodes PD-1 and PD-2 to the first FD region FD1 and the second FD region FD2 is substantially the same. As described above, by making the capacitances C of the first FD region FD1 and the second FD region FD2 substantially the same, the magnitudes of the signals generated by the first signal generating unit and the second signal generating unit are substantially the same. Therefore, the conversion gains during photoelectric conversion between the first signal generating unit and the second signal generating unit are substantially the same.

[0082] In addition, the capacitance C of the third FD region FD3 in the third signal generating unit is set to be substantially the same as the capacitance C of the first FD region FD1 in the first signal generating unit (the capacitance C of the second FD region FD2 in the second signal generating unit), so that the conversion gain during photoelectric conversion is substantially the same in the third signal generating unit and the first signal generating unit (second signal generating unit). Therefore, when the same amount of light is incident on the first and second photodiodes PD-1 and PD-2 as described above, the magnitude of the signal generated in the third signal generating unit is substantially twice that of the signal generated in the first signal generating unit (the signal generated in the second signal generating unit). As described above, it is possible to prevent the conversion gain from decreasing when signals based on the charges generated by the first photodiode PD-1 and the second photodiode PD-2 are read out collectively, compared to when signals based on the charges generated by the first photodiode PD-1 or the second photodiode PD-2 are read out individually.

[0083] In the second embodiment, various control signals supplied to the imaging element 3 may have the same timing as that shown in the time chart of FIG.

[0084] According to the second embodiment described above, in addition to the effects and advantages described in the first embodiment, the following effects and advantages can be obtained. In the pixel 20R (N+1 row: FIG. 14) of the image sensor 3, the first FD region FD1 and the second FD region FD2 are shared between, for example, one pixel 20G (N row) adjacent in the column direction, and the third FD region FD3 is shared between the other pixel 20G (N+2 row) adjacent in the column direction. This allows the space of nine transistors per two pixels to be reduced compared to the first embodiment (FIG. 5) in which there is no sharing. That is, while the example of FIG. 5 has 12 transistors per pixel (24 transistors per two pixels), the example of FIG. 14 requires six transistors in the pixel 20G and nine transistors in the pixel 20R (15 transistors for two pixels), which increases the mounting efficiency.

[0085] The following modifications are also within the scope of the present invention, and one or more of the modifications may be combined with the above-described embodiment. (Modification 1 of the second embodiment) In the first modification of the second embodiment, the first to third FD regions FD1 to FD3, the first to third amplification transistors AMP1 to AMP3, the first to third reset transistors RST1 to RST3, and the first to third selection transistors SEL1 to SEL3 are shared between two pixels adjacent to each other in the column direction. Although schematic diagrams for explaining the circuit diagram and layout are omitted, as in the case of the second embodiment, the space required for nine transistors per two pixels can be reduced compared to the first embodiment (FIG. 5) in which no sharing is performed. That is, while the first embodiment has 24 transistors per two pixels, in the first modification of the second embodiment, as in the second embodiment, only 15 transistors are required per two pixels adjacent in the column direction, thereby improving the mounting efficiency.

[0086] (Modification 2 of the second embodiment) In the second modification of the second embodiment, a readout operation is described in which a control signal is supplied to the image sensor 3 of the circuit diagram illustrated in Fig. 13 at a timing different from that in Fig. 9. Fig. 15 is a diagram focusing on the pixel 20R in the N+1th row, the pixel 20G in the N+2th row, and the pixel 20R in the N+3th row among the pixels 20 arranged in M ​​columns (arranged in the vertical direction) in Fig. 3 in the second modification of the second embodiment. Fig. 15 shows a readout circuit shared between the pixel 20G in the N+2th row and the pixel 20R in the N+3th row, and a readout circuit shared between the pixel 20R in the N+1th row and the pixel 20G in the N+2th row, and omits the illustration of other readout circuitry.

[0087] In order to make it easier to understand the timing of the control signals described later, the two FD regions shared between the pixel 20R in the N+3 row and the pixel 20G in the N+2 row are designated by FD1 and FD2, respectively. The first and second photodiodes included in the pixel 20R in the N+3 row are designated by PD-5 and PD-6, respectively. The first and second transfer transistors that transfer the charge generated in the first photodiode PD-5 and the charge generated in the second photodiode PD-6 to the FD region FD1 and the FD region FD2, respectively, are designated by Tx-7 and Tx-8.

[0088] Next, the symbol of the FD region shared between the pixel 20G in the N+2th row and the pixel 20R in the N+1th row is FD3. The symbols of the first and second photodiodes included in the pixel 20G in the N+2th row are PD-1 and PD-2. The symbols of the first and second transfer transistors that transfer the charge generated in the first photodiode PD-1 and the charge generated in the second photodiode PD-2 to the FD region FD1 and the FD region FD2, respectively, are Tx-1 and Tx-2. Furthermore, the symbol of the third transfer transistor unit that transfers the charge generated in the first photodiode PD-1 and the charge generated in the second photodiode PD-2 to the FD region FD3, respectively, is Tx-3.

[0089] Next, the reference symbols of the two FD regions shared between the pixel 20R in the (N+1)th row and the pixel 20G in the (N+1)th row are FD4 and FD5, respectively. The reference symbols of the first and second photodiodes included in the pixel 20R in the (N+1)th row are PD-3 and PD-4. In addition, the reference symbol of the third transfer transistor unit that transfers the charges generated in the first and second photodiodes PD-3 and PD-4 to the FD region FD3 is Tx4.

[0090] Furthermore, the symbols of the first and second transfer transistors that transfer the charges generated in the first photodiode PD-3 and the charges generated in the second photodiode PD-4 to the FD region FD4 and FD region FD5, respectively, are Tx-5 and Tx-6.

[0091] <Explanation of the time chart> 16 is a time chart illustrating various control signals supplied to the image sensor 3 of the second modification of the second embodiment. The readout operation from the first and second photodiodes PD-5 and PD-6 included in the pixel 20R in the (N+3)th row during a period in which readout for focus adjustment is performed will be described.

[0092] When the first and second control signals φSEL1 and φSEL2 are supplied at H level, the first selection transistor SEL1 that outputs the first signal and the second selection transistor SEL2 that outputs the second signal are turned on. When a reset pulse of H level is supplied as the first control signal φRST1, the first reset transistor RST1 is turned on and the potential of the FD region FD1 is reset. Similarly, when a reset pulse of H level is supplied as the second control signal φRST2, the second reset transistor RST2 is turned on and the potential of the FD region FD2 is reset. At the time indicated by the dashed line t1, the first and second signals at the reset level are read out via the first and second vertical signal lines 25a and 25b, respectively.

[0093] Next, a transfer pulse of H level is supplied as the control signal φTx7, so that the first transfer transistor Tx-7 is turned on and the charge generated in the first photodiode PD-5 is transferred to the FD region FD1. Similarly, a transfer pulse of H level is supplied as the control signal φTx8, so that the second transfer transistor Tx-8 is turned on and the charge generated in the second photodiode PD-6 is transferred to the FD region FD2. As a result, at the time indicated by the dashed line t2, the first and second signals at the signal levels are read out via the first and second vertical signal lines 25a and 25b.

[0094] Next, a readout operation from the first and second photodiodes PD-1 and PD-2 included in the pixel 20G in the (N+2)th row will be described. When the first and second control signals φSEL1 and φSEL2 are supplied at H level, the first selection transistor SEL1 that outputs the first signal and the second selection transistor SEL2 that outputs the second signal are turned on. When a reset pulse of H level is supplied as the first control signal φRST1, the first reset transistor RST1 is turned on and the potential of the FD region FD1 is reset. Similarly, when a reset pulse of H level is supplied as the second control signal φRST2, the second reset transistor RST2 is turned on and the potential of the FD region FD2 is reset. At the time indicated by the dashed line t3, the first and second signals at the reset level are read out via the first and second vertical signal lines 25a and 25b, respectively.

[0095] Next, a high-level transfer pulse is supplied as the control signal φTx1, turning on the first transfer transistor Tx-1 and transferring the charge generated in the first photodiode PD-1 to the FD region FD1. Similarly, a high-level transfer pulse is supplied as the control signal φTx2, turning on the second transfer transistor Tx-2 and transferring the charge generated in the second photodiode PD-2 to the FD region FD2. As a result, at the time indicated by the dashed line t4, the first and second signals at the signal levels are read out via the first and second vertical signal lines 25a and 25b.

[0096] The readout operation from the first and second photodiodes PD-1 and PD-2 included in the pixel 20G in the (N+2)th row during the period in which image readout is performed will be described. When an H-level control signal φSEL3 is supplied, the third selection transistor SEL3 that outputs the third signal is turned on. When an H-level reset pulse is supplied as the third control signal φRST3, the third reset transistor RST3 is turned on and the potential of the FD region FD3 is reset. At the time indicated by the dashed line t5, the third signal of the reset level is read out via the second vertical signal line 25b.

[0097] Subsequently, an H-level transfer pulse is supplied as the control signal φTx3, so that the third transfer transistor unit Tx-3 is turned on and the charges generated in the first photodiode PD-1 and the second photodiode PD-2 are transferred to the FD region FD3. As a result, at the time indicated by the dashed line t6, the third signal at the signal level is read out via the second vertical signal line 25b. In this way, the third signal by the first and second photodiodes PD-1 and PD-2 can be read out via the second vertical signal line 25b (output section) like the second signal.

[0098] Next, a readout operation from the first and second photodiodes PD-3 and PD-4 included in the pixel 20R in the (N+1)th row will be described. When the control signal φSEL3 of H level is supplied, the third selection transistor SEL3 that outputs the third signal is turned on. When a reset pulse of H level is supplied as the third control signal φRST3, the third reset transistor RST3 is turned on and the potential of the FD region FD3 is reset. At the time indicated by the dashed line t7, the third signal of the reset level is read out via the second vertical signal line 25b.

[0099] Next, an H-level transfer pulse is supplied as the control signal φTx4, so that the third transfer transistor unit Tx-4 is turned on and the charge generated in the first photodiode PD-3 and the charge generated in the second photodiode PD-4 are transferred to the FD region FD3. As a result, at the time indicated by the dashed line t8, the third signal at the signal level is read out via the second vertical signal line 25b. In this way, the third signal by the first and second photodiodes PD-3 and PD-4 can be read out via the second vertical signal line 25b (output section) like the second signal.

[0100] According to the second modification of the second embodiment, when reading out for focus adjustment, reading out can be performed row by row. Also, when reading out for images, reading out can be performed row by row. This makes it possible to read out signals while arbitrarily switching between reading out for focus adjustment and reading out for images for each row.

[0101] (Third embodiment) In the third embodiment, a one-pixel 4PD configuration will be described. The one-pixel 4PD configuration refers to a configuration in which each pixel 20 has four photodiodes PD-1, PD-2, PD-3, and PD-4 as a photoelectric conversion unit inside (behind) the microlens ML and the color filter. That is, each pixel 20 has, for example, a first photodiode PD-1 arranged at the upper right of the pixel position, a second photodiode PD-2 arranged at the upper left of the pixel position, a third photodiode PD-3 arranged at the lower right of the pixel position, and a fourth photodiode PD-4 arranged at the lower left of the pixel position.

[0102] As a result, a light beam that has passed through a first region of the pupil of the photographing lens 2 is incident on the first photodiode PD-1 of each pixel 20, a light beam that has passed through a second region of the pupil of the photographing lens 2 is incident on the second photodiode PD-2, a light beam that has passed through a third region of the pupil of the photographing lens 2 is incident on the third photodiode PD-3, and a light beam that has passed through a fourth region of the pupil of the photographing lens 2 is incident on the fourth photodiode PD-4.

[0103] In general, dividing the pupil area of ​​the photographing lens 2 horizontally (row direction) as in the first and second embodiments is suitable for performing focus detection on vertical patterns on the subject. In contrast, dividing the pupil area of ​​the photographing lens 2 vertically (column direction) is suitable for performing focus detection on horizontal patterns on the subject. In the third embodiment, a 4PD per pixel configuration makes it possible to perform focus detection regardless of the direction of the subject's pattern. The image sensor 3 having pixels 20 with a 4PD per pixel configuration will be described in detail below.

[0104] Fig. 17(a) is a diagram illustrating a circuit of a pixel 20 of an image sensor 3 according to a third embodiment. Fig. 17(b) is an enlarged view of a region U of a photoelectric conversion unit in Fig. 17(a). Region U has a first photodiode PD-1 arranged at the upper right of the pixel position, a second photodiode PD-2 arranged at the upper left of the pixel position, a third photodiode PD-3 arranged at the lower right of the pixel position, and a fourth photodiode PD-4 arranged at the lower left of the pixel position.

[0105] <Control signal> In the region U, the first transfer transistor Tx-1 is turned on by the first control signal φTx1 when transferring the charge generated in the first photodiode PD-1 to the FD region FD1. The second transfer transistor Tx-2 is turned on by the second control signal φTx2 when transferring the charge generated in the second photodiode PD-2 to the FD region FD2. The fifth transfer transistor unit Tx-5 is turned on by the fifth control signal φTx5 when transferring the charge generated in the first photodiode PD-1 and the charge generated in the second photodiode PD-2 together to the FD region FD5. That is, the transfer transistors Tx-5a and Tx-5b (not shown) of the fifth transfer transistor unit Tx-5 are simultaneously turned on by the fifth control signal φTx5.

[0106] In the region U, the third transfer transistor Tx-3 is turned on by the third control signal φTx3 when transferring the charge generated in the third photodiode PD-3 to the FD region FD3. The fourth transfer transistor Tx-4 is turned on by the fourth control signal φTx4 when transferring the charge generated in the fourth photodiode PD-4 to the FD region FD4. The sixth transfer transistor unit Tx-6 is turned on by the sixth control signal φTx6 when transferring the charge generated in the third photodiode PD-3 and the charge generated in the fourth photodiode PD-4 together to the FD region FD6. That is, the transfer transistors Tx-6a and Tx-6b (not shown) of the sixth transfer transistor unit Tx-6 are simultaneously turned on by the sixth control signal φTx6.

[0107] Furthermore, in the region U, the seventh transfer transistor unit Tx-7 is turned on by a seventh control signal φTx7 when transferring the charge generated in the first photodiode PD-1 and the charge generated in the third photodiode PD-3 together to the FD region FD7. That is, the transfer transistors Tx-7a and Tx-7b (not shown) of the seventh transfer transistor unit Tx-7 are simultaneously turned on by the seventh control signal φTx7.

[0108] Furthermore, in the region U, the eighth transfer transistor unit Tx-8 is turned on by an eighth control signal φTx8 when transferring the charge generated in the second photodiode PD-2 and the charge generated in the fourth photodiode PD-4 together to the FD region FD8. That is, the transfer transistors Tx-8a and Tx-8b (not shown) of the eighth transfer transistor unit Tx-8 are simultaneously turned on by the eighth control signal φTx8.

[0109] In the third embodiment, four vertical signal lines, i.e., first to fourth vertical signal lines 25a, 25b, 25c, and 25d, are provided for one pixel column of the image sensor 3. A signal based on the charge generated in the first photodiode PD-1 and a signal based on the sum of the charge generated in the first photodiode PD-1 and the charge generated in the third photodiode PD-3 are read out via the first vertical signal line 25a.

[0110] In addition, a signal based on the charge generated in the second photodiode PD-2 and a signal based on the sum of the charge generated in the first photodiode PD-1 and the charge generated in the second photodiode PD-2 are read out via the second vertical signal line 25b.

[0111] Furthermore, a signal based on the charge generated in the third photodiode PD-3 and a signal based on the sum of the charge generated in the third photodiode PD-3 and the charge generated in the fourth photodiode PD-4 are read out via the third vertical signal line 25c.

[0112] Furthermore, a signal based on the charge generated in the fourth photodiode PD-4 and a signal based on the sum of the charge generated in the second photodiode PD-2 and the charge generated in the fourth photodiode PD-4 are read out via the fourth vertical signal line 25d.

[0113] When the pupil region of the photographing lens 2 is divided horizontally (row direction) by the above-mentioned pixels 20, for example, a signal based on the sum of the charges generated in the first photodiode PD-1 and the third photodiode PD-3 and a signal based on the sum of the charges generated in the second photodiode PD-2 and the fourth photodiode PD-4 are read out. That is, the signals added up in the FD region 7 and the FD region 8 are read out.

[0114] Furthermore, when the pupil region of the photographing lens 2 is divided vertically (column direction) by the above-mentioned pixels 20, for example, a signal based on the sum of the charges generated in the first photodiode PD-1 and the second photodiode PD-2 and a signal based on the sum of the charges generated in the third photodiode PD-3 and the fourth photodiode PD-4 are read out. That is, the signals added up in the FD region 5 and the FD region 6 are read out.

[0115] <Explanation of the time chart> FIG. 18 is a time chart for explaining various control signals supplied to the image sensor 3 of the third embodiment. With reference to FIG. 18, a read operation in which signals based on charges generated in the first to fourth photodiodes PD-1 to PD-4 of the pixel 20 shown in FIG. 17(a) and FIG. 17(b) are read out individually will be explained. In the third embodiment, as described above, four vertical signal lines (first to fourth vertical signal lines 25a, 25b, 25c, 25d) are provided for one pixel column of the image sensor 3. This allows signals based on charges generated in the first to fourth photodiodes PD-1 to PD-4 to be read out in parallel at the same timing as described below. In FIG. 18, the signal waveforms of the first to fourth vertical signal lines 25a, 25b, 25c, and 25d are omitted.

[0116] When the first to fourth control signals φSEL1 to φSEL4 of H level are supplied from the vertical scanning circuit 21, the first selection transistor SEL1, which outputs a signal based on the charge generated in the first photodiode PD-1, the second selection transistor SEL2, which outputs a signal based on the charge generated in the second photodiode PD-2, the third selection transistor SEL3, which outputs a signal based on the charge generated in the third photodiode PD-3, and the fourth selection transistor SEL4, which outputs a signal based on the charge generated in the fourth photodiode PD-4, are each turned on.

[0117] Moreover, when a high-level reset pulse is supplied as the first control signal φRST1, the first reset transistor RST1 is turned on and the potential of the FD region FD1 is reset. Similarly, when high-level reset pulses are supplied as the second to fourth control signals φRST2 to φRST4, the second to fourth reset transistors RST2 to RST4 are turned on and the potentials of the FD regions FD2 to FD4 are reset. As a result, at the time indicated by the dashed line t1, reset-level signals are read out via the first to fourth vertical signal lines 25a to 25d, respectively.

[0118] Subsequently, H-level transfer pulses are supplied as the control signals φTx1 to φTx4 to the first to fourth transfer transistors Tx-1 to Tx-4, respectively, to turn on the first to fourth transfer transistors Tx-1 to Tx-4. As a result, the charges generated in the first to fourth photodiodes PD-1 to PD-4 are transferred to the FD regions FD1 to FD4, respectively. As a result, at the time indicated by the dashed line t2, the signal level signals are read out via the first to fourth vertical signal lines 25a to 25d, respectively.

[0119] Next, a read operation will be described when performing readout for focus adjustment to detect a phase difference in the vertical direction and readout for focus adjustment to detect a phase difference in the horizontal direction. Fig. 19 is a time chart illustrating various control signals supplied to the image sensor 3 of the third embodiment during readout for focus adjustment. In FIG. 19, the signal waveforms of the first to fourth vertical signal lines 25a, 25b, 25c, and 25d are omitted.

[0120] <Vertical division> As described above, in the case of division in the vertical direction, the signals added in the FD region 5 and the FD region 6 are read out. When the fifth and sixth control signals φSEL5 and φSEL6 of H level are supplied from the vertical scanning circuit 21, the fifth selection transistor SEL5 that outputs a signal based on the sum of the charges generated in the first and second photodiodes PD-1 and PD-2, respectively, and the sixth selection transistor SEL6 that outputs a signal based on the sum of the charges generated in the third and fourth photodiodes PD-3 and PD-4, respectively, are turned on.

[0121] Moreover, when an H-level reset pulse is supplied as the fifth control signal φRST5, the fifth reset transistor RST5 is turned on and the potential of the FD region FD5 is reset. Similarly, when an H-level reset pulse is supplied as the sixth control signal φRST6, the sixth reset transistor RST6 is turned on and the potential of the FD region FD6 is reset. As a result, at the time indicated by the dashed line t1, a reset level signal is read out via the first and third vertical signal lines 25b and 25c, respectively.

[0122] Subsequently, a fifth control signal φTx5 is supplied with a transfer pulse of H level, thereby turning on the fifth transfer transistor unit Tx-5. As a result, the charges generated in the first and second photodiodes PD-1 and PD-2 are transferred to the FD region FD5. At the same time as the fifth control signal φTx5 is supplied, a sixth control signal φTx6 is supplied with a transfer pulse of H level, thereby turning on the sixth transfer transistor unit Tx-6. As a result, the charges generated in the third and fourth photodiodes PD-3 and PD-4 are transferred to the FD region FD6. As a result, at the time indicated by the dashed line t2, a signal of the sum of the signal levels (a signal based on the sum of the charges generated in the first and second photodiodes PD-1 and PD-2, respectively, and a signal based on the sum of the charges generated in the third and fourth photodiodes PD-3 and PD-4, respectively) is read out via the second and third vertical signal lines 25b and 25c, respectively.

[0123] <Horizontal division> As described above, when dividing in the horizontal direction, the signals added in the FD region 7 and the FD region 8 are read out. When the seventh and eighth control signals φSEL7 and φSEL8 of H level are supplied from the vertical scanning circuit 21, the seventh selection transistor SEL7 that outputs a signal based on the sum of the charges generated in the first and third photodiodes PD-1 and PD-3, respectively, and the eighth selection transistor SEL6 that outputs a signal based on the sum of the charges generated in the second and fourth photodiodes PD-2 and PD-4, respectively, are turned on.

[0124] Moreover, when an H-level reset pulse is supplied as the seventh control signal φRST7, the seventh reset transistor RST7 is turned on and the potential of the FD region FD7 is reset. Similarly, when an H-level reset pulse is supplied as the eighth control signal φRST8, the eighth reset transistor RST8 is turned on and the potential of the FD region FD8 is reset. As a result, at the time indicated by the dashed line t3, signals of the respective reset levels are read out via the first and fourth vertical signal lines 25a and 25d.

[0125] Subsequently, a transfer pulse of H level is supplied as the seventh control signal φTx7, and the seventh transfer transistor unit Tx-7 is turned on. As a result, the charges generated in the first and third photodiodes PD-1 and PD-3 are transferred to the FD region FD7. At the same time as the seventh control signal φTx7 is supplied, a transfer pulse of H level is supplied as the eighth control signal φTx8, and the eighth transfer transistor unit Tx-8 is turned on. As a result, the charges generated in the second and fourth photodiodes PD-2 and PD-4 are transferred to the FD region FD8. As a result, at the time indicated by the dashed line t4, a signal of the sum of the signal levels (a signal based on the sum of the charges generated in the first and third photodiodes PD-1 and PD-3, and a signal based on the sum of the charges generated in the second and fourth photodiodes PD-2 and PD-4) is read out via the first and fourth vertical signal lines 25a and 25d.

[0126] Although various embodiments and modifications have been described above, the present invention is not limited to these. Other embodiments that are conceivable within the scope of the technical idea of ​​the present invention are also included within the scope of the present invention.

[0127] The disclosures of the following priority applications are incorporated herein by reference: Japanese Patent Application No. 68452, 2017 (filed March 30, 2017) [Explanation of symbols]

[0128] 1. Camera 2. Imaging optical system 3. Image sensor 9...Microprocessor 10…Focus calculation section 13...Image processing unit 20, 20G, 20R, 20B…pixels 21...Vertical scanning circuit 22...Horizontal scanning circuit 23, 24...Control signal lines 25a, 25b, 25c, 25d...Vertical signal line AMP1 to AMP8: Amplification transistors FD1~FD8…FD area PD-1~PD-4...Photodiodes SEL1 to SEL8: Selection transistors Tx-1, Tx-2, Tx-3, Tx-4...Transfer transistor Tx-3 to Tx-8: Transfer transistor section

Claims

[Claim 1] a first photoelectric conversion unit that converts light transmitted through the first microlens into an electric charge; a second photoelectric conversion unit that converts light transmitted through the first microlens into an electric charge and is disposed adjacent to the first photoelectric conversion unit in the first direction; a third photoelectric conversion unit configured to convert light transmitted through a second microlens disposed adjacent to the first microlens in a second direction intersecting the first direction into an electric charge; a fourth photoelectric conversion unit that converts light transmitted through the second microlens into an electric charge and is disposed adjacent to the third photoelectric conversion unit in the first direction; a first diffusion unit having one diffusion region to which the electric charges converted in the first photoelectric conversion unit and the electric charges converted in the third photoelectric conversion unit are transferred; a second diffusion unit having one diffusion region to which the electric charges converted in the second photoelectric conversion unit and the electric charges converted in the fourth photoelectric conversion unit are transferred; a first transistor having a gate electrically connected to the first diffusion portion and outputting a first signal; a second transistor having a gate electrically connected to the second diffusion portion and outputting a second signal; a first signal line for reading out the first signal output from the first transistor; a second signal line for reading out the second signal output from the second transistor; Equipped with the first diffusion unit is disposed between the first photoelectric conversion unit and the third photoelectric conversion unit in the second direction; the second diffusion unit is disposed between the second photoelectric conversion unit and the fourth photoelectric conversion unit in the second direction. Image sensor.

Images