Electronic device and program writing method therefor

Abstract

To provide an electronic device equipped with multiple sub processors, the electronic device being configured to avoid the need to prepare ports of a main processor corresponding to the number of target sub processors.SOLUTION: An electronic device includes a plurality of sub processors and a main processor. The main processor includes a group selection port which outputs selection signals for selecting the sub processors by group. Each of the sub processors includes a selection reception port for receiving a selection signal, and a start reception port for receiving an instruction to start a program write mode. At least one sub processor in each group has a start transmission port to transmit a start instruction to sub processors in other groups. The main processor selects a target group to which a program is to be written, transmits an instruction to any one sub processor in the other group, and starts individually the program write mode of one or more sub processors belonging to the targe group.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to an electronic device including a plurality of sub-processors having program-writing modes and a main processor communicating with each of the sub-processors, and a program-writing method therefor. [Background technology]

[0002] Some electronic devices include multiple processors such as microcomputers. Among these multiple processors, there are some in which multiple sub-processors are connected to a main processor. Conventionally, programs for microcomputers, particularly those with relatively small circuit scales, were often stored in non-rewritable read only memory (ROM). However, advances in semiconductor technology have made it possible to manufacture rewritable non-volatile memories such as flash memories at low cost and stably, and it has become common for even small microcomputers to store programs in rewritable non-volatile memories. As a result, processors with a program write mode are becoming more widespread.

[0003] When a processor is installed in an electronic device, the control program for the electronic device is written into the memory that stores the programs. However, updated programs are also written into the memory as necessary after that. These are so-called program updates to add new functions to the electronic device or to fix defects. It is desirable to be able to write programs on-board without requiring specialized knowledge or tools, so that users can update the programs themselves even after the device has already been shipped to the market and is in use.

[0004] In this regard, there is known a system that has multiple microcontrollers each having a non-volatile memory, each of which can be rewritten in an on-board state, and in which a specific microcontroller monitors the operation of the other microcontrollers and performs an operation to reset the other microcontrollers when an abnormality is detected (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2000-235487 A Summary of the Invention [Problem to be solved by the invention]

[0006] To update a program of a sub-processor via a main processor, it is necessary to connect the sub-processor to be updated to the main processor one-to-one. To achieve one-to-one connection, it is necessary to prepare selection signals and reset signals for the number of target sub-processors so that the target sub-processors can be individually selected, which increases the number of ports of the main processor. The present disclosure has been made in consideration of the above circumstances, and provides a configuration that does not require the preparation of ports of the main processor for the number of target sub-processors, even in electronic devices equipped with a large number of sub-processors. [Means for solving the problem]

[0007] The present disclosure provides an electronic device in which a plurality of sub-processors and a main processor are communicatively connected, the main processor having a group selection port that outputs a selection signal to select each sub-processor on a group basis, and a program send port that sends program data to each sub-processor, each sub-processor having a selection receiving port that receives the selection signal, a program receiving port that receives the program data, and a start receiving port that receives an instruction to start a program write mode, at least one sub-processor in each group having one or more start send ports that send the start instruction to any of the sub-processors in the other groups, the main processor using the group selection port to select a target group for program writing, sending an instruction to any of the sub-processors in the other groups to individually start the program write mode of one or more sub-processors belonging to the target group, and sending program data to the sub-processor that has started the program write mode using the program send port.

[0008] In addition, from a different perspective, the present disclosure provides a method for writing programs to an electronic device, comprising the steps of: a main processor communicatively connected to a plurality of sub-processors selecting a target group for program writing using a group selection port that selects each sub-processor on a group basis; sending an instruction to any of the sub-processors in the other groups via communication to individually start a program writing mode of one or more sub-processors belonging to the target group; and sending program data using a program sending port to the sub-processor that has started the program writing mode. Effect of the Invention

[0009] In the electronic device according to the present disclosure, the main processor selects a target group for program writing and sends instructions to one of the sub-processors in the other groups to individually start the program writing mode of one or more sub-processors belonging to the target group, thereby realizing a configuration that does not require preparing ports of the main processor for the number of target sub-processors, even in an electronic device having a large number of sub-processors. According to the program writing method of the present disclosure, even in an electronic device equipped with a large number of sub-processors, the sub-processors can be divided into multiple groups, and an unused port of any of the sub-processors can be assigned as the start sending port for the sub-processors of the other groups, making it possible to write programs to each sub-processor in each group. also exerts the same effect. [Brief description of the drawings]

[0010] [Figure 1] 1 is a block diagram showing an example configuration of an image processing device in an embodiment of the present disclosure. [Diagram 2] 2 is an explanatory diagram showing an example of signal connections between a main processor and a sub-processor of the image processing device shown in FIG. [Diagram 3] 3 is a first timing chart showing an example of a procedure for writing a program to each sub-processor shown in FIG. 2; [Figure 4] 4 is a second timing chart showing an example of a procedure for writing a program to each sub-processor shown in FIG. 2; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The present disclosure will be described in further detail below with reference to the drawings. Note that the following description is illustrative in all respects and should not be construed as limiting the present disclosure. (Embodiment 1) <Configuration example of image processing device> First, an image processing device, which is one aspect of the electronic device in this embodiment, will be described. FIG. 1 is a block diagram showing an example of the configuration of an image processing device in an embodiment of the present disclosure. The image processing device 100 in this embodiment is a multifunction peripheral including a scanner unit 40 that reads an original image and an engine unit 50 that prints the image. As shown in the block diagram of FIG. 1, the image processing device 100 includes a control unit 10, a storage device 20, a communication unit 22, an operation unit 30, the scanner unit 40 that reads an image, and the engine unit 50 that prints the image. The control unit 10 includes an operation control unit 11, a file control unit 12, a job management unit 13, a job execution unit 14, and an image processing unit 15. The control unit 10 controls the image processing device 100. The image processing unit 15 includes an input processing unit 16 and an output image generation unit 17.

[0012] The storage device 20 includes a volatile memory such as a DRAM and a non-volatile memory such as a HDD or a flash memory. The storage device 20 stores a control program executed by the processor and images read by the scanner unit 40 and processed by the image processing unit 15. It also stores data related to the control of the file control unit 12, the job management unit 13, the job execution unit 14, and the image processing unit 15. The storage device 20 may be integrated with the memory of the control unit 10. The communication unit 22 is a circuit for communicating data with external devices via a network.

[0013] The operation unit 30 has, for example, a liquid crystal or organic EL display device, and displays a screen according to the control of the operation control unit 11. The operation unit 30 also includes an operation input device such as a touch panel, and detects user operations on the operation unit 30. The operation control unit 11 recognizes an operation signal detected by the operation input device.

[0014] The scanner unit 40 includes a document table on which a document to be read is placed, a scanning mechanism that scans the document placed on the document table, a document feeder that transports the document, and an image sensor that reads the image of the scanned document. The engine unit 50 includes an image forming unit that forms a visible image to be printed by, for example, an electrophotographic method, a paper feed and transport mechanism that feeds printing paper, a transfer mechanism that transfers the visible image formed by the image forming unit to the fed printing paper, and a fixing mechanism that fixes the transferred image to the printing paper.

[0015] The file control unit 12 saves and reads files in the storage device 20, and expands files in the storage device 20. The job management unit 13 performs processes for registering, deleting, and stopping various jobs such as copy jobs, scanner jobs, and print jobs. When a job registered in the job management unit becomes executable, the job management unit 13 requests the job execution unit 14 to start executing the job. The job execution unit 14 determines whether or not the job registered by the job management unit 13 can be started, and causes the engine unit 50, the scanner unit 40, and the image processing unit 15 to execute the job according to the settings. The job execution unit 14 recognizes the state detected by the sensors (not shown) arranged in the scanner unit 40 and the engine unit 50. Then, it controls the operation of the motors, actuators, devices, etc. (not shown) arranged in the scanner unit 40 and the engine unit 50. Also, the image processing unit 15 controls the image-related processing of the image processing unit 15. Then, it executes the processing related to the job, such as reading the image of the document, printing, and previewing.

[0016] As a specific configuration, the control unit 10 is mainly composed of a processor. In addition to the processor, the control unit 10 is composed of hardware resources such as a work memory, an input / output interface circuit, a timer circuit, an image processing circuit, and a communication circuit. The processor executes a control program prestored in the storage device 20 to perform various jobs related to operation recognition, display control, reading of document images, printing of images, etc., that is, a series of processes related to image formation. The software resources and hardware resources work together to realize the functions of the control unit 10.

[0017] Furthermore, the operation unit 30, the scanner unit 40, and the engine unit 50 each include a processor. For example, the operation unit 30 includes a processor that controls a display device and a processor that controls an operation input device. The scanner unit 40 includes a processor that controls a scanning mechanism and an image sensor, and a processor that controls a document transport device. The engine unit 50 includes a processor that controls an image forming unit and a processor that controls a paper feed transport mechanism. The processor of the control unit 10 communicates with the processors of the operation unit 30, the scanner unit 40, and the engine unit 50 as a main processor and controls them together. The processors of the operation unit 30, the scanner unit 40, and the engine unit 50 each perform control as a sub-processor based on instructions from the main processor. The locations of the main processor and the sub-processor are indicated by dashed rectangles in FIG. 1.

[0018] <Example of signal connection between main processor and sub processor> Next, an example of signal connection between the main processor and the sub-processor will be described. FIG. 2 is an explanatory diagram showing an example of signal connection between the main processor and the sub-processor of the image processing device shown in FIG. 1. As shown in FIG. 2, the main processor 70 and the multiple sub-processors G1-0, ... G1-n, G2-0, ... G2-m are connected by a BOOT signal in addition to communication signals. There are two communication signal systems, one of which is an inter-processor communication system that communicates with the main processor 70 when writing a program for each sub-processor, and in the example shown in FIG. 2, SPI (Serial Peripheral Interface) communication is applied. SPICLK (clock signal), MOSI (main output / sub-node input signal), and MISO (main input / sub-node output signal) shown in the main processor 70 are signals for the SPI communication. Each signal is a common signal line regardless of the number of sub-processors. MOSI and MISO correspond to communication ports through which the main processor communicates with each sub-processor.

[0019] In the example shown in FIG. 2, there is one characteristic configuration for another CS (chip select) signal used in SPI communication, where the sub-CPUs are divided into multiple groups and a common signal line is used for each group. Specifically, in FIG. 2, the sub-CPUs are divided into a first group indicated by the SS0 signal and a second group indicated by the SS1 signal, and selection is performed for each group. In the main processor 70, the port that outputs SS0 and SS1 corresponds to the group selection port. In each sub-processor, the port that receives the SS0 signal or SS1 signal corresponds to the selection reception port. Another characteristic configuration is that the MOSI and MISO signals of the sub-processors belonging to the same group are connected in series, so that the signal circulates around the main processor 70. Note that the communication method between processors is not limited to SPI communication, and can be, for example, I 2 C or other communication methods may be used.

[0020] The remaining one of the two communication signal systems is a signal line for sending program data to be written to the target sub-processor. In the example shown in FIG. 2, a UART (Universal Asynchronous Receiver Transmitter) is used. The UART of the main processor 70 corresponds to a program sending port. The UART of each sub-processor corresponds to a program receiving port. When writing a program to multiple sub-processors in the same group, the main processor 70 does not write the programs to the multiple sub-processors simultaneously, but writes them one by one in order via a UART common to the sub-processors. At that time, the main processor 70 performs group SPI communication of the sub-processors that control the reset signal. According to this embodiment, since the program is written using a communication port (UART) common to each sub-processor, even in an electronic device having a large number of sub-processors, the number of ports of the main processor is not occupied in proportion to the number of sub-processors. The UART of the main processor 70 is preferably applied to control peripheral devices of the image processing device 100 during normal operation. An example of a peripheral device is a finisher. It may be a peripheral device that is installed as an option. When writing to the sub-processor, the connection switching circuit 80 is used to switch the UART signal line. Writing to the sub-processor is premised on switching the image processing device from normal operation mode to program update mode, and peripheral devices are not operated in program update mode. According to this embodiment, in normal operation mode where no program is written to the sub-processor, program data can be sent to the sub-processor by using a port for sending data to devices other than the sub-processor. Note that communication of program data (communication with peripheral devices, etc. in normal mode) is not limited to UART, and can be sent using, for example, I 2 C or other communication methods may be used.

[0021] The BOOT signal is a signal for transitioning the sub-processor from normal operation mode to program write mode. When this signal is asserted (high level) and the reset signal is released, the sub-processor starts up in program write mode. Note that even if the BOOT signal is asserted at a time other than when the reset is released, the sub-processor continues in normal operation mode. The port that receives the BOOT signal in each sub-processor corresponds to the boot signal port.

[0022] One of the more characteristic configurations of the example shown in FIG. 2 is that the reset signal of each sub-processor is connected to the sub-processors of different groups. Specifically, the reset signal of the sub-processors G1-0, G1-1 to G1-n of the first group is connected to the sub-processor G2-0 of the second group. The reset signal of the sub-processors G2-0, G2-1 to G2-m of the second group is connected to the sub-processor G1-0 of the first group. The terminal that receives the reset signal of each sub-processor corresponds to the start receiving port. The port that sends the reset signal to the sub-processor of the other group corresponds to the start sending port. According to this embodiment, since the individual reset signal that starts the program writing mode of each sub-processor is provided not from the main processor but from the sub-processor of the other group, the number of ports of the main processor is not occupied in proportion to the number of sub-processors even in an electronic device having a large number of sub-processors.

[0023] <Example of procedure for writing a program to a sub-processor> Next, an example of the procedure for writing a program to each sub-processor in a configuration in which the main processor 70 and each sub-processor are connected as shown in Fig. 2 will be described. Fig. 3 and Fig. 4 are timing charts showing an example of the procedure for writing a program to each sub-processor shown in Fig. 2. As shown in Fig. 3, at time T0, the power supply to the image processing device 100 is turned on, the reset of the main processor 70 is released, and processing (normal operation) begins. When the power supply to each of the sub-processors G1-0 and G2-0 is turned on, the reset of the sub-processors in the other groups is released, and therefore each sub-processor begins normal operation.

[0024] When the main processor 70 starts writing a program to the sub-processor based on a user's instruction, the main processor 70 sends an instruction to the sub-processor G2-0 via SPI communication to reset all the sub-processors of the first group. In response to the instruction, the sub-processor G2-0 asserts a reset signal for the sub-processors G1-0 to G1-n (see time T1 shown in FIG. 3). The sub-processors G1-0 to G1-n of the first group are reset and stop processing. The sub-processors G2-0 to G2-m of the second group continue normal operation. After that, the main processor 70 asserts a BOOT signal (see time T2 shown in FIG. 3). The sub-processors G2-0 to G2-m of the second group continue normal operation even if the BOOT signal is asserted during normal operation. At the same time, the main processor 70 uses the connection switching circuit 80 to switch the connection destination of the UART from the peripheral device during normal operation to the sub-processor.

[0025] Next, the main processor 70 sends an instruction to the sub-processor G2-0 via SPI communication to release only the sub-processor G1-0 of the first group from reset. In response to the instruction, the sub-processor G2-0 negates the reset signal of the sub-processor G1-0 (see time T3 shown in FIG. 3). The sub-processor G1-0, which has been released from reset with the BOOT signal asserted, starts processing in program write mode. The other sub-processors of the first group are reset and do not perform any processing. The main processor 70 sends the program data to be written to the sub-processor G1-0 via UART. The sub-processor G1-0 receives the program data sent via UART and writes it to a specified memory area that stores the program it executes.

[0026] After writing the program to the sub-processor G1-0 is completed, the main processor 70 then sends an instruction to the sub-processor G2-0 via SPI communication to release only the sub-processor G1-1 of the first group from reset. In response to the instruction, the sub-processor G2-0 asserts the reset signal of the sub-processor G1-0 and negates the reset signal of G1-1 (see time T5 shown in FIG. 3). The sub-processor G1-1, which has been released from reset with the BOOT signal asserted, starts processing in program write mode. The other sub-processors of the first group are reset and do not perform any processing. The main processor 70 sends the program data to be written to the sub-processor G1-1 via UART. The sub-processor G1-1 receives the program data sent via UART and writes it to a specified memory area that stores the program it executes.

[0027] In this manner, the main processor 70 sequentially sets the sub-processors G1-0 to G1-n of the first group to the program write mode and writes the program. After writing the program to the sub-processor G1-n is completed, the main processor 70 then sends an instruction to the sub-processor G2-0 via SPI communication to reset all the sub-processors of the first group. In response to the instruction, the sub-processor G2-0 asserts the reset signal of the sub-processors G1-0 to G1-n (see time T6 shown in FIG. 3). Next, the main processor 70 negates the BOOT signal (see time T7 shown in FIG. 3), and thereafter negates the reset signal of all the sub-processors G1-0 to G1-n of the first group (see time T8 shown in FIG. 3). The sub-processors G1-0 to G1-n of the first group start processing in the normal operation mode.

[0028] Next, the main processor 70 sends an instruction to the sub-processor G1-0 via SPI communication to reset all sub-processors in the second group. In response to the instruction, the sub-processor G1-0 asserts a reset signal for the sub-processors G2-0 to G1-m (see time T11 shown in FIG. 4). The sub-processors G2-0 to G1-m in the second group enter a reset state and stop processing. The sub-processors G1-0 to G1-n in the first group continue normal operation. Thereafter, the main processor 70 asserts a BOOT signal (see time T12 shown in FIG. 4). The sub-processors G1-0 to G1-n in the first group continue normal operation even if the BOOT signal is asserted during normal operation.

[0029] Next, the main processor 70 sends an instruction to the sub-processor G1-0 via SPI communication to release only the sub-processor G2-0 of the second group from reset. In response to the instruction, the sub-processor G1-0 negates the reset signal of the sub-processor G2-0 (see time T13 shown in FIG. 4). The sub-processor G2-0, which has been released from reset with the BOOT signal asserted, starts processing in program write mode. The other sub-processors of the second group are reset and do not perform any processing. The main processor 70 sends the program data to be written to the sub-processor G2-0 via UART. The sub-processor G2-0 receives the program data sent via UART and writes it to a specified memory area that stores the program it executes.

[0030] After writing the program to the sub-processor G2-0 is completed, the main processor 70 then sends an instruction to the sub-processor G1-0 via SPI communication to release only the sub-processor G2-1 of the second group from reset. In response to the instruction, the sub-processor G1-0 asserts the reset signal of the sub-processor G2-0 and negates the reset signal of G2-1 (see time T15 shown in FIG. 4). The sub-processor G2-1, which has been released from reset with the BOOT signal asserted, starts processing in program write mode. The other sub-processors of the second group are reset and do not perform any processing. The main processor 70 sends the program data to be written to the sub-processor G2-1 via UART. The sub-processor G2-1 receives the program data sent via UART and writes it to a specified memory area that stores the program it executes.

[0031] In this manner, the main processor 70 sequentially switches the sub-processors G2-0 to G2-m of the second group to the program write mode and writes the program. After writing the program to the sub-processor G2-m is completed, the main processor 70 then sends an instruction to the sub-processor G1-0 via SPI communication to reset all the sub-processors of the second group. In response to the instruction, the sub-processor G1-0 asserts the reset signal of the sub-processors G2-0 to G2-m (see time T16 shown in FIG. 4). Then, the main processor 70 negates the BOOT signal (see time T17 shown in FIG. 4). At the same time, the main processor 70 uses the connection switching circuit 80 to switch the connection destination of the UART from the sub-processor to the peripheral device during normal operation. After that, it negates the reset signal of all the sub-processors G2-0 to G2-m of the second group (see time T18 shown in FIG. 3). The sub-processors G2-0 to G2-m of the first group start processing in the normal operation mode. The above is an example of the procedure for writing a program to a sub-processor.

[0032] (Embodiment 2) As shown in Fig. 2, it is essential that the reset signal of each sub-processor is connected to a sub-processor of a different group. However, it is not essential that all processors in the same group are connected to one sub-processor of the other group. The processors may be divided and connected to multiple sub-processors of the other group. The allocation of the reset signal of each sub-processor of the other group may be determined according to the situation such as the position where each sub-processor is placed and the number of ports that can be assigned to the reset signal of the sub-processor of the other group.

[0033] (Embodiment 3) 2, the number of groups is not limited to two. However, since an increase in the number of groups increases the number of selection signals of the main processor 70, the number of groups is preferably two from the viewpoint of reducing the number of ports required for the main processor 70. The number of groups may be three or more depending on the circumstances such as the position where each sub-processor is arranged and the number of ports that can be assigned to the reset signals of the sub-processors of other groups.

[0034] It should be understood that the present disclosure also includes any combination of the above-described aspects. In addition to the above-described embodiment, various modifications of the present disclosure are possible. These modifications should not be interpreted as not belonging to the scope of the present disclosure. The invention according to the present disclosure should include all modifications that are equivalent to the scope of the claims and that belong to the scope of the present disclosure. [Explanation of symbols]

[0035] 10: control unit, 11: operation control unit, 12: file control unit, 13: job management unit, 14: job execution unit, 15: image processing unit, 16: input processing unit, 17: output image generation unit, 20: storage device, 22: communication unit, 30: operation unit, 40: scanner unit, 50: engine unit, 70: main processor, 80: connection switching circuit, 100: image processing device G1-0, G1-1 to G1-n, G2-0, G2-1 to G2-m: Sub-processors

Claims

1. An electronic device in which a plurality of sub-processors and a main processor are communicatively connected, The main processor a group selection port that outputs a selection signal for selecting each sub-processor on a group basis; a program output port for transmitting program data to each sub-processor; Each Sub-Processor shall: a selection receiving port for receiving the selection signal; a program receiving port for receiving the program data; a start receiving port for receiving a program write mode start instruction; At least one sub-processor in each group has one or more start sending ports for sending the start instruction to any of the sub-processors in the other groups; The main processor uses the group selection port to select a target group for program writing, sends an instruction to one of the sub-processors in the other groups to individually start the program writing mode of one or more sub-processors belonging to the target group, and sends program data to the sub-processor that has started the program writing mode using the program send port.

2. The main processor communicating with each sub-processor using a common communication port; 2. An electronic device as claimed in claim 1, wherein the group select port of each sub-processor is driven by a group select line common to each sub-processor of the same group.

3. Each sub-processor has a reset port for receiving a reset signal, and a boot signal port for starting processing in the program write mode if the reset signal is asserted when the reset is released; the main processor drives the boot signal ports of the sub-processors with a common boot signal line; 2. The electronic device according to claim 1, wherein any one of the sub-processors of the other group has a reset output port as the start sending port for sending an individual reset signal as the start instruction to one or more sub-processors of the target group.

4. a connection switching circuit for switching a connection destination of the program sending port between each sub-processor and another communicable device; 4. The electronic device according to claim 3, wherein said connection switching circuit connects said program output port to each sub-processor when said boot signal line is in an asserted state, and connects said program output port to other devices when said boot signal line is in a negated state.

5. A main processor connected to a plurality of sub-processors for communication therewith, selecting a target group for program writing using a group selection port for selecting each sub-processor on a group basis; sending an instruction to any of the sub-processors of the other groups via communication to individually start a program writing mode of one or more sub-processors belonging to the target group; sending program data to the sub-processor that has initiated the program write mode using a program send port; 1. A method for programming an electronic device comprising:

6. the main processor selects a first group, instructs any one of the sub-processors in the other groups to start a program write mode for a first sub-processor in that group, sends program data for the first sub-processor that has started the program write mode, and when program writing for the first sub-processor is completed, operates the first sub-processor in a normal mode and instructs any one of the sub-processors in the other groups to start a program write mode for a second sub-processor, thereby sequentially writing programs for each sub-processor in the first group; 6. A program writing method as claimed in claim 5, further comprising the steps of: when writing of a program to each sub-processor in a first group is completed, selecting a second group and sequentially writing programs to each sub-processor in that group, thereby writing programs to each sub-processor in each group.

Images