Semiconductor device

Abstract

To provide an etching method capable of relatively easily obtaining a desired structure for an etching target structure including a plurality of mixed crystal layers.SOLUTION: In the present disclosure, a patterned resist is obtained on an aluminum alloy layer 2 of a laminated structure 3. Using the patterned resist as a mask, a second etching process is performed to selectively etch only the aluminum alloy layer 2 using an Al etchant F2. As a result, a patterned structure 13 is obtained having an etched region R2 that penetrates a part of the aluminum alloy layer 2 and exposes the surface of a chromium alloy layer 1.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to an etching method for an etching target structure having a plurality of mixed crystal layers, and a semiconductor device having a plurality of mixed crystal layers. [Background technology]

[0002] As one type of conventional field effect transistor, for example, a high electron mobility transistor (HEMT) using a compound semiconductor material has been known. A HEMT uses a high-mobility two-dimensional electron gas (2DEG) resulting from a heterojunction as a channel. Patent Document 1 discloses an example of a HEMT. The HEMT disclosed in Patent Document 1 includes an AlGaN layer (electron supply layer) provided on an electron transit layer, an AlN layer (insulating layer) provided on the AlGaN layer, and a gate electrode provided on the AlN layer via a nitride semiconductor layer.

[0003] In addition to the above-mentioned high electron mobility transistor (HEMT), selective etching to form circuit patterns is very important for all devices such as CMOS transistors, PN diodes, JFETs (Junction Field Effect Transistors), and TFTs (Thin Film Transistors).

[0004] There have been many attempts to develop power devices using wide band gap semiconductor materials that can be used to build high-voltage, highly efficient devices that are not possible with silicon (Si). Research and development of power devices using such materials, silicon carbide (SiC) and gallium nitride (GaN), has been particularly active in recent years. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2009-71061 A Summary of the Invention [Problem to be solved by the invention]

[0006] In addition to the above silicon carbide (SiC) and gallium nitride (GaN), for example, in switching (power conversion) devices, GaN is being developed that can withstand a wider range of voltages than conventional materials including SiC and GaN. 2 O 3 Gallium oxide-based power devices using this material are attracting attention. Gallium oxide-based power devices are expected to be compatible with a wide range of temperatures and voltages, including high temperatures and high voltages, and to be low cost, highly efficient, and highly reliable. 2 O 3 There are a wide range of possible application fields for power devices based on this system.

[0007] However, when considering the configuration of gallium oxide-based power devices, it is necessary to explore combinations of mixed crystal semiconductor layers (mixed crystal layers) that can form practical active layers. In addition, to configure power devices, it is necessary to develop technology that allows selective etching of each mixed crystal layer.

[0008] In general, when considering device formation, the design of the active layer is very important. In the above-mentioned HEMT, CMOS, PN diode, etc., active layers are sometimes stacked to achieve high performance devices, and the technology of selectively etching each layer to form a pattern plays a very important role.

[0009] There are two types of etching technology: dry etching and wet etching. Dry etching has high directionality and produces a high aspect ratio in the etching pattern, but its mechanism raises concerns about damage to thin films and consumes a large amount of energy during operation.

[0010] On the one hand, wet etching has a worse aspect ratio of etching than dry etching, but it is very simple and has a low operation cost. Moreover, compared with dry etching, it has a high etching speed and excellent etching selectivity.

[0011] Due to these advantages, wet etching is frequently used, for example, when forming a display.

[0012] An object of the present disclosure is to provide an etching method that can solve the above problems and relatively easily obtain a desired structure for an etching target structure including a plurality of mixed crystal layers.

Means for Solving the Problem

[0013] A first aspect of the etching method of the present disclosure includes: (a) obtaining an etching target structure including a first and a second mixed crystal layer; and (b) performing at least one of a first etching process of selectively etching the first mixed crystal layer using a first etchant on the etching target structure and a second etching process of selectively etching the second mixed crystal layer using a second etchant on the etching target structure. The first mixed crystal layer contains (M1 x Ga 1-x ) 2 O 3 (0 < x ≤ 1), the second mixed crystal layer contains (M2 y Ga 1-y ) 2 O 3 (0 < y ≤ 1), M1 = Cr, M2 is one of {Al, In, Fe}, the first mixed crystal layer has crystallinity when {x ≠ 1}, and the second mixed crystal layer has crystallinity when {y ≠ 1}.

[0014] A second aspect of the etching method of the present disclosure includes: (a) obtaining an etching target structure including a first and a second mixed crystal layer and a silicon oxide layer; and (b) performing at least one of a first etching process of selectively etching the first mixed crystal layer using a first etchant on the etching target structure, a second etching process of selectively etching the second mixed crystal layer using a second etchant on the etching target structure, and a third etching process of selectively etching the silicon oxide layer using a third etchant on the etching target structure. The first mixed crystal layer contains (M1 x Ga 1-x ) 2 O 3 (0 < x ≦ 1), the second mixed crystal layer contains (M2 y Ga 1-y ) 2 O 3 (0 < y ≦ 1), M1 = Cr, M2 is one of {Al, In, Fe}, the first mixed crystal layer has crystallinity when {x ≠ 1}, and the second mixed crystal layer has crystallinity when {y ≠ 1}.

Advantages of the Invention

[0015] In the first aspect of the etching method of the present disclosure, by performing step (b), the first mixed crystal layer or the second mixed crystal layer can be selectively etched from the etching target structure, so that a desired structure can be accurately obtained from the etching target structure by a relatively simple process.

[0016] In the second aspect of the etching method of the present disclosure, by performing step (b), the first mixed crystal layer, the second mixed crystal layer, or the silicon oxide film can be selectively etched from the etching target structure, so that a desired structure can be accurately obtained from the etching target structure by a relatively simple process.

[0017] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.

Brief Description of the Drawings

[0018] [Figure 1] 1A to 1C are cross-sectional views showing a processing procedure of a first basic etching method in the first embodiment. [Diagram 2] 1A to 1C are cross-sectional views showing a processing procedure of a first basic etching method. [Diagram 3] 5A to 5C are cross-sectional views showing a processing procedure of a second basic etching method in the first embodiment. [Figure 4] 1A to 1C are cross-sectional views showing a processing procedure of a second basic etching method. [Diagram 5] 10A to 10C are cross-sectional views showing a processing procedure of a third basic etching method in the second embodiment. [Figure 6] 10A to 10C are cross-sectional views showing a processing procedure of a third basic etching method. [Figure 7] 10A to 10C are cross-sectional views showing a processing procedure of a third basic etching method. [Figure 8] 11A to 11C are cross-sectional views showing a processing procedure of a fourth basic etching method in the second embodiment. [Figure 9] 10A to 10C are cross-sectional views showing a processing procedure of a fourth basic etching method. [Figure 10] 10A to 10C are cross-sectional views showing a processing procedure of a fourth basic etching method. [Figure 11] FIG. 2 is an explanatory diagram showing the characteristics of an etching agent in a table format. [Figure 12] FIG. 2 is an explanatory diagram showing, in tabular form, the composition of an Al etching agent and a Cr etching agent. [Figure 13] FIG. 11 is an explanatory diagram showing details of a third etching characteristic by a silicon oxide etchant in a graph form. [Figure 14] FIG. 11 is an explanatory diagram showing details of a third etching characteristic by a silicon oxide etchant in a graph form. [Figure 15] FIG. 11 is an explanatory diagram showing in a graph form the details of a second etching characteristic by an etching agent for Al. [Figure 16] FIG. 2 is an explanatory diagram showing in a graph form the details of a first etching characteristic by an etching agent for Cr. [Figure 17] 11A to 11C are cross-sectional views showing basic processing steps for obtaining a patterned structure in an etching method according to a third embodiment. [Figure 18] 1A to 1C are cross-sectional views showing basic processing steps. [Figure 19] 1A to 1C are cross-sectional views showing basic processing steps. [Figure 20] FIG. 1 is an explanatory diagram showing an outline of a first thin film manufacturing technique for obtaining a chromium mixed crystal layer. [Figure 21] FIG. 2 is an explanatory diagram showing an outline of a second thin film manufacturing technique for obtaining an aluminum mixed crystal layer. [Figure 22] FIG. 11 is a cross-sectional view showing a mesa etching process step in the third embodiment. [Diagram 23] 1A-1C are cross-sectional views showing a mesa etching process. [Figure 24] 1A-1C are cross-sectional views showing a mesa etching process. [Diagram 25] 1A-1C are cross-sectional views showing a mesa etching process. [Figure 26] 1A-1C are cross-sectional views showing a mesa etching process. [Figure 27] 1A-1C are cross-sectional views showing a mesa etching process. [Figure 28] 1A-1C are cross-sectional views showing a mesa etching process. [Figure 29] FIG. 13 is a cross-sectional view showing a second mask processing step in the third embodiment. [Diagram 30] FIG. 11 is a cross-sectional view showing a second mask processing step. [Diagram 31] FIG. 11 is a cross-sectional view showing a second mask processing step. [Diagram 32] FIG. 11 is a cross-sectional view showing a second mask processing step. [Diagram 33] FIG. 11 is a cross-sectional view showing a second mask processing step. [Diagram 34] FIG. 11 is a cross-sectional view showing a second mask processing step. [Diagram 35] FIG. 13 is a cross-sectional view showing a third mask processing step in the third embodiment. [Diagram 36]FIG. 11 is a cross-sectional view showing a third mask processing step. [Figure 37] FIG. 11 is a cross-sectional view showing a third mask processing step. [Figure 38] FIG. 11 is a cross-sectional view showing a third mask processing step. [Figure 39] FIG. 11 is a cross-sectional view showing a third mask processing step. [Diagram 40] FIG. 2 is a plan view showing an example of a planar structure of an intermediate patterning structure. [Diagram 41] FIG. 11 is a cross-sectional view showing a gate formation step in the third embodiment. [Diagram 42] 11A to 11C are cross-sectional views showing a gate forming step. [Diagram 43] 11A to 11C are cross-sectional views showing a gate forming step. [Diagram 44] 11A to 11C are cross-sectional views showing a gate forming step. [Diagram 45] 11A to 11C are cross-sectional views showing a gate forming step. [Diagram 46] 11A to 11C are cross-sectional views showing a gate forming step. [Figure 47] 1A to 1C are cross-sectional views showing a method for forming an indium mixed crystal layer using a buffer layer. [Figure 48] 1A to 1C are cross-sectional views showing a method for forming an indium mixed crystal layer using a buffer layer. [Figure 49] 3A to 3C are cross-sectional views showing an outline of a manufacturing process for an iron mixed crystal layer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] <Embodiment 1> The basic configuration and method of the present disclosure will be described.

[0020] First, gallium oxide crystals are polymorphic, and there are five types: α, β, γ, δ, and ε. The most stable material is the monoclinic β phase, but in this embodiment, the α phase is used as a representative. The reason is as follows.

[0021] (1) α-Ga 2 O 3is one of the general-purpose substrates (quartz, Si, sapphire) 2 O 3 Since it has the same crystal structure as silicon, epitaxial growth is possible, which promotes high-quality crystal growth. (2) There are many successful cases of producing mixed crystal films with corundum structure crystals. (3) Thin films with a corundum structure can be formed into conductive films using elements such as V (vanadium) and In (indium), but they can also be used as insulators or semiconductors, as seen in elements such as Ga (gallium) and Al (aluminum), allowing for a wide range of options. (4) It has been suggested that P-type and other types may also be possible. For the reasons mentioned above, the α phase will be described as a representative example, but the same is also applicable to other phases.

[0022] 1 and 2 are cross-sectional views showing a process of a first basic etching method according to a first embodiment of the present disclosure.

[0023] 1, the structure to be etched is a laminated structure 3 consisting of a chromium alloy layer 1 and an aluminum alloy layer 2 provided on the chromium alloy layer 1. The chromium alloy layer 1 corresponds to the "first alloy layer" and the aluminum alloy layer 2 corresponds to the "second alloy layer."

[0024] The chromium alloy layer 1 contains components satisfying the following chemical formula (1), and the aluminum alloy layer 2 contains components satisfying the following chemical formula (2). Furthermore, the chromium alloy layer 1 has crystallinity when {x≠1} in the chemical formula (1), and the aluminum alloy layer 2 has crystallinity when {y≠1} in the chemical formula (2).

[0025] Chromium mixed crystal layer 1...α-(Cr x Ga 1-x ) 2 O 3 (However, 0 <x≦1)…(1) Aluminum mixed crystal layer 2...α-(Al y Ga 1-y ) 2 O 3(However, 0 <y≦1)…(2)

[0026] 1, a chromium alloy crystal layer 1 and an aluminum alloy crystal layer 2 are laminated in this order from the bottom up to produce a laminated structure 3. That is, the chromium alloy crystal layer 1 is formed on a predetermined substrate (not shown), and then the aluminum alloy crystal layer 2 is formed on the chromium alloy crystal layer 1 to obtain the laminated structure 3. This laminated structure 3 is the structure to be etched.

[0027] Next, a photoresist (not shown) is formed on the aluminum mixed crystal layer 2 of the laminated structure 3 shown in FIG. 1, and then a patterned resist (not shown) is obtained by exposure treatment.

[0028] Then, using the patterned resist as a mask, a second etching process is performed using an Al etchant F2, which will be described later in detail, to selectively etch only the aluminum mixed crystal layer 2. The Al etchant F2 corresponds to the "second etchant", and the etching process using the Al etchant F2 is the "second etching process".

[0029] 2, a patterned structure 13 can be obtained having an etched region R2 that penetrates a part of the aluminum alloy layer 2 and exposes the surface of the chromium alloy layer 1. The patterned structure 13 includes a combination of the remaining laminated structure 3 other than the etched region R2 and a single layer structure consisting of only the chromium alloy layer 1 in the etched region R2.

[0030] 2 includes a laminated structure 3 made of a chromium alloy crystal layer 1 and an aluminum alloy crystal layer 2, and a single-layer structure in which only the lower chromium alloy crystal layer 1 is provided among the chromium alloy crystal layer 1 and the aluminum alloy crystal layer 2. In the patterned structure 13, the chromium alloy crystal layer 1 and the aluminum alloy crystal layer 2 are provided at different formation heights.

[0031] As a result, the laminated structure 3 remaining in the patterned structure 13 becomes an active layer (channel layer) that is the basis of the semiconductor device. For example, the chromium alloy layer 1 and the aluminum alloy layer 2 in the laminated structure 3 may become the basis of an electron generating layer and an electron passing layer of a HEMT.

[0032] 3 and 4 are cross-sectional views showing a process procedure of the second basic etching method according to the first embodiment of the present disclosure.

[0033] As shown in Fig. 3, a laminated structure 3B consisting of an aluminum alloy layer 2 and a chromium alloy layer 1 provided on the aluminum alloy layer 2 is an etching target structure. In the following, the description will be centered on the features of the second basic etching method, omitting the description of the same contents as those in the first basic etching method shown in Figs. 1 and 2 as appropriate.

[0034] 3, an aluminum alloy crystal layer 2 and a chromium alloy crystal layer 1 are laminated in this order from the bottom side to produce a laminated structure 3B. That is, the aluminum alloy crystal layer 2 is formed on a predetermined substrate (not shown), and then the chromium alloy crystal layer 1 is formed on the aluminum alloy crystal layer 2 to obtain the laminated structure 3B.

[0035] Next, a photoresist (not shown) is formed on the chromium mixed crystal layer 1 of the laminated structure 3B shown in FIG. 3, and then a resist (not shown) patterned by exposure processing is provided.

[0036] 4, a first etching process is performed using the patterned resist as a mask to selectively etch only the chromium mixed crystal layer 1 with a Cr etchant F1, which will be described in detail later. The Cr etchant F1 corresponds to the "first etchant," and the etching process using the Cr etchant F1 is the "first etching process."

[0037] 4, a patterned structure 13B can be obtained having an etched region R1 that penetrates a part of the chromium alloy layer 1 and exposes the surface of the aluminum alloy layer 2. The patterned structure 13B includes a combination of the remaining laminated structure 3B other than the etched region R1 and a single layer structure consisting of only the aluminum alloy layer 2 in the etched region R1.

[0038] 4 includes a laminated structure 3B made of an aluminum alloy layer 2 and a chromium alloy layer 1, and a single-layer structure in which only the lower aluminum alloy layer 2 is provided among the aluminum alloy layer 2 and the chromium alloy layer 1. In the patterned structure 13B, the aluminum alloy layer 2 and the chromium alloy layer 1 are provided at different formation heights.

[0039] As a result, the laminated structure 3B remaining on the patterned structure 13B becomes the active layer (channel layer) that is the basis of the semiconductor device.

[0040] In each of the above-mentioned first and second basic etching methods, it is preferable to use a mist CVD apparatus (not shown) as a thin film manufacturing apparatus for forming the chromium mixed crystal layer 1 and the aluminum mixed crystal layer 2, respectively.

[0041] A mist CVD apparatus generally includes a mist generating section that generates a plurality of raw material mists by atomizing (misting) a plurality of raw material solutions contained therein, a carrier gas inlet section into which a carrier gas for transporting the raw material mists is introduced, and a mist outlet section from which a mist flow containing the raw material mists in the carrier gas is delivered. Note that the laminated structure 3 can also be obtained by the HVPE (Hydride Vapor Phase Epitaxy) method in addition to the CVD method.

[0042] The patterned structure 13 (13B) obtained by the above-mentioned first (second) basic etching method has the following features.

[0043] (1) The multilayer structure 3 (3B) includes a chromium alloy layer 1 and an aluminum alloy layer 2, and the chromium alloy layer 1 and the aluminum alloy layer 2 are formed to different heights.

[0044] (2) The final patterned structure 13 (13B) is a laminated structure 3 (3B) made of the chromium mixed crystal layer 1 and the aluminum mixed crystal layer 2.

[0045] (3) Of the chromium mixed crystal layer 1 and the aluminum mixed crystal layer 2, a single-layer structure exists in which only the lower mixed crystal layer is formed.

[0046] The patterned structures 13 and 13B obtained by the first and second basic etching methods of the first embodiment can also be formed as intermediate layers of a semiconductor device, separate from the substrate, if necessary.

[0047] In addition, a predetermined thin film will be formed or a metal layer or the like will be connected to the etching region R2 shown in FIG. 2 and the etching region R1 shown in FIG.

[0048] In the first basic etching method according to the first embodiment of the present disclosure, by performing a second etching process using an etching agent F2 for Al, the aluminum alloy layer 2 can be selectively etched from the stacked structure 3, which is the structure to be etched, by using the chromium alloy layer 1 as an etching stopper.

[0049] Therefore, the desired patterned structure 13 can be obtained from the laminated structure 3 with high accuracy by the relatively simple first basic etching method.

[0050] Similarly, in the second basic etching method according to the first embodiment of the present disclosure, a first etching process is performed using an etching agent F1 for Cr, whereby the chromium alloy layer 1 can be selectively etched from the stacked structure 3B, which is the structure to be etched, using the aluminum alloy layer 2 as an etching stopper.

[0051] Therefore, the desired patterned structure 13B can be obtained with high accuracy from the laminated structure 3B by the relatively simple second basic etching method.

[0052] Moreover, the semiconductor device having the patterning structure 13 shown in FIG. 2 can be manufactured as follows.

[0053] By carrying out the first basic etching method using the etching agent F2 for Al with the laminated structure 3 as the etching target structure, the aluminum mixed crystal layer 2 which is the upper mixed crystal layer in the laminated structure 3 can be selectively removed by using the chromium mixed crystal layer 1 which is the lower mixed crystal layer in the laminated structure 3 as an etching stopper.

[0054] Therefore, by performing the relatively simple first basic etching method, the patterned structure 13 can be obtained with high accuracy.

[0055] Similarly, the semiconductor device having the patterning structure 13B shown in FIG. 4 can be manufactured with high accuracy by a relatively simple process by carrying out the second basic etching method using the Cr etching agent F1.

[0056] In this way, the combination of Al and Cr was discovered as a material that can be mixed with gallium oxide to form the active layer that is the basis of a semiconductor device.

[0057] <Embodiment 2> 5 to 7 are cross-sectional views showing a process procedure of the third basic etching method according to the second embodiment of the present disclosure.

[0058] 5, a layered structure 4 consisting of a chromium alloy layer 1, an aluminum alloy layer 2 provided on the chromium alloy layer 1, and a silicon oxide layer 6 provided on the aluminum alloy layer 2 is a structure to be etched. The chromium alloy layer 1 corresponds to a "first alloy layer" and the aluminum alloy layer 2 corresponds to a "second alloy layer."

[0059] Hereinafter, the description of the same contents as those of the first embodiment shown in Figs. 1 to 4 will be omitted as appropriate, and the features of the second embodiment will be mainly described with reference to Figs. 5 to 7.

[0060] 5, a chromium alloy crystal layer 1, an aluminum alloy crystal layer 2, and a silicon oxide layer 6 are laminated in this order from the bottom up to produce a laminated structure 4. That is, the chromium alloy crystal layer 1 is formed on a predetermined substrate (not shown), the aluminum alloy crystal layer 2 is then formed on the chromium alloy crystal layer 1, and the silicon oxide layer 6 is then formed on the aluminum alloy crystal layer 2, thereby obtaining the laminated structure 4.

[0061] Next, a photoresist (first resist) (not shown) is formed on the silicon oxide layer 6 of the laminated structure 4 shown in FIG. 5, and then the first resist (not shown) is patterned by exposure processing.

[0062] Then, using the patterned first resist as a mask, a third etching process is performed to selectively etch only the silicon oxide layer 6 using a silicon oxide etchant F3, which will be described later in detail. The silicon oxide etchant F3 corresponds to the "third etchant", and the etching process using the silicon oxide etchant F3 is the "third etching process".

[0063] As a result, as shown in FIG. 6, an etched region R6 is obtained in which the silicon oxide layer 6 is penetrated and the surface of the aluminum mixed crystal layer 2 is exposed.

[0064] Next, a photoresist (second resist) (not shown) is formed on the aluminum mixed crystal layer 2 in the etching region R6 shown in FIG. 6, and then the second resist (not shown) is patterned by exposure processing.

[0065] Then, using the patterned second resist as a mask, an etching process is performed using an Al etchant F2 to selectively etch only the aluminum mixed crystal layer 2. The Al etchant F2 corresponds to the "second etchant", and the etching process using the Al etchant F2 is the "second etching process".

[0066] As a result, as shown in FIG. 7, a patterned structure 14 can be obtained in the etching region R6, which has an etching region R2 that penetrates a part of the aluminum mixed crystal layer 2 and exposes the surface of the chromium mixed crystal layer 1.

[0067] The patterned structure 14 includes a triple-layer structure of the remaining chromium mixed crystal layer 1, aluminum mixed crystal layer 2 and silicon oxide layer 6 outside the etched region R6, a double-layer structure of the remaining chromium mixed crystal layer 1 and aluminum mixed crystal layer 2 outside the etched region R2 within the etched region R6, and a single layer structure consisting of only the chromium mixed crystal layer 1 in the etched region R2.

[0068] That is, the patterning structure 14 shown in FIG. 7 includes a laminated structure 4 (triple laminated structure) consisting of a chromium mixed crystal layer 1, an aluminum mixed crystal layer 2 and a silicon oxide layer 6, a double laminated structure consisting of two layers excluding the silicon oxide layer 6 which is the uppermost layer of the laminated structure 4, and a single layer structure in which only the chromium mixed crystal layer 1 which is the lowermost layer of the laminated structure 4 is provided.

[0069] The chromium mixed crystal layer 1, the aluminum mixed crystal layer 2 and the silicon oxide layer 6 are formed at different heights.

[0070] As a result, the double laminated structure of the chromium mixed crystal layer 1 and the aluminum mixed crystal layer 2 remaining in the patterned structure 14 becomes the active layer (channel layer) that is the basis of the semiconductor device.

[0071] 8 to 10 are cross-sectional views showing a process procedure of the fourth basic etching method according to the second embodiment of the present disclosure.

[0072] As shown in Fig. 8, a laminated structure 4B consisting of an aluminum alloy layer 2, a chromium alloy layer 1 provided on the aluminum alloy layer 2, and a silicon oxide layer 6 provided on the chromium alloy layer 1 is an etching target structure. Below, the description of the same contents as those in the third basic etching method shown in Figs. 5 to 7 will be omitted as appropriate, and the features of the fourth basic etching method will be mainly described with reference to Figs. 8 to 10.

[0073] 8, the laminated structure 4B is manufactured by laminating the aluminum alloy crystal layer 2, the chromium alloy crystal layer 1, and the silicon oxide layer 6 in this order from the bottom. That is, the aluminum alloy crystal layer 2 is formed on a predetermined substrate (not shown), the chromium alloy crystal layer 1 is then formed on the aluminum alloy crystal layer 2, and the silicon oxide layer 6 is then formed on the chromium alloy crystal layer 1, thereby obtaining the laminated structure 4B.

[0074] Next, a photoresist (first resist) (not shown) is formed on the silicon oxide layer 6 of the laminated structure 4B shown in FIG. 8, and then the first resist (not shown) is patterned by exposure processing.

[0075] Then, using the patterned first resist as a mask, a third etching process is carried out to selectively etch only the silicon oxide layer 6 using a silicon oxide etchant F3, which will be described later in detail.

[0076] As a result, as shown in FIG. 9, an etched region R6 is obtained in which the silicon oxide layer 6 is penetrated and the surface of the chromium mixed crystal layer 1 is exposed.

[0077] Next, a photoresist (second resist) (not shown) is formed on the chromium mixed crystal layer 1 in the etching region R6 shown in FIG. 9, and then the second resist (not shown) is patterned by exposure processing.

[0078] Then, using the patterned second resist as a mask, a first etching process is performed to selectively etch only the chromium mixed crystal layer 1 using a Cr etchant F1.

[0079] As a result, as shown in FIG. 10, a patterned structure 14B can be obtained in the etching region R6, which has an etching region R1 that penetrates a part of the chromium mixed crystal layer 1 and exposes the surface of the aluminum mixed crystal layer 2.

[0080] The patterning structure 14B includes a triple-layer structure of the remaining aluminum alloy layer 2, the chromium alloy layer 1 and the silicon oxide layer 6 outside the etched region R6, a double-layer structure of the aluminum alloy layer 2 and the chromium alloy layer 1 outside the etched region R1 within the etched region R6, and a single-layer structure consisting of only the aluminum alloy layer 2 in the etched region R1.

[0081] That is, the patterning structure 14B shown in FIG. 10 includes a laminated structure 4B (triple laminated structure) consisting of an aluminum alloy layer 2, a chromium alloy layer 1 and a silicon oxide layer 6, a double laminated structure consisting of two layers excluding the silicon oxide layer 6 which is the top layer of the laminated structure 4B, and a single layer structure in which only the aluminum alloy layer 2 which is the bottom layer of the laminated structure 4B is provided.

[0082] The aluminum mixed crystal layer 2, the chromium mixed crystal layer 1 and the silicon oxide layer 6 are formed at different heights.

[0083] In the third basic etching method according to the second embodiment of the present disclosure, by performing a third etching process using a silicon oxide etchant F3, the silicon oxide layer 6 can be selectively etched from the stacked structure 4, which is the etching target structure, by using the aluminum alloy layer 2 as an etching stopper.

[0084] In the third basic etching method according to the first embodiment of the present disclosure, after the third etching process, the second etching process using the Al etching agent F2 is performed, whereby the aluminum alloy layer 2 can be selectively etched from the structure shown in FIG. 6 with the chromium alloy layer 1 serving as an etching stopper.

[0085] Therefore, the desired patterned structure 14 can be obtained with high accuracy from the laminated structure 4 by the third basic etching method consisting of relatively simple processing steps shown in FIGS.

[0086] Similarly, in the fourth basic etching method according to the second embodiment of the present disclosure, by performing a third etching process using the silicon oxide etchant F3, the silicon oxide layer 6 can be selectively etched from the stacked structure 4B, which is the etching target structure, by using the chromium mixed crystal layer 1 as an etching stopper.

[0087] In the fourth basic etching method of the present disclosure, after the third etching process, the first etching process using the Cr etching agent F1 is performed, whereby the chromium alloy layer 1 can be selectively etched from the structure shown in FIG. 9 with the aluminum alloy layer 2 serving as an etching stopper.

[0088] Therefore, the desired patterned structure 14B can be obtained with high accuracy from the laminated structure 4B by the fourth basic etching method consisting of relatively simple processing steps shown in FIGS.

[0089] Moreover, a semiconductor device having the patterning structure 14 shown in FIG. 7 can be manufactured by the third basic etching method consisting of the relatively simple process steps shown in FIGS.

[0090] Therefore, a semiconductor device having the patterning structure 14 shown in FIG. 7 can be obtained relatively easily with high accuracy.

[0091] Similarly, a semiconductor device having a patterning structure 14B shown in FIG. 10 can be manufactured by the third basic etching method consisting of the relatively simple process steps shown in FIGS.

[0092] Therefore, a semiconductor device having the patterning structure 14B shown in FIG. 10 can be obtained relatively easily with high accuracy.

[0093] In this way, the combination of Al and Cr was discovered as a material that can be mixed with gallium oxide to form the active layer that is the basis of a semiconductor device.

[0094] <Details of etching agent> 11 is an explanatory diagram showing the characteristics of an etching agent in a table format. In the figure, cases where etching is practically possible are indicated with "O" and cases where etching is not possible are indicated with "X".

[0095] In FIG. 11, a buffered hydrofluoric acid (BHF) solution is shown as the silicon oxide etching agent F3. The BHF solution is a mixture of ultra-high purity hydrofluoric acid (HF) and ammonium fluoride solution (NH 4 F) is generally used. Of course, diluted HF or the like may be used as the BHF solution.

[0096] Also, an Al etching solution is shown as the Al etching agent F2, and a Cr etching solution is shown as the Cr etching agent F1. Also, both the Cr etching agent F1 and the Al etching agent F2 are shown to be used in a temperature environment of 135°C.

[0097] The silicon oxide layer 6 is made of SiO x is shown, the above-mentioned chemical formula (2) is shown as the constituent material of the aluminum mixed crystal layer 2, and the above-mentioned chemical formula (1) is shown as the chromium mixed crystal layer 1.

[0098] FIG. 12 is an explanatory diagram showing, in a table format, the composition of the Al etchant F2 and the Cr etchant F1.

[0099] As shown in FIG. 12, the Al etchant F2 is an Al etchant containing HNO 3 , C.H. 3 COOH, H 3 PO 4 and H 2 It contains O as a constituent.

[0100] Specifically, the Al etchant F2 is HNO 3 5-15% by weight, CH 3 COOH 5-15% by weight, H 3 PO 4 60-80% by weight, H 2 O is mixed at 10 to 20% by weight. At this time, the total of the above four weight percentages is adjusted to be 100%.

[0101] The second etching process using the Al etchant F2 is performed in a temperature environment of, for example, about 135°C.

[0102] As shown in FIG. 12, the Cr etching agent F1 is a Cr etching solution containing (NH 4 ) 2 Ce(NO 3 ) 6 , HClO 4 and H 2 It contains O as a constituent.

[0103] Specifically, (NH 4 ) 2 Ce(NO 3 ) 6 5-15% by weight, HClO 4 60-80% by weight, H 2 O is mixed at 10 to 20% by weight. At this time, the total of the above three weight percentages is adjusted to be 100%.

[0104] The first etching process using the Cr etchant F1 is performed in a temperature environment of, for example, about 135°C.

[0105] 11, the chromium mixed crystal layer 1 formed to satisfy the chemical formula (1) has a first etching characteristic in which the chromium mixed crystal layer 1 is etched only by the Cr etching agent F1 among the etching agents F1 to F3, and is not etched by the Al etching agent F2 and the silicon oxide etching agent F3. The above-mentioned first etching characteristic can be applied not only to the chromium mixed crystal layer 1 but also to Cr oxide.

[0106] Furthermore, the aluminum alloy layer 2 that satisfies the chemical formula (2) has a second etching characteristic that it is etched only by the Al etchant F2 among the etchants F1 to F3, and is not etched by the Cr etchant F1 and the silicon oxide etchant F3. The above-mentioned second etching characteristic can be applied not only to the aluminum alloy layer 2 but also to Al oxide.

[0107] In addition, SiO x The silicon oxide layer 6 made of SiO has a third etching characteristic that it is etched only by the silicon oxide etchant F3 among the etchants F1 to F3, and is not etched by the Al etchant F2 and the Cr etchant F1. x The specific composition is SiO 2 It becomes.

[0108] (Silicon oxide etching agent F3) 13 and 14 are explanatory diagrams showing details of the third etching characteristic by the silicon oxide etchant F3 in the form of graphs.

[0109] 13 and 14, the horizontal axis indicates the etching time (unit: second (s)), and the vertical axis indicates the etching depth (unit: nm). Also, the etching rate (nm / s) is appropriately indicated.

[0110] The leftmost Al in Figure 13 2 O 3 Refer to the graph of the system. As shown in the etching characteristic L31, Al 2 O 3 The sapphire substrate made of this material is not etched by the silicon oxide etchant F3.

[0111] Al 2 O 3corresponds to a layer in which the mixture ratio of Al and Ga in the AlGaO-based aluminum mixed crystal layer 2 having a configuration satisfying chemical formula (2) is (Al=100%, Ga=0%).

[0112] Next, let us refer to the CrGaO-based graph second from the left in Fig. 13. Regarding the mixture ratio of Cr and Ga in the CrGaO-based mixed crystal layer, the circle marks indicate a mixture ratio of (Cr=42%, Ga=58%), and the cross marks indicate a mixture ratio of (Cr=100%, Ga=0%).

[0113] As shown by the etching characteristic L32, the CrGaO-based chromium mixed crystal layer 1 satisfying the chemical formula (1) is not etched by the silicon oxide etchant F3.

[0114] Next, let us refer to the third graph from the left of Fig. 13 for the AlGaO system. Regarding the mixture ratio of Al and Ga in the second mixed crystal layer of the AlGaO system that satisfies chemical formula (2), the ▽ mark indicates a mixture ratio of (Al=0%, Ga=100%), and the ○ mark indicates a mixture ratio of (Al=18%, Ga=82%) (with Si added).

[0115] Al 2 O 3 As shown by the etching characteristics L31 and L33 in the graph of the AlGaO system and the graph of the AlGaO system, the aluminum mixed crystal layer 2 satisfying the above-mentioned chemical formula (2) is not etched by the silicon oxide etchant F3.

[0116] Next, let us refer to the fourth InGaO-based graph from the left in Fig. 13. Regarding the mixture ratio of In and Ga in the InGaO-based mixed crystal layer, the circle marks indicate a mixture ratio of (In=80%, Ga=20%), and the cross marks indicate a mixture ratio of (In=100%, Ga=0%).

[0117] As shown by the InGaO-based etching characteristics L34 and L35, the indium mixed crystal layer 2X containing a component satisfying the following chemical formula (3) is not etched by the silicon oxide etchant F3.

[0118] Indium mixed crystal layer 2X...α-(In y Ga 1-y ) 2 O 3 (However, 0 <y≦1)…(3)

[0119] Next, let us refer to the FeGaO-based graph, the fifth from the left in Fig. 13. With regard to the mixture ratio of Fe and Ga in the FeGaO-based mixed crystal layer, the ◇ symbol indicates a mixture ratio of (Fe=70%, Ga=30%; (film formation temperature 335°C)), the square symbol indicates a mixture ratio of (Fe=70%, Ga=30%; (film formation temperature 350°C)), and the △ symbol indicates a mixture ratio of (Fe=100%, Ga=0%; (film formation temperature 350°C)).

[0120] As shown by the FeGaO-based etching characteristic L36, the iron mixed crystal layer 2Y containing a component satisfying the following chemical formula (4) is not etched by the silicon oxide etchant F3.

[0121] Iron mixed crystal layer 2Y…α-(Fe y Ga 1-y ) 2 O 3 (However, 0 <y≦1)…(4)

[0122] Next, the SiO 2 Refer to the graph of the series. The details of the graph on the right side of FIG. 13 are shown in FIG. 14. The triangle marks indicate the first measured value, and the circle marks indicate the second measured value. Since the first etching of the silicon oxide layer 6 having the first thickness was completed in 10 seconds or less, the second etching of the silicon oxide layer 6 having the second thickness, which is thicker than the first thickness, was performed for confirmation, and the etching rate was measured.

[0123] SiO x As shown in the etching characteristics L37 of the system, SiO 2 SiO x The silicon oxide layer 6 made of the above-mentioned material is etched by the silicon oxide etchant F3.

[0124] 13 and 14, it is recognized that the third etching characteristic for the silicon oxide etchant F3 shown in FIG. 11 with respect to the chromium mixed crystal layer 1, the aluminum mixed crystal layer 2, and the silicon oxide layer 6 is correct.

[0125] Furthermore, it was recognized that the indium mixed crystal layer 2X and the iron mixed crystal layer 2Y, like the aluminum mixed crystal layer 2, were not etched by the silicon oxide etchant F3.

[0126] (Al etching agent F2) FIG. 15 is an explanatory diagram showing in a graph form the details of the second etching characteristic by the Al etchant F2.

[0127] 15, the horizontal axis indicates the etching time (unit: seconds (s)), and the vertical axis indicates the etching depth (unit: nm). Also, the etching rate (nm / s) is appropriately indicated.

[0128] Al at the left of Figure 15 2 O 3 See the graph of the system. Al 2 O 3 In the graph, the cross marks indicate sapphire substrates, and the circles indicate AlO x This shows the case of a thin film. x The thin film was formed by the mist CVD method.

[0129] Al 2 O 3 As shown by the etching characteristic L11 in the graph of the system, the sapphire substrate is not etched by the Al etchant F2.

[0130] On the other hand, Al 2 O 3 As shown in the etching characteristic L12 in the graph of the system, AlO x The film is etched with Al etchant F2.

[0131] AlO xThe thin film corresponds to a layer in which the mixture ratio of Al and Ga in the AlGaO-based aluminum mixed crystal layer 2 is (Al=100%, Ga=0%).

[0132] Next, let us refer to the CrGaO-based graph second from the left in Fig. 15. Regarding the mixture ratio of Cr and Ga in the CrGaO-based chromium mixed crystal layer 1, the circle marks indicate a mixture ratio of (Cr=32%, Ga=68%), and the cross marks indicate a mixture ratio of (Cr=100%, Ga=0%).

[0133] As shown by the etching characteristic L13, the chromium mixed crystal layer 1 satisfying the chemical formula (1) is not etched by the Al etchant F2.

[0134] Next, let us refer to the AlGaO-based graph, the third from the left in Figure 15. Regarding the mixture ratio of Al and Ga in the AlGaO-based mixed crystal layer, the ▽ symbol indicates a mixture ratio of (Al=0%, Ga=100%), the △ symbol indicates a mixture ratio of (Al=11%, Ga=89%) (with Si addition), the ◇ symbol indicates a mixture ratio of (Al=12%, Ga=88%) (with Si addition), and the □ symbol indicates a mixture ratio of (Al=25%, Ga=75%) (with Si addition).

[0135] Al 2 O 3 As shown by etching characteristics L12, L14 and L15 in the graph of the AlGaO system and the graph of the AlGaO system, the aluminum mixed crystal layer 2 satisfying the above-mentioned chemical formula (2) is etched by the Al etchant F2.

[0136] Next, let us refer to the fourth InGaO-based graph from the left in Fig. 15. Regarding the mixture ratio of In and Ga in the InGaO-based indium mixed crystal layer 2X, the circle and triangle marks indicate a mixture ratio of (In=80%, Ga=20%), and the cross mark indicates a mixture ratio of (In=100%, Ga=0%).

[0137] As shown by the InGaO-based etching characteristics L16 and L17, the indium mixed crystal layer 2X satisfying the chemical formula (3) is etched by the Al etchant F2.

[0138] Next, let us refer to the FeGaO-based graph, the fifth from the left in Fig. 15. Regarding the mixture ratio of Fe and Ga in the FeGaO-based mixed crystal layer, the ◇ symbol indicates a mixture ratio of (Fe=70%, Ga=30%; (film formation temperature 335°C)), the square symbol indicates a mixture ratio of (Fe=70%, Ga=30%; (film formation temperature 350°C)), and the ▽ symbol indicates a mixture ratio of (Fe=100%, Ga=0% (film formation temperature 400°C)).

[0139] As shown by the FeGaO-based etching characteristics L18 and L19, the iron mixed crystal layer 2Y satisfying the chemical formula (4) is etched by the Al etchant F2.

[0140] Next, the SiO 2 Refer to the graph of the system.

[0141] SiO x As shown in the etching characteristic L20 of the system, SiO 2 SiO x The silicon oxide layer 6 made of this material is not etched by the Al etchant F2.

[0142] As described above, it is recognized from FIG. 15 that the second etching characteristics of the Al etchant F2 shown in FIG. 11 for the chromium mixed crystal layer 1, the aluminum mixed crystal layer 2, and the silicon oxide layer 6 are correct.

[0143] However, AlO corresponding to the aluminum mixed crystal layer 2 when {y=1} in chemical formula (2) x To allow the thin film to be etched by the Al etchant F2, the AlO x It is preferable to form a thin film. The mist method is not limited to the mist CVD method.

[0144] In addition, it was recognized that the indium mixed crystal layer 2X and the iron mixed crystal layer 2Y are also etched in the same manner as the aluminum mixed crystal layer 2 by the Al etchant F2.

[0145] (Cr etching agent F1) FIG. 16 is an explanatory diagram showing in a graph form the details of the first etching characteristic by the Cr etchant F1.

[0146] 16, the horizontal axis indicates the etching time (unit: seconds (s)), and the vertical axis indicates the etching depth (unit: nm). Also, the etching rate (nm / s) is appropriately indicated.

[0147] Al at the left of Figure 16 2 O 3 Refer to the graph of the system. As shown in the etching characteristic L21, Al 2 O 3 The sapphire substrate made of this material is not etched by the Cr etchant F1.

[0148] Next, let us refer to the CrGaO-based graph second from the left in Fig. 16. Regarding the mixture ratio of Cr and Ga in the CrGaO-based mixed crystal layer, the triangle mark indicates a mixture ratio of (Cr=20%, Ga=80%), the square mark indicates a mixture ratio of (Cr=32%, Ga=68%), and the cross mark indicates a mixture ratio of (Cr=100%, Ga=0%).

[0149] As shown by the etching characteristics L22 and L23, the chromium mixed crystal layer 1 satisfying the chemical formula (1) is etched by the Cr etchant F1.

[0150] Next, let us refer to the AlGaO-based graph, the third from the left in Figure 16. Regarding the mixture ratio of Al and Ga in the AlGaO-based mixed crystal layer, the ▽ symbol indicates a mixture ratio of (Al=0%, Ga=100%), and the ◇ symbol indicates a mixture ratio of (Al=12%, Ga=88%) (with Si added).

[0151] Al 2 O 3 As shown by the etching characteristics L21 and L24 in the graph of the AlGaO system and the graph of the AlGaO system, the aluminum mixed crystal layer 2 satisfying the above-mentioned chemical formula (2) is not etched by the Cr etchant F1.

[0152] Next, let us refer to the fourth InGaO-based graph from the left in Fig. 16. Regarding the mixture ratio of In and Ga in the InGaO-based mixed crystal layer, the circle marks indicate a mixture ratio of (In=80%, Ga=20%), and the cross marks indicate a mixture ratio of (In=100%, Ga=0%).

[0153] As shown by the InGaO-based etching characteristic L25, the indium mixed crystal layer 2X satisfying the chemical formula (3) is not etched by the Cr etchant F1.

[0154] Next, let us refer to the FeGaO-based graph, the fifth from the left in Fig. 16. With regard to the mixture ratio of Fe and Ga in the FeGaO-based mixed crystal layer, the ◇ symbol indicates a mixture ratio of (Fe=70%, Ga=30%; (film formation temperature 335°C)), the square symbol indicates a mixture ratio of (Fe=70%, Ga=30%; (film formation temperature 350°C)), and the ▽ symbol indicates a mixture ratio of (Fe=100%, Ga=0% (film formation temperature 400°C)).

[0155] As shown by the FeGaO-based etching characteristic L26, the iron mixed crystal layer 2Y satisfying the chemical formula (4) is not etched by the Cr etchant F1.

[0156] Next, the SiO 2 See the graph of the system. SiO x As shown in the etching characteristics L27 of the system, SiO 2 SiO x The silicon oxide layer 6 made of this material is not etched by the Cr etchant F1.

[0157] As described above, it is recognized from FIG. 16 that the first etching characteristic of the Cr etchant F1 shown in FIG. 11 for the chromium mixed crystal layer 1, the aluminum mixed crystal layer 2, and the silicon oxide layer 6 is correct.

[0158] Furthermore, it was recognized that the indium mixed crystal layer 2X and the iron mixed crystal layer 2Y, like the aluminum mixed crystal layer 2, were not etched by the Cr etchant F1.

[0159] <Summary and Effects of the First and Second Embodiments> From the facts shown in FIGS. 11 to 16, the first and second etching methods of the first embodiment can be summarized as follows.

[0160] The etching method of the first embodiment performs the following steps (a) and (b).

[0161] Step (a) is a step of obtaining a structure to be etched, which includes first and second mixed crystal layers.

[0162] Step (b) is a step of performing at least one of a first etching process for selectively etching a first mixed crystal layer of the etching target structure using a Cr etching agent F1, and a second etching process for selectively etching the second mixed crystal layer of the etching target structure using an Al etching agent F2.

[0163] The first mixed crystal layer contains a component that satisfies the following chemical formula (5), and the second mixed crystal layer contains a component that satisfies the following chemical formula (6).

[0164] (M1 x Ga 1-x ) 2 O 3 (0 <x≦1)…(5) (M2 y Ga 1-y ) 2 O 3 (0 <y≦1)…(6) In the chemical formula (5), M1=Cr, and in the chemical formula (6), M2=one of {Al, In, Fe}.

[0165] Furthermore, the first mixed crystal layer satisfying chemical formula (5) has crystallinity when {x≠1}, and the second mixed crystal layer satisfying chemical formula (6) has crystallinity when {y≠1}.

[0166] In the etching method of the first embodiment, by performing the above-mentioned step (b), the first mixed crystal layer or the second mixed crystal layer can be selectively etched from the structure to be etched, so that a desired structure can be obtained from the structure to be etched relatively easily.

[0167] In addition, in the semiconductor device having the patterning structure 13 (13B) shown in FIG. 2 (FIG. 4), by performing the above step (b), the upper mixed crystal layer of the first and second mixed crystal layers can be selectively removed using the lower mixed crystal layer as an etching stopper.

[0168] Therefore, the patterned structure 13 (13B) of the semiconductor device manufactured in accordance with the first embodiment can be obtained with high accuracy by carrying out the relatively simple etching method of the first embodiment.

[0169] Moreover, from the facts shown in FIGS. 11 to 16, the third and fourth etching methods of the second embodiment can be summarized as follows.

[0170] The etching method of the second embodiment performs the following steps (a) and (b).

[0171] Step (a) is a step of obtaining a structure to be etched, which includes first and second mixed crystal layers and a silicon oxide layer.

[0172] Step (b) is a step of performing at least one of a first etching process for selectively etching a first mixed crystal layer on the structure to be etched using a first etching agent, a second etching process for selectively etching a second mixed crystal layer on the structure to be etched using a second etching agent, and a third etching process for selectively etching a silicon oxide layer on the structure to be etched using a third etching agent.

[0173] The components of the first and second mixed crystal layers are the same as those in the first embodiment.x The constituent materials are:

[0174] In the etching method of the second embodiment, by performing the above-mentioned step (b), the first mixed crystal layer, the second mixed crystal layer, or the silicon oxide film can be selectively etched from the structure to be etched, so that a desired structure can be obtained from the structure to be etched relatively easily.

[0175] In addition, in the semiconductor device having the patterning structure 14 (14B) shown in FIG. 7 (FIG. 10), by performing the third etching process included in the above step (b), the uppermost layer of the first and second mixed crystal layers and the silicon oxide layer can be selectively removed using the intermediate layer as an etching stopper.

[0176] Furthermore, as in the second embodiment, by performing the first etching process or the second etching process following the third etching process, the intermediate layer can be selectively removed using the first and second mixed crystal layers and the lowest layer of the silicon oxide layer as an etching stopper.

[0177] Therefore, the patterned structure 14 (14B) of the semiconductor device manufactured in accordance with the second embodiment can be obtained with high accuracy by carrying out the relatively simple etching method of the second embodiment.

[0178] In addition, in the second embodiment, by using a buffered hydrofluoric acid solution (BHF solution) as the silicon oxide etchant F3, it is possible to selectively remove the silicon oxide film from the etching target structure, which is the stacked structure 4 of the second embodiment.

[0179] Furthermore, as the Al etchant F2 in the first and second embodiments, HNO 3 5-15% by weight, CH 3 COOH 5-15% by weight, H 3 PO 4 60-80% by weight, H 2 The etching solution used contains 10 to 20% by weight of O.

[0180] In this manner, by using the etching solution mixed in the above-mentioned mixing ratio as the Al etching agent F2, the aluminum mixed crystal layer 2 can be selectively removed from the etching target structure, which is the stacked structure 3 of the first embodiment or the stacked structure 4 of the second embodiment.

[0181] In addition, as the Cr etching agent F1 in the first and second embodiments, (NH 4 ) 2 Ce(NO 3 ) 6 5-15% by weight, HClO 4 60-80% by weight, H 2 The etching solution used contains 10 to 20% by weight of O.

[0182] In this manner, by using the etching solution mixed in the above-mentioned mixing ratio as the Cr etching agent F1, the chromium mixed crystal layer 1 can be selectively removed from the etching target structure, which is the stacked structure 3 (3B) of the first embodiment or the stacked structure 4 (4B) of the second embodiment.

[0183] It should be noted that, with respect to the effects of the above-mentioned etchants F1 to F3, the same effects can be obtained even if the aluminum mixed crystal layer 2 is replaced with an indium mixed crystal layer 2X or an iron mixed crystal layer 2Y.

[0184] In addition, when the chromium mixed crystal layer 1 has {x≠1} in the chemical formula (5), it is presumed that if it has crystallinity, it will exhibit the etching characteristics shown in FIGS. 13, 15, and 16 regardless of the ratio with Ga.

[0185] Similarly, when the aluminum alloy layer 2, the indium alloy layer 2X, and the iron alloy layer 2Y are represented by chemical formula (6) where {y ≠ 1}, if they have crystallinity, they are presumed to exhibit the etching characteristics shown in FIGS. 13, 15, and 16, regardless of the ratio with Ga.

[0186] This is because, if it is confirmed that a mixed crystal layer in which elements E1 and E2 are mixed at a predetermined mixing ratio has predetermined etching characteristics with respect to the etching agent W, it can be presumed that even if the mixed crystal layer in which elements E1 and E2 are mixed at a ratio other than the predetermined ratio, the above-mentioned predetermined etching characteristics with respect to the etching agent W are the same. However, the mixed crystal layer needs to have crystallinity, that is, to be single crystal or polycrystal.

[0187] In addition, AlO x When the layers do not contain Ga, i.e., when x=1 in chemical formulas (1) and (5), and when y=1 in chemical formulas (2) to (4) and (6), they do not need to be crystalline and may be amorphous.

[0188] Conversely, the first mixed crystal layer including the chromium mixed crystal layer 1 satisfying chemical formula (5) must have crystallinity when {x ≠ 1}. Similarly, the second mixed crystal layer including the aluminum mixed crystal layer 2, the indium mixed crystal layer 2X, and the iron mixed crystal layer 2Y, each of which satisfies chemical formula (6), must have crystallinity when {y ≠ 1}.

[0189] In the first and second embodiments, the first etching process using the Cr etching agent F1, the second etching process using the Al etching agent F2, and the third etching process using the silicon oxide etching agent F3 are all wet etching.

[0190] <Embodiment 3> In the third embodiment, the etching method disclosed in the second embodiment is developed to show a case where a HEMT (High Electron Mobility Transistor) is manufactured by using a combination of first and second mixed crystal layers and a selective etching technique.

[0191] 17 to 19 are cross-sectional views showing basic processing steps for obtaining the laminated structure 4 in the third embodiment. Fig. 20 is an explanatory diagram showing an outline of a first thin film manufacturing technique for obtaining a chromium alloy layer 1, and Fig. 21 is an explanatory diagram showing an outline of a second thin film manufacturing technique for obtaining an aluminum alloy layer 2. The basic processing steps will be described below with reference to Figs. 17 to 21, respectively.

[0192] 17, a CrGaO-based chromium mixed crystal layer 1 is formed by mist CVD on a sapphire substrate 8. The sapphire substrate 8 is a C-plane sapphire substrate.

[0193] 20, a Cr mist can be obtained by storing a Cr solution in the Cr chamber C1 and applying ultrasonic vibration to the Cr chamber C1. A Ga solution can be stored in the Ga chamber C2 and applying ultrasonic vibration to the Ga chamber C2. Then, the Cr mist obtained from the Cr chamber C1 and the Ga mist obtained from the Ga chamber C2 are mixed on the surface of the sapphire substrate 8, whereby a chromium mixed crystal layer 1 can be formed on the sapphire substrate 8.

[0194] Next, as shown in FIG. 18, an AlGaO-based aluminum mixed crystal layer 2 is formed on the chromium mixed crystal layer 1 by mist CVD.

[0195] 21, an Al mist can be obtained by storing an Al solution in the Al chamber C3 and applying ultrasonic vibration to the Ga chamber C2. A Ga solution can be stored in the Ga chamber C4 and applying ultrasonic vibration to the Ga chamber C4, thereby obtaining a Ga mist. The Al mist obtained from the Al chamber C3 and the Ga mist obtained from the Ga chamber C4 are mixed on the surface of the chromium mixed crystal layer 1, thereby forming an aluminum mixed crystal layer 2 on the chromium mixed crystal layer 1.

[0196] 18, in the state where the aluminum alloy layer 2 is formed, a high-mobility two-dimensional electron gas (2DEG) due to a heterojunction can be generated near the interface between the chromium alloy layer 1 and the aluminum alloy layer 2. Therefore, the stacked structure of the chromium alloy layer 1 and the aluminum alloy layer 2 may realize an active layer that generates a 2DEG.

[0197] 19, a silicon oxide layer 6 is formed on the aluminum mixed crystal layer 2 by using a plasma CVD method. As the plasma CVD method, a plasma-enhanced chemical vapor deposition (PECVD) method using TEOS as a raw material is adopted.

[0198] As a result, a laminated structure 4 can be obtained in which the chromium mixed crystal layer 1, the aluminum mixed crystal layer 2, and the silicon oxide layer 6 are laminated in this order on the sapphire substrate 8.

[0199] 22 to 28 are cross-sectional views showing the mesa etching process (first mask processing step) in embodiment 3. The mesa etching process will be described below with reference to FIGS.

[0200] After obtaining the laminated structure 4 shown in FIG. 19, a photoresist 9 is applied onto the silicon oxide layer 6 by spin coating, as shown in FIG.

[0201] 23, ultraviolet light 10 is selectively irradiated from above the photoresist 9. The area of ​​the photoresist 9 that has been exposed to the ultraviolet light 10 becomes the ultraviolet irradiated area.

[0202] Next, as shown in FIG. 24, the ultraviolet irradiated area of ​​the photoresist 9 is removed, and the photoresist 9 is patterned.

[0203] Thereafter, as shown in FIG. 25, a third etching process is performed to etch the silicon oxide layer 6 using a silicon oxide etchant F3 with the patterned photoresist 9 as a mask (first mask).

[0204] At this time, since the aluminum mixed crystal layer 2 directly below the silicon oxide layer 6 functions as an etching stopper against the silicon oxide etchant F3, only the silicon oxide layer 6 can be selectively removed by the third etching process. As a result, a patterned silicon oxide layer 6 can be obtained.

[0205] Thereafter, acetone 12 is irradiated onto the entire surface of the photoresist 9, and then, as shown in FIG. 26, the photoresist 9 irradiated with the acetone 12 is entirely removed.

[0206] 27, a second etching process is performed to etch the aluminum mixed crystal layer 2 using the patterned silicon oxide layer 6 as a mask and an Al etchant F2. The second etching process is performed in a temperature environment of 135° C.

[0207] At this time, since the chromium mixed crystal layer 1 directly below the aluminum mixed crystal layer 2 functions as an etching stopper against the Al etchant F2, only the aluminum mixed crystal layer 2 can be selectively removed by the second etching process.

[0208] As a result, after the second etching process is performed, a patterned aluminum alloy layer 2 can be obtained. The second etching process can be performed simply without forming a photoresist. In addition, the silicon oxide layer 6 on the aluminum alloy layer 2 is not etched away by the second etching process.

[0209] 28, a first etching process is performed to etch the chromium mixed crystal layer 1 using the patterned silicon oxide layer 6 as a mask and an etching agent F1 for Cr. The first etching process is performed in a temperature environment of 135° C. Alternatively, the first etching process may be performed in a temperature environment of about 65° C.

[0210] At this time, since the sapphire substrate 8 directly below the chromium mixed crystal layer 1 functions as an etching stopper against the Cr etchant F1, only the chromium mixed crystal layer 1 can be selectively removed by the first etching process. Moreover, the aluminum mixed crystal layer 2 and the silicon oxide layer 6 on the chromium mixed crystal layer 1 are also not etched away by the Cr etchant F1.

[0211] As a result, after the first etching process, a patterned chromium alloy layer 1 can be obtained. The first etching process can be performed simply without forming a photoresist. In addition, the aluminum alloy layer 2 and the silicon oxide layer 6 on the chromium alloy layer 1 are not etched away by the first etching process.

[0212] It has been confirmed that the first etching process can be performed in a temperature range of 65° C. to 135° C., and since this is a temperature range of 50° C. or higher, the etching selectivity can be improved.

[0213] In this manner, the mesa etching process makes it possible to obtain with high accuracy the intermediate patterned structure 34A from the laminated structure 4. The intermediate patterned structure 34A has a laminated structure of the chromium mixed crystal layer 1, the aluminum mixed crystal layer 2 and the silicon oxide layer 6.

[0214] (Second mask process) 29 to 34 are cross-sectional views showing the second mask processing step in embodiment 3. The second mask processing step will be described below with reference to FIGS.

[0215] First, as shown in FIG. 29, a photoresist 15 is applied by spin coating to cover the entire surface of the sapphire substrate 8 including the intermediate patterning structure 34A shown in FIG.

[0216] 30, ultraviolet light 16 is selectively irradiated from above the photoresist 15. The area of ​​the photoresist 15 that has been exposed to the ultraviolet light 16 becomes the ultraviolet irradiated area.

[0217] 31, the ultraviolet irradiated area of ​​the photoresist 15 is removed to pattern the photoresist 15. The patterned photoresist 15 serves as a second mask.

[0218] Thereafter, as shown in FIGS. 31 and 32, a third etching process is performed in which the silicon oxide layer 6 is etched using a silicon oxide etchant F3 with the patterned photoresist 15 as a mask.

[0219] At this time, since the aluminum mixed crystal layer 2 directly below the silicon oxide layer 6 functions as an etching stopper against the silicon oxide etchant F3, only the silicon oxide layer 6 can be selectively removed by the third etching process. As a result, a patterned silicon oxide layer 6 can be obtained.

[0220] Thereafter, acetone 12 is irradiated onto the entire surface of the photoresist 15, and then, as shown in FIG. 33, the photoresist 9 irradiated with the acetone 12 is entirely removed.

[0221] Next, as shown in FIG. 34, a second etching process is performed to etch the aluminum mixed crystal layer 2 using the patterned silicon oxide layer 6 as a mask and an Al etchant F2.

[0222] At this time, since the chromium alloy layer 1 directly below the aluminum alloy layer 2 functions as an etching stopper against the Al etchant F2, only the aluminum alloy layer 2 can be selectively removed by the second etching process. As a result, a patterned aluminum alloy layer 2 can be obtained.

[0223] In this manner, the intermediate patterning structure 34B can be obtained with high accuracy from the intermediate patterning structure 34A by the second mask processing step. The intermediate patterning structure 34B has a laminated structure of the chromium mixed crystal layer 1, the aluminum mixed crystal layer 2, and the silicon oxide layer 6.

[0224] 35 to 39 are cross-sectional views showing the third mask processing step in embodiment 3. Hereinafter, the third mask processing step will be described with reference to FIGS.

[0225] First, as shown in FIG. 35, a photoresist 17 is applied by spin coating to cover the entire surface of the sapphire substrate 8 including the intermediate patterning structure 34B shown in FIG.

[0226] 36, ultraviolet rays 18 are selectively irradiated from above the photoresist 17. The areas of the photoresist 17 that have been exposed to the ultraviolet rays 18 become the ultraviolet irradiated areas.

[0227] 37, the ultraviolet irradiated area of ​​the photoresist 17 is removed, and the photoresist 17 is patterned. As a result, through holes 57 are formed on the side surfaces of the aluminum mixed crystal layer 2 and the silicon oxide layer 6. The patterned photoresist 17 serves as a third mask.

[0228] 38, a Ti metal layer 22 is formed by sputtering, and then an Au metal layer 23 is formed by thermal evaporation on the Ti metal layer 22. As a result, a metal laminate structure 31 is obtained in which the Ti metal layer 22 and the Au metal layer 23 are laminated in this order. The metal laminate structure 31 is also formed inside the through-hole 57.

[0229] 39, a lift-off process is performed to leave a pair of metal laminate structures 31 adjacent to the aluminum alloy layer 2 and the silicon oxide layer 6 on the chromium alloy layer 1. One of the pair of metal laminate structures 31 functions as a source electrode, and the other functions as a drain electrode.

[0230] In this manner, the intermediate patterning structure 34C can be obtained with high accuracy from the intermediate patterning structure 34B by the third mask processing step. The intermediate patterning structure 34B includes a stacked structure of the chromium mixed crystal layer 1, the aluminum mixed crystal layer 2, and the silicon oxide layer 6, and a pair of metal stacked structures 31.

[0231] The pair of metal laminated structures 31 are formed directly on the surface of the chromium alloy layer 1. This structure was realized because an Al etchant F2 capable of selectively etching only the aluminum alloy layer 2 in the laminated structure including the chromium alloy layer 1 and the aluminum alloy layer 2 was found.

[0232] 40 is a plan view showing an example of the planar structure of the intermediate patterning structure 34B. In this figure, the metal laminate structure 31 is omitted. As shown in this figure, a pair of metal laminate structures 31 (not shown) are formed on two chromium mixed crystal layers 1 selectively and separately formed in circular regions of a sapphire substrate 8. An aluminum mixed crystal layer 2 is formed directly under the silicon oxide layer 6 in FIG.

[0233] 41 to 46 are cross-sectional views showing a gate formation step in accordance with the embodiment 3. Hereinafter, the gate formation step will be described with reference to FIGS.

[0234] First, as shown in FIG. 41, a photoresist 19 is applied by spin coating to cover the entire surface of the sapphire substrate 8 including the intermediate patterning structure 34C shown in FIG.

[0235] 42, ultraviolet rays 20 are selectively irradiated from above the photoresist 19. The area of ​​the photoresist 19 that is exposed to the ultraviolet rays 20 becomes the ultraviolet irradiated area.

[0236] 43, the ultraviolet irradiated area of ​​the photoresist 19 is removed to pattern the photoresist 19. As a result, a part of the surface of the silicon oxide layer 6 is exposed, and a through hole 59 is formed in the silicon oxide layer 6.

[0237] Thereafter, as shown in FIG. 44, a third etching process is performed in which the silicon oxide layer 6 is etched using a silicon oxide etchant F3 with the patterned photoresist 19 as a mask.

[0238] At this time, since the aluminum mixed crystal layer 2 directly below the silicon oxide layer 6 functions as an etching stopper against the silicon oxide etchant F3, only the silicon oxide layer 6 can be selectively removed by the third etching process. As a result, a patterned silicon oxide layer 6 having through holes 60 extending from the through holes 59 can be obtained.

[0239] 45, a Ti electrode layer 25 is formed by sputtering, and then an Au electrode layer 26 is formed by thermal evaporation on the Ti electrode layer 25. As a result, a metal laminate structure 32 in which the Ti electrode layer 25 and the Au electrode layer 26 are laminated in this order can be obtained. The metal laminate structure 32 is also formed inside the through-hole 60.

[0240] 46, a lift-off process is performed to leave only the metal stack structure 32 on the silicon oxide layer 6. The remaining metal stack structure 32 functions as a gate electrode.

[0241] In this manner, a HEMT final structure 35 can be obtained from the intermediate patterning structure 34C by the gate formation process. The HEMT final structure 35 includes a stacked structure of the chromium alloy layer 1, the aluminum alloy layer 2, and the silicon oxide layer 6, a pair of metal stacked structures 32, and one metal stacked structure 32.

[0242] <Specific manufacturing details> Hereinafter, a detailed description will be given of the manufacturing methods of the chromium mixed crystal layer 1, the aluminum mixed crystal layer 2, the indium mixed crystal layer 2X, the iron mixed crystal layer 2Y, and the silicon oxide layer 6 shown in the embodiments 1 to 3. Note that the following content is merely an example, and it goes without saying that the manufacturing methods are not limited to these.

[0243] (Chromium mixed crystal layer 1)…Thickness: Approximately 500 nm "Chromium-based film forming materials" Raw material solution: Ammonium dichronite ((NH 4 ) 2 Cr 2 O 7 )solution Solvent: Pure water: hydrochloric acid (99.5:0.5) mixed solvent Solute concentration…0.040mol / L

[0244] "Gallium-based film forming materials" Raw material solution: Gallium acetylacetonate solution Solvent: Pure water: hydrochloric acid (99.5:0.5) mixed solvent Solute concentration…0.020mol / L

[0245] (Aluminum alloy layer 2)…Thickness: about 300 nm "Aluminum-based film forming materials" Raw material solution: Aluminum acetylacetonate solution Solvent: Pure water: hydrochloric acid (99.5:0.5) mixed solvent Solute concentration: 0.040mol / L

[0246] "Gallium-based film forming materials" Same as chromium mixed crystal layer

[0247] (Indium mixed crystal layer 2X) "Indium-based film forming materials" Raw material solution: In 2 O 3 solution Solvent: Pure water Solute concentration: 0.050mol / L

[0248] "Gallium-based film forming materials" Same as chromium mixed crystal layer

[0249] (Iron mixed crystal layer 2Y) "Iron-based film forming materials" Raw material solution: Fecl 3 6H 2 O solution Solvent: Pure water Solute concentration: 0.1mol / L

[0250] "Gallium-based film forming materials" Raw material solution...Gacl 3 aqueous solution Solvent: Pure water Solute concentration…0.1mol / L

[0251] "Auxiliary materials" Raw material solution: Ammonia water (NH 3 aq) Solvent: Pure water

[0252] (Common items) "Gas type" Carrier gas: Nitrogen gas Dilution gas: Nitrogen gas

[0253] "Sapphire Substrate 8" Material: C-face sapphire substrate Heating temperature: 400℃

[0254] "Mist generating means" Ultrasonic transducer: 2.4MHz, 24V, 0.625A, 3 pieces used

[0255] (Silicon oxide layer 6) Film thickness: about 300 nm

[0256] <Other> In the first to third embodiments, the same effect can be obtained by using an indium mixed crystal layer 2X or an iron mixed crystal layer 2Y instead of the aluminum mixed crystal layer 2. This is because the aluminum mixed crystal layer 2, the indium mixed crystal layer 2X, and the iron mixed crystal layer 2Y, which are second mixed crystal layers satisfying chemical formula (6), have a common second etching characteristic.

[0257] When forming the indium mixed crystal layer 2X, it is preferable to form a buffer layer. Figures 47 and 48 are cross-sectional views showing a method of forming the indium mixed crystal layer 2X using a buffer layer.

[0258] As shown in Fig. 47, a buffer layer 41 is formed on a substrate 40 such as a sapphire substrate 8. Thereafter, as shown in Fig. 48, an indium mixed crystal layer 2X is formed on the buffer layer 41.

[0259] In addition, when forming the iron mixed crystal layer 2Y, as described above, in addition to the gallium-based film-forming material and the iron-based film-forming material, ammonia solution in the form of mist NH 3 It is preferable to use a mist (ammonia mist).

[0260] Fig. 49 is an explanatory diagram showing a schematic outline of the manufacturing process of the iron mixed crystal layer 2Y. Fig. 49 shows the manufacturing process of the iron mixed crystal layer 2Y on a substrate 40 such as a sapphire substrate 8. The iron mixed crystal layer 2Y is manufactured by the following steps (1) to (4).

[0261] (1) obtaining Fe mist M1; (2) obtaining Ga mist M2; (3) NH 3 Steps to get Mist M3: (4) Fe mist M1, Ga mist M2, and NH 3 A step of supplying the mist M3 onto the substrate 40 to form an iron mixed crystal layer 2Y on the substrate 40.

[0262] In addition, NH in step (3) 3The mist M3 can be obtained by misting the ammonia solution, which is the "auxiliary material" described above.

[0263] In this manner, by forming the iron mixed crystal layer 2Y using ammonia mist as an auxiliary material, the iron mixed crystal layer 2Y can be obtained with high accuracy and a desired thickness.

[0264] In the etching method of the first embodiment, the laminated structure 3 (3B) of the chromium alloy layer 1 and the aluminum alloy layer 2 is the structure to be etched. However, the structure to be etched is not limited to the laminated structure 3.

[0265] For example, a two-layer independent structure including a chromium mixed crystal layer 1 and an aluminum mixed crystal layer 2 formed independently without contacting each other on a sapphire substrate 8 can be the etching target structure. That is, at least one of the first etching process using the Cr etching agent F1 and the second etching process using the Al etching agent F2 may be performed on the two-layer independent structure.

[0266] For example, the two-layer independent structure can be subjected to a first etching process using a Cr etchant F1 by using a resist patterned on the chromium alloy layer 1 as a mask, thereby patterning only the chromium alloy layer 1. In this case, since the aluminum alloy layer 2 is not etched by the Cr etchant F1, there is no need to form a resist on the aluminum alloy layer 2.

[0267] In the etching methods shown in the second and third embodiments, the stacked structure 4 (4B) including the chromium mixed crystal layer 1, the aluminum mixed crystal layer 2, and the silicon oxide layer 6 is the structure to be etched. However, the structure to be etched is not limited to the stacked structure 4.

[0268] For example, a three-layer independent structure including a chromium alloy layer 1, an aluminum alloy layer 2, and a silicon oxide layer 6 formed independently without contacting each other on a sapphire substrate 8 may be used as the etching target structure. That is, at least one of the first etching process using a Cr etching agent F1, the second etching process using an Al etching agent F2, and the third etching process using a silicon oxide etching agent F3 may be performed on the three-layer independent structure.

[0269] For example, the three-layer independent structure can be subjected to a first etching process using a Cr etchant F1 by using a resist patterned on the chromium alloy layer 1 as a mask to pattern the chromium alloy layer 1. At this time, since the aluminum alloy layer 2 and the silicon oxide layer 6 are not etched by the Cr etchant F1, there is no need to form a resist on the aluminum alloy layer 2 and the silicon oxide layer 6.

[0270] In addition, within the scope of the present disclosure, it is possible to freely combine the respective embodiments, and to appropriately modify or omit the respective embodiments. [Industrial Applicability]

[0271] The etching method and semiconductor device according to the present disclosure can form an etching technique for a semiconductor device using gallium oxide and an active layer of the semiconductor device, and can provide basic techniques for gallium oxide-based semiconductor devices, which is extremely useful in industry. [Explanation of symbols]

[0272] 1 Chromium mixed crystal layer 2 Aluminum alloy layer 2X Indium alloy layer 2Y iron mixed crystal layer 3,3B,4,4B laminated structure 6 Silicon oxide layer 13, 13B, 14, 14B Patterning structure 31,32 Metal laminate structure 34A~34C Intermediate patterning structure 35 Final HEMT structure

Claims

1. A semiconductor device including a patterning structure having first and second mixed crystal layers, the first and second mixed crystal layers being formed at different heights; The patterning structure comprises: a laminated structure including the first and second mixed crystal layers; a single layer structure in which only the lower mixed crystal layer is provided in the laminated structure, The first mixed crystal layer is (M1 ｘ G １－ｘ ) ２ O ３ (0<x≦1), The second mixed crystal layer is (M2 ｙ G １－ｙ ) ２ O ３ (0<y≦1), M1=Cr; M2=one of {Al, In, Fe}; the first mixed crystal layer has crystallinity when {x≠1}; The second mixed crystal layer has crystallinity when {y≠1}. Semiconductor device.

2. A semiconductor device including a patterning structure having first and second mixed crystal layers and a silicon oxide layer, the first and second mixed crystal layers and the silicon oxide layer being provided at different formation heights from each other, The patterning structure comprises: a triple stack structure including the first and second mixed crystal layers and the silicon oxide layer; A double laminate structure consisting of two layers excluding the top layer of the triple laminate structure; Among the three-layered structure, only the bottom layer is provided, and the three-layered structure includes a single layer structure, The first mixed crystal layer is (M1 ｘ G １－ｘ ) ２ O ３ (0<x≦1), The second mixed crystal layer is (M2 ｙ G １－ｙ ) ２ O ３ (0<y≦1), M1=Cr; M2=one of {Al, In, Fe}; the first mixed crystal layer has crystallinity when {x≠1}; The second mixed crystal layer has crystallinity when {y≠1}. Semiconductor device.

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