Liquid crystal display device

Abstract

To provide a liquid crystal display device with which it is possible to suppress an impact of parasitic capacitance arising from a difference in a length of source leader lines and display an image with better display quality.SOLUTION: A liquid crystal display device comprises a source driver, a plurality of source leader lines respectively connecting a plurality of source bus lines and the source driver, and a plurality of pieces of capacitance wiring intersecting the plurality of source bus lines and connected to common potential. Each capacitance wiring overlaps the plurality of source bus lines. The plurality of source leader lines includes a first source leader line and a second source leader line whose parasitic capacitance is larger than that of the first source leader line, the first and the second source leader lines are connected to the first and the second source bus lines, respectively, and the parasitic capacitance formed by the second source bus line and the plurality of pieces of capacitance wiring is smaller than the parasitic capacitance formed by the first source bus line and the plurality of pieces of capacitance wiring.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a liquid crystal display device. [Background technology]

[0002] A liquid crystal display device includes a plurality of gate bus lines and a plurality of source bus lines connected to pixels in a display area. Among these, the source bus lines are connected to source drivers arranged around the periphery of the display area by source lead-out lines.

[0003] Since the spacing between the source bus lines and the spacing between the source driver terminals are different, the lengths of the source lead lines are different from each other, and the resistance and parasitic capacitance also differ depending on the length. Therefore, depending on the position of the source bus line, the dullness of the data signal applied to the source bus line may differ, and the display quality may deteriorate. For example, even if an image signal is input so that the entire display area is displayed in a uniform color, striped brightness unevenness may occur.

[0004] In order to suppress such a problem, Patent Document 1 discloses that a common line separate from the data line (source bus line) is arranged to adjust the parasitic capacitance. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Special Publication No. 2019-536093 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present disclosure is to provide a liquid crystal display device capable of suppressing the effects of resistance and parasitic capacitance caused by differences in the lengths of source lead lines and displaying images with superior display quality. [Means for solving the problem]

[0007] A liquid crystal display device according to an embodiment of the present disclosure includes a substrate having a main surface including a display region and a non-display region located outside the display region, a plurality of gate bus lines located in the display region and extending in a first direction, a plurality of source bus lines located in the display region and extending in a direction intersecting the plurality of gate bus lines, the plurality of source bus lines including at least one first source bus line and at least one second source bus line, a plurality of pixels that are two-dimensionally arranged in the display region and are surrounded by adjacent pairs of gate bus lines of the plurality of gate bus lines and adjacent pairs of source bus lines of the plurality of source bus lines, at least one source driver arranged in the non-display region, a plurality of source lead lines each connecting one end of the plurality of source bus lines to the source driver, and a plurality of source lead lines located in the display region and surrounding the at least one first source bus line and the at least one second source bus line. the plurality of capacitance wirings are arranged to intersect with each other and connected to a common potential, each capacitance wiring having a first portion extending in the first direction and a plurality of second portions extending along the extension direction of the source bus lines and overlapping the source bus lines at positions where the capacitance wiring intersects with the at least one first source bus line and the at least one second source bus line, the plurality of source pull-out lines include at least one first source pull-out line and at least one second source pull-out line having a larger parasitic capacitance than the first source pull-out line, the at least one first source pull-out line is connected to the at least one first source bus line and the at least one second source pull-out line is connected to the at least one second source bus line, and a parasitic capacitance formed between the second source bus line and the plurality of capacitance wirings is smaller than a parasitic capacitance formed between the first source bus line and the plurality of capacitance wirings. Effect of the Invention

[0008] According to an embodiment of the present disclosure, a liquid crystal display device is provided that is capable of suppressing the influence of resistance and parasitic capacitance caused by differences in the lengths of source lead lines and displaying images with higher display quality. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a schematic cross-sectional view showing an example of the configuration of a liquid crystal display device according to the first embodiment. [Diagram 2] FIG. 2 is a schematic plan view showing the configuration of an active matrix substrate in the liquid crystal display device shown in FIG. [Diagram 3] FIG. 3 is a circuit diagram showing an example of the configuration of each pixel of the display device shown in FIG. [Figure 4] FIG. 4 is a plan view showing the main structure of one pixel of the active matrix substrate. [Diagram 5] FIG. 5 is a cross-sectional view of the liquid crystal panel taken along line AA in FIG. [Figure 6] FIG. 6 is a cross-sectional view of the liquid crystal panel taken along line BB in FIG. [Figure 7] FIG. 7 is a schematic diagram showing a cross-sectional structure of a source lead line. [Figure 8] FIG. 8 is a schematic diagram showing a cross-sectional structure of a source lead line. [Figure 9] FIG. 9 is a schematic diagram showing a cross-sectional structure of a source lead line. [Figure 10] FIG. 10 is a schematic diagram showing a cross-sectional structure of a source lead line. [Figure 11] FIG. 11 is a schematic diagram showing a cross-sectional structure of a source lead line. [Figure 12] FIG. 12 is a plan view showing the capacitance lines and the pixel electrodes. [Figure 13] FIG. 13 is a plan view showing the capacitance lines and the source bus lines. [Figure 14] FIG. 14 is a plan view showing the capacitance lines and the source bus lines. [Figure 15] FIG. 15 is a plan view showing the capacitance lines and the source bus lines. [Figure 16] FIG. 16 is a schematic plan view showing the configuration of an active matrix substrate in a liquid crystal display device according to the second embodiment. [Figure 17] FIG. 17 is a plan view showing the capacitance lines and the source bus lines. [Figure 18] FIG. 18 is a plan view showing the capacitance lines and the source bus lines. [Figure 19] FIG. 19 is a plan view showing the capacitance lines and the source bus lines. [Figure 20] FIG. 20 is a plan view showing pixel electrodes, source bus lines, and capacitance lines according to another example of the second embodiment. [Figure 21] FIG. 21 is a plan view showing the capacitance lines and the source bus lines. [Figure 22] FIG. 22 is a plan view showing the capacitance lines and the source bus lines. [Figure 23] FIG. 23 is a plan view showing the capacitance lines and the source bus lines. [Figure 24] FIG. 24 is a schematic plan view showing the configuration of an active matrix substrate in a liquid crystal display device according to the third embodiment. [Diagram 25] FIG. 25 is a plan view showing pixel electrodes, source bus lines, gate bus lines and capacitance wiring. [Figure 26] FIG. 26 is a plan view showing the capacitance lines and the source bus lines. [Figure 27] FIG. 27 is a plan view showing the capacitance lines and the source bus lines. [Figure 28] FIG. 28 is a plan view showing the capacitance lines and the source bus lines. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] The liquid crystal display device disclosed in Patent Document 1 has a common line including a second subline that extends parallel to the gate bus line in each pixel unit, and a first subline that extends parallel to the source bus line and connects the second subline of each pixel unit. The second subline overlaps with the source bus line via an insulating layer, and the magnitude of the parasitic capacitance can be adjusted by the overlapping area between the second subline and the source bus line.

[0011] According to Patent Document 1, it is explained that the occurrence of band-like brightness unevenness can be avoided by making the parasitic capacitance of a source bus line connected to a source lead line having a large resistance value smaller than the parasitic capacitance of a source bus line connected to a source lead line having a small resistance value.

[0012] However, when the inventors of the present application examined the liquid crystal display device of Patent Document 1, they found that this structure would cause new problems because the common line is in a floating state and the first sub-line intersects with the gate bus line. Specifically, when the data signal applied to the source bus line or the scanning signal applied to the gate bus line changes, the potential of the pixel electrode may be affected through the capacitance between the source bus line and the common line, the capacitance between the gate bus line and the common line, and the capacitance between the pixel electrode and the common line. In view of these problems, the inventors of the present application came up with a novel liquid crystal display device.

[0013] Hereinafter, an embodiment of the present disclosure will be described based on the drawings. The present disclosure is not limited to the following embodiments, and appropriate design changes can be made within the scope of the configuration of the present disclosure. In the following description, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations thereof may be omitted. In addition, each configuration described in the embodiment and the modified example may be appropriately combined or modified within the scope of the gist of the present disclosure. In order to make the description easier to understand, in the drawings referred to below, the configuration may be shown in a simplified or schematic manner, or some components may be omitted. In addition, the dimensional ratio between the components shown in each drawing does not necessarily indicate the actual dimensional ratio.

[0014] [First embodiment] 1 is a schematic cross-sectional view showing an example of the configuration of a liquid crystal display device according to the present embodiment. A liquid crystal display device 101 includes a liquid crystal panel 50 and a control device 90. The liquid crystal panel 50 also includes an active matrix substrate 40, a counter substrate 80, and a liquid crystal layer 81.

[0015] The active matrix substrate 40 includes a substrate 10 having a principal surface 10a. The principal surface 10a has a display region DR and a non-display region NR located around the display region DR so as to surround the display region DR. The display region DR is a region that contributes to image display, and the non-display region is a region that does not display images.

[0016] As described in detail below, the active matrix substrate 40 includes a plurality of gate bus lines, a plurality of source bus lines, capacitance wiring, and a plurality of pixel electrodes. Each pixel electrode is connected to one of the plurality of gate bus lines and one of the plurality of source bus lines via a pixel transistor.

[0017] The active matrix substrate 40 and the counter substrate 80 are attached to each other with a predetermined gap therebetween by a seal 82 arranged in the non-display region NR, and a liquid crystal layer 81 is arranged between the active matrix substrate 40 and the counter substrate 80 in a region surrounded by the seal 82. In this embodiment, a color filter is provided on the surface of the substrate 21 included in the counter substrate 80 facing the liquid crystal layer 81. However, the color filter may also be provided on the surface of the substrate 10 included in the active matrix substrate 40 facing the liquid crystal layer 81.

[0018] As described below, the liquid crystal panel 50 further includes at least one gate driver and a plurality of source drivers. The gate driver and the source driver are arranged in an area other than the display area DR of the substrate 10, and drive the gate bus lines and the source bus lines, respectively. In this embodiment, the gate driver and the source driver are arranged in the non-display area NR.

[0019] The control device 90 includes a substrate 91 and a timing controller 92 mounted on the substrate 91. In this embodiment, the substrate 91 is a flexible substrate, the timing controller 92 is mounted on the substrate 91, and a terminal of the substrate 91 is connected to the active matrix substrate 40. The timing controller 92 receives a video signal from an external host computer and generates a scanning signal and a data signal. The generated scanning signal and data signal are output to a gate driver and a source driver.

[0020] The liquid crystal display device 101 further includes a pair of polarizing plates 96 and a backlight 95. The pair of polarizing plates 96 are positioned to sandwich the active matrix substrate 40 and the counter substrate 80. The backlight 95 is disposed to face one of the pair of polarizing plates 96.

[0021] FIG. 2 is a schematic plan view showing an example of an active matrix substrate 40. As described above, the main surface 10a of the substrate 10 has a display region DR and a non-display region NR. In this embodiment, the display region DR has a rectangular shape with the x-axis direction as the longitudinal direction. However, the display region may have other shapes, such as an oval, a polygon, or a rectangle with rounded upper two corners aligned in the x-axis direction. The non-display region NR is located around the display region DR. In this embodiment, the non-display region NR surrounds the display region.

[0022] The gate bus lines GL each extend in the x-axis direction (first direction) and are arranged in the y-axis direction (second direction), and the source bus lines SL each extend in the y-axis direction and are arranged in the x-axis direction.

[0023] The plurality of capacitance lines CL are arranged in the display region DR so as to intersect with some of the plurality of source bus lines SL.

[0024] 3 is a circuit diagram showing a configuration example of a pixel PX. Each pixel PX is disposed in an area surrounded by a pair of source bus lines SL among a plurality of source bus lines SL and a pair of gate bus lines GL among the plurality of gate bus lines GL. The pixel PX includes a switching element such as a thin film transistor (TFT) and a pixel electrode PE. Specifically, the gate electrode of the TFT is connected to the gate bus line GL, the source electrode is connected to the source bus line SL, and the drain electrode is connected to the pixel electrode.

[0025] 2 again. At least one gate driver 60 and each of the source drivers 70 are arranged outside the display region DR. In this embodiment, the active matrix substrate 40 includes a pair of gate drivers 60 arranged in the non-display region NR with the display region DR sandwiched therebetween in the x-axis direction.

[0026] In this embodiment, the gate driver 60 is integrally (monolithically) formed on the substrate 10. For example, the gate driver 60 includes a plurality of TFTs, and these TFTs are formed simultaneously with the TFTs of the pixels PX. The gate driver 60 may be configured as a bare chip or a packaged chip, and may be mounted in the non-display region NR of the substrate 10.

[0027] Both ends of the multiple gate bus lines GL reach the non-display area NR and are connected to the gate driver 60.

[0028] The multiple source drivers 70 are composed of bare chips or packaged chips, and are mounted in the non-display area NR of the substrate 10. One end of each of the multiple source bus lines SL is extended to the non-display area NR, and one end of each of the multiple source bus lines SL is connected to each of the source drivers 70 by multiple source lead-out lines LL formed on the substrate 10. In this embodiment, the source driver 70 is shown as four elements, but the number of source drivers 70 may be one to three or five or more.

[0029] Each of the multiple source lead-out lines LL is connected to each of the multiple terminals of the source driver 70, but the interval between the terminals of the source driver 70 is different from the arrangement interval in the x-axis direction of the source bus lines SL. More specifically, the interval between the terminals of the source driver 70 is narrower than the arrangement interval in the x-axis direction of the source bus lines SL. For this reason, the length of at least a part of the multiple source lead-out lines LL, i.e., the distance along the source lead-out line 70 from the connection part between the source lead-out line 70 and the source driver 70 to the connection part between the source lead-out line 70 and the source bus line SL, is different from that of the other source lead-out lines LL. Hereinafter, this distance is also simply referred to as the length of the source lead-out line.

[0030] In this embodiment, the plurality of source extraction lines LL include at least one first source extraction line LL1, at least one second source extraction line LL2, and at least one third source extraction line LL3. If the lengths of the first source extraction line LL1, the second source extraction line LL2, and the third source extraction line LL3 are l1, l2, and l3 respectively, they satisfy the relationship l1 < l2 < l3. Also, if the parasitic capacitances of the first source extraction line LL1, the second source extraction line LL2, and the third source extraction line LL3 are c1, c2, and c3 respectively, they satisfy the relationship c1 < c2 < c3 depending on the length of each source extraction line. These parasitic capacitances include the parasitic capacitance formed between two adjacent or overlapping source extraction lines LL and the parasitic capacitance formed at the overlapping portion between the source extraction line LL and a common electrode to be described later in the non-display region NR.

[0031] Also, if the resistances of the first source extraction line LL1, the second source extraction line LL2, and the third source extraction line LL3 are r1, r2, and r3 respectively, they satisfy the relationship r1 < r2 < r3 depending on the length of each source extraction line. When the parasitic capacitance and resistance of the source extraction line LL are large, the time constant (the product of the parasitic capacitance and the resistance) becomes large, and the delay of the data signal supplied from the source driver 70 to the source bus line SL via the source extraction line LL tends to be large, and stripe-like luminance unevenness is likely to occur. The luminance unevenness caused by the delay of the data signal may be alleviated by correcting the data signal or adjusting the common signal supplied to the common electrode, but it is difficult to correct the data signal or adjust the common signal when the difference in the delay of the data signal is large or when the number of source bus lines SL with different delays of the data signal is large.

[0032] The plurality of source extraction lines LL only need to include one or more of the first source extraction line LL1, the second source extraction line LL2, and the third source extraction line LL3 respectively, and each source extraction line may include two or more.

[0033] The multiple source bus lines SL include at least one first source bus line SL1, at least one second source bus line SL1, and at least one third source bus line SL3. The first source bus line SL1 is connected to the first source lead-out line LL1, the second source bus line SL2 is connected to the second source lead-out line LL2, and the third source bus line SL3 is connected to the third source lead-out line LL3.

[0034] A part of the source bus lines SL crosses the capacitance wiring CL to form a parasitic capacitance. If the parasitic capacitance formed by the first source bus line SL1 and the capacitance wiring CL is cc1, and the parasitic capacitance formed by the second source bus line SL2 and the capacitance wiring CL is cc2, then cc1 is larger than cc2. That is, the relationship cc1>cc2 is satisfied. This makes it possible to reduce the difference in parasitic capacitance caused by the difference in length between the first source lead line LL1 and the second source lead line LL2 by making the parasitic capacitances of the connected first source bus line SL1 and second source bus line SL2 different. The structure of the active matrix substrate 40 will be specifically described below.

[0035] Fig. 4 is a plan view showing the main structure of one pixel of active matrix substrate 40. Main metal layers, conductive layers, and semiconductor layers are shown in Fig. 4. Fig. 5 and Fig. 6 show the cross-sectional structure of liquid crystal panel 50 taken along lines AA and BB in Fig. 4.

[0036] In the cross section taken along line AA, in the active matrix substrate 40, a gate electrode 11 which is part of a gate bus line GL is disposed on a substrate 10, and a gate insulating layer 12 is disposed on the substrate 10 to cover the gate electrode 11 and the gate bus line GL. A semiconductor layer 13 is located on the gate insulating layer 12. A drain electrode 15 and a source electrode 14 which is part of a source bus line SL are located on the semiconductor layer 13.

[0037] An insulating layer 16 is disposed on the gate insulating layer 12, covering the source bus line SL including the source electrode 14, the drain electrode 15, and the semiconductor layer 13. Furthermore, a planarizing layer 17 is disposed on the insulating layer 16, and a common electrode 18 is disposed on the planarizing layer 17.

[0038] An insulating layer 19 is disposed on the planarization layer 17 to cover the common electrode 18. A pixel electrode PE is located on the insulating layer 19 (FIG. 6). The gate bus line GL and the source bus line SL are each a single layer film made of one type of metal material selected from copper, titanium, aluminum, molybdenum, tungsten, etc., or a laminated film or alloy made of different types of metal materials, and thus have electrical conductivity and light blocking properties. The common electrode 18 and the pixel electrode PE are made of a transparent conductive material (e.g., ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide)). If the liquid crystal display device 101 is a reflective or semi-transmissive type, the common electrode 18 and the pixel electrode PE may contain a metal material with high reflectivity, such as aluminum or silver.

[0039] In addition, in the counter substrate 80, a black matrix 22 is disposed on a substrate 21, and further, a color filter 23 is disposed. The color filter 23 has, for example, any one of red, blue, and green for each pixel, and a green color filter 23G and a red color filter 23R are shown in Figures 5 and 6. An overcoat layer 24 is disposed on the color filter 23.

[0040] Since both the AA and BB lines are located in positions that are covered by the black matrix 22, in Figures 5 and 6 the color filter 23 is located on the black matrix 22, but in the pixel opening region, the black matrix 22 is not arranged and the color filter 23 is formed on the substrate 21.

[0041] As shown in FIG. 4, the gate bus line GL extends in the x-axis direction, and the gate electrode 11 extends into each pixel PX (region surrounded by a dashed line).

[0042] In each pixel PX, the source bus line SL extends parallel to the y-axis in a region adjacent to the TFT. Also, the source electrode 14 extends toward the inside of each pixel PX. The source bus line SL has a bent portion SLc at the center of each pixel in the y-axis direction. At the bent portion SLc, the direction in which the source bus line SL extends changes, so that the source bus line SL has a V-shape in a region adjacent to the opening of each pixel. The source bus line SL extends parallel to the y-axis as a whole while bending at the bent portion SLc at an angle of, for example, 3° to 20° with respect to the y-axis.

[0043] The pixel electrode PE has a plurality of slit-shaped openings PEO extending in the y-axis direction and arranged in the x-axis direction. Each opening PEO has a first bent portion PEO1 and a second bent portion PEO2 respectively adjacent to a pair of gate bus lines GL, and a third bent portion PEO3 located between the first bent portion PEO1 and the second bent portion PEO2. The extending direction of the slits changes at the first bent portion PEO1, the second bent portion PEO2, and the third bent portion PEO3.

[0044] The pixel electrode PE is connected to the drain electrode 15 via contact holes provided in the insulating layer 19, the planarizing layer 17, and the insulating layer 16. Here, a bent portion adjacent to a gate bus line GL corresponding to a TFT having a drain electrode 15 to which a certain pixel electrode PE is connected is defined as a second bent portion PEO2, and a bent portion adjacent to a gate bus line GL adjacent to a gate bus line GL corresponding to a TFT having a drain electrode 15 to which a certain pixel electrode PE is connected is defined as a first bent portion PEO1.

[0045] In a plan view, the common electrode 18 continuously overlaps at least the entire opening PEO of each pixel electrode PE. In this embodiment, the common electrode 18 spreads over each pixel PX and is connected to the common electrode 18 of the adjacent pixel PX. As a result, the common electrode 18 covers the entire display region DR. In each pixel PX, the common electrode 18 is provided with an opening 18a that exposes a part of the drain electrode 15 in order to connect the pixel electrode PE and the drain electrode 15 described above. As shown in FIG. 2, the common electrode 18 is connected to a common line RL in the non-display region NR, and a common potential is supplied from the control device 90.

[0046] A spacer 20 is disposed between the counter substrate 80 and the active matrix substrate 40. A liquid crystal layer 81 is disposed in the gap between the counter substrate 80 and the active matrix substrate 40.

[0047] In the pixel having the above configuration, when a data signal is written to the pixel electrode PE via the TFT, a potential difference is generated between the pixel electrode PE and the overlapping common electrode 18. A fringe electric field (diagonal electric field) including a component normal to the main surface of the array substrate 40 in addition to a component along the main surface of the array substrate 40 is generated between the opening edge of the opening PEO of the pixel electrode PE and the common electrode 18. The alignment direction of the liquid crystal molecules contained in the liquid crystal layer 81 can be controlled by utilizing this fringe electric field. In other words, the liquid crystal panel 101 according to this embodiment operates in a FFS (Fringe Field Switching) mode.

[0048] The source lead-out lines LL arranged in the non-display region NR of the active-matrix substrate 40 can be configured in various ways. Figures 7 to 11 are schematic diagrams showing the cross-sectional structure of the source lead-out lines LL. As shown in Figure 7, the multiple source lead-out lines LL may be arranged, for example, on the substrate 10 and below the gate insulating layer 12. In this case, the source lead-out lines LL can be configured from the same metal layer as the metal layer that configures the gate bus lines GL and the capacitance lines CL.

[0049] 8 and 9, the multiple source lead lines LL may include, for example, a wiring LLA arranged on the substrate 10 and below the gate insulating layer 12, and a wiring LLB arranged on the gate insulating layer 12 and below the insulating layer 16. In this case, the wiring LLA can be configured as described above. The wiring LLB can be configured from the same metal layer as the metal layer that configures the source bus line SL and the drain electrode 15. In this case, the wiring LLA and the wiring LLB may overlap in the stacking direction, or the wiring LLB may be shifted in the x-axis direction so as not to overlap with the wiring LLA.

[0050] 10 and 11, the source lead lines LL may include, for example, a wiring LLA arranged on the substrate 10 and below the gate insulating layer 12, a wiring LLB arranged on the gate insulating layer 12 and below the insulating layer 16, and a wiring LLC arranged on the insulating layer 16 and below the insulating layer 19. In this case, the wiring LLA and the wiring LLB can be configured as described above. The wiring LLC can be configured, for example, by the same conductive layer or metal layer as the conductive layer or metal layer constituting the common electrode 18. The wiring LLC can also be configured by the same metal layer as the metal layer provided so as to be in direct contact with the common electrode 18 (such a metal layer may be provided to reduce the resistance distribution in the display region DR of the common electrode 18). Furthermore, the wiring LLC may be configured to be disposed between an insulating layer additionally provided below the wiring LLA and the substrate 10. The wiring LLA, the wiring LLB, and the wiring LLC may overlap in the stacking direction, or the wiring LLB and the wiring LLC may be shifted in the x-axis direction with respect to the wiring LLA so as not to overlap each other.

[0051] In this way, by forming a part of the source lead-out line LL with one or more different metal layers, the source lead-out line LL formed with different metal layers can be arranged at different levels in the height direction. Therefore, for example, even if the arrangement pitch of the source lead-out lines LL is narrowed, the source lead-out lines LL can be prevented from contacting each other. In addition, the resistance of the source lead-out line LL can be reduced by increasing the width of the source lead-out line LL.

[0052] Furthermore, parasitic capacitance is formed by at least some of the multiple source lead-out lines LL partially or entirely overlapping in a plan view. Therefore, the parasitic capacitance of a source lead-out line LL that overlaps with another source lead-out line LL is likely to be larger than the parasitic capacitance of a source lead-out line LL that does not overlap with another source lead-out line LL. Note that the parasitic capacitance of the source lead-out line LL can be adjusted by appropriately adding parasitic capacitance due to the overlap between the source lead-out lines LL to some or all of the multiple source lead-out lines LL.

[0053] Next, the capacitance line CL will be described. Fig. 12 is a plan view showing the capacitance line CL and the pixel electrode PE, and Fig. 13, Fig. 14, and Fig. 15 are plan views showing the capacitance line CL and the source bus line SL.

[0054] The capacitance line CL has a first portion CL1 extending in the x-axis direction and a plurality of second portions CL2 each extending in the direction in which the source bus line SL extends and overlapping the source bus line SL at a position where the capacitance line CL intersects with the source bus line SL. The capacitance line CL is formed of, for example, the same metal layer as the gate electrode 11 and the gate bus line GL, and may include the same metal layer. In this case, the capacitance line CL does not intersect with the gate bus line GL, and a gate insulating layer 12 is located between the source bus line SL and the capacitance line CL.

[0055] The capacitance wiring CL may be formed using a metal layer different from that of the gate electrode 11 and the gate bus line GL. For example, as a wiring for reducing the resistance distribution of the common electrode 18, or as a touch sensor wiring when the liquid crystal display device has a touch sensor function, a wiring formed using a metal layer may be provided in a different layer via an insulating layer for any of the gate bus line GL, the source bus line SL, the common electrode 18, and the pixel electrode PE. The capacitance wiring CL may be formed using the same metal layer as this metal layer.

[0056] The capacitance line CL is preferably disposed at a position overlapping the first bend portion PEO1 or the second bend portion PEO2 of the opening portion PEO of the pixel electrode PE in the pixels PX arranged in the x-axis direction. In this embodiment, the capacitance line CL is disposed at the first bend portion PEO1 in the pixels PX arranged in the x-axis direction.

[0057] As shown in FIG. 4 and FIG. 6, the capacitance wiring CL is connected to the common electrode 18 through a contact hole 17h provided in the planarization layer 17 and the insulating layer 16. The contact hole 17h connecting each capacitance wiring CL to the common electrode 18 may be provided at least in one place in the display region DR, but may be provided in a plurality of places including near both ends of the capacitance wiring CL in order to provide redundancy in the connection with the capacitance wiring CL and reduce the resistance distribution of the common electrode 18. In addition, in the region where the contact hole 17h is formed, the alignment direction of the liquid crystal is easily disturbed, which may cause afterimages, so it is preferable to provide the contact hole 17h in a region overlapping with the black matrix 22. The alignment direction of the liquid crystal is easily disturbed in the vicinity of the spacer 20, so that the black matrix 22 is provided on the substrate 21 of the counter substrate 80 so as to overlap with the spacer 20. The contact hole 17h may be disposed in the vicinity of the spacer 20 so as not to increase the area occupied by the black matrix 22.

[0058] The length of the second portion CL2 of the capacitance line CL along the source bus line SL differs depending on the type of the source bus line SL that the second portion CL2 overlaps with. As shown in Figures 13 and 14, when the length of the second portion CL2 overlapping with the first source bus line SL1 along the first source bus line is ll1 and the length of the second portion CL2 overlapping with the second source bus line SL2 along the first source bus line is ll2, the relationship ll1>ll2 is satisfied.

[0059] The width of the second portion CL2 perpendicular to the extending direction of the second portion CL2 may be the same as the width of the source bus line SL or may be different. From the viewpoint of efficiently generating parasitic capacitance, the width of the second portion CL2 is preferably the same as the width of the source bus line SL. In addition, in the manufacturing process, the width of the source bus line SL and the width of the second portion CL2 may vary, and the position of the source bus line SL relative to the second portion CL2 may be shifted. Taking these into consideration, the width of the second portion CL2 may be made larger than the width of the source bus line SL by, for example, about 1 to 2 μm.

[0060] As shown in FIG. 15, the capacitance line CL does not intersect with the third source bus line SL3. Therefore, the parasitic capacitance generated by the third source bus line SL3 intersecting with the capacitance line CL is zero. Meanwhile, in this embodiment, the active matrix substrate 40 includes a plurality of dummy lines DL adjacent to the third source bus line SL3. Each dummy line DL extends in the x-axis direction and is adjacent to the third source bus line SL3. Also, each dummy line DL is located on an extension line of one of the plurality of capacitance lines CL and does not intersect with any of the source bus lines SL.

[0061] The dummy wiring DL does not intersect with the source bus line SL and therefore does not contribute much to an increase in the parasitic capacitance of the source bus line SL. On the other hand, by locating the dummy wiring DL on an extension line of the capacitance wiring CL, it is possible to reduce the difference in aperture ratio between a pixel in which the capacitance wiring CL is arranged and a pixel in which the capacitance wiring CL is not arranged.

[0062] As described above, since the length l2 of the second source lead wire LL2 is greater than the length L1 of the first source lead wire LL1, the resistance r2 of the second source lead wire LL2 is greater than the resistance r1 of the first source lead wire LL1 (r1 < r2), and the parasitic capacitance c2 of the second source lead wire LL2 is greater than the parasitic capacitance c1 of the first source lead wire LL1 (c1 < c2).

[0063] On the other hand, in each capacitance wiring CL, the length ll1 of the second portion CL2 overlapping with the first source bus line SL1 is longer than the length ll2 of the second portion CL2 overlapping with the second source bus line SL2 (ll1 > ll2). Here, in the portion overlapping with the second portion CL2, the widths of the first source bus line SL1 and the second source bus line SL2 are the same. For this reason, the area where the source bus line SL and the second portion CL2 overlap is proportional to the length of the second portion CL2, and the area where the second source bus line SL2 and the second portion CL2 overlap is smaller than the area where the first source bus line SL1 and the second portion CL2 overlap. That is, the area where the second source bus line SL2 and each capacitance wiring CL overlap is smaller than the area where the first source bus line SL1 and each capacitance wiring CL overlap. For this reason, the parasitic capacitance cc2 formed by the second source bus line SL2 and the plurality of capacitance wirings CL is smaller than the parasitic capacitance cc1 formed by the first source bus line and the plurality of capacitance wirings CL (cc1 > cc2).

[0064] The first source lead wire LL1 and the second source lead wire LL2 are respectively connected to the first source bus line SL1 and the second source bus line SL2. For this reason, in order to reduce the difference in parasitic capacitance between the first source lead wire LL1 and the second source lead wire LL2, the capacitance wiring CL forms parasitic capacitances between the first source bus line SL1 and the second source bus line SL2, respectively.

[0065] As a means for making the parasitic capacitance of the first source bus line SL1 larger than that of the second source bus line SL2, it is possible to make the width of the first source bus line SL1 larger than that of the second source bus line SL2 in the portion overlapping with the second portion CL2. However, in this case, the resistance of the first source bus line SL1 becomes smaller than that of the second source bus line SL2, and the difference in the resistance values ​​may cause a difference in the dullness of the data signal. Furthermore, in the case of a liquid crystal display device having a configuration in which the common electrode 18 is disposed in an upper layer (closer to the liquid crystal layer 81) than the pixel electrode PE, the parasitic capacitance between the first source bus line SL1 and the pixel electrode PE adjacent to the first source bus line SL1 may become larger than the parasitic capacitance between the second source bus line SL2 and the pixel electrode PE adjacent to the second source bus line SL1, which may easily cause display defects such as shadowing. Therefore, as described above, it is preferable that the width of the first source bus line SL1 and the width of the second source bus line SL2 are the same in the portion overlapping with the second portion CL2.

[0066] Moreover, the capacitance line CL is connected to the common electrode 18 and is maintained at a constant potential. Therefore, even if a data signal is applied to the pixel electrodes and the source bus lines by driving the liquid crystal display device, a change in parasitic capacitance due to the capacitance line is suppressed.

[0067] This capacitance wiring CL is arranged at the first bend portion PEO1 or the second bend portion PEO2 of the pixels arranged in the x-axis direction. At the bend portion of the slit-shaped opening PEO of the pixel electrode PE, the alignment direction of the liquid crystal is disturbed, making it difficult to transmit light with the correct gradation corresponding to the voltage applied to the pixel, and the contribution to the brightness of each pixel is small. Therefore, by arranging the capacitance wiring CL at the first bend portion PEO1 or the second bend portion PEO2, the aperture ratio of the pixel is reduced, but the effect on the actual brightness of the pixel can be suppressed.

[0068] In addition, since the length l3 of the third source lead line LL3 is greater than the length l2 of the second source lead line LL2, the resistance r3 of the third source lead line LL3 is greater than the resistance r2 of the second source lead line LL2 (r2 < r3), and the parasitic capacitance c3 of the third source lead line LL3 is greater than the parasitic capacitance c2 of the second source lead line LL2 (c2 < c3).

[0069] On the other hand, each capacitance wiring CL does not overlap with the third source bus line SL3. Therefore, the parasitic capacitance cc3 formed by the third source bus line SL3 and the plurality of capacitance wirings CL is smaller than the parasitic capacitance cc2 formed by the second source bus line and the plurality of capacitance wirings CL (cc2 > cc3).

[0070] By connecting the second source lead line LL2 and the third source lead line LL3 to the second source bus line SL2 and the third source bus line SL3 respectively, it can be said that the capacitance wiring CL forms a parasitic capacitance with the second source bus line SL2 so as to reduce the difference in parasitic capacitance between the second source lead line LL2 and the third source lead line LL3.

[0071] (Second Embodiment) FIG. 16 is a plan view showing an example of the active matrix substrate 40 in the liquid crystal display device 102 of the present embodiment. The liquid crystal display device of the present embodiment is different from the liquid crystal display device 101 of the first embodiment in that each capacitance wiring CL also intersects with the third source bus line SL3.

[0072] As shown in FIG. 16, each capacitance wiring CL intersects with all of the first source bus line SL1, the second source bus line SL2, and the third source bus line SL3. Specifically, each capacitance wiring CL extends from one end to the other end in the x-axis direction of the display region DR so as to intersect with all the source bus lines SL arranged in the display region. In the present embodiment, the liquid crystal display device 102 does not include dummy wiring DL.

[0073] 17, 18, and 19 are plan views showing the positions of the capacitance line CL and the source bus line SL. As shown in Fig. 17 and Fig. 18, the capacitance line CL has a second portion CL2 at the intersection of the first source bus line SL1 and the second source bus line SL2, similar to the first embodiment.

[0074] As shown in FIG. 19, the first portion CL1 of each capacitance line CL intersects with the third source bus line SL3. At the position where each capacitance line CL intersects with the third source bus line Sl3, the capacitance line CL does not have a second portion extending along the direction in which the third source bus line extends. Here, the width of the second source bus line SL2 and the width of the third source bus line SL3 are the same at the portion overlapping with the capacitance line CL. Therefore, the area where the third source bus line SL3 and the capacitance line CL overlap is smaller than the area where the second source bus line SL2 and the capacitance line CL overlap. Therefore, the parasitic capacitance cc3 formed by the third source bus line and the multiple capacitance lines CL is smaller than the parasitic capacitance cc2 formed by the second source bus line and the multiple capacitance lines CL (cc2>cc3).

[0075] Therefore, similar to the first embodiment, the capacitance line CL forms a parasitic capacitance between the second source bus line SL2 and the third source bus line SL3, respectively, so as to reduce the difference in parasitic capacitance between the second source lead line LL2 and the third source lead line LL3.

[0076] In the above embodiment, each capacitance line CL is arranged at the first bend portion PEO1 in the pixels PX aligned in the x-axis direction, but each capacitance line CL may be arranged at the second bend portion PEO2.

[0077] FIG. 20 is a plan view showing the pixel electrodes PE, the source bus lines SL and the capacitance lines CL, and FIGS. 21, 22 and 23 are plan views showing the positions of the capacitance lines CL and the source bus lines SL.

[0078] The first portion CL1 of each capacitance line CL is disposed at a position overlapping with the second bent portion PEO2 of the opening PEO of the pixel electrode PE in the pixel PX arranged in the x-axis direction. The second portion CL2 extends from the first portion CL1 toward the center of each pixel along the direction in which the source bus line SL extends.

[0079] The second bent portion PEO2 is close to the drain electrode 15 of the TFT. The pixel electrode PE is connected to the drain electrode 15 via a contact hole provided in the insulating layer 19, the planarizing layer 17, and the insulating layer 16. Therefore, above the drain electrode 15, the alignment of the liquid crystal is disturbed due to the influence of the contact hole. By arranging each capacitance line CL at a position overlapping with the second bent portion PEO2, each capacitance line CL can cover the area where the alignment of the liquid crystal is disturbed due to the contact hole. Therefore, in addition to the area where the alignment of the liquid crystal is disturbed due to the bending of the slit-shaped opening of the pixel electrode PE described in the first embodiment, at least a part of the area where the alignment of the liquid crystal is disturbed due to the contact hole can be shielded. This makes it possible to obtain a display with a high contrast and with less residual images.

[0080] Third embodiment Fig. 24 is a plan view showing an example of an active matrix substrate 40 in the liquid crystal display device of this embodiment. Fig. 25 is a plan view showing the pixel electrodes PE, source bus lines SL, gate bus lines, and capacitance lines CL of each pixel. Figs. 26, 27, and 28 are plan views showing the source bus lines SL and capacitance lines CL of each pixel.

[0081] The liquid crystal display device of this embodiment differs from the liquid crystal display device 101 of the first embodiment in that each capacitance line CL is disposed at a third bent portion PEO3 of the aperture portion PEO of the pixel electrode PE.

[0082] As shown in FIG. 26, each capacitance line CL is arranged such that the first portion CL1 overlaps with the third bent portion PEO3 of the opening PEO in the pixel arranged in the first direction. The first portion CL1 of each capacitance line CL extends in the x-axis direction so as to intersect with the first source bus line SL1, the second source bus line SL2, and the third source bus line SL3. That is, each capacitance line CL extends in the x-axis direction so as to intersect with a plurality of source bus lines SL. As shown in FIG. 24, both ends of each capacitance line CL extend to the non-display area NR, and in the non-display area, each capacitance line CL is connected to a common line RL, and a common potential is supplied from the control device 90. In this embodiment, as in the first and second embodiments, a contact hole that connects the capacitance line CL and the common electrode 18 may be provided in the display area DR.

[0083] 26 and 27, each capacitance line CL extends along the direction in which the first and second source bus lines extend at a position where the capacitance line CL intersects with the first and second source bus lines, and has a second portion CL2 that overlaps the source bus lines. The second portion CL2 extends from the first portion CL1 toward the first bend portion PEO1 and the second bend portion PEO2, respectively. In the embodiment shown in FIGS. 26 and 27, the second portion CL2 extends toward both the first bend portion PEO1 and the second bend portion PEO2 in this way, but the second portion CL2 may extend in only one direction.

[0084] As shown in FIG. 28, the capacitance line CL does not have the second portion CL2 at the position where it overlaps with the third source bus line SL3.

[0085] In each capacitance line CL, the length ll1 of the second portion CL2 overlapping with the first source bus line SL1 is longer than the length ll2 of the second portion CL2 overlapping with the second source bus line SL2 (ll1>ll2). Here, in the portion overlapping with the second portion CL2, the width of the first source bus line SL1 and the width of the second source bus line SL2 are the same. Therefore, the area where the second source bus line SL2 and the second portion CL2 overlap is smaller than the area where the first source bus line SL1 and the second portion CL2 overlap. Therefore, the parasitic capacitance cc2 formed by the second source bus line SL2 and the plurality of capacitance lines CL is smaller than the parasitic capacitance cc1 formed by the first source bus line and the plurality of capacitance lines CL (cc1>cc2). Here, the length of the second portion is the total length of the length of the second portion extending to the first bend portion PEO1 and the length of the second portion extending to the second bend portion PEO2, and does not include the first portion CL1. Furthermore, each capacitance line CL does not have a second portion extending along the direction in which the third source bus line extends at a position where it intersects with the third source bus line SL3. Here, the width of the second source bus line SL2 and the width of the third source bus line SL3 are the same at the portion overlapping with the second portion CL2. Therefore, the area where the third source bus line SL3 and the capacitance line CL overlap is smaller than the area where the second source bus line SL2 and the capacitance line CL overlap. Therefore, the parasitic capacitance cc3 formed by the third source bus line and the multiple capacitance lines CL is smaller than the parasitic capacitance cc2 formed by the second source bus line and the multiple capacitance lines CL (cc2>cc3).

[0086] In the liquid crystal display device of this embodiment, as in the first and second embodiments, the difference in parasitic capacitance caused by different lengths of source lead lines can be reduced by making the parasitic capacitance of the connected source bus lines different. In addition, since the capacitance lines are connected to a common potential, even if a grayscale signal is applied to the pixel electrodes and source bus lines by driving the display device, the change in the parasitic capacitance of the capacitance lines is suppressed. In addition, since the first portion of the capacitance line CL is arranged to overlap the third bend portion PEO3 where the alignment of the liquid crystal is disturbed, the decrease in the effective aperture ratio is suppressed. [Other forms] The liquid crystal display device of the present disclosure is not limited to the above-mentioned embodiment, and various modifications are possible. First, in each of the above-mentioned embodiments, the capacitance line CL has two types (first and second) of second portions CL2 with different lengths, but the capacitance line CL may have three or more types of second portions CL2 with different lengths. Also, the source lead-out line LL includes three types of lead-out lines with different lengths, but may include four or more types of lead-out lines with different lengths. For example, the capacitance line CL may have m types of second portions CL2 with different lengths, and the source lead-out line LL may include n types of lead-out lines with different lengths. Here, m is an integer of 2 or more, and n is an integer of 3 or more. Also, m and n may be the same number or different numbers.

[0087] In this case, one of two source bus lines overlapping with any two second portions having different lengths is designated as a first source bus line SL1, and the other is designated as a second source bus line SL2. Also, the source lead-out lines LL connected to the first source bus line SL1 and the second source bus line SL2 are designated as a first source lead-out line LL1 and a second source lead-out line LL2, respectively. If the first source bus line SL1 and the first source lead-out line LL1 thus determined satisfy the above-mentioned relationship with the second source bus line SL2 and the second source lead-out line LL2, the liquid crystal display device can achieve the effects described in each embodiment.

[0088] In this case, the third source bus line SL3 has the above-mentioned structure, that is, in the first embodiment, it is at least one of the source bus lines that do not intersect with the capacitance line CL, and the third source lead-in line LL3 is a source lead-in line connected to that source bus line. If the third source bus line SL3 and the third source lead-in line LL3 determined in this manner satisfy the above-mentioned relationship with the second source bus line SL2 and the second source lead-in line LL2, the liquid crystal display device can achieve the effects described in each embodiment.

[0089] Furthermore, the shape and arrangement of each component of the liquid crystal display device described in each embodiment is merely an example, and each component may have another shape or be arranged in another manner.

[0090] The liquid crystal display device of the present disclosure can also be explained as follows.

[0091] The liquid crystal display device according to the first configuration comprises: a substrate having a main surface including a display area and a non-display area located outside the display area; a plurality of gate bus lines located in the display area and extending in a first direction; a plurality of source bus lines located in a display region and extending in a direction intersecting the plurality of gate bus lines, the plurality of source bus lines including at least one first source bus line and at least one second source bus line; a plurality of pixels that are two-dimensionally arranged in a display region and are surrounded by a pair of adjacent gate bus lines among a plurality of gate bus lines and a pair of adjacent source bus lines among a plurality of source bus lines; At least one source driver disposed in the non-display area; a plurality of source lead lines each connecting one end of a plurality of source bus lines to a source driver; a plurality of capacitance wirings located in a display region and arranged so as to intersect with at least one first source bus line and at least one second source bus line, the plurality of capacitance wirings being connected to a common potential; Equipped with each capacitance line has a first portion extending in a first direction, and a plurality of second portions extending along the direction in which the source bus lines extend and overlapping the source bus lines at positions where the capacitance line intersects with at least one first source bus line and at least one second source bus line; the plurality of source leads include at least one first source lead and at least one second source lead; At least one first source lead-out line is connected to at least one first source bus line, and at least one second source lead-out line is connected to at least one second source bus line; the at least one second source lead-out is longer than the at least one first source lead-out; The area where the second source bus line and one of the plurality of capacitance lines overlap is smaller than the area where the first source bus line and one of the plurality of capacitance lines overlap.

[0092] A liquid crystal display device according to a second configuration includes the first configuration, The second source lead is longer than the first source lead, Of the multiple second portions of each capacitance line, the length along the second source bus line of the second portion that overlaps with the second source bus line may be shorter than the length along the first source bus line of the second portion that overlaps with the first source bus line.

[0093] A liquid crystal display device according to a third configuration includes the first configuration, the plurality of source leads further includes at least one third source lead; the plurality of source bus lines further includes at least one third source bus line connected to at least one third source lead line; the at least one third source lead-out is longer than the at least one second source lead-out; The third source bus line does not need to intersect with the multiple capacitance lines.

[0094] A liquid crystal display device according to a fourth configuration has the third configuration, Further comprising a plurality of dummy wirings arranged in the display area; Each dummy wiring extends in the first direction, is adjacent to the third source bus line, and is located on an extension line of one of the plurality of capacitance wirings, and does not necessarily intersect with any of the source bus lines.

[0095] A liquid crystal display device according to a fifth aspect of the present invention has the following configuration in the first aspect: the plurality of source leads further includes at least one third source lead; the plurality of source bus lines further includes at least one third source bus line connected to the at least one third source lead-out line; the at least one third source lead-out is longer than the at least one second source lead-out; the first portion of each capacitance line extends so as to intersect with the third source bus line; The area where the third source bus line and one of the plurality of capacitance lines overlap may be smaller than the area where the second source bus line and one of the plurality of capacitance lines overlap.

[0096] A liquid crystal display device according to a sixth aspect of the present invention has the fifth aspect, Each capacitance line may not have a second portion extending in the direction in which the third source bus line extends at a position where the capacitance line intersects with the third source bus line.

[0097] A liquid crystal display device according to a seventh aspect of the present invention has the first or second aspect, Each of the plurality of pixels includes a pixel electrode and a TFT connected to the pixel electrode; the pixel electrode has a plurality of slit-shaped openings extending along the plurality of source bus lines; Each of the capacitance lines may be disposed in the display region so as to overlap with a bending position of a plurality of openings of pixel electrodes of pixels arranged in the first direction among the plurality of pixels.

[0098] A liquid crystal display device according to an eighth aspect of the present invention has the seventh aspect, Each of the plurality of openings may have a first bent portion and a second bent portion respectively adjacent to the pair of gate bus lines, and a third bent portion located between the first bent portion and the second bent portion.

[0099] A liquid crystal display device according to a ninth aspect of the present invention has the eighth aspect, Each capacitance line may be disposed in the display region so as to overlap with a first bent portion or a second bent portion of the pixels arranged in the first direction.

[0100] A liquid crystal display device according to a tenth aspect of the present invention has the eighth aspect, each capacitance line is disposed in the display region so as to overlap with a third bend portion in the pixels arranged in the first direction; The plurality of second portions may extend from the first portion toward the first bend and the second bend, respectively.

[0101] A liquid crystal display device according to an eleventh aspect has any one of the first to tenth aspects, A common electrode is further provided so as to overlap the pixel electrode in the display region, The plurality of capacitance lines may be electrically connected to a common electrode in the display region.

[0102] A liquid crystal display device according to a twelfth configuration is the eleventh configuration, wherein each of the plurality of capacitance lines may be electrically connected to the common electrode at a plurality of points in the display region.

[0103] A liquid crystal display device according to a thirteenth aspect of the present invention has any one of the first to twelfth aspects, The plurality of capacitance wirings extend to reach the non-display area, The plurality of capacitance wirings may be connected to a wiring that supplies a common potential in the non-display area.

[0104] A liquid crystal display device according to a fourteenth aspect of the present invention has the tenth aspect, The plurality of capacitance lines and the plurality of gate bus lines may include the same metal layer.

[0105] A liquid crystal display device according to a fifteenth aspect of the present invention has the third or fifth aspect, At least two of the at least one first source lead-out line, the at least one second source lead-out line, and the at least one third source lead-out line may partially overlap each other in a plan view. [Explanation of symbols]

[0106] 10...substrate, 10a...main surface, 11...gate electrode, 12...gate insulating layer, 13...semiconductor layer, 14...source electrode, 15...drain electrode, 16...insulating layer, 17...planarization layer, 17h...contact hole, 18...common electrode, 18a...opening, 19...insulating layer, 20...spacer, 21...substrate, 22...black matrix, 23, 23G, 23R...filter, 24...overcoat layer, 40...active matrix substrate, 50...liquid crystal panel, 60...gate driver, 70...source driver, 80...opposite substrate, 81...liquid crystal layer, 82...seal, 90...control device, 91...substrate, 92...timing controller, 95...backlight, 96...polarizing plate, 101...liquid crystal display device, 102...liquid crystal display device

Claims

1. a substrate having a main surface including a display area and a non-display area located outside the display area; a plurality of gate bus lines located in the display area and extending in a first direction; a plurality of source bus lines located in the display region and extending in a direction intersecting the plurality of gate bus lines, the plurality of source bus lines including at least one first source bus line and at least one second source bus line; a plurality of pixels that are two-dimensionally arranged in the display region, each surrounded by a pair of adjacent gate bus lines among the plurality of gate bus lines and a pair of adjacent source bus lines among the plurality of source bus lines; At least one source driver disposed in the non-display area; a plurality of source lead lines each connecting one end of the plurality of source bus lines to the source driver; a plurality of capacitance lines located in the display area and arranged to intersect with the at least one first source bus line and the at least one second source bus line, the plurality of capacitance lines being connected to a common potential; Equipped with each capacitance line has a first portion extending in the first direction, and a plurality of second portions extending along the direction in which the source bus lines extend and overlapping the source bus lines at positions intersecting the at least one first source bus line and the at least one second source bus line; the plurality of source lead-outs include at least one first source lead-out and at least one second source lead-out; the at least one first source lead-out line is connected to the at least one first source bus line, the at least one second source lead-out line is connected to the at least one second source bus line, the at least one second source lead-out is longer than the at least one first source lead-out; an overlapping area between the second source bus line and one of the plurality of capacitance lines is smaller than an overlapping area between the first source bus line and one of the plurality of capacitance lines; LCD display device.

2. the second source lead-out line is longer than the first source lead-out line; 2. The liquid crystal display device of claim 1, wherein, among the plurality of second portions of each of the capacitance lines, a length along the second source bus line of the second portion that overlaps with the second source bus line is shorter than a length along the first source bus line of the second portion that overlaps with the first source bus line.

3. the plurality of source lead-out lines further include at least one third source lead-out line; the plurality of source bus lines further include at least one third source bus line to which the at least one third source lead line is connected; the at least one third source lead-out is longer than the at least one second source lead-out; The liquid crystal display device according to claim 1 , wherein the third source bus line does not intersect with the plurality of capacitance lines.

4. Further comprising a plurality of dummy wirings arranged in the display area, 4. The liquid crystal display device of claim 3, wherein each dummy wiring extends in the first direction, is adjacent to the third source bus line, is located on an extension line of one of the plurality of capacitance wirings, and does not intersect with any of the source bus lines.

5. the plurality of source lead-out lines further include at least one third source lead-out line; the plurality of source bus lines further include at least one third source bus line connected to the at least one third source lead-out line; the at least one third source lead-out is longer than the at least one second source lead-out; the first portion of each capacitance line extends so as to intersect with the third source bus line, 2 . The liquid crystal display device according to claim 1 , wherein an overlapping area between said third source bus line and one of said plurality of capacitance wirings is smaller than an overlapping area between said second source bus line and one of said plurality of capacitance wirings.

6. 6. The liquid crystal display device according to claim 5, wherein each of the capacitance lines does not have a second portion extending in a direction in which the third source bus line extends at a position where the capacitance line intersects with the third source bus line.

7. Each of the plurality of pixels includes a pixel electrode and a TFT connected to the pixel electrode; the pixel electrode has a plurality of slit-shaped openings extending along the plurality of source bus lines, 2. The liquid crystal display device according to claim 1, wherein each capacitance line is arranged in the display region so as to overlap with a bending position of a plurality of openings of the pixel electrode of a pixel among the plurality of pixels that is arranged in the first direction.

8. 8. The liquid crystal display device according to claim 7, wherein each of the plurality of openings has a first bend and a second bend respectively adjacent to the pair of gate bus lines, and a third bend located between the first bend and the second bend.

9. 9. The liquid crystal display device according to claim 8, wherein each capacitance line is arranged in the display region so as to overlap with the first bent portion or the second bent portion in pixels arranged in a first direction.

10. each capacitance line is disposed in the display region so as to overlap with the third bent portion in the pixel arranged in the first direction; The liquid crystal display device according to claim 8 , wherein the second portions extend from the first portion toward the first bent portion and the second bent portion, respectively.

11. a common electrode disposed in the display region so as to overlap with the pixel electrode; 11. The liquid crystal display device according to claim 1, wherein the plurality of capacitance lines are electrically connected to the common electrode in the display region.

12. The liquid crystal display device according to claim 11 , wherein each of the plurality of capacitance wirings is electrically connected to the common electrode at a plurality of points in the display region.

13. the plurality of capacitance lines extend to reach the non-display area, 11. The liquid crystal display device according to claim 1, wherein the plurality of capacitance lines are connected to a line that supplies a common potential in the non-display area.

14. 2. The liquid crystal display device according to claim 1, wherein said plurality of capacitance lines and said plurality of gate bus lines include the same metal layer.

15. 6. The liquid crystal display device according to claim 3, wherein at least two of the at least one first source lead-out line, the at least one second source lead-out line, and the at least one third source lead-out line partially overlap each other in a planar view.

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