Motor controller

Abstract

To provide a technique for reducing the processing burden on a multi-cored semiconductor device while also assuring the synchroneity of motor controlling data.SOLUTION: A motor controller comprises a multi-cored semiconductor device including first and second cores employed to diagnose a three-phase current value required to control a motor using the first and second cores. The first core computes first computation data based on a first group of data related to a three-phase current value and writes it in a buffer, and a second core computes second computation data based on a second group of data related to a three-phase current value. The second core reads out the first computation data written into the buffer by the first core and compares the first computation data with the second computation data, so as to directly make reference to the first computation data written into the buffer by the first core using an address of the buffer for reading out, when performing diagnosis to determine whether or not the first and second computation data are within a threshold.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present disclosure relates to a motor control device, and more particularly to a motor control device using a multi-core semiconductor device that can guarantee concurrency of motor control data. [Background technology]

[0002] In motor control, there is data such as three-phase current values ​​(Iu, Iv, Iw) whose simultaneity must be guaranteed. If a multi-core microcomputer is used for motor control to distribute the processing load, the same data group may be updated and referenced between core tasks with different control periods. In such cases, depending on the timing of referencing the data group, the simultaneity of the data group may not be guaranteed, with one data being the updated current value and the other data being the previous value that has not been updated. Here, a multi-core microcomputer is a semiconductor device (also called a multi-core type semiconductor device) that serves as a control microprocessor having multiple CPU (central processing unit) cores.

[0003] When the use of interrupt inhibition was considered to guarantee the concurrency of data groups, it was found that the processing load would increase in tasks with fast control cycles, which could lead to task failure. Therefore, it was necessary to guarantee the concurrency of data groups used in motor control without using interrupt inhibition. Patent Document 1 discloses a method of guaranteeing the concurrency of data groups without using interrupt inhibition. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2001-282650 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in Patent Document 1, a three-sided buffer (hereinafter referred to as a triple buffer) is used, and an update flag is used for control so that the same buffer cannot be accessed for calculation and reference. The same control can be achieved by replacing this with a two-sided buffer (hereinafter referred to as a double buffer). However, when an update flag is used, a branching process is inevitably generated as to whether or not to access the buffer for calculation and reference. The occurrence of this branching process leads to an increase in the processing load of the multi-core semiconductor device.

[0006] The present disclosure provides a technique that can ensure the concurrency of a group of motor control data and reduce the processing load of a multi-core semiconductor device. [Means for solving the problem]

[0007] A motor control device according to an embodiment of the present disclosure is a motor control device that uses a multi-core semiconductor device including a first core and a second core to diagnose three-phase current values ​​required for controlling a motor, using the first core and the second core, the first core calculates first calculation data based on the first data group related to the three-phase current values ​​and writes the first calculation data to a buffer; The second core calculates second calculation data based on a second set of data related to the three-phase current values; When the second core reads the first calculated data written to the buffer by the first core, compares the first calculated data with the second calculated data, and performs a diagnosis to determine whether the first calculated data and the second calculated data are within a threshold, the second core directly references and reads the first calculated data written to the buffer by using the address of the buffer.

[0008] That is, when the concurrency of motor control data used in motor control is ensured, for example, by a double buffer, the processing load of the multi-core semiconductor device is reduced by using the addresses of two buffers. This address is notified to the first core (calculation side core) that performs the calculation process and the second core (reference side core) that performs the reference process. In this way, if the address of the access destination is known in advance, there is no branching process caused by the update flag, and the processing load of the multi-core semiconductor device can be reduced. Specific solutions will be described in the following Examples 1, 2, and 3. Effect of the Invention

[0009] By applying the present disclosure, it is possible to suppress an increase in the processing load of a multi-core semiconductor device for a group of data used in motor control and to guarantee the concurrency of the group of data. [Brief description of the drawings]

[0010] [Figure 1] 1 is an overall block diagram of a motor control device according to a first embodiment. [Diagram 2] 3 is a diagram showing the relationship between core allocation and motor current control blocks in the motor control device according to the first embodiment. FIG. [Diagram 3] A timing chart showing the update timing and reference timing of three-phase current values ​​(Iu, Iv, Iw) to explain the problem. [Figure 4] 11 is a diagram showing a method for ensuring concurrency of data between cores using a double buffer according to a comparative example. [Diagram 5] FIG. 11 is a flowchart of a process of a calculation side core of a double buffer using flags according to a comparative example. [Figure 6] FIG. 11 is a flowchart of a process of a reference core of a double buffer using flags according to a comparative example. [Figure 7] FIG. 4 is a diagram showing a method for ensuring concurrency of data between cores using a double buffer according to the first embodiment. [Figure 8] FIG. 11 is a flowchart of a process of a calculation side core in a double buffer using address reference according to the first embodiment. [Figure 9] FIG. 11 is a flowchart of a process of a reference side core in a double buffer using address reference according to the first embodiment. [Figure 10] FIG. 11 is a flowchart of a process of a calculation side core in a double buffer using address reference according to the second embodiment. [Figure 11] FIG. 11 is a flowchart of a process of a reference side core in a double buffer using address reference according to the second embodiment. [Figure 12] FIG. 11 is a diagram showing data exchange in a double buffer using a timestamp according to the third embodiment. [Figure 13] FIG. 11 is a flowchart of a process of a calculation side core in a double buffer using a time stamp and an address reference according to the third embodiment. [Figure 14] FIG. 11 is a flowchart of a process of a reference side core in a double buffer using a time stamp and an address reference according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the embodiments will be described in detail with reference to the drawings. EXAMPLES

[0012] In the first embodiment, it is assumed that different cores perform control using calculated data of the same periodic task. In addition, it is assumed that the processes using these calculated data are known to be calculated by the same periodic task.

[0013] 1 is an overall block diagram of a motor control device focusing on current control of a motor according to embodiment 1. A motor control device 109 can be used, for example, as a motor control device that controls a motor 101 that drives the tires of an electric vehicle.

[0014] The motor control device 109 has a motor current control unit 104 for controlling the output of the motor 101, and outputs current detection values ​​(Id^, Iq^) obtained by dq conversion from three-phase motor current values ​​(Iu, Iv, Iw) and a rotation angle θe detected by a rotation angle detection unit 107 in a current detection unit 103. The current control unit 104 outputs voltage commands (Vd*, Vq*) so that the current detection values ​​(Id^, Iq^) match the current command values ​​(Id*, Iq*) output from a current command unit 105. The three-phase voltage conversion unit 106 converts the voltage commands (Vd*, Vq*) and the rotation angle θe into three-phase motor applied voltages, and then controls the semiconductor switch elements of the inverter circuit 102 to turn ON / OFF using a drive signal that has been pulse-width modulated (PWM) to adjust the output voltage (Vu, Vv, Vw). In order to distribute these processes, the motor control device 109 employs a multi-core microcomputer 108.

[0015] Here, the multi-core microcomputer 108 can be, for example, a semiconductor device (also called a multi-core type semiconductor device) serving as a control microprocessor having multiple CPU (central processing unit) cores. As is well known, the three-phase motor 101 has coils for three phases, namely, U phase, V phase, and W phase, and the motor current value Iu indicates the current value of the U phase, the motor current value Iv indicates the current value of the V phase, and the motor current value Iw indicates the current value of the W phase. The output voltage Vu indicates the voltage value of the U phase, the output voltage Vv indicates the voltage value of the V phase, and the output voltage Vw indicates the voltage value of the W phase.

[0016] The inverter circuit 102 is supplied with a DC voltage Edc from the battery BBT. The analog-to-digital conversion circuit ADC is provided to convert three-phase motor current values ​​(Iu-a, Iv-a, Iw-a) as analog values ​​into three-phase motor current values ​​(Iu, Iv, Iw) as digital values. The resolver 110 is an electromechanical sensor that can measure the accurate angular position of the rotating shaft of the motor 101. The resolver-to-digital conversion circuit RDC converts a signal indicating the angular position detected by the resolver 110 into an angle signal and a position signal that are digital signals for the multi-core semiconductor device, and supplies them to the rotation angle detection unit 107.

[0017] 2 is a diagram showing the relationship between the core allocation and the motor current control block of the motor control device according to the first embodiment, and is a block diagram focusing on the input of three-phase motor current values ​​(Iu, Iv, Iw) to an ASIL side core (Core0 209: calculation side core, also called the first core) and a QM side core (Core1 208: reference side core, also called the second core). In FIG. 2, an analog-to-digital conversion circuit ADC and a current detection unit 201 (corresponding to the current detection unit 103 in FIG. 1) are shown. Here, ASIL is an abbreviation for Automotive Safety Integrity Level, and QM is an abbreviation for Quality Management level.

[0018] The current detection unit 201 has motor current values ​​(Iu_Lv2 205, Iv_Lv2 206, Iw_Lv2 207) for the ASIL side core (Core0 209) and motor current values ​​(Iu_Lv1 202, Iv_Lv1 203, Iw_Lv1 204) for the QM side core (Core1 208). The ASIL side core (Core0 209) calculates data (first calculated data Da) based on the motor current values ​​(Iu_Lv2 205, Iv_Lv2 206, Iw_Lv2 207) as a first data group. Moreover, the QM-side core (Core1 208) calculates data (second calculated data Db) based on the motor current values ​​(Iu_Lv1 202, Iv_Lv1 203, Iw_Lv1 204) as the second data group.

[0019] The QM side core (Core1 208) may receive a value (Da) calculated by the ASIL side core (Core0 209), compare it with a value (Db) calculated by the QM side core (Core1 208), and perform a diagnosis to determine whether or not the values ​​(Da, Db) are within a threshold. In this case, if the data (Da, Db) calculated based on the motor current values ​​(Iu_Lv2 205, Iv_Lv2 206, Iw_Lv2 207) and the motor current values ​​(Iu_Lv2 205, Iv_Lv2 206, Iw_Lv2 207) as data groups of the same period are not compared, a misdiagnosis may occur. Here, since the ASIL-side core (Core0 209) merely performs the calculation process of the first calculation data Da, it is assumed that there is no infringement from the QM-side core (Core1 208).

[0020] 3 is a timing chart showing the update timing and reference timing of three-phase current values ​​(Iu, Iv, Iw) to explain the problem. This is a timing chart showing the update timing of the motor current values ​​(Iu_Lv2 304, Iv_Lv2 305, Iw_Lv2 306) of the ASIL side core (Core0 209) and the motor current values ​​(Iu_Lv1 301, Iv_Lv1 302, Iw_Lv1 303) of the QM side core (Core1 208).

[0021] At timing t1 308, the motor current values ​​(Iu_Lv2 304, Iv_Lv2 305, Iw_Lv2 306) as the first data group and the motor current values ​​(Iu_Lv1 301, Iv_Lv1 302, Iw_Lv1 303) as the second data group are all current values, and there is no problem with the data to be diagnosed (simultaneity of the first data group and the second data group is guaranteed). However, at timing t2 307, when Core 1 208 receives the ASIL motor current values ​​(Iu_Lv2 304, Iv_Lv2 305, Iw_Lv2 306) from Core 0 209 and performs diagnosis, the timing of the V-phase current value (ASIL: Iv_Lv2 305, QM: Iv_Lv1 302) and the W-phase current value (ASIL: Iv_Lw2 306, QM: Iw_Lv1 303) do not match the previous values ​​(Iv_Lv2 305, Iw_Lv2 306) and the current values ​​(Iv_Lv1 302, Iw_Lv1 303). For this reason, data of the same period (here, all current values) should be compared as in timing t1 308, but data of different periods (here, current value and previous value) are compared as in timing t2 307, which may lead to erroneous diagnosis. Also, the data communicating between cores among these are motor current values ​​(Iu_Lv2, Iv_Lv2, Iw_Lv2) for ASIL.

[0022] FIG. 4 is a diagram showing a method for ensuring concurrency of data between cores using a double buffer according to a comparative example.

[0023] In order for Core 1 401 to access a group of data that has been synchronized, it prepares two buffers (a first side of the double buffer 403 (also called Data 1 403) and a second side of the double buffer 404 (also called Data 2 404)) and accesses the group of data once it has been synchronized. When controlled by multiple cores, Core 1 401 and Core 0 402 process asynchronously, so there is a possibility that Core 1 401 and Core 0 402 may write (or calculate) and reference the same buffer at the same time. For this reason, if Core 0 402 writes data and Core 1 401 references the data, Core 0 402 on the writing side needs to specify the reference destination of Core 1 401's data. In Fig. 4, when Core 0 402 writes data to Data 2 404, it is necessary to prohibit Core 1 401 from accessing Data 2 404 during that time (while the data is being written). In other words, by Core 0 402 sending a reference notification 405 to Core 1 401, the simultaneous access of Core 1 401 and Core 0 402 to the same buffer is prohibited, thereby guaranteeing the concurrency of the data group.

[0024] FIG. 5 is a flowchart of processing by a calculation side core of a double buffer using flags according to a comparative example, and is a flowchart of processing by Core 0 402 (data calculation side core: also referred to as data writing side core) in FIG.

[0025] In the branch process 501, the ON / OFF state of the flag is confirmed. Here, for example, the ON flag can be a high level value such as "1", and the OFF flag can be a low level value such as "0". For double buffering, the ON or OFF value of the flag controls the write destination. If the flag is OFF in the branch process 501 (true: YES), the first side (403) of the double buffer is updated in the process 502, the flag is turned ON in the process 503, and the reference destination is notified to the Core 1 401, which is the reference side, in the process 506 so as to refer to the first side (403) of the double buffer. Also, if the flag is ON in the branch process 501 (false: NO), the second side (404) of the double buffer is updated in the process 504, and the flag is turned OFF in the process 505. Then, the reference destination is notified to the Core 1 401, which is the reference side, in the process 506 so as to refer to the second side (404) of the double buffer. In this way, until the reference destination notification 405 is performed in process 506, Core 1 401 refers to data different from the calculation destination.

[0026] FIG. 6 is a flowchart of processing by a reference core of a double buffer using flags according to a comparative example, and is a flowchart of processing by Core 1 401 (data reference core).

[0027] The flag notified in process 506 in FIG. 5 is judged in branch process 601. Branch process 601 can also be called a process for selecting a reference destination. If the flag is OFF in branch process 601 (YES), the second side (404) of the double buffer is referenced in reference process 602. If the flag is ON in branch process 601 (NO), the first side (403) of the double buffer is referenced in reference process 603. The method shown in FIG. 5 and FIG. 6 is used to ensure data concurrency using the double buffer (403, 404). However, this method has a problem in that it cannot be applied when the branch process 601 is involved and the processing load of Core 1 401 cannot be increased even slightly.

[0028] Fig. 7 is a diagram illustrating a method for ensuring concurrency of data between cores using a double buffer according to the embodiment 1. Fig. 7 illustrates data exchange using a double buffer without using the flags described in Fig. 5 and Fig. 6, and illustrates a method for controlling the access destination of the double buffer by an address.

[0029] The double buffer DDB has a first data buffer (hereinafter also referred to as the first side) 703 and a second data buffer (hereinafter also referred to as the second side) 704 as data buffers. Here, we consider a case where the first side 703 and the second side 704 of the double buffer DDB have fixed top addresses. Here, for example, the first side 703 has top address 703AD, and the second side 704 has top address 704AD. Then, by using the top address (703AD or 704AD) in place of a flag, the concurrency of the control data group is guaranteed. For example, when Core 0 702, the data calculation core (writing core), finishes writing the first write data Da1 as the first calculated data Da to the first side 703 of the double buffer DDB, Core 0 702 notifies 706 the reference address to Core 1 701, the data reference core, of the address 705 of the data that references the starting address 703AD of the first side 703.

[0030] Core 1 701 accesses the data (Da1) of the first side 703 of the double buffer DDB via the notified address 705 (here, the first address 703AD). The referencing core Core 1 701 receives the value (Da1) calculated by the writing core Core 0 702 and compares it with the value calculated by the referencing core Core 1 701 (first comparison data Db1 of the second calculated data Db) to perform a diagnosis to determine whether it is within a threshold value. It is assumed that the first write data Da1 and the first comparison data Db1 are based on data of the same period.

[0031] That is, the calculation core (Core 0 702) calculates data (first write data Da1 of the first calculated data Da) based on the motor current values ​​(Iu_Lv2 205, Iv_Lv2 206, Iw_Lv2 207) as the first data group. Also, the QM core (Core 1 701) calculates data (first comparison data Db1 of the second calculated data Db) based on the motor current values ​​(Iu_Lv1 202, Iv_Lv1 203, Iw_Lv1 204) as the second data group. The first data group and the second data group are data of the same period. Here, the data Da1 is one or more data based on the motor current values ​​(Iu_Lv2 205, Iv_Lv2 206, Iw_Lv2 207), and may be, for example, the current values ​​of the motor current values ​​(Iu_Lv2 205, Iv_Lv2 206, Iw_Lv2 207). Similarly, the data Db1 is one or more data based on the motor current values ​​(Iu_Lv1 202, Iv_Lv1 203, Iw_Lv1 204), and may be, for example, the current values ​​of the motor current values ​​(Iu_Lv1 202, Iv_Lv1 203, Iw_Lv1 204).

[0032] Also, for example, when Core 0 702 finishes writing the second write data Da2 of the first calculated data Da to the second side 704 of the double buffer DDB, Core 0 702 notifies Core 1 701 of the reference address 706, using the start address 704AD of the second side 704 as the address 705 of the referenced data.

[0033] Core 1 701 calculates the address 705 of the data to be referenced via the notified address (start address 704AD), and uses the address 705 to access the data (Da2) on the second side 704 of the double buffer DDB. The referencing core Core 1 701 refers to and receives the value (Da2) calculated by the writing core Core 0 702, compares it with the value calculated by the referencing core Core 1 701 (second comparison data Db2 of the second calculated data Db), and performs a diagnosis to determine whether it is within a threshold value. Here, the second write data Da2 and the second comparison data Db2 are based on data of the same period.

[0034] That is, the calculation side core (Core 0 702) calculates data (second write data Da2 of the first calculated data Da) based on the next motor current values ​​(Iu_Lv2 205, Iv_Lv2 206, Iw_Lv2 207) as the next first data group. Also, the QM side core (Core 1 701) calculates data (second comparison data Db2 of the second calculated data Db) based on the next motor current values ​​(Iu_Lv1 202, Iv_Lv1 203, Iw_Lv1 204) as the next second data group. The first data group and the second data group are data of the same next period. Here, the data Da2 is one or more data based on the motor current values ​​(Iu_Lv2 205, Iv_Lv2 206, Iw_Lv2 207), and may be, for example, the current values ​​of the motor current values ​​(Iu_Lv2 205, Iv_Lv2 206, Iw_Lv2 207). Similarly, the data Db2 is one or more data based on the motor current values ​​(Iu_Lv1 202, Iv_Lv1 203, Iw_Lv1 204), and may be, for example, the current values ​​of the motor current values ​​(Iu_Lv1 202, Iv_Lv1 203, Iw_Lv1 204).

[0035] Here, the motor current values ​​(Iu_Lv2 205, Iv_Lv2 206, Iw_Lv2 207) as the first data group related to the calculation of the first write data Da1 and the motor current values ​​(Iu_Lv2 205, Iv_Lv2 206, Iw_Lv2 207) as the first data group related to the calculation of the second write data Da2 are in a relationship between a current value and a next value in the next cycle following the current value, or in a relationship between a previous value and a current value in the next cycle following the previous value. Similarly, the motor current values ​​(Iu_Lv1 202, Iv_Lv1 203, Iw_Lv1 204) as the second data group used to calculate the first comparison data Db1 and the motor current values ​​(Iu_Lv1 202, Iv_Lv1 203, Iw_Lv1 204) as the second data group used to calculate the second comparison data Db2 have a relationship between a current value and a next value in the next cycle following the current value, or a relationship between a previous value and a current value in the next cycle following the previous value.

[0036] In this case, it is assumed that Core 1 701 can know the address where the calculated data (Da1, Da2) of Core 0 702 has been written if it knows the start address 703AD of the first side 703 or the start address 704AD of the second side 704. For example, Core 1 701 knows in advance that Core 0 702 will write the data (Da1, Da2) to an address space (area) where a specific address (ADD1, ADD2) has been added to the start address (703AD or 704AD). In other words, in the data (Da1, Da2), data Da1 is stored at the address (703AD+ADD1), and data Da2 is stored at the address (704AD+ADD2).

[0037] In this way, by calculating the address 705 of the referenced data (Da1, Da2) using the start address 703AD of the first side 703 or the start address 704AD of the second side 704, Core 1 701 can access the double buffer DDB without being aware of the first side 703 or the second side 704 of the double buffer DDB. In other words, since it is no longer necessary to use the flag described in the comparative example, branching processing of the flag value is not required.

[0038] In this example, the start address 703AD or the start address 704AD is notified, but is not limited to this. If the address to which Core 0 702 writes data is a predetermined first write address on the first side 703 or a predetermined second write address on the second side 704, the predetermined first write address or the predetermined second write address may be notified to Core 1 701 by the reference address notification 706.

[0039] FIG. 8 is a flowchart of the process of the calculation side core in the double buffer using address reference according to the first embodiment, that is, the process of the calculation side core, that is, the writing side core (Core 0 702). In the branch process 801, it is determined whether the head address notified to the reference side core (Core 1 701) (i.e., the head address of the buffer referenced by the reference side core 701) is the same as the head address of the first side 703 of the double buffer DDB. If the head address notified to the reference side core (Core 1 701) is the same as the head address (703AD) of the first side 703 (true: YES), the update process 802 updates or writes the data (Da2) of the second side 704 of the double buffer DDB, and the notification process 804 notifies the reference side core (Core 1 701) of the head address (704AD) of the double buffer DDB to be referenced. If the branch process 801 determines that the starting address to be notified to the referencing core (Core 1 701) is different from the starting address (703AD) of the first side 703 (No), the update process 803 updates or writes the data (Da1) of the first side 703 of the double buffer DDB, and the notification process 804 notifies the referencing core (Core 1 701) of the starting address (703AD) of the double buffer DDB to be referenced.

[0040] 9 is a flowchart of the process of the referencing core in the double buffer using address reference according to the first embodiment, and is a flowchart of the process of the referencing core (Core 1 701). The head address (704AD or 703AD) notified in the save process 901 is saved or stored in a local storage device or register. In process 902, the head address (704AD or 703AD) is used to access data (Da1 or Da2) on the first side 703 or the second side 704 of the double buffer DDB.

[0041] The motor control device 109 of the first embodiment described above can be summarized as follows. That is, the motor control device 109 is a motor control device that uses a multi-core semiconductor device 108 including a first core 702 and a second core 701 to diagnose three-phase current values ​​(Iu, Iv, Iw) required for controlling the motor 101 using the first core 702 and the second core 701. The first core 702 calculates first calculated data Da (Da1) based on a first data group (Iu_Lv2, Iv_Lv2, Iw_Lv2) related to the three-phase current values ​​(Iu, Iv, Iw) and writes the first calculated data Da (Da1) to a buffer (DDB, 703). The second core 701 calculates second calculated data Db (Db1) based on a second data group (Iu_Lv1, Iv_Lv1, Iw_Lv1) related to the three-phase current values ​​(Iu, Iv, Iw).

[0042] Then, the second core 701 reads the first calculated data (Da1) written by the first core 702 to the buffer 703, compares the first calculated data (Da1) with the second calculated data (Db1), and performs a diagnosis to determine whether the first calculated data (Da1) and the second calculated data (Db1) are within a threshold value, by directly referencing the first calculated data (Da1) written by the first core 702 to the buffer 703 using the address of the buffer (DDB, 703) and reading it.

[0043] In addition, when the second core 701 accesses the first calculated data (Da1) calculated by the first core 702 after the first calculated data (Da1) of the first core 702 and the second calculated data (Db1) of the second core 701 have been calculated, the motor control device 109 compares the first calculated data (Da1) of the first core 702 calculated in the current cycle with the second calculated data (Db1) of the second core 701.

[0044] In addition, when the buffer DDB is composed of multiple buffers (703, 704), and the first core 702 stores the first calculated data (Da1, Da2) in the multiple buffers (703, 704), the second core 701 receives an address (703AD or 704AD) indicating which buffer (703 or 704) the first core 702 used for the calculation, and the second core 701 uses the address (703AD or 704AD) to access the first calculated data (Da1 or Da2) in the corresponding buffer (703 or 704).

[0045] (Effects of Example 1) By using the methods of Figures 8 and 9, since flags are not used, there is no need to include branching processing in the referencing core (Core 1 701), and the processing load of the multi-core semiconductor device, and even the processing load of the referencing core (Core 1 701), can be reduced more than the double-buffer concurrency assurance method of the comparative example. EXAMPLES

[0046] The second embodiment is based on the premise that different cores perform control using calculated data (also called output data) of the same periodic task. In the first embodiment, the writing side core (Core 0 702) is provided with a process for selecting (notifying) which buffer (first surface 703 or second surface 704) to write to, whereas the second embodiment is described below with a process for selecting (notifying) which buffer (first surface 703 or second surface 704) to write to in the reference side core (Core 1 701).

[0047] FIG. 10 is a flowchart of the process of the calculation side core in the double buffer using address reference according to the second embodiment, and is a flowchart of the process of the calculation side core (Core 0 702) when the process of selecting (notifying) which buffer (first side 703 or second side 704) to write to is inserted in the reference side core (Core 1 701). In the save process 1001, the address (start address: 704AD or 703AD) of the calculation destination buffer (703 or 704) notified by the reference side core (Core 1 701) is saved or stored in a local storage device or register to prevent the address of the calculation destination being rewritten during calculation. In process 1002, the address (704AD or 703AD) is used to access the first calculation data (Da1, Da2) of the first side 703 or the second side 704 of the double buffer DDB.

[0048] FIG. 11 is a flowchart of the process of the referencing core in the double buffer using address reference according to the second embodiment. FIG. 11 is a flowchart of the process of the referencing core (Core 1 701) when a process of selecting which buffer to write to is inserted in the referencing core (Core 1 701). In the branch process 1101, it is determined whether the first address (704AD or 703AD) of the first side 703 of the double buffer DDB and the buffer (703 or 704) referenced by the calculating core (Core 0 702) are the same. If the branch process 1101 is true (YES), in the reference process 1102, the first calculated data (Da1) in the first side 703 of the double buffer DDB is referenced. Then, in the notification process 1104, the calculating core (Core 0 702) is notified to calculate the first calculated data (Da2) in the second side 704 of the double buffer DDB. If the result of branch process 1101 is NO, then reference process 1103 refers to the first calculated data (Da2) in the second side 704 of the double buffer DDB, and notification process 1105 notifies the calculation side core (Core 0 702) to calculate the first calculated data (Da1) in the first side 703 of the double buffer DDB.

[0049] The motor control device 109 of the second embodiment described above can be summarized as follows: That is, when the buffer DDB is composed of multiple buffers (703, 704) and the first core 702 stores the first calculated data (Da1, Da2) in the multiple buffers (703, 704), the first core 702 receives an address (703AD or 704AD) indicating which buffer (703 or 704) the second core 701 referenced among the multiple buffers (703, 704), and the first core 702 uses the address (703AD or 704AD) to calculate the first calculated data (Da1 or Da2) in the other buffer (704 or 703: the other buffer of the double buffers 703 and 704) while avoiding the buffer (703 or 704: one of the double buffers 703 and 704) being referenced by the second core 701.

[0050] (Effects of Example 2) By using the first and second embodiments in combination, it is possible to deal with the need to reduce the processing load of either the calculation core (Core 0 702) or the reference core (Core 1 701) of the multi-core semiconductor device, that is, the calculation / reference processing core. In the first embodiment, the processing load of the reference core (Core 1 701) can be reduced, and in the second embodiment, the processing load of the calculation core (Core 0 702) can be reduced. EXAMPLES

[0051] This third embodiment is based on the premise that control is performed using calculated data in different cores. In addition, it is based on the premise that the processes using these calculated data do not know that they are calculated in the same periodic task. FIG. 12 is a diagram showing data exchange in a double buffer using a timestamp according to the third embodiment. FIG. 13 is a flowchart of calculation side processing in a double buffer using a timestamp and address reference according to the third embodiment. FIG. 14 is a flowchart of reference side processing in a double buffer using a timestamp and address reference according to the third embodiment.

[0052] In FIG. 12, the above preconditions and the method shown in the first embodiment are combined. In FIG. 12, when Core 0 1202 is the data calculation core and Core 1 1201 is the data reference core, Core 1 1201 knows which buffer (first surface 1203, second surface 1204) of which double buffer DDB to access from the reference address notification process 1206, as in the first or second embodiment. In FIG. 12, the start address 1203AD of the first surface 1203 and the start address 1204AD of the second surface 1204 are set, and the start address 1203AD of the first surface 1203 or the start address 1204AD of the second surface 1204 is notified to Core 1 1201 by the reference address notification process 1206. Core 1 1201 calculates address 1205 of the data to be referenced via the notified start address 1203AD of the first side 1203 or start address 1204AD of the second side 1204, and uses address 1205 to access the first calculated data (Da1) of the first side 1203 or the first calculated data (Da2) of the second side 1204 of the double buffer DDB. By calculating address 1205 of the data to be referenced using start address 1203AD of the first side 1203 or start address 704AD of the second side 1204, it is possible to access the double buffer DDB without being aware of the first side 1203 or second side 1204 of the double buffer DDB.

[0053] Even if the reference address is known, Core 1 1201 cannot guarantee the concurrency of data if the control period (calculation period) of the calculation process is unknown. Therefore, Core 0 1202 assigns a first timestamp 1208 to the stored data (Da1) of the first side 1203 after the first calculated data (Da1) is stored in the first side 1203 of the double buffer DDB (or at the time of calculation). In addition, Core 0 1202 assigns a first timestamp 1209 to the stored data (Da2) of the second side 1204 after the first calculated data (Da2) is stored in the second side 1204 of the double buffer DDB (or at the time of calculation). Core 1 1201 also assigns a second timestamp 1207 to the second calculated data (Db1, Db2) when it calculates the second calculated data (Db1, Db2) on its own core. Core 1 1201 can access the first timestamp (1208, 1209) given by Core 0 1202 via the address (address 1205 of the reference data: first address 1203AD or 1204AD of the reference) notified by the reference address notification process 1206 from Core 0 1202. Using this first timestamp (1208, 1209) and second timestamp 1207, it is determined whether the data was calculated in the same cycle.

[0054] FIG. 13 is a flowchart of the process of the calculation side core (Core 0 1202) described in FIG. 12. In branch process 1301, it is determined whether the first address (1203AD or 1204AD) of the buffer referenced by the first side 1203 of the double buffer DDB and the reference side core (Core 1 1201) is the same. If the result of branch process 1301 is true (YES), the first calculated data (Da2) of the second side 1204 of the double buffer DDB is updated or written in update process 1302, and the first timestamp 1209 of the second side 1204 of the double buffer DDB is updated in update process 1304. If the result of branch process 1301 is no (NO), the first calculated data (Da1) of the first side 1203 of the double buffer DDB is updated or written in process 1302, and the first timestamp 1208 of the first side 1203 of the double buffer DDB is updated in update process 1305. Then, in a notification process 1306, the reference side core (1201) is notified of the start address (1203AD or 1204AD) of the buffer to be referenced.

[0055] Fig. 14 is a flowchart of the process of the referencing core (1201) described in Fig. 12. The address (1203AD or 1204AD) notified to the referencing core (1201) from the calculating core (1202) in the save process 1401 is saved or stored in a local storage device or register, thereby preventing the address of the reference destination from being rewritten. Then, the notified address is used in process 1402 to access the first calculated data (Da1 or Da2) in the buffer (1203 or 1204). Up to this point, it is the same as Fig. 9, but it is necessary to check whether the first calculated data (Da1 or Da2) accessed in process 1402 is guaranteed to be simultaneous with the second calculated data (Db1 or Db2) created by the referencing core (1201) before using it. Therefore, in the branch process 1403, it is confirmed whether the absolute value of the difference between the second timestamp (1207) of the second calculated data (Db1, Db2) of the referencing core (1201) and the first timestamp (1208, 1209) of the first calculated data (Da1 or Da2) of the calculating core (1202) is within the allowable range. In this case, within the allowable range means within the calculation period of the calculating core (1202), and can be within 100 μs, for example. If the branch process 1403 is true (YES), as in the use process 1404, it is assumed that the first calculated data (Da1 or Da2) of the calculating core (1202) and the second calculated data (Db1, Db2) of the referencing core (1201) are synchronized (treated as synchronized data), and the data of the calculating core (1202) obtained via the notified address (current value data: see FIG. 2) is used. If the answer is No in the branch process 1403, the data (current value data) of the calculation side core (1202) is not used, and the previous value is used. In other words, when the absolute value of the timestamp difference is outside the allowable range, the previous value data is used as the most recent data with concurrency.

[0056] In this way, the referencing core (1201) can always use data with guaranteed concurrency.

[0057] (Modification) In Example 1-3, in the case of data from different cores and with the same cycle, a configuration has been described in which the second core (referencing core 701, 1201, Core 1) accesses the first calculated data (Da1 or Da2) of the first core (calculating core 702, 1202, Core 0) only after the first calculated data (Da1 or Da2) of the first core and the second calculated data (Db1 or Db2) of the second core have been calculated, and then the second calculated data (Db1, Db2) of the second core calculated in the current cycle is compared with the data of the first core (Da1, Da2); however, this is not limited to this.

[0058] For example, in the case of data of different cores and the same period, if the timing when the second core (referring core 701, 1201, Core 1) accesses the first calculated data (Da1, Da2) of the first core (calculating core 702, 1202, Core 0) is always before the first calculated data (Da1, Da2) of the first core is newly calculated (the previous value before the data of the current value), the second core saves the second calculated data (Db1, Db2) of the previous period (previous value). Then, the second core compares the saved second calculated data of the previous period (previous value) with the first calculated data (Da1, Da2) of the previous period (previous value) calculated by the first core. Even in this configuration, the referencing core (701, 1201) can always use data whose simultaneity is guaranteed. [Explanation of symbols]

[0059] 101...Motor section 102...Inverter circuit 103...Current detection unit 103...Current detection unit 104...Current control unit 105...Current command section 106...Three-phase voltage conversion section 201...Current detection unit 202…U-phase current value for QM 203…V-phase current value for QM 204…W-phase current value for QM 205…U-phase current value for ASIL 206…V-phase current value for ASIL 207…W-phase current value for ASIL 208…Core QM allocation 209…ASIL-assigned Core 301…QM U-phase current value timing chart 302…QM V-phase current value timing chart 303…QM W-phase current value timing chart 304…ASIL U-phase current value timing chart 305…ASIL V-phase current value timing chart 306…ASIL W-phase current value timing chart 307…Time when QM and ASIL data cannot be synchronized 308…Timing when QM and ASIL data can be synchronized 401…Core QM allocation 402…ASIL-assigned Core 403...First side of double buffer 404...Second side of double buffer 405…Reference destination notification 501... Branching process 502... Processing if branch 501 is true 503: Processing if branch 501 is true 504: Processing if branch 501 is negative 505... Processing if branch 501 is negative 506...Notification of the referral destination to the referrer 601... Reference selection process 602... Processing the second side of the double buffer 603... Processing the first side of the double buffer 701…Core QM allocation 702…ASIL-assigned Core 703...First side of double buffer 704...2nd side of double buffer 705...Address of the data to be referenced 706...Referred address notification 801...Branch processing 802...Update the second side of the double buffer 803...Update the first side of the double buffer 804...Notifies the reference side of the start address of the buffer to be referenced 901: The address of the referenced buffer notified by the calculation side is saved locally. 902: Buffer access process using address 1001: The address of the destination buffer notified by the reference side is saved locally. 1002: Buffer access process using address 1101...Branch processing 1102... First page of double buffer is referenced and processed 1103... Processing the second side of the double buffer 1104...Notification to the calculation side to calculate on the second side of the double buffer 1105...Notification to the calculation side to calculate on the first side of the double buffer 1201…Core QM allocation 1202…ASIL-assigned Core 1203...first side of double buffer 1204...2nd side of double buffer 1205...Address of the data to be referenced 1206...Referred address notification 1207…Timestamp of data created on Core 1 1208...Timestamp of the first side of the double buffer created on Core 0 1209…Timestamp of the second side of the double buffer created on Core 0 1301...Branch processing 1302...Update the second side of the double buffer 1303...Update the first side of the double buffer 1304...Update timestamp of second side of double buffer 1305...Update timestamp of first side of double buffer 1306...Notify the reference side of the start address of the buffer to be referenced 1401: Locally saves the address of the referenced buffer notified by the calculation side 1402: Buffer access process using address 1403...Branch processing 1404: Processing using data obtained via the notified address

Claims

1. A motor control device that uses a multi-core semiconductor device including a first core and a second core to diagnose three-phase current values ​​required for controlling a motor, using the first core and the second core, the first core calculates first calculation data based on a first data group related to the three-phase current values ​​and writes the first calculation data to a buffer; The second core calculates second calculation data based on a second data group related to the three-phase current values; the second core reads out the first calculated data written by the first core to the buffer, compares the first calculated data with the second calculated data, and, when performing a diagnosis of determining whether the first calculated data and the second calculated data are within a threshold, directly references and reads out the first calculated data written by the first core to the buffer by using an address of the buffer. Motor control device.

2. 2. The motor control device according to claim 1, A motor control device that compares the first calculated data of the first core calculated in a current cycle with the second calculated data of the second core when the second core accesses the first calculated data calculated by the first core after the first calculated data of the first core and the second calculated data of the second core have been calculated.

3. 2. The motor control device according to claim 1, A motor control device wherein, when the second core accesses the first calculated data calculated by the first core before the first calculated data of the first core is calculated, the second core saves the second calculated data of the previous cycle calculated in the previous cycle, and compares the saved second calculated data of the previous cycle with the first calculated data of the previous cycle calculated by the first core.

4. 2. The motor control device according to claim 1, The buffer is composed of a plurality of buffers, A motor control device, wherein when the first core stores the first calculated data in the multiple buffers, the second core receives an address indicating which of the multiple buffers the first core stored the calculation in, and the second core uses the address to access the first calculated data in the corresponding buffer.

5. 2. The motor control device according to claim 1, The buffer is composed of a plurality of buffers, A motor control device, wherein when the first core stores the first calculated data in the multiple buffers, the first core receives an address indicating which of the multiple buffers the second core referenced, and the first core uses the address to calculate the first calculated data in another buffer, avoiding the buffer being referenced by the second core.

6. 2. The motor control device according to claim 1, A motor control device, in a case where a calculation period of the first calculated data of the first core and the second calculated data of the second core is unknown, a first timestamp is assigned when the first calculated data is calculated, and a second timestamp is assigned when the second calculated data is calculated, and when an absolute value of the difference between the first timestamp and the second timestamp is within an acceptable range, the data are treated as being synchronized.

7. 7. The motor control device according to claim 6, When the absolute value of the difference between the first timestamp and the second timestamp is outside an acceptable range, the first calculated data and the second calculated data are not used, and the latest first calculated data and second calculated data that have achieved synchronicity are compared.

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