Reactance compensation circuit

Abstract

To provide a reactance compensation circuit capable of achieving both an increase in a compensation range of a reactance and an increase in power consumption.SOLUTION: A reactance compensation circuit 8 includes three phase adjustment main circuits 3(1) to 3(3), which are connected in series to a load 1 to which power is supplied from a power transmission circuit 2. A signal generation circuit 5 outputs a common control signal 1 to drive circuits 7(1) to 7(3) provided correspondingly to the main circuits 3(1) to 3(3) based on phase information of an output voltage Vs obtained from the power transmission circuit 2. A delay units 6(1) to 6(3) provided on input sides of the drive circuits 7(1) to 7(3) delay a phase of the control signal 1 by different delay amounts, respectively.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a circuit for compensating for reactance in an apparatus that supplies power to a load from a power transmission circuit. [Background technology]

[0002] For example, Patent Document 1 discloses a configuration for compensating for the reactance component of an antenna, which is a load, in a wireless power supply device in order to adjust the resonant frequency. In Patent Document 1, the reactance is compensated for by operating a main circuit including a capacitor and a switching element as a voltage source with a phase delay of 90 degrees from the output voltage of the power transmission circuit. In order to expand the range of reactance that can be compensated for, a configuration in which multiple main circuits are cascaded is known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2013 / 057896 Summary of the Invention [Problem to be solved by the invention]

[0004] However, when the above-mentioned cascade connection is assumed, the voltage applied to the switching element becomes higher than the desired value due to the parasitic capacitance between the wiring connecting the capacitors and switching elements, which are components constituting the main circuit, and the ground inside the drive circuit or the power transmission circuit. This restricts the withstand voltage of the switching elements used, making it difficult to expand the compensation range of the reactance as desired. Therefore, if the wiring width of the main circuit is narrowed to reduce the parasitic capacitance, the allowable current value decreases, making it impossible to meet the need for higher power.

[0005] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a reactance compensation circuit which is capable of expanding the range of reactance compensation while also achieving high power. [Means for solving the problem]

[0006] According to the reactance compensation circuit of claim 1, a plurality of main phase adjustment circuits, each having one or more switching elements and capacitors, are connected in series to a load (1) to which power is supplied from a power transmission circuit (2, 22). A signal generation circuit (5) outputs a common control signal to a plurality of delay devices (6(1) to 6(3)) provided corresponding to the plurality of main phase adjustment circuits (3(1) to 3(3), 32(1) to 32(3)) based on phase information of an output voltage obtained from the power transmission circuit. The plurality of delay devices each have a different delay phase amount, and output control signals of different phases to the corresponding drive circuits 7(1) to 7(3). Each drive circuit generates a drive signal for a switching element based on the phase of the control signal output by the corresponding delay device.

[0007] Assuming that multiple drive circuits are controlled by a common control signal, a difference in the amplitude of the current flowing through each phase adjustment main circuit will cause a difference in the amount of charge charged to the capacitor when the switching element is turned on. This difference in the amount of charge will result in a difference in the voltage applied to the switching element. In response to this, in claim 1, multiple delay devices are used to delay the phase of the control signal input to each drive circuit by different phases. This makes it possible to adjust the difference in the amount of charge charged to each capacitor to be smaller. Therefore, by reducing the difference in the voltage applied to each switching element, the reactance compensation range can be expanded and power can be increased.

[0008] Specifically, as in the reactance compensation circuit described in claim 2, the amount of delay phase imparted by a plurality of delay elements is set to be larger for a delay element corresponding to a main phase adjustment circuit located closer to the load, thereby making it possible to adjust the voltages applied to each switching element to be approximately equal. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram illustrating a configuration of a reactance compensation circuit connected to a power transmission circuit and a load according to a first embodiment. [Diagram 2] A waveform diagram showing the amount of charge stored in the capacitor C1 of each main circuit during one cycle of switching operation when the multiple drive circuits in FIG. 1 are operated by a common control signal. [Diagram 3] FIG. 1 is a waveform diagram showing the amount of charge charged in the capacitor C1 of each main circuit during one period of switching operation in the first embodiment. [Figure 4] FIG. 2 shows the reactance compensation range obtained when the multiple drive circuits in FIG. 1 are operated with a common control signal. [Diagram 5] FIG. 4 in the first embodiment [Figure 6] FIG. 2 is a diagram showing a specific configuration example of a drive circuit and a main circuit according to a second embodiment. [Figure 7] FIG. 13 is a diagram illustrating a specific configuration example of a signal generating circuit according to a third embodiment. [Figure 8] FIG. 13 is a diagram showing a configuration example of a fourth embodiment in which a signal generating circuit is also provided in a power transmitting circuit. [Figure 9] FIG. 13 is a diagram showing a configuration of a reactance compensation circuit having a phase delay correction circuit connected to a power transmission circuit and a load according to a fifth embodiment. [Figure 10] FIG. 1 is a diagram showing a specific configuration example of a phase delay correction circuit; [Figure 11] 1 is a timing chart showing the operation of a phase delay correction circuit; [Figure 12] Flowchart showing the operation of the phase delay correction circuit [Figure 13] A timing chart showing how the voltage applied to each main circuit changes depending on the operation of the phase delay correction circuit. [Figure 14] A diagram showing specific numerical examples of delay times provided by a delay device for the parasitic capacitance of the main circuit and the reactance component of the load. [Figure 15]FIG. 15 is a diagram showing variations in voltages applied to the switching elements of each main circuit that occur when an appropriate delay time is not set in FIG. 14. [Figure 16] FIG. 13 is a sixth embodiment, showing a configuration in which an LC filter circuit is mounted on both ends of a load in the first embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] (First embodiment) As shown in FIG. 1, AC power is supplied to a load 1 by a power transmission circuit 2. Three main circuits 3(1)-3(3) for phase adjustment are connected in series between the load 1 and ground. The main circuit 3 is configured by connecting two series circuits, each of which includes one switching element and one capacitor, in parallel. The switching elements SW1 and SW2 are, for example, N-channel MOSFETs. It is assumed here that the frequency of the AC power supplied by the power transmission circuit 2 is, for example, in the MHz band.

[0011] A common connection point of the switching elements SW1 and SW2 of the main circuit 3(1) is connected to the load 1. A common connection point of the capacitors C1 and C2 of the main circuit 3(1) is connected to a common connection point of the switching elements SW1 and SW2 of the main circuit 3(2). A common connection point of the capacitors C1 and C2 of the main circuit 3(2) is connected to a common connection point of the switching elements SW1 and SW2 of the main circuit 3(3). A common connection point of the capacitors C1 and C2 of the main circuit 3(2) is connected to ground.

[0012] The impedance of the load 1 is Zl (=R+jX), and the impedance seen from the power transmission circuit 2 toward the load side is Zin. In addition, the currents input to the main circuits 3(1) to 3(3), respectively, are designated as I1 to I3. The main circuits 3(1)-3(3) are controlled by a control unit 4. The control unit 4 includes a signal generating circuit 5, delay units 6(1)-6(3), and drive circuits 7(1)-7(3). The signal generating circuit 5 acquires phase information of the output voltage Vs from the power transmitting circuit 2, and outputs a control signal 1, which is a common control signal, to the delay units 6(1)-6(3). The delay units 6(1)-6(3) delay the control signal 1 by different phases to generate control signals 2-4, and output them to the drive circuits 7(1)-7(3).

[0013] The drive circuit 7(1) outputs drive signals 1 and 2 to drive the switching elements SW1 and SW2 of the main circuit 3(1) based on a control signal 2. The drive circuit 7(2) outputs drive signals 3 and 4 to drive the switching elements SW1 and SW2 of the main circuit 3(2) based on a control signal 3. The drive circuit 7(3) outputs drive signals 5 and 6 to drive the switching elements SW1 and SW2 of the main circuit 3(3) based on a control signal 4. The drive signals 2, 4, and 6 are the inverted levels of the drive signals 1, 3, and 5, respectively. The above, excluding the load 1 and the power transmission circuit 2, constitutes a reactance compensation circuit 8.

[0014] Next, the operation of this embodiment will be described. For comparison, Fig. 2 assumes that there are no delay devices 6(1)-6(3) and a common control signal 1 is output as is to the drive circuits 7(1)-7(3). The capacitor C1 is charged for a predetermined time from the timing when the switching element SW1 is turned on, but the amplitudes of the currents I1-I3 are different due to the parasitic capacitance between the wiring connecting the capacitors and switching elements, which are components constituting each main circuit, and the ground inside the drive circuit or power transmission circuit. The amplitude of the current I1 on the side closer to the load 1 is large, and the amplitude of the current I3 on ​​the side farther from the load 1 is small.

[0015] Capacitor C1 is charged and discharged during the period when switching element SW1 is on. The amount of charge Q obtained by subtracting the amount of discharge from the amount of charge is shown by hatching in the figure, and increases in the order of main circuits 3(1) to 3(3). The voltage applied to switching element SW1 is determined by the amount of charge stored in capacitor C1, so as shown in FIG. 4, it increases in the order of main circuits 3(1) to 3(3).

[0016] In contrast, in this embodiment, the control signal 1 is delayed by different phases by the delay units 6(1) to 6(3) to generate the control signals 2 to 4. In Fig. 3, the phase delay amount of the delay unit 6(3) is set to zero to make the main circuit 3(3) have the same waveform as in Fig. 2. By setting a constant phase delay amount for each of the delay units 6(1) to (2) and setting the phase delay amount of the delay unit 6(1) to be greater than that of the delay unit 6(2), it is possible to adjust the amount of electric charge Q charged in the capacitor C1 during one cycle in which the switching element SW1 is turned on to be equal in the main circuits 3(1) to 3(3).

[0017] Without the delay devices 6(1)-6(3) of this embodiment, as described above, the amount of charge stored in the capacitors C1, C2 in each of the main circuits 3(1)-3(3) would be different, and the magnitude of the voltage applied to each of the switching elements SW1, SW2 would be different, as shown in Fig. 4. Therefore, in the case of the figure, the compensation range of the reactance is limited by the main circuit 3(1), and is narrower than the range of the desired characteristics obtained in the absence of the above-mentioned parasitic capacitance.

[0018] In contrast, in the present embodiment, the difference in the amount of charge stored in the capacitors C1, C2 is eliminated by the amount of phase delay provided by the delay devices 6(1)-6(3), and the voltages applied to the switching elements SW1, SW2 of each of the main circuits 3(1)-3(3) are adjusted to be equal, as shown in FIG. 5. This makes it possible to widen the compensation range of reactance to the range with the desired characteristics that would be obtained in the absence of parasitic capacitance.

[0019] As described above, according to this embodiment, in the reactance compensation circuit 8, the three phase adjustment main circuits 3(1)-3(3) are connected in series to the load 1 to which power is supplied from the power transmission circuit 2. The signal generation circuit 5 outputs a common control signal 1 to the delay devices 6(1)-6(3) provided corresponding to the main circuits 3(1)-3(3) based on phase information of the output voltage Vs obtained from the power transmission circuit 2. The delay devices 6(1)-6(3) delay the phase of the control signal 1 by different phases, and output the control signals 2-4 to the drive circuits 7(1)-(3).

[0020] This allows adjustment so that the difference in the amount of charge stored in each capacitor C1, C2 becomes smaller. Therefore, by reducing the difference in the voltage applied when each switching element SW1, SW2 is turned on, the reactance compensation range can be expanded and power can be increased. Specifically, by setting the delay phase amount provided by the delay devices 6(1)-6(3) to increase in order of arrangement closer to the load 1, the voltages applied to each switching element SW1, SW2 can be adjusted so that they are approximately equal.

[0021] Second embodiment As shown in Fig. 6, the second embodiment shows a configuration example of a drive circuit 7. The drive circuit 7 includes a gate drive IC 13 and a pulse transformer 14. The output terminal of the gate drive IC 13 is connected to a primary coil 15 of the pulse transformer 14. The pulse transformer 14 includes two secondary coils 16 and 17, where the secondary coil 16 is of positive phase and the secondary coil 17 is of negative phase. The switching elements SW1 and SW2 of the main circuit 3 are each represented by an N-channel MOSFET. Both ends of the secondary coil 16 are connected to the gate and source of the switching element SW1, and both ends of the secondary coil 17 are connected to the gate and source of the switching element SW2.

[0022] In this way, by configuring the drive circuit 7 using the pulse transformer 14, it is possible to insulate the input and output and to drive the switching elements SW1 and SW2 at a high frequency in the MHz band. If the driving capability of the gate drive IC 13 allows it, it is also possible to drive three or more switching elements.

[0023] Third embodiment As shown in Fig. 7, the third embodiment shows an example of the configuration of a signal generating circuit 5. The signal generating circuit 5 includes a transformer 18 and a comparator 19. A sine wave voltage Vs output by the power transmitting circuit 2 is input to a primary coil 20 of the transformer 18. One end of a secondary coil 21 is connected to the ground, and the other end is connected to an inverting input terminal of the comparator 19. A non-inverting input terminal of the comparator 19 is connected to a DC power supply. The sine wave of the input voltage Vs is stepped down by the transformer 18 and input to the comparator 19, where it is converted into a control signal 1 having a rectangular wave.

[0024] (Fourth embodiment) As shown in FIG. 8, the fourth embodiment shows a configuration in which the signal generating circuit 5 is disposed inside a power transmitting circuit 22 that replaces the power transmitting circuit 2. The power transmitting circuit 22 has a resonant inverter 23 including a series circuit of an inductor and an N-channel MOSFET connected between a DC power source and ground, and a plurality of capacitors and inductors connected to the series circuit, and transmits AC power by driving the FET. In addition, since a drive circuit portion 24 that drives the FET and a signal generating circuit that generates a control signal for the drive circuit are required, the signal generating circuit 5 in the first embodiment can be shared with the signal generating circuit of the power transmitting circuit 22. In this way, by using the signal generating circuit 5 built in the power transmitting circuit 22, the reactance compensation circuit can be configured to be more compact.

[0025] Fifth embodiment As shown in Fig. 9, the reactance compensation circuit 31 of the fifth embodiment includes a main circuit 32 in place of the main circuit 3. In the main circuit 32, Zener diodes ZDi1 and ZDi2 are connected in parallel to the switching elements SW1 and SW2, respectively. The Zener diodes ZDi1 and ZDi2 are for protecting the switching elements SW1 and SW2 from overvoltage. The primary side of a transformer 33, which serves as a voltage detector for the phase adjustment main circuit, is connected to the cathode of ZDi1 and the anode of ZDi2. The secondary sides of the transformers 33(1) to 33(3) output voltages V1b to V3b obtained by stepping down the voltages V1a to V3a applied between the cathode of ZDi1 and the anode of ZDi2.

[0026] In the control unit 34 replacing the control unit 10, instead of the delay units 6(1) to 6(3), a delay unit 35 and phase delay correction circuits 36(1) and 36(2) corresponding to the correction unit are arranged. The delay unit 35 outputs the control signal 1 output from the signal generation circuit 5, delayed by, for example, up to 180 degrees, as the control signal 2. The control signal 2 is input to the phase delay correction circuits 36(1) and 36(2) and the drive circuit 7(3). The phase delay correction circuit 36(1) receives voltages V1b and V3b, generates a control signal 3, and inputs it to the drive circuit 7(1). The phase delay correction circuit 36(2) receives voltages V2b and V3b, and generates a control signal 4, which is input to the drive circuit 7(2).

[0027] 11, in the phase delay correction circuit 36, the control signal 2 is input to a triangular wave generating unit 37 consisting of a resistor element Rtr and a capacitor Ctr. The common connection point of the resistor element Rtr and the capacitor Ctr is connected to a clock terminal CLK of a D flip-flop 40 via a coupling capacitor 38 and a buffer 39.

[0028] The positive terminal of the variable DC power supply 41 is connected to ground via resistor elements 42 and 43. A common connection point of the resistor elements 42 and 43 is connected to the input terminal of the buffer 39, i.e., node A. The voltage V1b or V2b and the voltage V3b are input to a phase delay control unit 44. The phase delay control unit 44 outputs a voltage command according to the difference between the voltage V1b or V2b and the voltage V3b, and controls the voltage Vb of the variable DC power supply 41.

[0029] The preset terminal PRE of the D flip-flop 40 is connected to the ground, and the input terminal D is pulled up to the power supply. A control signal 3 or 4 is output from the output terminal Q. The output terminal Q is connected to the ground via a resistor element 45 and a capacitor 46. The output terminal Q is also connected to a common connection point of the resistor element 45 and the capacitor 46 via a resistor element 47 and a Schottky barrier diode 48. The common connection point is connected to the clear terminal CLR of the D flip-flop 40 via an inverter 49. When the level of the output terminal Q becomes low, the capacitor 46 is discharged, the output signal of the inverter 49 becomes high level, and the D flip-flop 40 is cleared.

[0030] 11, in the phase delay correction circuit 36, the voltage Vb of the variable DC power supply 41 controlled by the phase delay control unit 44 is applied as an offset to the triangular wave generated by the triangular wave generating unit 37 based on the input control signal 2. This changes the timing at which the amplitude of the triangular wave exceeds the threshold Vth of the buffer 39. In response to this change, the phase of the control signal 3 or 4 changes.

[0031] Next, the operation of the fifth embodiment will be described. The flow chart shown in FIG. 12 shows the circuit operation of the phase delay correction circuit 36. FIG. 13 shows the process in which the voltages applied to each main circuit by the phase delay correction circuit 36 ​​become closer. Only one of the phase delay correction circuits 36(1) and 36(2) always operates. FIGS. 12 and 13 show that the phase delay correction circuit 36(1) operates first, and then the phase delay correction circuit 36(2) operates. As shown in FIG. 13, after each voltage V1a(b) to V3a(b) is saturated, the phase delay correction circuit 36(1) compares the voltages V1a(b) and V3a(b) (S1; FIG. 13 (times A and B)). If (V1a(b)>V3a(b)), (S2; YES), it is determined whether the difference between the voltages V1a(b) and V3a(b) is equal to or less than the allowable value (S3).

[0032] If the difference is not equal to or less than the allowable value (S3; NO), the drive signals 1 and 2 output to the main circuit 32(1) are delayed by Δt (S7) and the process returns to step S1. The loop of steps S1 to S3 → S7 → S1 corresponds to the section from time A to time C shown in FIG. 13. If the difference is equal to or less than the allowable value (S3; YES), the phase delay correction circuit 36(2) compares the voltages V2a(b) and V3a(b) (S4; FIG. 13 (times C and D)). If the result of the determination in step S2 is "NO," the process also proceeds to step S4. If (V2a(b)>V3a(b)) (S5; YES), it is determined whether or not the difference between the voltages V2a(b) and V3a(b) is equal to or less than the allowable value (S6).

[0033] If the difference is not below the allowable value (S6; NO), the drive signals 3, 4 output to the main circuit 32(2) are delayed by Δt (S8) and the process returns to step S1. If the difference is below the allowable value (S6; YES), the process ends. The process also ends if the answer is "NO" in step S5. The end of the process corresponds to the period from time C to time E shown in FIG. 13. The above process is repeatedly executed while power is being transmitted from the power transmission circuit 2.

[0034] Here, it is assumed that the main circuit 32 is configured to support the case where the power transmission circuit 2 transmits 1.5 kW of power at an AC frequency of 6.78 MHz. Also, assuming that the parasitic capacitance of each main circuit 32 is 20 pF to 100 pF, the phase delay applied to the main circuits 32(1) and 32(2) is limited to a range of 0.1 ns to 10 ns. This limitation will be explained below.

[0035] 14 shows the phase delay setting values ​​for the parasitic capacitance and the load reactance component, which are calculated by performing a circuit simulation on the reactance compensation circuit 31 and which make the voltages applied to the switching elements SW1 and SW2 of the main circuits 32(1) to 32(3) equal. The larger the parasitic capacitance and the load reactance component, the larger the required delay amount. Even when the parasitic capacitance is 100 pF and the load reactance is 162 Ω, which is equal to the maximum compensable reactance obtained under ideal conditions with the parasitic capacitance at zero, the required delay is about 6 ns to 8 ns.

[0036] 15, when a delay greater than necessary is set, the voltage applied to the switching elements SW1 and SW2 of the main circuits 32(2) and (3) is greater than that of the main circuit 32(1) that is directly connected to the load, and the reactance compensation range is narrower than when an appropriate delay is set. From these results, the conclusion was drawn that in the sixth embodiment, the phase delay applied to the main circuits 32(1) and 32(2) is limited to a range of 0.1 ns to 10 ns. This conclusion is also applicable to the first embodiment.

[0037] Sixth embodiment 16, the sixth embodiment has a configuration in which LC filter circuits 52 and 53 are arranged on both ends of the load 1 of the first embodiment. This makes it possible to attenuate harmonic noise generated by the switching operation of the main circuit 3 in the reactance compensation circuit 8 before it flows into the load 1.

[0038] (Other embodiments) The phase adjustment main circuit may include one or more switching elements and capacitors. The number of phase adjustment main circuits may be two or four or more. The switching element is not limited to an N-channel MOSFET. The limited range of the delay time presented in the sixth embodiment is based on the conditions of the frequency, power, circuit constants, etc. in the simultaneous embodiment, and is not limited to the above limited range.

[0039] Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure. [Explanation of symbols]

[0040] In the drawing, 1 is a load, 2 is a power transmission circuit, 3 is a main circuit, 4 is a control unit, 5 is a signal generating circuit, 6 is a delay device, 7 is a drive circuit, SW1 and SW2 are switching elements, C1 and C2 are capacitors, and 8 is a reactance compensation circuit including 3 to 7.

Claims

1. A load (1) to which power is supplied from a power transmission circuit (2, 22); A plurality of phase adjustment main circuits (3(1) to 3(3), 32(1) to 32(3)) are connected in series to the load, each of which has one or more switching elements (SW1, SW2) and capacitors (C1, C2); A plurality of drive circuits (7(1) to 7(3)) provided corresponding to the plurality of phase adjustment main circuits; a signal generating circuit (5) that outputs a common drive control signal to the plurality of drive circuits based on phase information of an output voltage obtained from the power transmitting circuit; A plurality of delay devices (6(1) to 6(3)) are provided on the input sides of the plurality of drive circuits, respectively, and delay the phase of a drive control signal; The plurality of delay elements are reactance compensation circuits each having a different delay phase amount for the input drive control signal.

2. 2. The reactance compensation circuit according to claim 1, wherein the plurality of delay elements are set so that the delay amount of a delay element corresponding to a main phase adjustment circuit located closer to the load becomes larger.

3. The reactance compensation circuit according to claim 2, wherein the plurality of delay devices delay the phase of the drive signal input to each phase adjustment main circuit so that the drive signal has a phase difference of 0.1 ns to 10 ns with respect to the drive signal input to an adjacent phase adjustment main circuit.

4. a main circuit detection unit (33) provided in each of the plurality of phase adjustment main circuits and configured to detect an amplitude value of a voltage generated in the main circuit; a correction unit (36(1), 36(2)) provided in at least a part of the plurality of delay devices and configured to correct a delay amount to be applied based on a detection value of the main circuit detection unit; 4. The reactance compensation circuit according to claim 1, further comprising: Zener diodes (ZDi1, ZDi2) connected in parallel with the switching elements of the phase adjustment main circuit in order to limit a voltage applied to the switching elements.

Images