Semiconductor element and semiconductor device

Abstract

To reduce variation of a connection state of an electrode terminal.SOLUTION: A semiconductor element 30 comprises: an element surface 31; a first electrode 44A and a second electrode 44B that are formed on the element surface 31; a plurality of first electrode terminals 50 that contact with the first electrode 44A; a plurality of second electrode terminals 60 that contact with the second electrode 44B; a first area 31A on which the plurality of first electrode terminals 50 are arranged; a second area 31B on which the plurality of second electrode terminals 60 are arranged. The number of the second electrode terminals 60 per unit area in the second area 31B is lower than the number of the first electrode terminals 50 per unit area in the first area 31A. In a plan view, area of the second electrode terminal 60 is larger than area of the first electrode terminal 50.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present disclosure relates to semiconductor elements and semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor element and a wiring portion in which the semiconductor element is bonded to the wiring portion by flip-chip bonding, and a sealing resin that seals the semiconductor element and the wiring portion. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-161149 A Summary of the Invention [Problem to be solved by the invention]

[0004] The semiconductor element includes a plurality of electrode terminals that are electrically connected to the wiring portion by being bonded to the wiring portion. If the height dimensions of the plurality of electrode terminals vary, the electrical connection state between the plurality of electrode terminals and the wiring portion varies, which may cause variation in the electrical characteristics of the semiconductor device. [Means for solving the problem]

[0005] A semiconductor element according to one embodiment of the present disclosure comprises an element surface, an element back surface facing opposite to the element surface, a first electrode and a second electrode formed on the element surface, a plurality of first electrode terminals in contact with the first electrode, a plurality of second electrode terminals in contact with the second electrode, a first region in which the plurality of first electrode terminals are arranged, and a second region in which the plurality of second electrode terminals are arranged, wherein the number of the second electrode terminals per unit area in the second region is less than the number of the first electrode terminals per unit area in the first region, and when viewed from a thickness direction that is perpendicular to the element surface, the area of ​​the second electrode terminals is greater than the area of ​​the first electrode terminals.

[0006] A semiconductor element according to one embodiment of the present disclosure comprises a surface of an element, a back surface of an element facing opposite to the surface of the element, a first electrode and a second electrode formed on the surface of the element, a plurality of first electrode terminals in contact with the first electrode, a plurality of second electrode terminals in contact with the second electrode, a first region in which the plurality of first electrode terminals are arranged, and a second region in which the plurality of second electrode terminals are arranged, wherein the number of the second electrode terminals per unit area in the second region is less than the number of the first electrode terminals per unit area in the first region, and a dummy terminal is provided in the second region.

[0007] A semiconductor device according to one embodiment of the present disclosure comprises a substrate having a plurality of first surface wirings and a plurality of second surface wirings formed on a surface of the substrate, a semiconductor element mounted on both the plurality of first surface wirings and the plurality of second surface wirings, and a sealing resin that seals the semiconductor element, wherein the plurality of first electrode terminals are individually electrically connected to the plurality of first surface wirings, and the plurality of second electrode terminals are individually electrically connected to the plurality of second surface wirings.

[0008] A semiconductor device according to one embodiment of the present disclosure comprises a plurality of first leads and a plurality of second leads, a semiconductor element mounted on both the plurality of first leads and the plurality of second leads, and a sealing resin that seals the semiconductor element, wherein the plurality of first electrode terminals are individually electrically connected to the plurality of first leads, and the plurality of second electrode terminals are individually electrically connected to the plurality of second leads. Effect of the Invention

[0009] According to the semiconductor element and the semiconductor device according to an aspect of the present disclosure, it is possible to reduce the variation in the connection state of the electrode terminals. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a schematic perspective view of a semiconductor device according to a first embodiment. [Diagram 2]FIG. 2 is a schematic plan view showing the internal structure of the semiconductor device of FIG. [Diagram 3] FIG. 3 is a schematic plan view of the semiconductor device of FIG. 2 with some semiconductor elements omitted. [Figure 4] FIG. 4 is a schematic rear view of the semiconductor device of FIG. [Diagram 5] FIG. 5 is a schematic plan view of a semiconductor device. [Figure 6] FIG. 6 is a schematic cross-sectional view of the semiconductor element taken along line F6-F6 in FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view of the semiconductor device taken along line F7-F7 in FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view showing an enlargement of the first electrode terminal and its periphery in FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view showing an enlargement of the second electrode terminal and its periphery in FIG. [Figure 10] FIG. 10 is a schematic plan view of a semiconductor element of a comparative example. [Figure 11] FIG. 11 is a schematic cross-sectional view of the semiconductor element taken along line F11-F11 in FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view of a semiconductor device of a comparative example including the semiconductor element of FIG. [Figure 13] FIG. 13 is a schematic plan view of a semiconductor element in the semiconductor device of the second embodiment. [Figure 14] FIG. 14 is a schematic cross-sectional view of the semiconductor element taken along line F14-F14 in FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view of a semiconductor device. [Figure 16] FIG. 16 is an enlarged schematic cross-sectional view of the dummy terminal and its periphery in FIG. [Figure 17] FIG. 17 is a schematic plan view of a semiconductor element in the semiconductor device of the third embodiment. [Figure 18] FIG. 18 is a schematic cross-sectional view of the semiconductor element taken along line F18-F18 in FIG. [Figure 19]FIG. 19 is a schematic plan view of a semiconductor element in a semiconductor device according to a modified example. [Figure 20] FIG. 20 is a schematic plan view of a semiconductor element in a semiconductor device according to a modified example. [Figure 21] FIG. 21 is a schematic plan view of a semiconductor element in a semiconductor device according to a modified example. [Figure 22] FIG. 22 is a schematic plan view of a semiconductor element in a semiconductor device according to a modified example. [Diagram 23] FIG. 23 is a schematic plan view of a semiconductor element in a semiconductor device according to a modified example. [Figure 24] FIG. 24 is a schematic plan view of a semiconductor device according to a modified example, in which some semiconductor elements are omitted from the semiconductor device. [Diagram 25] FIG. 25 is a schematic cross-sectional view of a semiconductor device according to a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, some embodiments of the semiconductor element and the semiconductor device including the semiconductor element in the present disclosure will be described with reference to the accompanying drawings. Note that, for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0012] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0013] First Embodiment A semiconductor device 10 according to a first embodiment will be described with reference to FIGS. FIG. 1 shows a perspective structure of a semiconductor device 10 of the first embodiment. FIG. 2 shows a planar structure of the semiconductor device 10 of FIG. 1 with a sealing resin 80, which will be described later, removed. FIG. 3 shows a planar structure of a first lead 21 and a second lead 22, which will be described later, of the semiconductor device 10. FIG. 4 shows a rear structure of the semiconductor device 10. FIG. 5 shows a planar structure of a semiconductor element 30, which will be described later, of the semiconductor device 10. FIG. 6 shows a schematic cross-sectional structure of the semiconductor element 30 taken along line F6-F6 in FIG. 5. FIG. 7 shows a schematic cross-sectional structure of the semiconductor device 10 taken along line F7-F7 in FIG. 2. FIG. 8 shows a schematic cross-sectional structure of a first electrode terminal 50, which will be described later, of the semiconductor element 30 and its periphery. FIG. 9 shows a schematic cross-sectional structure of a second electrode terminal 60, which will be described later, of the semiconductor element 30 and its periphery. In FIG. 2, the sealing resin 80 is shown by a two-dot chain line in order to make the drawing easier to understand. In FIG. 3, the semiconductor element 30 is shown by a two-dot chain line in order to make the drawing easier to understand. Furthermore, the term "planar view" used in the present disclosure refers to viewing the semiconductor device 10 in the Z direction of the mutually orthogonal XYZ axes shown in Figure 1. Here, the X direction is an example of the "first direction" and the Y direction is an example of the "second direction."

[0014] [Overall configuration of semiconductor device] The overall configuration of a semiconductor device 10 will be described with reference to FIGS. As shown in FIG. 1, the semiconductor device 10 is formed in a rectangular flat plate shape with the thickness direction being the Z direction. The semiconductor device 10 has a device front surface 11 and a device back surface 12 facing opposite sides to each other in the Z direction, and four device side surfaces 13 to 16 connecting the device front surface 11 and the device back surface 12 in the Z direction. The device side surfaces 13 and 14 constitute both end surfaces of the semiconductor device 10 in the X direction, and the device side surfaces 15 and 16 constitute both end surfaces of the semiconductor device 10 in the Y direction. In the example shown in FIG. 1, the semiconductor device 10 is formed in a square shape in a plan view. The semiconductor device 10 is a surface mount type package format in which the device back surface 12 becomes a mounting surface when mounted on, for example, a circuit board (not shown). In the example shown in FIG. 1, the package format of the semiconductor device 10 is a QFN (Quad Flat Non-leaded Package) type. Note that the shape of the semiconductor device 10 in a plan view is not limited to a square shape and can be arbitrarily changed. The dimensions of the semiconductor device 10 in the X direction, Y direction, and Z direction can be arbitrarily changed. Furthermore, the package format of the semiconductor device 10 is not limited to QFN, but can be changed arbitrarily.

[0015] The semiconductor device 10 may be configured as a power conversion device such as a DC / DC converter, an AC / DC converter, etc. In the first embodiment, the semiconductor device 10 is configured as a DC / DC converter.

[0016] 2 and 3, the semiconductor device 10 includes a plurality of (three in the first embodiment) first leads 21 and a plurality of (four in the first embodiment) second leads 22, a semiconductor element 30 disposed on the plurality of first leads 21 and the plurality of second leads 22, and a sealing resin 80 that seals the plurality of first leads 21, the plurality of second leads 22, and the semiconductor element 30. The plurality of first leads 21 and the plurality of second leads 22 include portions exposed from the sealing resin 80. In FIGS. 1 and 4, each of the plurality of first leads 21 and the plurality of second leads 22 exposed from the sealing resin 80 is marked with a dot.

[0017] As shown in FIG. 1, the sealing resin 80 constitutes the external structure of the semiconductor device 10. More specifically, the sealing resin 80 is formed in a rectangular flat plate shape with the thickness direction being the Z direction. The sealing resin 80 has a sealing front surface 81 and a sealing back surface 82 facing opposite sides to each other in the Z direction, and four sealing side surfaces 83 to 86 connecting the sealing front surface 81 and the sealing back surface 82 in the Z direction. The sealing front surface 81 constitutes the device front surface 11, and the sealing back surface 82 constitutes the device back surface 12. The sealing side surface 83 constitutes the device side surface 13, the sealing side surface 84 constitutes the device side surface 14, the sealing side surface 85 constitutes the device side surface 15, and the sealing side surface 86 constitutes the device side surface 16. The sealing resin 80 also supports a plurality of first leads 21 and a plurality of second leads 22.

[0018] 2 and 3, each of the first leads 21 and each of the second leads 22 are formed of a conductive material. As the conductive material, for example, a material containing one or more appropriately selected from Ti (titanium), TiN (titanium nitride), Au (gold), Ag (silver), Cu (copper), Al (aluminum), and W (tungsten) is used.

[0019] Each of the first leads 21 and each of the second leads 22 is formed, for example, by etching a metal plate. The method of forming each of the first leads 21 and each of the second leads 22 can be changed as desired. In one example, each of the first leads 21 and each of the second leads 22 may be formed by punching, bending, or the like, a metal plate. In the following description, the multiple first leads 21 will be referred to as "first leads 21A-21C," and the multiple second leads 22 will be referred to as "second leads 22A-22D."

[0020] The first lead 21A and the first lead 21B are configured to receive DC power (voltage) to be converted in the semiconductor device 10. In the first embodiment, the first lead 21A is a positive electrode (P terminal), and the first lead 21B is a negative electrode (N terminal). The first lead 21C is configured to output AC power (voltage) converted by a switching circuit 42A (see FIG. 7) of the semiconductor element 30, which will be described later.

[0021] 3, the first leads 21A to 21C are arranged spaced apart from one another in the X direction in a plan view. The first lead 21A is arranged closer to the sealing side surface 83 than the first leads 21B and 21C. The first lead 21B is arranged closer to the sealing side surface 84 than the first leads 21A and 21C.

[0022] The first leads 21A to 21C are formed in a band shape extending in the Y direction across the sealing side surface 85 and the sealing side surface 86 in a plan view. Therefore, the first leads 21A to 21C are exposed from the sealing side surface 85 and the sealing side surface 86. The first lead 21B includes a plurality of protruding portions 21BA that protrude toward any of the sealing side surfaces 84 to 86 in a plan view. The multiple protruding portions 21BA are arranged spaced apart from each other in the Y direction. The multiple protruding portions 21BA are exposed from the sealing side surfaces 84 to 86.

[0023] 3 and 4, the first leads 21A to 21C have a first lead front surface 21S and a first lead back surface 21R facing opposite sides to each other in the Z direction. The first lead front surface 21S faces the same side as the sealing front surface 81, and the first lead back surface 21R faces the same side as the sealing back surface 82. The first lead front surface 21S is covered with the sealing resin 80. On the other hand, the first lead back surface 21R is exposed from the sealing back surface 82. The semiconductor element 30 is supported by the first lead front surfaces 21S of the first leads 21A to 21C.

[0024] In each of the first leads 21A to 21C, the area of ​​the first lead front surface 21S is larger than the area of ​​the first lead back surface 21R in a plan view. Therefore, the first leads 21A to 21C include at least one anchor portion that is a portion where the first lead front surface 21S and the first lead back surface 21R do not overlap in a plan view. Such an anchor portion can be formed, for example, by half-etching processing from the first lead back surface 21R. In each of the first leads 21A to 21C, the inclusion of the anchor portion prevents the first leads 21A to 21C from falling off the sealing back surface 82 of the sealing resin 80.

[0025] For example, Sn (tin) plating may be applied to each of the first lead back surfaces 21R of the first leads 21A-21C and the portions of the first leads 21A-21C exposed from the sealing side surfaces 84-86. Note that instead of Sn plating, multiple metal platings, for example, Ni (nickel), Pd (palladium), and Au (gold) layered in this order, may be used.

[0026] The second leads 22A to 22D constitute either a ground terminal of a control circuit 42B of the semiconductor element 30 described below, a terminal to which power (voltage) for driving the control circuit 42B is input, or a terminal to which an electrical signal is input to be transmitted to the control circuit 42B (see FIG. 7).

[0027] 3, the second leads 22A to 22D are arranged closer to the sealing side surface 83 than the first leads 21A to 21C. The second leads 22A to 22D are arranged to be spaced apart from one another in, for example, the Y direction. In one example, the second leads 22A to 22D are arranged to overlap one another when viewed from the Y direction.

[0028] As shown in Figs. 3 and 4, the second leads 22A to 22D have a second lead front surface 22S and a second lead back surface 22R facing opposite sides to each other in the Z direction. The second lead front surface 22S faces the same side as the first lead front surface 21S, and the second lead back surface 22R faces the same side as the first lead back surface 21R. The semiconductor element 30 is supported by the second lead front surfaces 22S of the second leads 22A to 22D. The second lead back surface 22R is exposed from the sealing back surface 82 of the sealing resin 80. Each of the second leads 22A to 22D includes a portion exposed from the sealing side surface 83 of the sealing resin 80.

[0029] In each of the second leads 22A to 22D, the area of ​​the second lead front surface 22S is larger than the area of ​​the second lead back surface 22R in a plan view. Therefore, the second leads 22A to 22D include at least one anchor portion that is a portion where the second lead front surface 22S and the second lead back surface 22R do not overlap in a plan view. Such an anchor portion can be formed, for example, by half-etching processing from the second lead back surface 22R. In each of the second leads 22A to 22D, the inclusion of the anchor portion prevents the second leads 22A to 22D from falling off the sealing back surface 82 of the sealing resin 80.

[0030] For example, Sn plating may be applied to each of the second lead back surfaces 22R of the second leads 22A-22D and the portions of the second leads 22A-22D exposed from the sealing side surface 83. Note that instead of Sn plating, a plurality of metal platings, for example, Ni, Pd, and Au laminated in this order, may be used.

[0031] As shown in FIG. 2, the semiconductor element 30 is disposed in the center of the semiconductor device 10 in a plan view. The semiconductor element 30 is formed in a rectangular flat plate shape with the Z direction as the thickness direction. The semiconductor element 30 includes an element front surface 31 (see FIG. 5), an element back surface 32 facing the opposite side to the element front surface 31, and element side surfaces 33 to 36 connecting the element front surface 31 and the element back surface 32 in the Z direction. The element front surface 31 faces the same side as the sealing back surface 82, and the element back surface 32 faces the same side as the sealing surface 81. Therefore, the element front surface 31 faces the first lead surfaces 21S of the first leads 21A to 21C and the second lead surfaces 22S of the second leads 22A to 22D in the Z direction. The element side surface 33 faces the same side as the sealing side surface 83, the element side surface 34 faces the same side as the sealing side surface 84, the element side surface 35 faces the same side as the sealing side surface 85, and the element side surface 36 faces the same side as the sealing side surface 86.

[0032] The element surface 31 includes a first region 31A and a second region 31B. The first region 31A and the second region 31B are aligned in the X direction. The first region 31A is disposed closer to the element side surface 34 than the second region 31B. The first region 31A and the second region 31B are rectangular regions in a plan view. The area of ​​the first region 31A is larger than the area of ​​the second region 31B. In one example, the area of ​​the first region 31A is about twice the area of ​​the second region 31B.

[0033] The first region 31A is a region of the element surface 31 facing the first leads 21A-21C in the Z direction. Therefore, it can be said that the first region 31A is a region that electrically connects the first leads 21A-21C and the semiconductor element 30. The second region 31B is a region of the element surface 31 facing the second leads 22A-22D in the Z direction. Therefore, it can be said that the second region 31B is a region that electrically connects the second leads 22A-22D and the semiconductor element 30.

[0034] The second region 31B is a region of the element surface 31 that is closer to the element side surface 33 than the first leads 21A to 21C. In one example, of both ends of the second region 31B in the X direction, the end closer to the first region 31A is disposed in a position adjacent to the first lead 21A in the X direction in a plan view.

[0035] 6, the semiconductor element 30 includes a semiconductor substrate 41, a semiconductor layer 42, a passivation film 43, a first electrode 44A, a second electrode 44B, an insulating layer 45, a plurality of first electrode terminals 50, and a plurality of second electrode terminals 60. The semiconductor layer 42, the passivation film 43, the first electrode 44A, the second electrode 44B, the insulating layer 45, the plurality of first electrode terminals 50, and the plurality of second electrode terminals 60 are provided on the semiconductor substrate 41. The semiconductor element 30 is a flip-chip type LSI (Large Scale Integration) having a circuit configured therein.

[0036] The semiconductor substrate 41 is formed in a rectangular plate shape with the thickness direction being in the Z direction. The semiconductor substrate 41 is formed of a material containing, for example, Si (silicon) or SiC (silicon carbide). The semiconductor substrate 41 includes a substrate front surface 41A and a substrate back surface 41B that face opposite each other in the Z direction. The substrate front surface 41A faces the same side as the element front surface 31, and the substrate back surface 41B faces the same side as the element back surface 32. In one example, the substrate back surface 41B constitutes the element back surface 32.

[0037] The semiconductor layer 42 is formed on the substrate surface 41A. The semiconductor layer 42 includes a plurality of types of p-type semiconductors and n-type semiconductors based on differences in the amounts of elements to be doped. The semiconductor layer 42 includes a switching circuit 42A and a control circuit 42B electrically connected to the switching circuit 42A. In other words, the semiconductor element 30 includes the switching circuit 42A and the control circuit 42B.

[0038] The switching circuit 42A is a circuit including switching elements formed of semiconductors such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors). In one example, the switching circuit 42A is divided into two areas: a high-voltage area (upper arm circuit) and a low-voltage area (lower arm circuit). Each of the high-voltage area and the low-voltage area is composed of at least one transistor. In one example, the transistor is composed of an n-channel MOSFET.

[0039] The switching circuit 42A is formed in the first region 31A. That is, the first region 31A is a region in which a first transistor and a second transistor connected in series with each other are formed. Here, the at least one transistor formed in the high voltage region (upper arm circuit) is an example of a first transistor, and the at least one transistor formed in the low voltage region (lower arm circuit) is an example of a second transistor.

[0040] The control circuit 42B includes, for example, a gate driver for driving the switching circuit 42A, a bootstrap circuit corresponding to the high voltage region of the switching circuit 42A, and the like. The control circuit 42B is configured to perform control for driving the switching circuit 42A. The control circuit 42B can be said to be a circuit for controlling the first transistor and the second transistor. The control circuit 42B is formed in the second region 31B. The semiconductor layer 42 further includes a wiring layer (not shown). The wiring layer is configured to electrically connect, for example, the switching circuit 42A and the control circuit 42B.

[0041] The passivation film 43 has electrical insulation properties and is formed to cover the semiconductor layer 42. The passivation film 43 is configured, for example, of a laminated structure of a SiO2 (silicon oxide) film and a SiN (silicon nitride) film. In one example, the surface of the passivation film 43 configures the element surface 31.

[0042] As shown in FIG. 5, the first electrode 44A and the second electrode 44B are formed on the element surface 31. That is, the first electrode 44A and the second electrode 44B are formed on the passivation film 43. A plurality of the first electrodes 44A and the second electrodes 44B are provided. The plurality of first electrodes 44A are formed in the first region 31A of the element surface 31. The plurality of first electrodes 44A are electrically connected to the switching circuit 42A. The plurality of second electrodes 44B are formed in the second region 31B of the element surface 31. The plurality of second electrodes 44B are electrically connected to the control circuit 42B.

[0043] The multiple first electrodes 44A are formed according to the number of first leads 21. In the first embodiment, three first electrodes 44A are formed according to first leads 21A to 21C (see FIG. 3), which are the three first leads 21. For convenience, the three first electrodes 44A are referred to as "first electrode 44AA," "first electrode 44AB," and "first electrode 44AC."

[0044] The first electrodes 44AA to 44AC are arranged spaced apart from each other in the X direction. Each of the first electrodes 44AA to 44AC is formed in a strip shape extending in the Y direction in a plan view. In one example, the first electrodes 44AA to 44AC have the same dimensions in the Y direction. The first electrodes 44AA to 44AC individually face the first leads 21A to 21C in the Z direction. More specifically, the first electrode 44AA faces the first lead 21A in the Z direction, the first electrode 44AB faces the first lead 21B in the Z direction, and the first electrode 44AC faces the first lead 21C in the Z direction.

[0045] The first electrode 44AA is electrically connected to the first lead 21A via a plurality of first electrode terminals 50. The first electrode 44AB is electrically connected to the first lead 21B via another plurality of first electrode terminals 50. The first electrode 44AC is further electrically connected to the first lead 21C via another plurality of first electrode terminals 50. As a result, the switching circuit 42A is electrically connected to the first leads 21A to 21C. The configuration and arrangement of the first electrode terminals 50, as well as the connection structure between the first leads 21A to 21C and the plurality of first electrodes 44A will be described later. For convenience, the first electrode terminal 50 connected to the first electrode 44AA will be referred to as the "first electrode terminal 50A", the first electrode terminal 50 connected to the first electrode 44AB will be referred to as the "first electrode terminal 50B", and the first electrode terminal 50 connected to the first electrode 44AC will be referred to as the "first electrode terminal 50C".

[0046] The multiple second electrodes 44B are formed according to the number of second leads 22. In the first embodiment, two second electrodes 44B are formed corresponding to the second leads 22A to 22D (see FIG. 3), which are the four second leads 22. For convenience, the two second electrodes 44B are referred to as "second electrode 44BA" and "second electrode 44BB."

[0047] In one example, the second electrode 44BA faces the second leads 22A and 22B in the Z direction, and the second electrode 44BB faces the second leads 22C and 22D in the Z direction. In the first embodiment, the second electrodes 44BA and 44BB are arranged at the same position in the X direction and spaced apart from each other in the Y direction. The second electrodes 44BA and 44BB are formed in a rectangular shape with the Y direction as the long side and the X direction as the short side in a plan view.

[0048] The second electrode 44BA is electrically connected to the second leads 22A, 22B via a plurality of second electrode terminals 60. The second electrode 44BB is electrically connected to the second leads 22C, 22D via another plurality of second electrode terminals 60. As a result, the control circuit 42B is electrically connected to the second leads 22A to 22D. The configuration and arrangement of the plurality of second electrode terminals 60, as well as the connection structure between the second leads 22A to 22D and the plurality of second electrodes 44B will be described later. For convenience, the second electrode terminal 60 connected to the second electrode 44BA will be referred to as the "second electrode terminal 60A," and the second electrode terminal 60 connected to the second electrode 44BB will be referred to as the "second electrode terminal 60B."

[0049] In the following description, when the first electrodes 44AA-44AC are used without distinction for the first electrodes 44A, they are simply referred to as the first electrodes 44A, and when the second electrodes 44BA, 44BB are used without distinction for the second electrodes 44B, they are simply referred to as the second electrodes 44B. Furthermore, when the first electrode terminals 50A-50C are used without distinction for the first electrode terminals 50, they are simply referred to as the first electrode terminals 50, and when the second electrode terminals 60A, 60B are used without distinction for the second electrode terminals 60, they are simply referred to as the second electrode terminals 60.

[0050] As shown in FIG. 6, the insulating layer 45 is formed on the element surface 31. The insulating layer 45 covers the passivation film 43, the first electrodes 44A, and a portion of the second electrodes 44B. The insulating layer 45 is formed of an insulating material such as a phenolic resin or a polyimide resin. The insulating layer 45 includes a plurality of first openings 45A (three in the first embodiment) and a plurality of second openings 45B (two in the first embodiment). The first openings 45A expose the first electrodes 44AA to 44AC individually. The second openings 45B expose the second electrodes 44BA and 44BB (see FIG. 5) individually.

[0051] The first electrode terminals 50A to 50C are provided individually in the multiple first openings 45A. The first electrode terminal 50A is electrically connected to the first electrode 44AA exposed from one of the first openings 45A. As shown in Fig. 5, a plurality of first electrode terminals 50A are provided. The plurality of first electrode terminals 50A are arranged at the same position in the X direction and spaced apart from each other in the Y direction.

[0052] As shown in Fig. 6, the first electrode terminal 50B is electrically connected to a first electrode 44AB exposed from another first opening 45A. As shown in Fig. 5, a plurality of first electrode terminals 50B are provided. The plurality of first electrode terminals 50B are arranged at the same position in the X direction and spaced apart from each other in the Y direction.

[0053] As shown in Fig. 6, the first electrode terminal 50C is electrically connected to a first electrode 44AC exposed from another first opening 45A. As shown in Fig. 5, a plurality of first electrode terminals 50C are provided. The plurality of first electrode terminals 50C are arranged at the same position in the X direction and spaced apart from each other in the Y direction. In one example, the number of the first electrode terminals 50A to 50C is the same as each other. Note that the number of each of the first electrode terminals 50A to 50C can be changed arbitrarily.

[0054] In this manner, the first electrode terminals 50A-50C are electrically connected to the switching circuit 42A (see FIG. 6). In other words, it can be said that the first electrode terminals 50A-50C are electrically connected to the first transistor and the second transistor. In one example, the first electrode terminal 50A is electrically connected to the drain of the first transistor. The first electrode terminal 50B is electrically connected to the source of the second transistor. The first electrode terminal 50C is electrically connected to the source of the first transistor and the drain of the second transistor.

[0055] As shown in FIG. 6, the second electrode terminals 60 are provided individually in the second openings 45B. The second electrode terminal 60A is electrically connected to the second electrode 44BA exposed from one of the second openings 45B. A plurality of second electrode terminals 60A (two in the first embodiment) are provided. The plurality of second electrode terminals 60A, the second electrode terminal 60B is electrically connected to the second electrode 44BB (see FIG. 5) exposed from another one of the second openings 45B. A plurality of second electrode terminals 60B (two in the first embodiment) are provided. As shown in FIG. 5, the plurality of second electrode terminals 60B are arranged at the same position in the X direction and spaced apart from each other in the Y direction. In this manner, the second electrode terminals 60A, 60B are electrically connected to the control circuit 42B (see FIG. 6).

[0056] The multiple first electrode terminals 50 and the multiple second electrode terminals 60 are provided on the element surface 31 side in the Z direction. As shown in Fig. 7, the semiconductor element 30 is arranged so that the element surface 31 faces the multiple first leads 21A to 21C and the multiple second leads 22A to 22D. Therefore, the first electrode terminals 50 protrude toward the first leads 21A to 21C beyond the element surface 31 in the Z direction. The second electrode terminals 60 protrude toward the second leads 22A to 22D beyond the element surface 31 in the Z direction.

[0057] [Configuration of the area surrounding the electrodes of semiconductor elements, and connection structure between the electrode terminals and leads] 2 and 7 to 9, the configuration of each first electrode 44A, each second electrode 44B and their surroundings of the semiconductor element 30, and the connection structure between the semiconductor element 30 and the first leads 21A to 21C and second leads 22A to 22D will be described.

[0058] 8, each of the first electrodes 44A is electrically connected to a wiring layer (not shown) provided on the semiconductor layer 42 through an opening (not shown) formed in the passivation film 43. As a result, each of the first electrodes 44A is electrically connected to the switching circuit 42A.

[0059] Each of the first electrodes 44A is composed of a plurality of metal layers stacked from the passivation film 43 toward the opposite side to the semiconductor layer 42. Each of the first electrodes 44A includes a first metal layer 44P, a second metal layer 44Q, and a third metal layer 44R. The first metal layer 44P is in contact with the passivation film 43. The first metal layer 44P is formed of a material containing Cu, for example. The second metal layer 44Q is stacked on the first metal layer 44P. The second metal layer 44Q is formed of a material containing Ni, for example. The third metal layer 44R is stacked on the second metal layer 44Q. The third metal layer 44R is formed of a material containing Pd, for example. The configuration and material of each of the first electrodes 44A can be arbitrarily changed.

[0060] 9, each second electrode 44B is electrically connected to a wiring layer (not shown) provided on the semiconductor layer 42 through an opening (not shown) formed in the passivation film 43. As a result, each second electrode 44B is electrically connected to the control circuit 42B. The configuration of each second electrode 44B is the same as the configuration of each first electrode 44A. Therefore, the components of each second electrode 44B are given the same reference numerals as the components of each first electrode 44A, and detailed description thereof will be omitted.

[0061] 8, first electrode terminal 50A electrically connected to first electrode 44A exposed from first opening 45A of insulating layer 45 includes a first portion embedded in first opening 45A and a second portion protruding from insulating layer 45. The second portion includes a portion overlapping insulating layer 45 on the periphery of first opening 45A in plan view.

[0062] The first electrode terminal 50 includes a first pillar portion 51 and a first solder portion 57. The first pillar portion 51 is a portion that contacts the first electrode 44A. The first solder portion 57 is provided at the tip portion of the first pillar portion 51. The first pillar portion 51 includes the first portion and the second portion.

[0063] The first pillar 51 includes a first seed layer 52, a first plating layer 53, and a first front-side plating layer 54. The first pillar 51 has a structure in which the first seed layer 52, the first plating layer 53, and the first front-side plating layer 54 are laminated in this order from the first electrode 44A side.

[0064] The first seed layer 52 is in contact with the first electrode 44A and the insulating layer 45. The first seed layer 52 is formed of a material containing Cu, for example. The first seed layer 52 is formed by electroless plating, for example. The material and the method of forming the first seed layer 52 can be changed as desired. In one example, the first seed layer 52 may be formed by a sputtering method.

[0065] The first plating layer 53 is in contact with the first seed layer 52. The first plating layer 53 is formed of a material containing Cu, for example. The first plating layer 53 is formed by electrolytic plating. Note that the material and the method of forming the first plating layer 53 can be changed as desired.

[0066] The first surface-side plating layer 54 is in contact with the first plating layer 53. The first surface-side plating layer 54 functions to suppress a chemical reaction between the first plating layer 53 and the first solder portion 57 by being interposed between the first plating layer 53 and the first solder portion 57. For this reason, a metal material capable of suppressing the chemical reaction is appropriately selected for the first surface-side plating layer 54. Examples of the metal material include Ni and Fe (iron). In one example, when the first plating layer 53 contains Cu and the first solder portion 57 contains Sn, the first surface-side plating layer 54 may be formed of a material containing Ni. The first surface-side plating layer 54 is formed by, for example, electrolytic plating. Note that the material and the method of forming the first surface-side plating layer 54 can be arbitrarily changed. A first recess 55 is formed on the tip surface 56 of the first pillar portion 51, the central portion of which is recessed from the peripheral portion. Here, the tip surface 56 of the first pillar portion 51 is the surface on the opposite side to the first electrode 44A in the Z direction, and is the surface with which the first solder portion 57 comes into contact.

[0067] The first solder portion 57 is interposed between the first pillar portion 51 and one of the first leads 21A to 21C to which the first pillar portion 51 faces, thereby electrically connecting the first pillar portion 51 and the first lead. In Fig. 8, the first solder portion 57 electrically connects the first pillar portion 51 and the first lead 21A. The first solder portion 57 is formed of, for example, a solder containing Sn (SnAg, etc.).

[0068] A first plating layer 70A is interposed between the first solder portion 57 and the first lead surface 21S of the first leads 21A to 21C in the Z direction. The first plating layer 70A electrically connects the first solder portion 57 and the first leads 21A to 21C. The first plating layer 70A serves to suppress a chemical reaction between the first leads 21A to 21C and the first solder portion 57. The material of the first plating layer 70A is not particularly limited, and a metal material capable of suppressing a chemical reaction may be appropriately selected. Examples of the metal material include Ni and Fe. In the example shown in FIG. 8, the first plating layer 70A is provided so as to cover a part of the first lead surface 21S.

[0069] The first plating layer 70A includes a laminated structure of a first layer 71, a second layer 72, and a third layer 73. The first layer 71 is laminated on the first lead surface 21S of the first leads 21A to 21C. In one example, when the first leads 21A to 21C contain Cu and the first solder portion 57 contains Sn, the first layer 71 contains Ni. The second layer 72 is laminated on the first layer 71. The material of the second layer 72 contains, for example, Pd. The third layer 73 is laminated on the second layer 72. The third layer 73 is in contact with, for example, the first solder portion 57. The material of the third layer 73 contains, for example, Au. The materials of the first to third layers 71 to 73 can be changed arbitrarily.

[0070] As shown in FIG. 9, the second electrode terminal 60 electrically connected to the second electrode 44B exposed from the second opening 45B of the insulating layer 45 includes a first portion embedded in the second opening 45B and a second portion protruding from the insulating layer 45. The second portion includes a portion overlapping with the insulating layer 45 at the periphery of the second opening 45B in a plan view. The configuration of the second electrode terminal 60 is the same as that of the first electrode terminal 50. That is, the second electrode terminal 60 includes a second pillar portion 61 and a second solder portion 67. The second pillar portion 61 includes a second seed layer 62, a second plating layer 63, and a second front surface side plating layer 64. The second pillar portion 61 is provided with a second recess 65. The tip surface 66 of the second pillar portion 61 is provided with a second solder portion 67. The components of the second electrode terminal 60 are the same as those of the first electrode terminal 50, and therefore detailed description thereof will be omitted.

[0071] The second solder portion 67 of the second electrode terminal 60 is interposed between the second pillar portion 61 and one of the second leads 22A to 22D to which the second pillar portion 61 faces, thereby electrically connecting the second pillar portion 61 and the second lead. In Fig. 9, the second solder portion 67 electrically connects the second pillar portion 61 and the second lead 22C.

[0072] The second plating layer 70B is interposed between the second solder portion 67 and the second lead surface 22S of the second leads 22A to 22D in the Z direction. The second plating layer 70B electrically connects the second solder portion 67 and the second leads 22A to 22D. The second plating layer 70B functions to suppress a chemical reaction between the second leads 22A to 22D and the second solder portion 67. The material of the second plating layer 70B is not particularly limited, and a metal material capable of suppressing a chemical reaction may be appropriately selected. Examples of the metal material include Ni and Fe. In the example shown in FIG. 9, the second plating layer 70B is provided so as to cover a part of the second lead surface 22S. The configuration of the second plating layer 70B is the same as that of the first plating layer 70A. Therefore, the same reference numerals are given to the components of the second plating layer 70B that are common to the first plating layer 70A, and the description thereof will be omitted.

[0073] [Configuration and arrangement of electrode terminals of semiconductor element] The configuration and arrangement of the first electrode terminal 50 and the second electrode terminal 60 will be described with reference to FIGS.

[0074] As shown in FIG. 5, a plurality of first electrode terminals 50 (24 in the first embodiment) are arranged in the first region 31A. A plurality of second electrode terminals 60 (4 in the first embodiment) are arranged in the second region 31B. The ratio of the area of ​​the second region 31B to the area of ​​the first region 31A is smaller than the ratio of the number of second electrode terminals 60 to the number of first electrode terminals 50. Therefore, the number of second electrode terminals 60 per unit area in the second region 31B is smaller than the number of first electrode terminals 50 per unit area in the first region 31A. Here, the number of second electrode terminals 60 per unit area in the second region 31B can be calculated by dividing the area of ​​the second region 31B from the number of second electrode terminals 60. The number of first electrode terminals 50 per unit area in the first region 31A can be calculated by dividing the area of ​​the first region 31A from the number of first electrode terminals 50.

[0075] The multiple first electrode terminals 50A, the multiple first electrode terminals 50B, and the multiple first electrode terminals 50C are arranged apart from each other in the X direction. In the example shown in FIG. 5, the multiple second electrode terminals 60 are disposed at one of both ends in the X direction of the rear surface 32 of the element that is closer to the side surface 33 of the element.

[0076] In one example, a distance D1 between the second electrode terminals 60 and the first electrode terminals 50A in the X direction is greater than a distance D2 between the first electrode terminals 50A and the first electrode terminals 50B in the X direction. Also, in one example, the distance D2 is greater than a distance D3 between the first electrode terminals 50B and the first electrode terminals 50C in the X direction.

[0077] In plan view, the first electrode terminals 50A-50C have the same shape, and the second electrode terminals 60A, 60B have the same shape. On the other hand, in plan view, the first electrode terminals 50A-50C have a different shape from the second electrode terminals 60A, 60B. In the example shown in FIG. 5, the first electrode terminals 50A-50C are formed in a circular shape in plan view. The second electrode terminals 60A, 60B are formed in a rectangular shape in plan view. In one example, the second electrode terminals 60A, 60B are formed in a rectangular shape with the Y direction as the longitudinal direction and the X direction as the transverse direction. In one example, the areas of the second electrode terminals 60 are equal to each other in plan view. In one example, the areas of the first electrode terminals 50 are equal to each other in plan view.

[0078] In a plan view, the area of ​​each second electrode terminal 60 is larger than the area of ​​each first electrode terminal 50. Here, the area of ​​the first electrode terminal 50 in a plan view can be defined by the area of ​​the tip surface 56 of the first pillar portion 51 of the first electrode terminal 50 in a plan view. The area of ​​the second electrode terminal 60 can be defined by the area of ​​the tip surface 66 of the second pillar portion 61 of the second electrode terminal 60 in a plan view.

[0079] The shape of each of the first electrode terminals 50 and each of the second electrode terminals 60 in a planar view can be changed arbitrarily. In one example, the shape of each of the first electrode terminals 50 in a planar view may be any of an ellipse, an oval, a rectangle, and a polygon. In one example, the shape of each of the second electrode terminals 60 in a planar view may be any of a circle, an ellipse, an oval, and a polygon. Also, for example, the shape of each of the first electrode terminals 50 in a planar view may be the same as the shape of each of the second electrode terminals 60.

[0080] 6, the height dimension H2 of each second electrode terminal 60 is slightly higher than the height dimension H1 of each first electrode terminal 50. Here, the height dimension H2 of the second electrode terminal 60 can be defined as the maximum distance in the Z direction between the second electrode 44B and the tip surface 66 of the second pillar portion 61 of the second electrode terminal 60. The height dimension H1 of the first electrode terminal 50 can be defined as the maximum distance in the Z direction between the first electrode 44A and the tip surface 56 of the first pillar portion 51 of the first electrode terminal 50.

[0081] 8 and 9, the thickness T1 of the first seed layer 52 of the first pillar portion 51 of the first electrode terminal 50 is equal to, for example, the thickness T2 of the second seed layer 62 of the second pillar portion 61 of the second electrode terminal 60. Here, if the difference between the thickness T1 and the thickness T2 is, for example, within 10% of the thickness T1, it can be said that the thickness T1 of the first seed layer 52 is equal to the thickness T2 of the second seed layer 62. The thickness T4 of the second plating layer 63 of the second pillar portion 61 of the second electrode terminal 60 is slightly thicker than, for example, the thickness T3 of the first plating layer 53 of the first pillar portion 51 of the first electrode terminal 50. In addition, the thickness T5 of the first front surface side plating layer 54 of the first electrode terminal 50 is equal to, for example, the thickness T6 of the second front surface side plating layer 64 of the second electrode terminal 60. Here, if the difference between thickness T5 and thickness T6 is within 10% of thickness T5, for example, it can be said that thickness T5 of the first surface-side plating layer 54 is equal to thickness T6 of the second surface-side plating layer 64. In this way, because thickness T4 of the second plating layer 63 is slightly thicker than thickness T3 of the first plating layer 53, height dimension H2 of each second electrode terminal 60 is slightly greater than height dimension H1 of each first electrode terminal 50.

[0082] Here, the height dimension H2 of each second electrode terminal 60 is changed according to the area of ​​each second electrode terminal 60 in a planar view. That is, the height dimension H2 of each second electrode terminal 60 decreases as the area of ​​each second electrode terminal 60 in a planar view increases. For this reason, by adjusting the area of ​​each second electrode terminal 60 in a planar view, the height dimension H2 of each second electrode terminal 60 may be equal to the height dimension H1 of each first electrode terminal 50, or the height dimension H2 may be slightly smaller than the height dimension H1.

[0083] [Method of manufacturing semiconductor devices] The following describes an example of a schematic method for manufacturing the semiconductor element 30. In particular, the manufacturing process for the first electrode terminal 50 and the second electrode terminal 60 will be described in detail below.

[0084] The manufacturing method of the semiconductor element 30 includes a step of preparing a semiconductor substrate 41, a step of forming a semiconductor layer 42 and a passivation film 43 on the semiconductor substrate 41, and a step of forming a plurality of first electrodes 44A, a plurality of second electrodes 44B, and an insulating layer 45 on the semiconductor layer 42. The semiconductor substrate 41 is formed of a semiconductor wafer containing, for example, Si. In the step of forming the semiconductor layer 42, a switching circuit 42A and a control circuit 42B are formed. The passivation film 43 is formed so as to cover the semiconductor layer 42. Each of the first electrodes 44A and each of the second electrodes 44B are formed on the passivation film 43. The insulating layer 45 is formed so as to cover each of the first electrodes 44A and each of the second electrodes 44B. Meanwhile, a first opening 45A and a second opening 45B are formed in the insulating layer 45, through which a part of each of the first electrodes 44A and each of the second electrodes 44B is exposed.

[0085] The method for manufacturing the semiconductor element 30 includes the steps of forming a plurality of first electrode terminals 50 and a plurality of second electrode terminals 60. This step includes the steps of forming a seed layer, forming a first plating layer 53 and a second plating layer 63, forming a first front surface side plating layer 54 and a second front surface side plating layer 64, forming a first solder portion 57 and a second solder portion 67, and forming a first seed layer 52 and a second seed layer 62.

[0086] In the step of forming the seed layer, the seed layer is formed by, for example, electroless plating on the entire surface of the insulating layer 45 and on each of the first electrodes 44A and each of the second electrodes 44B exposed from the insulating layer 45. The seed layer may be formed by a sputtering method.

[0087] In the step of forming the first plating layer 53 and the second plating layer 63, the first plating layer 53 and the second plating layer 63 are formed on the seed layer by electrolytic plating using the seed layer as a conductive path. More specifically, a resist having openings in areas where the first plating layer 53 and the second plating layer 63 are to be formed is formed on the seed layer. Then, the first plating layer 53 and the second plating layer 63 are formed on the seed layer exposed from the resist.

[0088] In the process of forming the first surface side plating layer 54 and the second surface side plating layer 64, the first surface side plating layer 54 is formed on the first plating layer 53, and the second surface side plating layer 64 is formed on the second plating layer 63, for example, by electrolytic plating.

[0089] In the process of forming the first solder portion 57 and the second solder portion 67, the first solder portion 57 is formed on the first front-side plating layer 54, and the second solder portion 67 is formed on the second front-side plating layer 64, for example, by electrolytic plating. The resist is then removed.

[0090] In the step of forming the first seed layer 52 and the second seed layer 62, the seed layer is patterned to form the first seed layer 52 and the second seed layer 62. That is, the seed layer exposed from the first plating layer 53 and the second plating layer 63 in a plan view is removed to form the first seed layer 52 and the second seed layer 62. Through the above steps, the first electrode terminals 50 and the second electrode terminals 60 are manufactured, and the semiconductor element 30 is manufactured.

[0091] [Effect] The operation of the first embodiment will be described with reference to Figs. 5 to 7 and 10 to 12. Fig. 10 shows a schematic planar structure of a semiconductor element 30X of a comparative example. Fig. 11 shows a schematic cross-sectional structure of the semiconductor element 30X taken along line F11-F11 in Fig. 10. Fig. 12 shows a schematic cross-sectional structure of a semiconductor device 10X including the semiconductor element 30X of a comparative example. In the following description, the first electrode terminal and the second electrode terminal of the semiconductor element 30X of the comparative example will be referred to as the "first electrode terminal 50X" and the "second electrode terminal 60X".

[0092] 10, in the semiconductor element 30X of the comparative example, the arrangement of the multiple first electrode terminals 50X and the multiple second electrode terminals 60X is the same as the arrangement of the multiple first electrode terminals 50 and the multiple second electrode terminals 60 of the first embodiment. On the other hand, in the semiconductor element 30X of the comparative example, the area of ​​each second electrode terminal 60X in a plan view is smaller than the area of ​​each second electrode terminal 60 (see FIG. 5) in a plan view. In one example, the area of ​​each second electrode terminal 60X in a plan view is the same as the area of ​​each first electrode terminal 50X in a plan view.

[0093] The multiple first electrode terminals 50X are densely arranged in the first region 31A. Therefore, the maximum dimension of each first electrode terminal 50X in a planar view (for example, the diameter of the first electrode terminal 50X in a planar view) is greater than the distance between a given first electrode terminal 50X and the first electrode terminal 50X adjacent to this first electrode terminal 50X in the Y direction.

[0094] On the other hand, the second electrode terminals 60X are spaced apart in the second region 31B. Therefore, the maximum dimension of the second electrode terminals 60X in a plan view (for example, the diameter of the second electrode terminal 60X in a plan view) is smaller than the distance between a given second electrode terminal 60X and the second electrode terminal 60X adjacent to the given second electrode terminal 60X in the Y direction. In this way, the ratio of the total area of ​​the second electrode terminals 60X to the area of ​​the second region 31B is lower than the ratio of the total area of ​​the first electrode terminals 50X to the area of ​​the first region 31A.

[0095] The second electrode terminals 60X in the second region 31B are disposed apart from the first electrode terminals 50X in the first region 31A. Therefore, it can be said that the second electrode terminals 60X in the second region 31B are disposed sparsely relative to the first electrode terminals 50X in the first region 31A. Therefore, the current density in electrolytic plating when forming each of the first electrode terminals 50X and each of the second electrode terminals 60X is higher for the second electrode terminals 60X (second electrode 44B) than for the first electrode terminals 50X (first electrode 44A). As a result, as shown in FIG. 11, the height dimension HX2 of each of the second electrode terminals 60X is higher than the height dimension HX1 of each of the first electrode terminals 50X. As a result, as shown in FIG. 12, when the semiconductor element 30X is mounted on the first leads 21A-21C and the second leads 22A-22D, due to variations in the height dimensions HX1, HX2, the semiconductor element 30X is mounted in an inclined state with respect to the first lead surfaces 21S of the first leads 21A-21C and the second lead surfaces 22S of the second leads 22A-22D.

[0096] When the semiconductor element 30X is mounted in a tilted state with respect to the first lead surface 21S and the second lead surface 22S in this manner, voids may occur at the joints between the multiple first electrode terminals 50X and the first lead surface 21S, which may reduce the connection strength between the multiple first electrode terminals 50X and the first leads 21A-21C, or increase the electrical resistance between the multiple first electrode terminals 50X and the first leads 21A-21C.

[0097] In this regard, in the first embodiment, as shown in FIG. 5, the area of ​​each second electrode terminal 60 in plan view is larger than the area of ​​each first electrode terminal 50 in plan view. As a result, the current density when electrolytic plating is performed to form each second electrode terminal 60 is smaller than the current density when forming the second electrode terminal 60X of the comparative example. In other words, the current density when electrolytic plating is performed to form each second electrode terminal 60 approaches the current density when electrolytic plating is performed to form each first electrode terminal 50. As a result, the difference HD (HD=H2-H1) between the height dimension H2 of each second electrode terminal 60 and the height dimension H1 of each first electrode terminal 50 in the first embodiment shown in FIG. 6 is smaller than the difference HDX (HDX=HX2-HX1) between the height dimension HX2 of each second electrode terminal 60X and the height dimension HX1 of each first electrode terminal 50X shown in FIG. 11. 7, the semiconductor element 30 is prevented from being mounted in a tilted state with respect to the first lead surface 21S and the second lead surface 22S. This prevents a decrease in the connection strength between the multiple first electrode terminals 50 and the first leads 21A-21C and an increase in the electrical resistance between the multiple first electrode terminals 50 and the first leads 21A-21C.

[0098] [effect] According to the first embodiment, the following effects can be obtained. (1-1) A semiconductor element 30 includes an element front surface 31, an element back surface 32 facing the opposite side to the element front surface 31, a first electrode 44A and a second electrode 44B formed on the element front surface 31, a plurality of first electrode terminals 50 in contact with the first electrode 44A, a plurality of second electrode terminals 60 in contact with the second electrode 44B, a first region 31A in which the plurality of first electrode terminals 50 are arranged, and a second region 31B in which the plurality of second electrode terminals 60 are arranged. The number of second electrode terminals 60 per unit area in the second region 31B is smaller than the number of first electrode terminals 50 per unit area in the first region 31A. In a plan view, the area of ​​the second electrode terminals 60 is larger than the area of ​​the first electrode terminals 50.

[0099] This configuration can reduce variation between the height dimension H1 of the multiple first electrode terminals 50 and the height dimension H2 of the multiple second electrode terminals 60. Therefore, when the semiconductor element 30 is joined to, for example, the first lead 21 and the second lead 22, variation between the bonding strength between the first electrode terminal 50 and the first lead 21 and the bonding strength between the second electrode terminal 60 and the second lead 22 is suppressed. Therefore, variation in the connection state between the multiple first electrode terminals 50 and the multiple second electrode terminals 60 can be reduced.

[0100] (1-2) The second electrode terminal 60 has a rectangular shape in a plan view. According to this configuration, it is easier to increase the area of ​​the second electrode terminal 60 in a planar view, compared to when the shape of the second electrode terminal 60 in a planar view is circular.

[0101] <Second embodiment> A semiconductor device 10 of the second embodiment will be described with reference to Figures 13 to 16. The semiconductor device 10 of the second embodiment differs from the semiconductor device 10 of the first embodiment mainly in the shape of each second electrode terminal 60 and in that a third electrode 44C and a dummy terminal 90 are provided on the semiconductor element 30. In the following, components common to the first embodiment are denoted by the same reference numerals, and descriptions thereof may be omitted.

[0102] Fig. 13 shows a schematic planar structure of the semiconductor element 30 in the semiconductor device 10 of the second embodiment. Note that the insulating layer 45 is omitted in Fig. 13. Fig. 14 shows a schematic cross-sectional structure of the semiconductor element 30 cut along line F14-F14 in Fig. 13. Fig. 15 shows a schematic cross-sectional structure of the semiconductor device 10 cut along the XZ plane. Fig. 16 shows a schematic cross-sectional structure of the dummy terminal 90 and its periphery in Fig. 15 in an enlarged scale.

[0103] As shown in FIG. 13, each second electrode terminal 60 is formed in a circular shape in a plan view. That is, in the second embodiment, the shape of each second electrode terminal 60 in a plan view is the same as the shape of each first electrode terminal 50 in a plan view. In addition, in one example, the area of ​​each second electrode terminal 60 in a plan view is equal to the area of ​​each first electrode terminal 50 in a plan view. Here, if the difference between the area of ​​each second electrode terminal 60 in a plan view and the area of ​​each first electrode terminal 50 in a plan view is, for example, within 10% of the area of ​​each second electrode terminal 60 in a plan view, it can be said that the area of ​​each second electrode terminal 60 in a plan view is equal to the area of ​​each first electrode terminal 50 in a plan view. In the second embodiment, the distance between the second electrode terminals 60 adjacent to each other in the Y direction on the second electrode 44B is greater than that in the first embodiment.

[0104] The semiconductor element 30 further includes a third electrode 44C formed in the second region 31B of the element surface 31. The third electrode 44C is provided between the first electrode 44AA corresponding to the first lead 21A and the second electrode 44B in the X direction and closer to the second electrode 44B. The third electrode 44C is formed in a strip shape extending in the Y direction in a plan view. In one example, the dimension in the Y direction of the third electrode 44C is equal to the dimension in the Y direction of the first electrode 44A. The dimension and shape in the Y direction of the third electrode 44C can be changed arbitrarily. In one example, the dimension in the Y direction of the third electrode 44C may be larger than the dimension in the Y direction of the first electrode 44A.

[0105] As shown in FIG. 14, the third electrode 44C is disposed at the same position as the first electrode 44A and the second electrode 44B in the Z direction. Therefore, the third electrode 44C is covered by the insulating layer 45. Meanwhile, the insulating layer 45 has a third opening 45C that exposes a part of the third electrode 44C. The third electrode 44C is insulated from the first electrode 44A and the second electrode 44B. In one example, the third electrode 44C is in an electrically floating state. Note that the configuration of the third electrode 44C is the same as that of the first electrode 44A, for example. Therefore, the same reference numerals are attached to the configuration of the third electrode 44C that is common to the first electrode 44A, and the description thereof will be omitted.

[0106] At least one dummy terminal 90 is provided on the third electrode 44C exposed from the insulating layer 45. In one example, a plurality of dummy terminals 90 (four in the second embodiment) are provided. The plurality of dummy terminals 90 are arranged at the same positions in the X direction and spaced apart from each other in the Y direction. Each dummy terminal 90 contacts the exposed third electrode 44C through the third opening 45C.

[0107] As shown in Fig. 13, the shapes of the dummy terminals 90 are the same as one another in a plan view. On the other hand, the shapes of the dummy terminals 90 are different from the shapes of the first electrode terminals 50 in a plan view. On the other hand, the shapes of the dummy terminals 90 are different from the shapes of the second electrode terminals 60 in a plan view. In the example shown in Fig. 13, each dummy terminal 90 is formed in a rectangular shape in a plan view. In one example, each dummy terminal 90 is formed in a rectangular shape with the Y direction as the longitudinal direction and the X direction as the lateral direction.

[0108] In a plan view, the area of ​​each dummy terminal 90 is larger than the area of ​​each first electrode terminal 50. In a plan view, the area of ​​each dummy terminal 90 is larger than the area of ​​each second electrode terminal 60. Here, the area of ​​the dummy terminal 90 in a plan view can be defined by the area of ​​a tip surface 96 (see FIG. 16 ) of a third pillar portion 91 of the dummy terminal 90 in a plan view.

[0109] In the second embodiment, the shape of each of the first electrode terminals 50, the shape of each of the second electrode terminals 60, and the shape of each of the dummy terminals 90 in a plan view can be changed arbitrarily. In one example, the shape of each of the first electrode terminals 50 and each of the second electrode terminals 60 in a plan view may be any of an ellipse, an oval, a rectangle, and a polygon. In one example, the shape of each of the dummy terminals 90 in a plan view may be any of a circle, an ellipse, an oval, and a polygon. Also, for example, the shape of each of the dummy terminals 90 in a plan view may be the same as the shape of each of the first electrode terminals 50 or each of the second electrode terminals 60.

[0110] 14, the height dimension H3 of each dummy terminal 90 is lower than the height dimension H2 of each second electrode terminal 60. Moreover, the height dimension H3 of each dummy terminal 90 is slightly lower than the height dimension H1 of each first electrode terminal 50. Here, the height dimension H3 of the dummy terminal 90 can be defined as the maximum distance between the third electrode 44C and the tip surface 96 of the third pillar portion 91 of the dummy terminal 90 in the Z direction.

[0111] The difference HD (HD = H2 - H1) between the height dimension H1 of each first electrode terminal 50 and the height dimension H2 of each second electrode terminal 60 is smaller than the difference HDX (HDX = HX2 - HX1) between the height dimension HX2 of each second electrode terminal 60X and the height dimension HX1 of each first electrode terminal 50X shown in Figure 11.

[0112] Here, the height dimension H2 of each second electrode terminal 60 is changed according to the area of ​​each dummy terminal 90 in a plan view. That is, the height dimension H2 of each second electrode terminal 60 decreases as the area of ​​each dummy terminal 90 in a plan view increases. Therefore, by adjusting the area of ​​each dummy terminal 90 in a plan view, the height dimension H2 of each second electrode terminal 60 may be equal to the height dimension H1 of each first electrode terminal 50, or the height dimension H2 may be slightly smaller than the height dimension H1.

[0113] As shown in FIG. 15, the semiconductor device 10 includes a third lead 23 arranged opposite the dummy terminal 90 in the Z direction. A plurality of third leads 23 may be provided, for example, according to the number of dummy terminals 90. The third lead 23 is arranged apart from both the first lead 21 and the second lead 22. In other words, the third lead 23 is insulated from both the first lead 21 and the second lead 22. The number of third leads 23 can be changed arbitrarily. In one example, a common third lead 23 may be provided for the plurality of third leads 23.

[0114] The third lead 23 has a third lead front surface 23S and a third lead back surface 23R that face opposite each other in the Z direction. The third lead front surface 23S faces the same side as the first lead front surface 21S, and the third lead back surface 23R faces the same side as the first lead back surface 21R. The semiconductor element 30 is supported by the second lead front surface 22S of the third lead 23. The third lead back surface 23R is exposed from the sealing back surface 82 of the sealing resin 80.

[0115] As shown in FIG. 16, the connection structure between the dummy terminal 90 and the second lead 22 is the same as, for example, the connection structure between the second electrode terminal 60 and the second lead 22. That is, each dummy terminal 90 includes a third pillar portion 91 and a third solder portion 97. The third pillar portion 91 includes a third seed layer 92, a third plating layer 93, and a third front surface side plating layer 94. The third solder portion 97 is formed on the third front surface side plating layer 94. The third pillar portion 91 is provided with a third recess 95. The third pillar portion 91 has a tip surface 96 provided with the third solder portion 97. In addition, each dummy terminal 90 is manufactured in a process common to, for example, the first electrode terminal 50 and the second electrode terminal 60.

[0116] The third solder portion 97 of the dummy terminal 90 is interposed between the third pillar portion 91 and the third lead 23, thereby electrically connecting the third pillar portion 91 and the third lead 23. The third plating layer 70C is interposed between the third solder portion 97 and the third lead surface 23S of the third lead 23 in the Z direction. The third plating layer 70C electrically connects the third solder portion 97 and the third lead 23. The third plating layer 70C functions to suppress a chemical reaction between the third lead 23 and the third solder portion 97. The material of the third plating layer 70C is not particularly limited, and a metal material capable of suppressing the chemical reaction may be appropriately selected. Examples of the metal material include Ni and Fe. In the example shown in FIG. 16, the third plating layer 70C is provided so as to cover a part of the third lead surface 23S. The configuration of the third plating layer 70C is the same as that of the first plating layer 70A. Therefore, the same reference numerals are given to the components of the third plating layer 70C that are common to the first plating layer 70A, and the description thereof will be omitted.

[0117] As shown in FIG. 8, FIG. 9, and FIG. 16, the thickness T7 of the third seed layer 92 of the third pillar portion 91 of the dummy terminal 90 is equal to the thickness T2 of the second seed layer 62 of the second pillar portion 61 of the second electrode terminal 60, for example. Here, if the difference between the thickness T7 and the thickness T2 is within 10% of the thickness T7, for example, it can be said that the thickness T7 of the third seed layer 92 is equal to the thickness T2 of the second seed layer 62. The thickness T8 of the third plating layer 93 of the third pillar portion 91 of the dummy terminal 90 is slightly thinner than the thickness T3 of the first plating layer 53 of the first pillar portion 51 of the first electrode terminal 50, for example. In addition, the thickness T9 of the third front surface side plating layer 94 of the dummy terminal 90 is equal to the thickness T6 of the second front surface side plating layer 64 of the second electrode terminal 60, for example. Here, if the difference between the thickness T9 and the thickness T6 is, for example, within 10% of the thickness T9, it can be said that the thickness T9 of the third surface-side plating layer 94 is equal to the thickness T6 of the second surface-side plating layer 64. In this way, the thickness T8 of the third plating layer 93 is slightly thinner than the thickness T3 of the first plating layer 53, and therefore the height dimension H3 of each dummy terminal 90 is smaller than the height dimension H1 of each first electrode terminal 50. In addition, the thickness T8 of the third plating layer 93 is thinner than, for example, the thickness T5 of the second plating layer 63 of the second pillar portion 61 of the second electrode terminal 60. As a result, the height dimension H3 of each dummy terminal 90 is smaller than the height dimension H2 of each second electrode terminal 60.

[0118] [effect] According to the second embodiment, the following effects can be obtained. (2-1) The semiconductor element 30 includes an element front surface 31, an element back surface 32 facing the opposite side to the element front surface 31, a first electrode 44A and a second electrode 44B formed on the element front surface 31, a plurality of first electrode terminals 50 in contact with the first electrode 44A, a plurality of second electrode terminals 60 in contact with the second electrode 44B, a first region 31A in which the plurality of first electrode terminals 50 are arranged, and a second region 31B in which the plurality of second electrode terminals 60 are arranged. The number of second electrode terminals 60 per unit area in the second region 31B is smaller than the number of first electrode terminals 50 per unit area in the first region 31A. A dummy terminal 90 is provided in the second region 31B.

[0119] According to this configuration, the current density when electrolytic plating is performed to form each second electrode terminal 60 is smaller than that when the dummy terminal 90 is not provided. In other words, the current density when electrolytic plating is performed to form each second electrode terminal 60 approaches the current density when electrolytic plating is performed to form each first electrode terminal 50. This reduces the variation between the height dimension H1 of the multiple first electrode terminals 50 and the height dimension H2 of the multiple second electrode terminals 60. Therefore, when the semiconductor element 30 is joined to, for example, the first lead 21 and the second lead 22, the bonding strength between the first electrode terminal 50 and the first lead 21 and the bonding strength between the second electrode terminal 60 and the second lead 22 are suppressed from varying from each other. Therefore, the variation in the connection state between the multiple first electrode terminals 50 and the multiple second electrode terminals 60 can be reduced.

[0120] (2-2) The dummy terminals 90 are disposed closer to the second electrode terminals 60 than the first electrode terminals 50 are. According to this configuration, the current density when electrolytic plating is performed to form each of the second electrode terminals 60 tends to be small.

[0121] (2-3) The semiconductor element 30 further includes a third electrode 44C formed in the second region 31B of the element surface 31. The third electrode 44C is provided between the first electrode 44A and the second electrode 44B in the X direction and closer to the second electrode 44B. The dummy terminal 90 is in contact with the third electrode 44C.

[0122] According to this configuration, the dummy terminals 90 can be manufactured in the same process as the first electrode terminals 50 and the second electrode terminals 60. Therefore, the manufacturing process of the semiconductor element 30 can be simplified.

[0123] (2-4) The height dimension H3 of the dummy terminal 90 is smaller than the height dimension H2 of the second electrode terminal 60. According to this configuration, the height dimension H3 of the dummy terminals 90 is greater than the height dimension H2 of the second electrode terminals 60, so that the variation in the connection state between the second electrode terminals 60 and the first electrode terminals 50 can be suppressed.

[0124] (2-5) The shape of the dummy terminal 90 in a plan view is rectangular. According to this configuration, it is easier to increase the area of ​​the dummy terminal 90 in a plan view, compared to when the shape of the dummy terminal 90 in a plan view is circular.

[0125] <Third embodiment> A semiconductor device 10 of the third embodiment will be described with reference to Figures 17 and 18. The semiconductor device 10 of the third embodiment is mainly different from the semiconductor device 10 of the second embodiment in that the third electrode 44C is omitted. In the following, components common to the second embodiment are denoted by the same reference numerals, and descriptions thereof may be omitted.

[0126] 17, the semiconductor device 10 of the third embodiment does not include a third electrode 44C (see FIG. 13). That is, each dummy terminal 90 is provided on an insulating layer 45. Each dummy terminal 90 is in an electrically floating state.

[0127] As shown in FIG. 18, the height dimension H3 of each dummy terminal 90 is equal to the height dimension H2 of each second electrode terminal 60. The height dimension H3 of each dummy terminal 90 is equal to the height dimension H1 of each first electrode terminal 50. Therefore, the height dimension H2 of each second electrode terminal 60 is equal to the height dimension H1 of each first electrode terminal 50. Here, the height dimension H3 of the dummy terminal 90 can be defined by, for example, the maximum distance in the Z direction between the surface of the second electrode 44B and the tip surface 96 of the third pillar portion 91 of the dummy terminal 90. Also, if the difference between the height dimension H3 and the height dimension H2 is, for example, within 10% of the height dimension H3, it can be said that the height dimension H3 of each dummy terminal 90 is equal to the height dimension H2 of each second electrode terminal 60. If the difference between the height dimension H3 and the height dimension H1 is, for example, within 10% of the height dimension H3, it can be said that the height dimension H3 of each dummy terminal 90 is equal to the height dimension H1 of each first electrode terminal 50. That is, the height dimension H3 of each dummy terminal 90 being equal to the height dimension H2 of each second electrode terminal 60 means that the position of the tip surface 96 of each dummy terminal 90 and the position of the tip surface 66 of each second electrode terminal 60 are the same in the Z direction. Also, the height dimension H3 of each dummy terminal 90 being equal to the height dimension H1 of each first electrode terminal 50 means that the position of the tip surface 96 of each dummy terminal 90 and the position of the tip surface 56 of each first electrode terminal 50 are the same in the Z direction. According to the third embodiment, effects equivalent to (2-1), (2-2), and (2-5) of the second embodiment can be obtained.

[0128] <Example of change> The above-described embodiments may be modified as follows: Furthermore, the above-described embodiments and the following modifications may be combined with each other to the extent that no technical contradiction occurs.

[0129] In the second and third embodiments, the number of dummy terminals 90 can be changed arbitrarily. In one example, the number of dummy terminals 90 may be one. In another example, the number of dummy terminals 90 may be five or more.

[0130] In the third embodiment, it is possible to arbitrarily change the number and arrangement of the plurality of dummy terminals 90. For example, examples of the arrangement of the plurality of dummy terminals 90 include a first modification shown in FIG. 19 and a second modification shown in FIG.

[0131] 19, in the first modified example, the multiple dummy terminals 90 may be arranged to surround the multiple second electrode terminals 60A and the multiple second electrode terminals 60B from three sides in a plan view. More specifically, the multiple dummy terminals 90 include a dummy terminal 90 arranged at a position overlapping the multiple second electrode terminals 60A and closer to the sealing side surface 85 than the multiple second electrode terminals 60A when viewed from the Y direction. The multiple dummy terminals 90 include a dummy terminal 90 arranged at a position overlapping the multiple second electrode terminals 60B and closer to the sealing side surface 86 than the multiple second electrode terminals 60B when viewed from the Y direction. The multiple dummy terminals 90 include a dummy terminal 90 arranged at a position overlapping the multiple second electrode terminals 60A, 60B when viewed from the Y direction and between the multiple second electrode terminals 60A and the multiple second electrode terminals 60B in the Y direction.

[0132] As shown in FIG. 20, in the second modified example, the multiple dummy terminals 90 may be arranged to surround the multiple second electrode terminals 60A and the multiple second electrode terminals 60B individually in a plan view. That is, the multiple dummy terminals 90 include multiple dummy terminals 90 arranged to surround the multiple second electrode terminals 60A in a plan view. The multiple dummy terminals 90 include multiple dummy terminals 90 arranged to surround the multiple second electrode terminals 60B in a plan view. In this case, the second electrode 44B and the multiple second electrode terminals 60A, 60B are arranged at a position spaced apart from the sealing side surface 84 in the X direction. That is, the multiple dummy terminals 90 are arranged between the second electrode 44B and the sealing side surface 84 in the X direction. In other words, the second electrode 44B is arranged at a distance from the sealing side surface 84 in the X direction by an area in which the multiple dummy terminals 90 are arranged.

[0133] 19 and the second modified example shown in FIG. 20 can be similarly applied to the second embodiment. In this case, the semiconductor device 10 includes a third electrode 44C that surrounds each of the second electrodes 44B in a plan view. In addition, in the first modified example and the second modified example, the dummy terminal 90 that is arranged between the second electrode terminals 60A and 60B in the Y direction at a position that overlaps with the second electrode terminals 60A and 60B when viewed from the Y direction may be omitted.

[0134] In the third embodiment, the combination of the shapes of the dummy terminals 90 and the second electrode terminals 60 in a plan view can be changed arbitrarily. Examples of the combination of the shapes of the dummy terminals 90 and the second electrode terminals 60 in a plan view include a first modified example shown in Fig. 21, a second modified example shown in Fig. 22, and a third modified example shown in Fig. 23.

[0135] As shown in Fig. 21, in the first modified example, the second electrode terminal 60 has a rectangular shape in a plan view, and the dummy terminal 90 has a circular shape in a plan view. In the example shown in Fig. 21, the second electrode terminal 60 has a rectangular shape in a plan view with the Y direction as the longitudinal direction and the X direction as the lateral direction. In this case, the area of ​​the second electrode terminal 60 in a plan view is larger than the area of ​​the dummy terminal 90 in a plan view.

[0136] 22, in the second modified example, the shape of the second electrode terminal 60 in a plan view is circular, and the shape of the dummy terminal 90 in a plan view is circular. That is, the shape of the second electrode terminal 60 in a plan view and the shape of the dummy terminal 90 in a plan view may be the same. In one example, the area of ​​the second electrode terminal 60 in a plan view is equal to the area of ​​the dummy terminal 90 in a plan view.

[0137] As shown in Fig. 23, in the third modified example, the shape of the second electrode terminal 60 in a plan view is rectangular, and the shape of the dummy terminal 90 in a plan view is rectangular. That is, the shape of the second electrode terminal 60 in a plan view and the shape of the dummy terminal 90 in a plan view may be the same as each other. In one example, the area of ​​the second electrode terminal 60 in a plan view is equal to the area of ​​the dummy terminal 90 in a plan view. Also, the area of ​​the dummy terminal 90 in a plan view is larger than the area of ​​the first electrode terminal 50 in a plan view. The area of ​​the second electrode terminal 60 in a plan view is larger than the area of ​​the first electrode terminal 50 in a plan view.

[0138] In the third embodiment, the dummy terminals 90 are provided on the insulating layer 45, but this is not limiting. The dummy terminals 90 may be provided on the element surface 31 of the semiconductor element 30, for example. In each embodiment, the number and arrangement of the second leads 22 can be changed arbitrarily. In one example, as shown in FIG. 24, the semiconductor device 10 includes the second leads 22A to 22H. The second leads 22A to 22H are arranged closer to the sealing side surface 83 than the first leads 21A to 21C. The second leads 22A to 22F are arranged, for example, spaced apart from each other in the Y direction. The second leads 22A, 22B, 22C, 22D, 22E, and 22F are arranged in this order from the sealing side surface 85 toward the sealing side surface 86. The second lead 22G is arranged between the second lead 22A and the first lead 21A in the X direction. The second lead 22H is arranged between the second lead 22F and the first lead 21A in the X direction.

[0139] The number and arrangement of the second electrode terminals 60 are appropriately changed according to the number and arrangement of the second leads 22. Although not shown, the second electrodes 44B are appropriately changed according to the number and arrangement of the second electrode terminals 60.

[0140] The semiconductor element 30 includes second electrode terminals 60A-60H as the multiple second electrode terminals 60. In the example shown in FIG. 24, the second electrode terminals 60A-60H are formed in a rectangular shape in a plan view. The second electrode terminals 60A-60H in a plan view include those having different shapes and sizes. The shapes and sizes of the second electrode terminals 60A-60H in a plan view are appropriately changed according to the shapes and sizes of the second leads 22A-22H facing the second region 31B of the semiconductor element 30.

[0141] 24, the ratio of the area of ​​the second region 31B to the area of ​​the first region 31A is smaller than the ratio of the number of second electrode terminals 60 to the number of first electrode terminals 50. Therefore, the number of second electrode terminals 60 per unit area in the second region 31B is smaller than the number of first electrode terminals 50 per unit area in the first region 31A. The area of ​​each of the second electrode terminals 60A-60H in a plan view is larger than the area of ​​the first electrode terminal 50 in a plan view.

[0142] In each embodiment, the configuration of the second electrodes 44B can be changed arbitrarily. In one example, the number of the second electrodes 44B may be set according to the number of the second electrode terminals 60. If there are four second electrode terminals 60, the four second electrodes 44B may be provided at a distance from each other. The four second electrode terminals 60 may be individually electrically connected to the four second electrodes 44B. In other words, the semiconductor device 10 may include a plurality of second electrode terminals 60 that are individually electrically connected to a plurality of second electrodes 44B.

[0143] In each embodiment, it is possible to arbitrarily change the configuration for supporting the semiconductor element 30. In one example, as shown in Fig. 25, the semiconductor device 10 includes a substrate 100 instead of the first leads 21A to 21C and the second leads 22A to 22D.

[0144] The substrate 100 is formed in the shape of a rectangular flat plate with its thickness direction in the Z direction. The substrate 100 has a substrate front surface 101 and a substrate back surface 102 which face opposite each other in the Z direction. The substrate front surface 101 faces the same side as the device front surface 11, and the substrate back surface 102 faces the same side as the device back surface 12. The substrate back surface 102 constitutes the device back surface 12. The substrate 100 is formed of an insulating material. An example of the insulating material is epoxy resin.

[0145] The semiconductor device 10 includes a plurality of first surface wirings 111 and a plurality of second surface wirings 112 formed on a substrate surface 101. Each of the first surface wirings 111 and each of the second surface wirings 112 are formed by a metal layer formed on the substrate surface 101. The metal layer includes at least one of Cu, Al, Ag, Au, Ni, and Ti, for example.

[0146] The first surface wirings 111 are individually and electrically connected to the first electrode terminals 50 of the semiconductor element 30. The first surface wirings 111 are provided in accordance with the first electrode terminals 50A to 50C (see FIG. 2). That is, the first surface wirings 111 include a first surface wiring 111 corresponding to the first electrode terminal 50A, a first surface wiring 111 corresponding to the first electrode terminal 50B, and a first surface wiring 111 corresponding to the first electrode terminal 50C.

[0147] A plurality of second electrode terminals 60 are individually and electrically connected to the plurality of second surface wirings 112. The plurality of second surface wirings 112 are provided in accordance with the second electrode terminals 60A to 60D (see FIG. 2). That is, the plurality of second surface wirings 112 include a second surface wiring 112 corresponding to the second electrode terminal 60A, a second surface wiring 112 corresponding to the second electrode terminal 60B, a second surface wiring 112 corresponding to the second electrode terminal 60C, and a second surface wiring 112 corresponding to the second electrode terminal 60D. The configuration and arrangement of each of the first electrode terminals 50 and each of the second electrode terminals 60 are, for example, similar to those in the first embodiment.

[0148] The semiconductor device 10 includes a plurality of first back surface wirings 113 and a plurality of second back surface wirings 114 formed on the back surface 102 of the substrate, and a plurality of first through wirings 115 and a plurality of second through wirings 116 that penetrate the substrate 100 in the Z direction.

[0149] The multiple first back surface wirings 113 are electrically connected to the multiple first front surface wirings 111 via the multiple first through wirings 115. Therefore, the multiple first back surface wirings 113 are individually and electrically connected to the first electrode terminals 50A to 50C.

[0150] The multiple second back surface wirings 114 are electrically connected to the multiple second front surface wirings 112 via the multiple second through wirings 116. Therefore, the multiple second back surface wirings 114 are individually and electrically connected to the second electrode terminals 60A to 60D.

[0151] The sealing resin 80 is provided on the substrate surface 101 of the substrate 100. The sealing resin 80 seals the semiconductor element 30, the plurality of first surface wirings 111, and the plurality of second surface wirings 112. According to the semiconductor device 10 shown in FIG. 25, the same effect as in the first embodiment can be obtained. Note that, in the modified example shown in FIG. 25, the semiconductor elements 30 of the second and third embodiments can also be applied. Also, in the modified example shown in FIG. 25, the sealing resin 80 may be omitted from the semiconductor device 10.

[0152] One or more of the various examples described in this specification may be combined to the extent that they are not technically inconsistent. The terms "first", "second", "third", etc. in this disclosure are used merely to distinguish objects and do not rank the objects.

[0153] In this specification, "at least one of A and B" should be understood to mean "A only, or B only, or both A and B." The term "on" as used in this disclosure includes the meanings "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" is intended to mean that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0154] The Z direction used in this disclosure does not necessarily have to be a vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" of the Z direction described in this specification being "up" and "down" of the vertical direction. For example, the X direction may be a vertical direction, or the Y direction may be a vertical direction.

[0155] <Additional Notes> The technical ideas that can be understood from this disclosure are described below. Note that, for the purpose of aiding understanding, not for the purpose of limitation, the components described in the appendices are given the reference numbers of the corresponding components in the above embodiment. The reference numbers are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numbers.

[0156] [Appendix 1] An element front surface (31) and an element back surface (32) facing the opposite side to the element front surface (31); A first electrode (44A) and a second electrode (44B) formed on the element surface (31); a plurality of first electrode terminals (50) in contact with the first electrode (44A); a plurality of second electrode terminals (60) in contact with the second electrode (44B); a first region (31A) in which a plurality of the first electrode terminals (50) are arranged; a second region (31B) in which a plurality of the second electrode terminals (60) are arranged; Equipped with the number of the second electrode terminals (60) per unit area in the second region (31B) is smaller than the number of the first electrode terminals (50) per unit area in the first region (31A); When viewed in a thickness direction (Z direction) that is a direction perpendicular to the element surface (31), the area of ​​the second electrode terminal (60) is larger than the area of ​​the first electrode terminal (50). A semiconductor element (30).

[0157] [Appendix 2] the first region (31A) is a region in which a first transistor and a second transistor connected in series with each other are formed, the second region (31B) is a region in which a control circuit for controlling the first transistor and the second transistor is formed, the plurality of first electrode terminals (50) are electrically connected to the first transistor and the second transistor; The plurality of second electrode terminals (60) are electrically connected to the control circuit. 2. The semiconductor device of claim 1.

[0158] [Appendix 3] The shape of the second electrode terminal (60) as viewed from the thickness direction (Z direction) is different from the shape of the first electrode terminal (50) as viewed from the thickness direction (Z direction), The first electrode terminal (50) has a circular shape when viewed from the thickness direction (Z direction). 3. A semiconductor device according to claim 1 or 2.

[0159] [Appendix 4] The second electrode terminal (60) has a rectangular shape when viewed from the thickness direction (Z direction). 4. The semiconductor device of claim 3.

[0160] [Appendix 5] the first electrode terminal (50) includes a first seed layer (52) in contact with the first electrode (44A) and a first plating layer (53) laminated on the first seed layer (52); The second electrode terminal (60) includes a second seed layer (62) in contact with the second electrode (44B) and a second plating layer (63) laminated on the second seed layer (62). 5. A semiconductor device according to any one of claims 1 to 4.

[0161] [Appendix 6] The thickness (T1) of the first seed layer (52) and the thickness (T2) of the second seed layer (62) are equal to each other. 6. The semiconductor device of claim 5.

[0162] [Appendix 7] An element front surface (31) and an element back surface (32) facing the opposite side to the element front surface (31); A first electrode (44A) and a second electrode (44B) formed on the element surface (31); a plurality of first electrode terminals (50) in contact with the first electrode (44A); a plurality of second electrode terminals (60) in contact with the second electrode (44B); a first region (31A) in which a plurality of the first electrode terminals (50) are arranged; a second region (31B) in which a plurality of the second electrode terminals (60) are arranged; Equipped with the number of the second electrode terminals (60) per unit area in the second region (31B) is smaller than the number of the first electrode terminals (50) per unit area in the first region (31A); A dummy terminal (90) is provided in the second region (31B). A semiconductor element (30).

[0163] [Appendix 8] The dummy terminal (90) is disposed closer to the second electrode terminal (60) than to the first electrode terminal (50). 8. The semiconductor device of claim 7.

[0164] [Appendix 9] When viewed from a thickness direction (Z direction) of the semiconductor element (30), the second electrode terminal (60) is disposed apart from the first electrode terminal (50) in a first direction (X direction), a third electrode (44C) formed in the second region (31B) of the element surface (31); The third electrode (44C) is provided between the first electrode (44A) and the second electrode (44B) in the first direction (X direction) and closer to the second electrode (44B), The dummy terminal (90) is in contact with the third electrode (44C). 9. The semiconductor device according to claim 7 or 8.

[0165] [Appendix 10] The height dimension (H3) of the dummy terminal (90) is smaller than the height dimension (H2) of the second electrode terminal (60). 10. A semiconductor device according to any one of claims 7 to 9.

[0166] [Appendix 11] The height dimension (H3) of the dummy terminal (90) is smaller than the height dimension (H1) of the first electrode terminal (50). 11. A semiconductor device according to any one of claims 7 to 10.

[0167] [Appendix 12] an insulating layer (45) having a first opening (45A) and a second opening (45B) is formed on the element surface (31); the first electrode terminal (50) is electrically connected to the first electrode (44A) through the first opening (45A); the second electrode terminal (60) is electrically connected to the second electrode (44B) through the second opening (45B); The dummy terminal (90) is provided on the insulating layer (45), The area of ​​the dummy terminal (90) as viewed from the thickness direction (Z direction) of the semiconductor element (30) is larger than the area of ​​the first electrode terminal (50) as viewed from the thickness direction (Z direction). 9. The semiconductor device according to claim 7 or 8.

[0168] [Appendix 13] The height dimension (H3) of the dummy terminal (90) is equal to the height dimension (H2) of the second electrode terminal (60). 13. The semiconductor device of claim 12.

[0169] [Appendix 14] When viewed from a thickness direction (Z direction) of the semiconductor element (30), the second electrode terminal (60) is disposed apart from the first electrode terminal (50) in a first direction (X direction), A direction perpendicular to the first direction (X direction) as viewed from the thickness direction (Z direction) is defined as a second direction (Y direction), The second electrode terminals (60) are arranged apart from each other in the second direction (Y direction), The dummy terminals (90) are provided in a plurality of locations spaced apart from each other in the second direction (Y direction). 14. A semiconductor device according to any one of claims 7 to 13.

[0170] [Appendix 15] The dummy terminals (90) are provided in plurality so as to surround the second electrode terminals (60) when viewed from the thickness direction (Z direction) of the semiconductor element (30). 14. A semiconductor device according to any one of claims 7 to 13.

[0171] [Appendix 16] The shape of the dummy terminal (90) when viewed from the thickness direction (Z direction) of the semiconductor element (30) is rectangular. 16. A semiconductor device according to any one of claims 7 to 15.

[0172] [Appendix 17] the first electrode terminal (50) includes a first seed layer (52) in contact with the first electrode (44A) and a first plating layer (53) laminated on the first seed layer (52); the second electrode terminal (60) includes a second seed layer (62) in contact with the second electrode (44B) and a second plating layer (63) laminated on the second seed layer (62); The dummy terminal (90) includes a third seed layer (92) in contact with the third electrode (44C), and a third plating layer (93) laminated on the third seed layer (92). 10. The semiconductor device of claim 9.

[0173] [Appendix 18] A substrate (100) having a substrate surface (101) on which a plurality of first surface wirings (111) and a plurality of second surface wirings (112) are formed; A semiconductor element (30) according to any one of appendices 1 to 17 mounted on both the plurality of first surface wirings (111) and the plurality of second surface wirings (112); a sealing resin (80) for sealing the semiconductor element (30); Equipped with the first electrode terminals (50) are individually and electrically connected to the first surface wirings (111); The second electrode terminals (60) are individually and electrically connected to the second surface wirings (112). A semiconductor device (10).

[0174] [Appendix 19] A plurality of first leads (21) and a plurality of second leads (22); A semiconductor element (30) according to any one of appendices 1 to 17 mounted on both of the plurality of first leads (21) and the plurality of second leads (22); a sealing resin (80) for sealing the semiconductor element (30); Equipped with the first electrode terminals (50) are individually and electrically connected to the first leads (21); The second electrode terminals (60) are individually and electrically connected to the second leads (22). A semiconductor device (10).

[0175] [Appendix 20] the semiconductor element (30) includes a dummy terminal (90) formed in the second region (31B); The dummy terminal (90) is insulated from the plurality of first surface wirings (111) and the plurality of second surface wirings (112). 19. The semiconductor device according to claim 18.

[0176] [Appendix 21] the semiconductor element (30) includes a dummy terminal (90) formed in the second region (31B); The dummy terminal (90) is insulated from the first leads (21) and the second leads (22). 20. The semiconductor device according to claim 19.

[0177] [Appendix 22] The shape of the second electrode terminal (60) when viewed from the thickness direction (Z direction) is different from the shape of the first electrode terminal (50) when viewed from the thickness direction (Z direction). 2. The semiconductor device of claim 1.

[0178] [Appendix 23] The second electrode terminal (60) has a rectangular shape when viewed from the thickness direction (Z direction). 23. The semiconductor device of claim 22.

[0179] [Appendix 24] The first electrode terminal (50) has a circular shape when viewed from the thickness direction (Z direction). 24. The semiconductor device according to claim 22 or 23.

[0180] [Appendix 25] Further comprising a dummy terminal (90) formed in the second region (31B), The shape of the dummy terminal (90) when viewed from the thickness direction (Z direction) is rectangular. 25. A semiconductor device according to any one of claims 22 to 24.

[0181] [Appendix 26] Further comprising a dummy terminal (90) formed in the second region (31B), The shape of the dummy terminal (90) when viewed from the thickness direction (Z direction) is circular. 25. A semiconductor device according to any one of claims 22 to 24.

[0182] [Appendix 27] The shape of the second electrode terminal (60) when viewed from the thickness direction (Z direction) is the same as the shape of the first electrode terminal (50) when viewed from the thickness direction (Z direction). 2. The semiconductor device of claim 1.

[0183] [Appendix 28] The first electrode terminal (50) and the second electrode terminal (60) have a circular shape when viewed in the thickness direction (Z direction). 28. The semiconductor device of claim 27.

[0184] [Appendix 29] Further comprising a dummy terminal (90) formed in the second region (31B), The shape of the dummy terminal (90) when viewed from the thickness direction (Z direction) is rectangular. 29. The semiconductor device according to claim 27 or 28.

[0185] [Appendix 30] Further comprising a dummy terminal (90) formed in the second region (31B), The shape of the dummy terminal (90) when viewed from the thickness direction (Z direction) is circular. 29. The semiconductor device according to claim 27 or 28.

[0186] [Appendix 31] The dummy terminal (90) is provided on the element surface (31), The area of ​​the dummy terminal (90) as viewed from the thickness direction (Z direction) of the semiconductor element (30) is larger than the area of ​​the first electrode terminal (50) as viewed from the thickness direction (Z direction). 9. The semiconductor device according to claim 7 or 8.

[0187] The above description is merely illustrative. Those skilled in the art may recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of describing the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and alterations that fall within the scope of the present disclosure, including the scope of the claims. [Explanation of symbols]

[0188] 10...Semiconductor device 11…Device surface 12...Back of the device 13~16…Device side 21, 21A~21C…First lead 21S…First lead surface 21R…First lead back 21BA…Protruding part 22, 22A~22H…2nd lead 22S…2nd lead surface 22R…2nd lead back 23…3rd lead 23S…3rd lead surface 23R…3rd lead back 30...Semiconductor element 31...Element surface 31A…First area 31B…Second area 32…Back side of element 33~36: Side of element 41...Semiconductor substrate 41A…Substrate surface 41B…Back side of board 42...Semiconductor layer 42A…Switching circuit 42B…Control circuit 43...Passivation film 44A, 44AA~44AC...First electrode 44B,44BA,44BB…2nd electrode 44C...Third electrode 44P…first metal layer 44Q…Second metal layer 44R…Third metal layer 45…Insulating layer 45A~45C...1st~3rd opening 50,50A~50C…1st electrode terminal 51…First pillar section 52…First seed layer 53…First plating layer 54…First surface plating layer 55…First recess 56…Tip surface 57…First solder part 60,60A~60H…Second electrode terminal 61…Second pillar section 62…Second seed layer 63…Second plating layer 64…Second surface plating layer 65…Second recess 66…Tip surface 67…Second solder part 70A…First plating layer 70B: Second plating layer 70C…Third plating layer 71…1st layer 72…Second layer 73...Third layer 80…Sealing resin 81…Sealing surface 83~86…Sealing side 90...Dummy terminal 91…Third pillar section 92…3rd seed layer 93...Third plating layer 94…Third surface plating layer 95…3rd recess 96…Tip surface 97…Third solder part 100...Substrate 101...Substrate surface 102…Back side of board 111...1st surface wiring 112…Second surface wiring 113…First rear wiring 114…Second back wiring 115...First through wiring 116...Second through wiring H1: Height of the first electrode terminal H2: Height of the second electrode terminal H3: Height of dummy terminal HD: Difference in height between the second electrode terminal and the first electrode terminal T1: Thickness of the first seed layer T2: Thickness of the second seed layer T3: Thickness of the first plating layer T4: Thickness of second plating layer T5: Thickness of the first surface plating layer T6: Thickness of plating layer on second surface T7…Thickness of the third seed layer T8: Thickness of the third plating layer T9…Thickness of the plating layer on the third surface D1: Distance between the first electrode terminal and the second electrode terminal in the X direction D2, D3: Distance between adjacent first electrode terminals in the X direction

Claims

1. a front surface of the element and a back surface of the element facing in a direction opposite to the front surface of the element; A first electrode and a second electrode formed on a surface of the element; a plurality of first electrode terminals in contact with the first electrode; a plurality of second electrode terminals in contact with the second electrode; a first region in which a plurality of the first electrode terminals are arranged; a second region in which a plurality of the second electrode terminals are arranged; Equipped with the number of the second electrode terminals per unit area in the second region is smaller than the number of the first electrode terminals per unit area in the first region; When viewed in a thickness direction that is a direction perpendicular to the surface of the element, the area of ​​the second electrode terminal is larger than the area of ​​the first electrode terminal. Semiconductor element.

2. the first region is a region in which a first transistor and a second transistor connected in series with each other are formed, the second region is a region in which a control circuit that controls the first transistor and the second transistor is formed, the first electrode terminals are electrically connected to the first transistor and the second transistor; The second electrode terminals are electrically connected to the control circuit. The semiconductor device according to claim 1 .

3. a shape of the second electrode terminal when viewed from the thickness direction is different from a shape of the first electrode terminal when viewed from the thickness direction, The first electrode terminal has a circular shape when viewed in the thickness direction. The semiconductor device according to claim 1 .

4. The second electrode terminal has a rectangular shape when viewed in the thickness direction. The semiconductor device according to claim 3 .

5. the first electrode terminal includes a first seed layer in contact with the first electrode and a first plating layer laminated on the first seed layer; The second electrode terminal includes a second seed layer in contact with the second electrode, and a second plating layer laminated on the second seed layer. The semiconductor device according to claim 1 .

6. The first seed layer and the second seed layer have an equal thickness. The semiconductor device according to claim 5 .

7. a front surface of the element and a back surface of the element facing in a direction opposite to the front surface of the element; A first electrode and a second electrode formed on a surface of the element; a plurality of first electrode terminals in contact with the first electrode; a plurality of second electrode terminals in contact with the second electrode; a first region in which a plurality of the first electrode terminals are arranged; a second region in which a plurality of the second electrode terminals are arranged; Equipped with the number of the second electrode terminals per unit area in the second region is smaller than the number of the first electrode terminals per unit area in the first region; A dummy terminal is provided in the second region. Semiconductor element.

8. The dummy terminal is disposed closer to the second electrode terminal than the first electrode terminal. The semiconductor device according to claim 7.

9. When viewed from a thickness direction of the semiconductor element, the second electrode terminal is disposed apart from the first electrode terminal in a first direction, a third electrode formed in the second region of the element surface; the third electrode is provided between the first electrode and the second electrode in the first direction and closer to the second electrode, The dummy terminal is in contact with the third electrode. The semiconductor device according to claim 7.

10. The height dimension of the dummy terminal is smaller than the height dimension of the second electrode terminal. The semiconductor device according to claim 7.

11. The height dimension of the dummy terminal is smaller than the height dimension of the first electrode terminal. The semiconductor device according to claim 7.

12. an insulating layer having a first opening and a second opening is formed on a surface of the element; the first electrode terminal is electrically connected to the first electrode in the first opening, the second electrode terminal is electrically connected to the second electrode in the second opening, the dummy terminal is provided on the insulating layer, The area of ​​the dummy terminal as viewed in a thickness direction of the semiconductor element is larger than the area of ​​the first electrode terminal as viewed in the thickness direction. The semiconductor device according to claim 7.

13. The height dimension of the dummy terminal is equal to the height dimension of the second electrode terminal. The semiconductor device of claim 12.

14. When viewed from a thickness direction of the semiconductor element, the second electrode terminal is disposed apart from the first electrode terminal in a first direction, When viewed from the thickness direction, a direction perpendicular to the first direction is defined as a second direction, The second electrode terminals are arranged spaced apart from each other in the second direction, The dummy terminals are provided in a plurality of locations spaced apart from one another in the second direction. The semiconductor device according to claim 7.

15. The dummy terminals are provided in a plurality so as to surround the second electrode terminal when viewed in a thickness direction of the semiconductor element. The semiconductor device according to claim 7.

16. The shape of the dummy terminal when viewed in the thickness direction of the semiconductor element is rectangular. The semiconductor device according to claim 7.

17. the first electrode terminal includes a first seed layer in contact with the first electrode and a first plating layer laminated on the first seed layer; the second electrode terminal includes a second seed layer in contact with the second electrode and a second plating layer laminated on the second seed layer, The dummy terminal includes a third seed layer in contact with the third electrode, and a third plating layer laminated on the third seed layer. The semiconductor device according to claim 9.

18. a substrate having a substrate surface, the substrate surface having a plurality of first surface wirings and a plurality of second surface wirings formed thereon; a semiconductor element according to any one of claims 1 to 17 mounted on both the plurality of first surface wirings and the plurality of second surface wirings; a sealing resin for sealing the semiconductor element; Equipped with the first electrode terminals are electrically connected to the first surface wirings individually; The second electrode terminals are electrically connected to the second surface wirings. Semiconductor device.

19. a plurality of first leads and a plurality of second leads; The semiconductor element according to any one of claims 1 to 17, which is mounted on both the plurality of first leads and the plurality of second leads; a sealing resin for sealing the semiconductor element; Equipped with the first electrode terminals are electrically connected to the first leads individually; The second electrode terminals are electrically connected to the second leads individually. Semiconductor device.

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