Semiconductor device

Abstract

To provide a semiconductor device in which even if the number of semiconductor chips increases, the wiring layout will not become difficult.SOLUTION: A semiconductor device 100 includes a base body 3, a first semiconductor chip 1 and a second semiconductor chip 2 disposed on the base body 3, and a base body wire 4 formed on the base body 3. The first semiconductor chip 1 and the second semiconductor chip 2 include switching elements. The first semiconductor chip 1 includes a first control pad 11 and a second control pad 12, at least one of which is connected to a control electrode of the switching element, and a connection part that connects the first control pad 11 and the second control pad 12. The second semiconductor chip 2 includes a third control pad 21 connected to the control electrode of the switching element. The base body wire 4 is connected to the first control pad 11 of the first semiconductor chip 1. The second control pad 12 of the first semiconductor chip 1 is connected to the third control pad 21 of the second semiconductor chip 2.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a power semiconductor module in which a first power semiconductor element and a second power semiconductor element connected in parallel have a plurality of gate pads which are wire-bonded to a plurality of gate wiring portions, respectively. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-46279 A Summary of the Invention [Problem to be solved by the invention]

[0004] Since the gate pads of each chip are wire-bonded to the gate wiring section, the number of wire bonds increases as the number of chips increases, making the wiring layout difficult.

[0005] The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device in which the wiring layout does not become difficult even if the number of semiconductor chips increases. [Means for solving the problem]

[0006] One aspect of the present invention is a semiconductor device comprising a base, a first semiconductor chip and a second semiconductor chip arranged on the base, and base wiring formed on the base. A switching element is formed on each of the first semiconductor chip and the second semiconductor chip. The first semiconductor chip has a first control pad and a second control pad, at least one of which is connected to a control electrode of the switching element, and a connection portion connecting the first control pad and the second control pad. The second semiconductor chip has a third control pad connected to the control electrode of the switching element. The base wiring is connected to the first control pad of the first semiconductor chip. The second control pad of the first semiconductor chip is connected to the third control pad of the second semiconductor chip. Effect of the Invention

[0007] According to one aspect of the present invention, it is possible to provide a semiconductor device in which the wiring layout does not become difficult even if the number of semiconductor chips increases. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view showing the configuration of a semiconductor device 100 according to the first embodiment. [Figure 2A] FIG. 2A is a plan view showing a connection portion 14A disposed inside first semiconductor chip 1. FIG. [Figure 2B] FIG. 2B is a cross-sectional view taken along line BB in FIG. 2A. [Diagram 3] FIG. 3 is a plan view showing the layout of wiring connected to the control electrodes of switching elements formed inside each semiconductor chip included in the semiconductor device 100 of FIG. [Figure 4] FIG. 4 is a plan view showing the configuration of a semiconductor device 101 according to the third embodiment. [Diagram 5] FIG. 5 is a plan view for illustrating first lead frame 33 connected to first electric-current pad 13 of first semiconductor chip 1. As shown in FIG. [Figure 6]FIG. 6 is a plan view showing a specific configuration of first semiconductor chip 1A according to a modified example and lead frames 33 and 34 connected to first semiconductor chip 1A. [Figure 7] FIG. 7 is a plan view showing a specific configuration of lead frames 33, 34 connected to first semiconductor chip 1A and second semiconductor chip 2A. [Figure 8] FIG. 8 is a plan view showing the layout of pads 51 to 54 formed on the surface of first semiconductor chip 1B. [Figure 9] FIG. 9 is a plan view showing the layout of pads 61 to 64 formed on the surface of the first semiconductor chip 1C. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The embodiments will be described with reference to the drawings. In the description of the drawings, the same parts are given the same reference numerals and the description will be omitted. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each part, etc. are different from the actual ones. In addition, it goes without saying that the drawings include parts whose dimensional relationships or ratios differ from each other.

[0010] In addition, the embodiments described below are merely examples of devices or methods for embodying the technical ideas, and are not intended to specify the shapes, structures, arrangements, etc. of the components described below. Various modifications can be made to the embodiments within the scope of the claims.

[0011] (First embodiment) The configuration of a semiconductor device 100 according to a first embodiment will be described with reference to Figures 1, 2A, and 2B. Figure 1 is a plan view showing the configuration of the semiconductor device 100 according to the first embodiment. The semiconductor device 100 includes a base 3, a plurality of semiconductor chips 1 and 2 arranged on the base 3, and a base wiring 4 formed on the base 3. Each of the plurality of semiconductor chips 1 and 2 has a switching element (not shown) formed thereon.

[0012] In the embodiment, a first semiconductor chip 1 and a second semiconductor chip 2 are exemplified as the multiple semiconductor chips. The semiconductor device 100 is not limited to this, and may further include a third, fourth, ... semiconductor chip. In this case, the third, fourth, ... semiconductor chips may have the same structure as the first semiconductor chip 1.

[0013] The substrate 3 includes a direct bonded copper (DBC) substrate in which a metal pattern such as copper is directly attached to an insulating substrate such as a ceramic substrate, other ceramic substrates, and a printed wiring board (PWB: Printed Wiring Board, PCB).

[0014] A base wiring 4 is formed on the surface of the base 3. The base wiring 4 is made of a conductive material, and is one of the wirings for transmitting and receiving electrical signals to each switching element of the first semiconductor chip 1 and the second semiconductor chip 2. The base wiring 4 is made of, for example, a copper wiring pattern in a DBC board. The base 3 may have wiring other than the base wiring 4 formed thereon, but this is not shown here. The base wiring 4 may also be called a land portion.

[0015] The first semiconductor chip 1 and the second semiconductor chip 2 are bonded to the surface of the base 3. The first semiconductor chip 1 and the second semiconductor chip 2 are bonded to the surface of the base 3 by a bonding method such as soldering or metal sintering. When the semiconductor device 100 includes three or more semiconductor chips, the three or more semiconductor chips may be arranged in a one-dimensional direction or in a two-dimensional direction. Although not shown, a cooler that cools the semiconductor device by dissipating heat generated from the first semiconductor chip 1 and the second semiconductor chip 2 to the outside may be bonded to the back surface of the base 3 opposite to the front surface bonded to the first semiconductor chip 1 and the second semiconductor chip 2.

[0016] The first semiconductor chip 1 and the second semiconductor chip 2 each have a switching element (not shown) formed thereon. The switching element is, for example, a power switching element such as an insulated gate bipolar transistor (IGBT), a heterojunction bipolar transistor (HBT), a MOS transistor, or a high electron mobility transistor (HEMT). In the embodiment, the structure and manufacturing method of the switching element are not particularly limited, and known element structures and manufacturing methods can be applied. The switching element has a pair of main electrodes through which a main current flows, and a control electrode that controls the conduction and interruption between the pair of main electrodes, or the amount of current flowing between the pair of main electrodes.

[0017] FIG. 2A is a plan view showing a connection portion 14A arranged inside the first semiconductor chip 1. FIG. 2B is a cross-sectional view taken along the line BB in FIG. 2A. In FIG. 2A and FIG. 2B, the switching elements formed on the substrate of the first semiconductor chip 1 and the wiring connected to the main electrodes of the switching elements are not shown. As shown in FIG. 1, FIG. 2A, and FIG. 2B, the first semiconductor chip 1 has a first control pad 11 and a second control pad 12 arranged on its surface, and a connection portion 14A connecting the first control pad 11 and the second control pad 12. At least one of the first control pad 11 and the second control pad 12 is connected to the control electrode of the switching element (not shown). The first control pad 11 and the second control pad 12 are each a thin metal film containing at least one of Cu (copper) and Al (aluminum).

[0018] As shown in FIG. 2A and FIG. 2B, the connection portion 14A may connect the first control pad 11 and the second control pad 12 inside the first semiconductor chip 1. That is, the connection portion 14A may be disposed inside the first semiconductor chip 1. This allows the areas of the pads 11, 12, and 13 formed on the surface of the first semiconductor chip 1 to be set large. Specifically, the connection portion 14A is formed in a wiring layer stacked on the surface of the semiconductor substrate of the first semiconductor chip 1. Contact plugs 15 and 16 formed adjacent to each other in the stacking direction are connected to the connection portion 14A. The connection portion 14A may connect the first control pad 11 and the second control pad 12 via the contact plugs 15 and 16. One end of each of the contact plugs 15 and 16 is connected to the first control pad 11 or the second control pad 12. The other ends of the contact plugs 15 and 16 are connected to both ends of the connection portion 14A. The connection portion 14A is, for example, a wiring made of polycrystalline silicon doped with a high concentration of impurities or a metal such as Cu or Al.

[0019] Alternatively, the connection portion 14A may connect the first control pad 11 and the second control pad 12 on the surface of the first semiconductor chip 1. In other words, the connection portion 14A may be disposed on the surface of the first semiconductor chip 1. One pad having one planar pattern combining the first control pad 11, the second control pad 12, and the connection portion 14A shown in FIG. 2A may be formed on the surface of the first semiconductor chip 1.

[0020] The second semiconductor chip 2 has a third control pad 21 formed on the surface of the second semiconductor chip 2. The third control pad 21 is connected to a control electrode of a switching element formed on the second semiconductor chip 2. The second semiconductor chip 2 may have not only the third control pad 21 but also a fourth control pad 22. In this case, the third control pad 21 and the fourth control pad 22 are connected by a member similar to the connection portion 14A that connects the first control pad 11 and the second control pad 12.

[0021] As shown in FIG. 1, the first semiconductor chip 1 is disposed at a position on the base 3 closer to the base wiring 4 than the second semiconductor chip 2. The first control pad 11 is formed at a position on the first semiconductor chip 1 closer to the base wiring 4 than the second control pad 12. The base wiring 4 is connected to the first control pad 11 of the first semiconductor chip 1 by a wiring. This makes it possible to shorten the length of the wiring. The base wiring 4 is connected to the first control pad 11 by a bonding wire 5a made of Au (gold) or a gold alloy, as an example of the wiring.

[0022] The third control pad 21 is formed at a position on the second semiconductor chip 2 closer to the first semiconductor chip 1 than the fourth control pad 22. The third control pad 21 of the second semiconductor chip is connected to the second control pad 12 of the first semiconductor chip 1 by wiring. This allows the length of the wiring to be shortened. For example, the third control pad 21 is connected to the second control pad 12 by a bonding wire 5b made of Au or a gold alloy, which is an example of wiring. Instead of the bonding wires 5a, 5a, the surface of a base on which metal wiring is printed may be pressed against and fixed to the surfaces of the first semiconductor chip 1 and the second semiconductor chip 2, thereby connecting the third control pad 21 and the second control pad 12 by metal wiring.

[0023] When the semiconductor device 100 includes third, fourth, etc. semiconductor chips, the control pads of the third, fourth, etc. semiconductor chips can be sequentially connected to the fourth control pad 22 of the second semiconductor chip 2. This allows the control pads of the multiple semiconductor chips included in the semiconductor device 100 to be connected in series. This eliminates the need to connect each of the control pads of the multiple semiconductor chips to the base wiring 4 by bonding wires or the like. Even if the number of semiconductor chips increases, a wiring layout in which bonding wires do not cross over each other is possible.

[0024] 1, the first control pad 11 and the second control pad 12 may be disposed on the outer periphery of the surface of the first semiconductor chip 1. This makes it possible to shorten the length of the bonding wires 5a and 5b that connect the first semiconductor chip 1 to the adjacent base wiring 4 or the third control pad 21 of the second semiconductor chip 2, thereby suppressing delays in the control signals input to the switching elements.

[0025] The third control pad 21 and the fourth control pad 22 may be disposed on the outer periphery of the surface of the second semiconductor chip 2. This makes it possible to shorten the length of the bonding wire 5b that connects the third control pad 21 of the second semiconductor chip 2 to the adjacent second control pad 12 of the first semiconductor chip 1, thereby suppressing delays in the control signals input to the switching elements.

[0026] In the first embodiment, the first semiconductor chip 1 may have a first current-carrying pad 13 formed on the surface of the first semiconductor chip 1 and connected to one main electrode of the switching element. By arranging the first control pad 11 and the second control pad 12 in the outer periphery of the surface of the first semiconductor chip 1, the current capacity of the first current-carrying pad 13 can be increased. The second semiconductor chip 2 may have a third current-carrying pad 23 formed on the surface of the second semiconductor chip 2 and connected to one main electrode of the switching element. By arranging the third control pad 21 and the fourth control pad 22 in the outer periphery of the surface of the second semiconductor chip 2, the current capacity of the third current-carrying pad 23 can be increased.

[0027] The connection portion 14A of the first semiconductor chip 1 connects the first control pad 11 and the second control pad 12. The second control pad 12 of the first semiconductor chip 1 is connected to the third control pad 21 of the second semiconductor chip 2. Therefore, if the first control pad 11 of the first semiconductor chip 1 is connected to the base wiring 4, the control electrodes of the switching elements of both the first semiconductor chip 1 and the second semiconductor chip 2 can be connected to the base wiring 4. Therefore, it is not necessary to make each of the control pads 11, 12, 21, and 22 of each semiconductor chip 1 and 2 the base wiring 4. Therefore, even if the number of semiconductor chips included in the semiconductor device 100 increases, the number of bonding wires connected to the base wiring 4 remains constant, making it possible to make a wiring layout. Even if the number of semiconductor chips increases, the semiconductor device 100 makes it possible to make a wiring layout in which the bonding wires do not cross over each other. The first embodiment can provide a semiconductor device in which the wiring layout is not difficult.

[0028] 1, the first control pad 11 and the base wiring 4 are connected at one location (one bonding wire 5a), but may be connected at multiple locations, that is, there may be multiple bonding wires 5a.

[0029] Connection portion 14A connects first control pad 11 and second control pad 12 inside first semiconductor chip 1. This allows the areas of pads 11, 12, and 13 formed on the surface of first semiconductor chip 1 to be set large.

[0030] The semiconductor device according to claim 1, characterized in that the first semiconductor chip 1 and the second semiconductor chip 2 are made of wide bandgap semiconductors. Wide bandgap semiconductors include SiC (silicon carbide) and GaN (gallium nitride). By using wide bandgap semiconductors as the first semiconductor chip 1 and the second semiconductor chip 2, it is possible to reduce losses generated in switching elements and to miniaturize the semiconductor device 100.

[0031] Second embodiment In the second embodiment, a layout example of control wiring connected to control electrodes of switching elements formed in each semiconductor chip will be described with reference to Fig. 3. Here, the first semiconductor chip 1 will be described as an example, but the other semiconductor chips including the second semiconductor chip 2 also have a similar configuration.

[0032] The first semiconductor chip 1 has control wiring 25, 19a, 19b connected to the control electrodes of the switching elements, and impedance adjustment units 17, 18 that connect the control wiring 19a, 19b to at least one of the first control pad 11 and the second control pad 12. Fig. 3 shows an example in which both the first control pad 11 and the second control pad 12 are connected to the second control wiring 19a, 19b by the impedance adjustment units 17, 18, respectively.

[0033] The control wirings 25, 19a, 19b include a first control wiring 25 and second control wirings 19a, 19b. Although not shown, a countless number of unit cells having a switching function are formed on the surface of the semiconductor substrate of the first semiconductor chip 1. Reference numeral 24 in FIG. 3 indicates an active region in which a countless number of unit cells are formed. The switching element of the first semiconductor chip 1 is an assembly of the countless unit cells. Each control electrode of the countless unit cells is first connected to a plurality of first control wirings 25 extending in the Y direction. Then, both ends of the plurality of first control wirings 25 are respectively connected to second control wirings 19a, 19b extending in the X direction perpendicular to the Y direction. One end of the impedance adjustment unit 17 is connected to the second control wiring 19a. The other end of the impedance adjustment unit 17 is connected to the first control pad 11. One end of the impedance adjustment unit 18 is connected to the second control wiring 19b. The other end of the impedance adjustment unit 18 is connected to the second control pad 12. In other words, the first control pad 11 is connected to the second control wiring 19a via the impedance adjuster 17. The second control pad 12 is connected to the second control wiring 19b via the impedance adjuster .

[0034] The first semiconductor chip 1 has a connection portion 14B that connects the first control pad 11 and the second control pad 12. The connection portion 14B is disposed in an area other than the active area 24 of the switching element, and connects the first control pad 11 and the second control pad 12 by bypassing the active area 24. The connection portion 14B is common to the connection portion 14A of FIG. 2A and FIG. 2B except for this point. The impedance adjustment portions 17 and 18 may be in contact with the connection portion 14B or may be in contact with the contact plugs 15 and 16 shown in FIG. 2B. The first semiconductor chip 1 may have only one of the combination of the second control wiring 19a and the impedance adjustment portion 17 and the combination of the second control wiring 19b and the impedance adjustment portion 18. Even in this case, the first control pad 11 and the second control pad 12 can be connected to the control electrode of the switching element. The connection portion 14B, the impedance adjustment portions 17, 18, the second control wirings 19a, 19b, and the first control wiring 25 may be formed in the same wiring layer in the multilayer wiring structure of the first semiconductor chip 1, or may be formed in different wiring layers.

[0035] The impedance adjustment units 17 and 18 are wirings formed in the wiring layer of the first semiconductor chip 1. The impedance adjustment units 17 and 18 are wirings made of, for example, polycrystalline silicon doped with a high concentration of impurities or metals such as Cu or Al, similar to the connection units 14A and 14B. The resistance and reactance of the impedance adjustment units 17 and 18 are adjusted using at least one of the material, impurity concentration, planar shape, width, and thickness of the wiring as a parameter. Alternatively, the adjustment may be performed by inserting an additional member such as a resistive member.

[0036] By adjusting the impedance between the control wiring and at least one of the first control pad and the second control pad using the impedance adjustment units 17 and 18, the current flowing through the control wiring can be adjusted for each semiconductor chip. For example, the capacitance and resistance of the impedance adjustment unit of the second semiconductor chip 2 far from the base wiring 4 are made smaller than that of the first semiconductor chip 1 close to the base wiring 4, so that the current can flow more easily through the second semiconductor chip 2. This makes it possible to reduce the difference in signal arrival time between the first semiconductor chip 1 directly connected to the base wiring 4 and the second semiconductor chip connected to the base wiring 4 via the first semiconductor chip 1. In other words, the difference in signal arrival time between semiconductor chips according to the distance from the base wiring 4 can be reduced. In addition, by adjusting the impedance of the impedance adjustment units 17 and 18 in the same chip, the difference in signal arrival time between unit cells in the same chip can be reduced. For example, the impedance of the impedance adjustment unit can be adjusted to be smaller as the distance of the path through which the control signal flows from the base wiring 4 increases.

[0037] Third embodiment The configuration of the semiconductor device 101 according to the third embodiment will be described with reference to FIG. 4. The first semiconductor chip 1 has a first control pad 31 and a second control pad 32. The first control pad 31 and the second control pad 32 sandwich the first energizing pad 13 when viewed from the normal direction of the surface of the first semiconductor chip 1, and are arranged on the outer periphery of the surface of the first semiconductor chip 1. This allows the area of ​​the first energizing pad 13 formed on the surface of the first semiconductor chip 1 to be larger than that of the semiconductor device 101 of FIG. 1. This improves the current capacity (allowable current) of the first energizing pad 13. This improves the degree of freedom of the wiring layout on the surface of the first semiconductor chip 1. In addition, the distance between the bonding wires 5a and 5b is shortened, thereby reducing signal delay.

[0038] The second semiconductor chip 2 has a third control pad 41 and a fourth control pad 42. Similar to the first control pad 31 and the second control pad 32, the third control pad 41 and the fourth control pad 42 are disposed on either side of the third conductive pad 23 when viewed from the normal direction of the surface of the second semiconductor chip 2, and are disposed on the outer periphery of the surface of the second semiconductor chip 2. This shortens the distance of the bonding wire 5b, thereby reducing signal delay. Also, the same effects as those of the first semiconductor chip 1 can be obtained.

[0039] The first control pad 31 is disposed adjacent to one side (the upper side in FIG. 4) of the first semiconductor chip 1 adjacent to the base wiring 4. This shortens the length of the bonding wire 5a connecting the base wiring 4 and the first control pad 31.

[0040] The second control pad 32 is arranged adjacent to the other side (the bottom side in FIG. 4) of the first semiconductor chip 1 corresponding to the first control pad 31. The third control pad 41 is arranged adjacent to one side (the top side in FIG. 4) of the second semiconductor chip 2 adjacent to the other side of the first semiconductor chip 1. This shortens the length of the bonding wire 5b connecting the second control pad 32 and the third control pad 41.

[0041] In the semiconductor device 101 shown in Fig. 4, the positions of the first control pad 31, the second control pad 32, the third control pad 41, and the fourth control pad 42 on the surface of the semiconductor chip, and the planar shapes of the first energizing pad 13 and the third energizing pad 23 are different from those of the semiconductor device 100 shown in Fig. 1. Except for these points, the semiconductor device 101 is common to the semiconductor device 100.

[0042] (Fourth embodiment) With reference to FIG. 5, the first lead frame 33 connected to the first current-carrying pad 13 of the first semiconductor chip 1 will be described. The semiconductor device according to the fourth embodiment further includes a first lead frame 33 connected to the first current-carrying pad 13 of the first semiconductor chip 1. A main current of the switching element flows through the first lead frame 33. The first lead frame 33 is made of a conductive material with high thermal conductivity (heat dissipation), such as Cu. The surface of the first semiconductor chip 1 has a square shape. FIG. 5 shows a rectangular shape as an example. The outer shape of the surface of the first semiconductor chip 1 has four sides 1a to 1d. The first control pad 31 and the second control pad 32 are disposed adjacent to two opposing sides 1a and 1c of the surface of the first semiconductor chip 1, respectively. The other configuration of the first semiconductor chip 1 in FIG. 5 is the same as the configuration of the first semiconductor chip 1 according to the third embodiment shown in FIG. 4, and therefore a description thereof will be omitted.

[0043] The first lead frame 33 extends from one of the two opposing sides 1b, 1d, which are two sides 1b, 1d different from the two sides 1a, 1c of the first semiconductor chip 1, to the outside of the surface of the first semiconductor chip 1. In the example of Fig. 5, the first lead frame 33 is led out from the side 1b of the surface of the first semiconductor chip 1 to the outside of the first semiconductor chip 1. However, the first lead frame 33 may be led out from the side 1d of the first semiconductor chip 1 to the outside of the first semiconductor chip 1.

[0044] The first lead frame 33 extends from a side 1b different from the sides 1a and 1c of the first semiconductor chip 1 to which the first control pad 31 and the second control pad 32 are adjacent, to the outside of the first semiconductor chip 1. This allows the width of the first lead frame 33 to be designed based on the overall length of one side 1b of the first semiconductor chip 1. This increases the width of the first lead frame 33, and allows the current capacity of the first lead frame 33 to be increased.

[0045] (Modification) When the switching element has a vertical structure, one main electrode is formed on the front surface of the semiconductor substrate, and the other main electrode is formed on the rear surface of the semiconductor substrate. Therefore, in the example shown in Figs. 1 to 5, only the first current-carrying pad 13 connected to one main electrode of the switching element is formed on the front surface of the semiconductor chip. In contrast, when the switching element has a horizontal structure, a pair of main electrodes is formed on the front surface of the semiconductor chip. Therefore, as shown in Fig. 6, a pair of current-carrying pads 13, 14 are formed on the chip front surface, and a lead frame is connected to each of the current-carrying pads 13, 14. In a modified example, the lead frames 33, 34 can be extended outside the front surface of the first semiconductor chip 1A from both of the two opposing sides 1b, 1d.

[0046] The first semiconductor chip 1A has conductive pads 13 and 14 formed on its surface. The conductive pads 13 and 14 have a first conductive pad 13 connected to one main electrode of the switching element and a second conductive pad 14 connected to the other main electrode of the switching element. The semiconductor device 100 includes a first lead frame 33 connected to the first conductive pad 13 and a second lead frame 34 connected to the second conductive pad 14. The first lead frame 33 extends to the outside of the first semiconductor chip 1A from one (side 1d) of two sides 1b and 1d different from the two opposing sides 1a and 1c on which the control pads 31 and 32 are arranged. The second lead frame 34 extends to the outside of the first semiconductor chip 1A from the other (side 1b) of two sides 1b and 1d different from the two opposing sides 1a and 1c on which the control pads 31 and 32 are arranged.

[0047] The second lead frame 34 extends from sides 1b and 1d, which are different from the sides 1a and 1b of the first semiconductor chip 1A on which the first control pad 31 and the second control pad 32 are arranged, to the outside of the first semiconductor chip 1A. This allows the width of the second lead frame 34 to be designed based on the overall length of one side 1b of the first semiconductor chip 1. This increases the width of the second lead frame 34, and allows the current capacity of the second lead frame 34 to be increased.

[0048] Fifth embodiment In the modification (FIG. 6), the configuration of the lead frames 33, 34 connected to the first semiconductor chip 1A has been described. The lead frames 33, 34 are also connected to the second semiconductor chip 2A. In the fifth embodiment, a specific layout of the lead frames 33, 34 connected to the first semiconductor chip 1A and the second semiconductor chip 2A will be described with reference to FIG. 7.

[0049] As shown in FIG. 7, the semiconductor device 102 includes a base 3, a base wiring 4, a first semiconductor chip 1A, a second semiconductor chip 2A, a first lead frame 33, and a second lead frame 34. The first semiconductor chip 1A has a first energizing pad 13 and a second energizing pad 14 formed on its surface, similar to the first semiconductor chip 1A shown in FIG. 6. The second semiconductor chip 2A also has a third energizing pad 43 and a fourth energizing pad 44 formed on its surface, similar to the first semiconductor chip 1A shown in FIG. 6. The third energizing pad 43 is connected to one of a pair of main electrodes of a switching element formed on the second semiconductor chip 2A, and the fourth energizing pad 44 is connected to the other of a pair of main electrodes of a switching element formed on the second semiconductor chip 2A.

[0050] The first lead frame 33 and the second lead frame 34 arranged on the base 3 are each branched into two. The two branch ends 33b and 33c of the first lead frame 33 are connected to the first current-carrying pad 13 and the third current-carrying pad 43, respectively. The two branch ends 34b and 34c of the second lead frame 34 are connected to the second current-carrying pad 14 and the fourth current-carrying pad 44, respectively. When viewed from the normal direction of the surface of the first semiconductor chip 1A, the length of the first lead frame 33 from the position 33a where the outer edge of the base 3 and the first lead frame 33 intersect to the first current-carrying pad 13 is the same as the length of the first lead frame 33 from the position 33a to the third current-carrying pad 43. Specifically, the length of the first lead frame 33 from the position 33a to the branch end 33b is equal to the length of the first lead frame 33 from the position 33a to the branch end 33c.

[0051] The length of the first lead frame 33 connected to the first conductive pad 13 of the first semiconductor chip 1A is equal to the length of the first lead frame 33 connected to the third conductive pad 43 of the second semiconductor chip 2A. This can eliminate the imbalance between the first semiconductor chip 1A and the second semiconductor chip 2A caused by the length of the first lead frame 33. Specifically, the inductance of the first lead frame 33 can be made uniform. The length of the second lead frame 34 connected to the second conductive pad 14 of the first semiconductor chip 1A may be equal to the length of the second lead frame 34 connected to the fourth conductive pad 44 of the second semiconductor chip 2A. Specifically, the length of the second lead frame 34 from the position 34a to the branch destination 34b may be equal to the length of the second lead frame 34 from the position 34a to the branch destination 34c. In FIG. 7, the first lead frame 33 and the second lead frame 34 are taken out in the same direction (upward in FIG. 7), but the first lead frame 33 and the second lead frame 34 may be taken out in different directions.

[0052] Sixth embodiment In the sixth embodiment, an example of the layout of pads 51 to 54 formed on the surface of a first semiconductor chip 1B will be described with reference to Fig. 8. The first semiconductor chip 1B has a first control pad 51, a second control pad 52, a first current-carrying pad 53, and a second current-carrying pad 54 formed on the surface thereof.

[0053] The first control pad 51 and the second control pad 52 are connected by a connection portion (not shown) formed inside the first semiconductor chip 1B. At least one of the first control pad 51 and the second control pad 52 is connected to a control electrode of a switching element formed on the first semiconductor chip 1B. The first current-carrying pad 53 is connected to one of a pair of main electrodes of the switching element, and the second current-carrying pad 54 is connected to the other of the pair of main electrodes of the switching element.

[0054] The first control pad 51 and the second control pad 52 are disposed at positions symmetrical with respect to the center of the surface of the first semiconductor chip 1B. This allows the area of ​​the conductive pads 53 and 54 to be increased. In addition, the degree of freedom in the layout of the lead frame connected to the conductive pads 53 and 54 is improved.

[0055] In the example shown in FIG. 8, the surface of the first semiconductor chip 1B has a rectangular shape. The first control pad 51 and the second control pad 52 are arranged at opposite corners of the surface of the first semiconductor chip 1B. The first control pad 51 is arranged at the upper left corner of the first semiconductor chip 1B. The second control pad 52 is arranged at the lower right corner of the first semiconductor chip 1B. The conductive pads 53 and 54 are arranged along a pair of long sides of the surface of the first semiconductor chip 1B, respectively. The width of the lead frame connected to the conductive pads 53 and 54 can be further increased as compared to the examples shown in FIGS. 6 and 7.

[0056] In the sixth embodiment, the connection portion connecting the first control pad 51 and the second control pad 52 may be formed in a region excluding the active region 24 (see FIG. 3) of the switching element. The same applies to the first control pad 61 and the second control pad 62 shown in FIG.

[0057] Seventh embodiment 8 shows an example in which the first control pad 51 and the control pad 52 are disposed at opposing corners. However, the control pads 51 and 52 may be disposed at positions symmetrical with respect to the center of the surface of the first semiconductor chip 1B, and may be disposed at the centers of two opposing sides 1a and 1c of the chip surface, for example, as shown in FIG.

[0058] As shown in FIG. 9, the first semiconductor chip 1C has a first control pad 61, a second control pad 62, a first current-carrying pad 63, and a second current-carrying pad 64 formed on its surface. The first control pad 61 and the second control pad 62 may be disposed on a line connecting the centers of two short sides 1a and 1c of the surface of the first semiconductor chip 1C having a rectangular shape. The positions of the first control pad 61 and the second control pad 62 may be on a line connecting the centers of the two short sides 1a and 1c, and may not be at the ends of the surface of the first semiconductor chip 1B. The second semiconductor chip may also have a layout of pads 61 to 64 similar to that of the first semiconductor chip 1C (not shown). The first semiconductor chip 1C and the second semiconductor chip are disposed in the same row on the base so that their short sides are adjacent to each other. This makes it possible to shorten the distance between the third control pad of the second semiconductor chip and the second control pad 62 of the first semiconductor chip 1C, that is, the length of the bonding wire connecting the third control pad and the second control pad 62, compared to the layout example of FIG. 8. 8, the first and second current-carrying pads 63 and 64 can be arranged along a pair of long sides on the chip surface. The width of the lead frame connected to the current-carrying pads 63 and 64 can be set large. The second semiconductor chip has the same pad layout structure as the first semiconductor chip 1C. This simplifies the wiring layout between the chips and ensures the width in the extraction direction of the current-carrying pads 63 and 64, so that the main current can be extracted to the outside with low resistance. [Explanation of symbols]

[0059] 1, 1A, 1B, 1C First semiconductor chip 2, 2A second semiconductor chip 3 Base 4 Base wiring 5a, 5b Bonding wire 11 First Control Pad 12 2nd Control Pad 13, 53, 63 First conductive pad 14, 54, 64 2nd conductive pad 14A, 14B Connection 17, 18 Impedance adjustment section 19a Second control wiring 19b Second control wiring 21, 41 3rd control pad 23, 43 3rd conductive pad 25 First control wiring 31, 51, 61 1st control pad 32, 52, 62 2nd control pad 33 First lead frame 34 Second lead frame 34a position 42 4th Control Pad 44 4th conductive pad 100~102 Semiconductor device

Claims

1. A substrate; a first semiconductor chip and a second semiconductor chip disposed on the base; A substrate wiring formed on the substrate; A semiconductor device comprising: A switching element is formed on each of the first semiconductor chip and the second semiconductor chip, The first semiconductor chip is a first control pad and a second control pad arranged on the surface thereof, at least one of which is connected to a control electrode of the switching element; a connection portion connecting the first control pad and the second control pad; having the second semiconductor chip has a third control pad formed on a surface thereof and connected to a control electrode of a switching element; the substrate wiring is connected to the first control pad of the first semiconductor chip; the second control pad of the first semiconductor chip is connected to the third control pad of the second semiconductor chip; Semiconductor device.

2. The first semiconductor chip is a control wiring disposed inside the switching element and connected to a control electrode of the switching element; an impedance adjustment unit that connects the control wiring to at least one of the first control pad and the second control pad; 2. The semiconductor device according to claim 1, comprising:

3. the first semiconductor chip has a first conductive pad formed on the surface and connected to one main electrode of a switching element; The first control pad and the second control pad are disposed on either side of the first conductive pad when viewed in a normal direction of the front surface, and are disposed on an outer periphery of the front surface. The semiconductor device according to claim 1 .

4. the semiconductor device includes a first lead frame connected to the first conductive pad; The surface of the first semiconductor chip is rectangular, the first control pad and the second control pad are disposed adjacent to two opposing sides of the surface, The first lead frame is extended from one of the two opposing sides to the outside of the surface. The semiconductor device according to claim 3 .

5. the first semiconductor chip has a second conductive pad formed on the surface and connected to another main electrode of the switching element; the semiconductor device includes a second lead frame connected to the second conductive pad; The second lead frame extends from the other of the two opposing sides of the surface that are different from the two sides to the outside of the surface. The semiconductor device according to claim 4.

6. the second semiconductor chip has a third conductive pad formed on a surface thereof and connected to one main electrode of the switching element; the first lead frame is connected to the first current-carrying pad and the third current-carrying pad; When viewed from the normal direction of the surface, a length of the first lead frame from a position where an outer edge of the base intersects with the first lead frame to the first current-carrying pad is equal to a length of the first lead frame from the position to the third current-carrying pad.

6. The semiconductor device according to claim 4 or 5.

7. 5. The semiconductor device according to claim 4, wherein the first control pad and the second control pad are arranged at positions symmetrical with respect to a center of the surface of the first semiconductor chip.

8. The semiconductor device according to claim 7 , wherein the first control pad and the second control pad are disposed at corners of the surface of the first semiconductor chip.

9. 8. The semiconductor device according to claim 7, wherein the first control pad and the second control pad are each disposed on a line connecting centers of two short sides of the surface of the first semiconductor chip having a rectangular shape.

10. 2. The semiconductor device according to claim 1, wherein the connection portion connects the first control pad and the second control pad inside the first semiconductor chip.

11. 2. The semiconductor device according to claim 1, wherein the first semiconductor chip and the second semiconductor chip are made of a wide band gap semiconductor.

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