Techniques for reducing phase shift in single crystal multiple output clock systems.

Abstract

Some aspects of the present disclosure provide a circuit for clock signal generation. The circuit generally includes a plurality of clock generation circuits configured to generate a plurality of clock signals from a clock signal, and a power supply circuit having an output coupled to a power supply input of the plurality of clock generation circuits. The circuit also includes a capacitor array coupled to the output of the power supply circuit and may include a plurality of capacitive elements, the capacitor array configured to selectively couple each of the plurality of capacitive elements to the output of the power supply circuit based on an amount of active one or more of the plurality of clock generation circuits.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. patent application Ser. No. 17 / 154,726, filed Jan. 21, 2021, which is expressly incorporated by reference in its entirety into this specification as if fully set forth below and for all applicable purposes.

[0002]

[0002] Certain aspects of the present disclosure relate generally to electronic components, and more particularly, to clock generation circuits. [Background technology]

[0003]

[0003] A wireless device may include a radio frequency (RF) front-end (RFFE) circuit for processing and amplifying signals for transmission and reception. In some implementations, a wireless device may include separate RF chips, each including an RFFE circuit, for wireless transmission and reception for various applications, such as near field communication (NFC) or cellular communication. Each of the RF chips may operate using an RF clock signal, which may be generated via a power management integrated circuit (PMIC). For example, the PMIC may include a regulator for generating a supply voltage, which may be used by a clock buffer to buffer an oscillating signal generated via a crystal oscillator. In some cases, multiple clock buffers may be used to buffer the oscillating signal for generation of multiple RF clock signals to be provided to the RF chips. Summary of the Invention

[0004]

[0004] The system, method, and device of the present disclosure each have several aspects, no single aspect of which is solely responsible for the desirable attributes of the present disclosure. Next, some features will be briefly described without limiting the scope of the present disclosure as expressed by the following claims. By considering this description, and especially by reading the section entitled "Description of the Preferred Embodiments," one can understand how the features of the present disclosure provide advantages including reduced cost and area consumption associated with clock generation circuits.

[0005]

[0005] Some aspects of the present disclosure provide a circuit for clock signal generation. The circuit generally includes a plurality of clock generation circuits configured to generate a plurality of clock signals from a clock signal, and a power supply circuit having an output coupled to a power supply input of the plurality of clock generation circuits. The circuit also includes a capacitor array coupled to the output of the power supply circuit and may include a plurality of capacitive elements, the capacitor array configured to selectively couple each of the plurality of capacitive elements to the output of the power supply circuit based on a quantity of one or more active clock generation circuits of the plurality of clock generation circuits.

[0006]

[0006] Some aspects of the present disclosure provide a method for clock signal generation. The method generally includes activating one or more clock generation circuits of a plurality of clock generation circuits, generating one or more clock signals from a clock signal via the one or more active clock generation circuits, and generating a supply voltage at an output of the power supply circuit coupled to a power supply input of the plurality of clock generation circuits via a power supply circuit. In some aspects, the method may also include selectively coupling each of a plurality of capacitive elements to an output of the power supply circuit based on an amount of the one or more active clock generation circuits.

[0007]

[0007] Some aspects of the present disclosure provide an apparatus for clock signal generation. The apparatus generally includes a means for activating one or more clock generating circuits of a plurality of clock generating circuits, a means for generating a supply voltage, the one or more active clock generating circuits configured to generate one or more clock signals from a clock signal, and the generating means generates a supply voltage at an output of the generating means coupled to a power supply input of the plurality of clock generating circuits. The apparatus may also include a means for selectively coupling each of a plurality of capacitive elements to an output of the generating means based on an amount of the one or more active clock generating circuits.

[0008]

[0008] Some aspects of the present disclosure provide a computer-readable medium having stored thereon instructions for causing a processor to activate one or more clock generation circuits of a plurality of clock generation circuits, the one or more active clock generation circuits being configured to generate one or more clock signals from a clock signal. The computer-readable medium may also include instructions stored thereon for causing the processor to selectively couple each of a plurality of capacitive elements to an output of a power supply circuit based on an amount of the one or more active clock generation circuits, the power supply circuit being configured to generate a supply voltage at an output of the power supply circuit coupled to a power supply input of the plurality of clock generation circuits.

[0009]

[0009] To the accomplishment of the foregoing and related ends, the one or more aspects comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative of but a few of the various ways in which the principles of the various aspects may be employed.

[0010]

[0010] So that the above-recited features of the present disclosure may be understood in detail, a more particular description may be given by referring to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings show only some embodiments of the present disclosure and therefore should not be considered as limiting the scope of the present disclosure, since the description may lead to other equally effective embodiments. [Brief description of the drawings]

[0011] [Figure 1]

[0011] FIG. 1 is a diagram of an example wireless communication network in accordance with certain aspects of the present disclosure. [Diagram 2]

[0012] 1 is a block diagram of an example access point (AP) and an example user terminal, in accordance with certain aspects of the present disclosure. [Diagram 3]

[0013] 1 is a block diagram of an example transceiver front end in accordance with certain aspects of the present disclosure. [Figure 4]

[0014] FIG. 1 illustrates a power management integrated circuit (PMIC) implemented with a single crystal oscillator (XO) multi-output clock architecture in accordance with some aspects of the present disclosure. [Diagram 5]

[0015] FIG. 2 illustrates a radio frequency (RF) clock signal and a supply voltage waveform for generating the RF clock signal for a PMIC implementation without a capacitor array. [Figure 6]

[0016] FIG. 2 illustrates an example implementation of a capacitor array of a PMIC in accordance with some aspects of the disclosure. [Figure 7]

[0017] FIG. 2 illustrates RF clock signal and supply voltage waveforms associated with a PMIC implemented with a capacitor array in accordance with certain aspects of the disclosure. [Figure 8]

[0018] FIG. 2 illustrates an example implementation of a switch and a capacitive element of a capacitor array in accordance with some aspects of the present disclosure. [Figure 9]

[0019] 4 is a flow diagram illustrating example operations for clock signal generation in accordance with certain aspects of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012]

[0020] For ease of understanding, wherever possible, the same reference numbers have been used to designate like elements that are common to each of the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation.

[0013]

[0021] Some aspects of the present disclosure generally relate to a clock generation circuit having different clock buffers to generate separate clock signals to be provided to multiple radio frequency (RF) chips. Each of the RF chips may include an RF front-end (RFFE) circuit to process signals for transmission and reception for various applications. At any time, one or more of the clock buffers may be active, and the clock buffers may be provided with a common supply signal. Depending on the amount of clock buffers that are active, the supply signal may experience varying levels of undershoot (e.g., voltage droop) when the output of the active clock buffer transitions from one logic state to another. This variation may cause different rise times of the clock signal generated by the active clock buffers, resulting in a phase shift associated with the clock signal, which may adversely affect the operation of the corresponding RF chip to which the clock signal is provided. Some aspects of the present disclosure provide a capacitor array that selectively couples capacitive elements to a supply node that provides a supply voltage based on the amount of active clock buffers. In this manner, the variation of the undershoot on the supply voltage is reduced, effectively reducing the phase shift associated with the clock signal.

[0014] Exemplary Wireless Communication System

[0022] FIG. 1 illustrates a wireless communication system 100 with an access point 110 and a user terminal 120 in which aspects of the disclosure may be implemented. For simplicity, only one access point 110 is shown in FIG. 1. An access point (AP) is generally a fixed station that communicates with user terminals and may also be referred to as a base station (BS), an evolved Node B (eNB), or some other terminology. A user terminal (UT) may be fixed or mobile and may also be referred to as a mobile station (MS), an access terminal, user equipment (UE), a station (STA), a client, a wireless device, or some other terminology. A user terminal may be a wireless device such as a cellular phone, a personal digital assistant (PDA), a handheld device, a wireless modem, a laptop computer, a tablet, a personal computer, etc.

[0015]

[0023] An access point 110 may communicate with one or more user terminals 120 at any given moment on the downlink and uplink. The downlink (or forward link) is the communication link from the access point to the user terminals, and the uplink (or reverse link) is the communication link from the user terminals to the access point. A user terminal may also communicate peer-to-peer with other user terminals. A system controller 130 couples to the access points and provides coordination and control for the access points.

[0016]

[0024] The wireless communication system 100 employs multiple transmit antennas and multiple receive antennas for data transmission on the downlink and uplink. The access point 110 may employ N transmit antennas to achieve transmit diversity for downlink transmissions and / or receive diversity for uplink transmissions. ap It can be equipped with N antennas. uA set of selected user terminals 120 may receive downlink transmissions and transmit uplink transmissions. Each selected user terminal may transmit user-specific data to and / or receive user-specific data from the access point. In general, each selected user terminal may be equipped with one or multiple antennas (i.e., N ut ≧1). N u The selected user terminals may have the same or different number of antennas.

[0017]

[0025] The wireless communication system 100 may be a time division duplex (TDD) system or a frequency division duplex (FDD) system. For a TDD system, the downlink and uplink share the same frequency band. For an FDD system, the downlink and uplink use different frequency bands. The wireless communication system 100 may also utilize a single carrier or multiple carriers for transmission. Each user terminal 120 may be equipped with a single antenna (e.g., to keep costs down) or multiple antennas (e.g., if the additional cost can be supported).

[0018]

[0026] In some aspects, a user terminal 120 or an access point 110 may include multiple RF chips for transmission and reception of signals for various applications. The multiple chips may receive separate clock signals that are generated using a common supply voltage. In some aspects, as described in more detail herein, a capacitor array may be used to reduce phase shifts associated with the clock signals to improve operation of the RF chips.

[0019]

[0027] 2 shows a block diagram of an access point 110 and two user terminals 120m and 120x in a wireless communication system 100. The access point 110 has N ap The user terminal 120m is equipped with N antennas 224a to 224ap. ut,m The user terminal 120x is equipped with N antennas 252ma to 252mu.ut,x The access point 110 is equipped with antennas 252xa-252xu. The access point 110 is a transmitting entity for the downlink and a receiving entity for the uplink. Each user terminal 120 is a transmitting entity for the uplink and a receiving entity for the downlink. As used herein, a "transmitting entity" is an independently operated apparatus or device capable of transmitting data over a frequency channel, and a "receiving entity" is an independently operated apparatus or device capable of receiving data over a frequency channel. In the following description, the subscript "dn" refers to the downlink, the subscript "up" refers to the uplink, and the subscript "n" refers to the downlink. up user terminals are selected for simultaneous transmission on the uplink, and N dn user terminals are selected for simultaneous transmission on the downlink, and N up is N dn may or may not be equal to N up and N dn , may be a static value or may change every scheduling interval. Beam-steering, beamforming, or some other spatial processing technique may be used at the access point and / or user terminal.

[0020]

[0028] On the uplink, at each user terminal 120 selected for uplink transmission, a TX data processor 288 receives traffic data from a data source 286 and control data from a controller 280. TX data processor 288 generates traffic data for the user terminal based on a coding and modulation scheme associated with the rate selected for the user terminal. up} to process (e.g., encode, interleave, and modulate) N ut,m A data symbol stream {s upA transceiver front end (TX / RX) 254 (also known as a radio frequency front end (RFFE)) receives and processes (e.g., converts to analog, amplifies, filters, and frequency upconverts) each symbol stream to generate an uplink signal. The transceiver front end 254 also provides N ut,m A controller 280 may route the uplink signal to one of the antennas. A controller 280 may control routing within the transceiver front end 254. A memory 282 may store data and program codes for the user terminal 120 and may interface with the controller 280.

[0021]

[0029] N up user terminals 120 may be scheduled for simultaneous transmission on the uplink, each of which transmits its set of processed symbol streams on the uplink to the access point.

[0022]

[0030] At the access point 110, N ap The antennas 224a through 224ap transmit on the uplink. up The access point front end 222 receives uplink signals from the user terminals. For receive diversity, the transceiver front end 222 may select a signal received from one of the antennas 224 for processing. Signals received from multiple antennas 224 may be combined for enhanced receive diversity. The access point front end 222 also performs processing complementary to that performed by the user terminal transceiver front end 254 and provides a recovered uplink data symbol stream. The recovered uplink data symbol stream may be a composite of the data symbol stream {s up} is an estimate of. The RX data processor 242 processes (e.g., demodulates, deinterleaves, and decodes) the recovered uplink data symbol stream according to the rate used for that stream to obtain decoded data. The decoded data for each user terminal may be provided to a data sink 244 for storage and / or to controller 230 for further processing.

[0023]

[0031] On the downlink, at access point 110, a TX data processor 210 processes N dn The TX data processor 210 receives traffic data for the N user terminals from a data source 208, control data from a controller 230, and possibly other data from a scheduler 234. Various types of data may be sent on different transport channels. The TX data processor 210 processes (e.g., encodes, interleaves, and modulates) the traffic data for each user terminal based on the rate selected for that user terminal. The TX data processor 210 processes (e.g., encodes, interleaves, and modulates) the traffic data for the N user terminals based on the rate selected for that user terminal. ap N to be transmitted from one of the antennas. dn The transceiver front end 222 may provide a downlink data symbol stream for one of more than one user terminal. The transceiver front end 222 receives and processes (e.g., converts to analog, amplifies, filters, and frequency upconverts) the symbol stream to generate a downlink signal. The transceiver front end 222 may also provide a downlink data symbol stream for one of more than one user terminal. ap A controller 230 may route downlink signals to one or more of the antennas 224. A controller 230 may control routing within the transceiver front end 222. A memory 232 may store data and program codes for the access point 110 and may interface with the controller 230.

[0024]

[0032] In each user terminal 120, N ut,mThe antennas 252 receive downlink signals from the access point 110. For receive diversity at the user terminal 120, the transceiver front end 254 may select signals received from one or more of the antennas 252 for processing. Signals received from the multiple antennas 252 may be combined for enhanced receive diversity. The user terminal's transceiver front end 254 also performs processing complementary to that performed by the access point's transceiver front end 222 and provides a recovered downlink data symbol stream. The RX data processor 270 processes (e.g., demodulates, deinterleaves, and decodes) the recovered downlink data symbol stream to obtain decoded data for the user terminal.

[0025]

[0033] In some aspects, the transceiver front end 254 or 222 may include multiple RF chips for transmitting and receiving signals for various applications. The multiple chips may receive separate clock signals that are generated using a common supply voltage. In some aspects, as described in more detail herein, a capacitor array may be used to reduce phase shifts associated with the clock signals to improve operation of the RF chips.

[0026]

[0034] 3 is a block diagram of an example transceiver front end 300, such as the transceiver front ends 222, 254 in FIG. 2, in which aspects of the disclosure may be implemented. The transceiver front end 300 includes a transmit (TX) path 302 (also known as a transmit chain) for transmitting signals via one or more antennas, and a receive (RX) path 304 (also known as a receive chain) for receiving signals via the antennas. When the TX path 302 and the RX path 304 share an antenna 303, the paths may be connected to the antenna via an interface 306.

[0027]

[0035] When receiving an in-phase (I) or quadrature-phase (Q) baseband analog signal from a digital-to-analog converter (DAC) 308, the TX path 302 may include a baseband filter (BBF) 310, a mixer 312, a driver amplifier (DA) 314, and a power amplifier (PA) 316. The BBF 310, the mixer 312, and the DA 314 may be included in a radio frequency integrated circuit (RFIC), while the PA 316 may be external to the RFIC.

[0028]

[0036] The BBF 310 filters the baseband signal received from the DAC 308, and the mixer 312 mixes the filtered baseband signal with a transmit local oscillator (LO) signal to convert the baseband signal to a different frequency (e.g., upconvert from baseband to RF). This frequency conversion process generates sum and difference frequencies between the LO frequency and the frequency of the signal of interest. The sum and difference frequencies are called beat frequencies. The beat frequencies are generally in the RF range, and therefore the signal output by the mixer 312 is generally an RF signal and may be amplified by the DA 314 and / or amplified by the PA 316 before transmission by the antenna 303.

[0029]

[0037] The RX path 304 includes a low noise amplifier (LNA) 322, a mixer 324, and a baseband filter (BBF) 326. The LNA 322, the mixer 324, and the BBF 326 may be included in a radio frequency integrated circuit (RFIC) that may or may not be the same RFIC that includes the TX path components. An RF signal received via the antenna 303 may be amplified by the LNA 322, and the mixer 324 mixes the amplified RF signal with a receive local oscillator (LO) signal to convert (i.e., downconvert) the RF signal to a different baseband frequency. The baseband signal output by the mixer 324 may be filtered by the BBF 326 before being converted by an analog-to-digital converter (ADC) 328 to a digital I or Q signal for digital signal processing.

[0030]

[0038] Although it is desirable for the output of the LO to remain stable in frequency, tuning the LO to different frequencies generally involves using a variable frequency oscillator, which may involve a compromise between stability and tunability. Modern systems may employ frequency synthesizers with voltage controlled oscillators (VCOs) to generate a stable, tunable LO with a specific tuning range. Thus, the transmit LO frequency may be generated by the TX frequency synthesizer 318, and the transmit LO frequency may be buffered or amplified by the amplifier 320 before being mixed with the baseband signal in the mixer 312. Similarly, the receive LO frequency may be generated by the RX frequency synthesizer 330, and the receive LO frequency may be buffered or amplified by the amplifier 332 before being mixed with the RF signal in the mixer 324.

[0031]

[0039] In some cases, the transceiver front end 300 may be part of an RF chip and operate using a clock signal that is generated using a supply voltage that is also used to generate one or more other clock signals for other RF chips. In some aspects, as described in more detail herein, a capacitor array may be used to reduce a phase shift associated with the clock signal to improve operation of the transceiver front end 300.

[0032] Exemplary Techniques for Clock Generation

[0040] As described herein, a wireless device may be implemented with multiple radio frequency (RF) chips for various applications. Each of the RF chips may operate using a separate RF clock signal. In some cases, the RF clock signal may be generated using a single crystal oscillator (XO). A multiple clock scheme based on a single XO provides cost savings compared to having an individual XO for each of the multiple clocks. However, this single XO multiple output clock architecture results in interdependencies between the clock channels, which may result in performance degradation resulting from phase shifts associated with the clock channels. Some aspects of the present disclosure are generally directed to techniques for reducing performance degradation associated with a single XO multiple output clock architecture in a manner that reduces cost and area consumption compared to conventional applications.

[0033]

[0041] 4 illustrates a power management integrated circuit (PMIC) 400 implemented with a single XO multiple output clock architecture in accordance with some aspects of the disclosure. The PMIC 400 includes RF devices 4101, 4102, ..., 410 n The PMIC may be implemented with a clock generation system 401 having a clock generation circuit for generating n separate RF clock signals RFCLK1, RFCLK2, ..., RFCLKn to be provided to a PMIC (e.g., an RF chip). For example, a PMIC may include an XO core and pre-buffer circuit 402 coupled to an XO 404, which may be external to the PMIC. The XO core and pre-buffer circuit 402 generates a pre-buffered clock signal that is provided to an RF clock buffer circuit 408. The RF clock buffer circuit 408 includes separate clock buffers 4061, 4062, ..., 406 n , where n is an integer greater than 2. As shown, clock buffers 4061, 4062, ..., 406 n Each of the RF devices 4101, 4102, ..., 410 n, RFCLKn to be provided to a respective one of the RF clock signals RFCLK1, RFCLK2, . . . , RFCLKn.

[0034]

[0042] For ease of understanding, the exemplary PMIC 400 is implemented with three clock buffers to generate three different clock signals, however, aspects described herein may be applied to implementations used to generate two or more clock signals (e.g., using two or more clock buffers). Moreover, although the examples provided herein are described with respect to RF clock signals, aspects described herein may be applied to generate clock signals at any suitable frequency for a variety of applications.

[0035]

[0043] As shown, RF clock buffers 4061, 4062, ..., 406 n may be supplied with the same regulated supply voltage (VREG_RF) generated by the power supply circuit 414 at its output 416. As shown, the power supply circuit 414 may include a regulator 412 (e.g., a low-dropout (LDO) regulator) to generate VREG_RF at the output 416 of the power supply circuit 414. VREG_RF is coupled to clock buffers 4061, 4062, ..., 4063 to generate multiple clock signals. n However, using a single supply voltage to generate multiple clock signals can have the disadvantage of a power-supply-pulling effect. For example, as described in more detail herein with respect to FIG. 5, clock buffers 4061, 4062, ..., 406 n The output of one of the clock buffers 4061, 4062, ..., 406 n416 is activated (e.g., enabled), a phase shift may be experienced. In some aspects, a capacitor array 420 may be coupled to the output 416 of the power supply circuit 414 to reduce this phase shift, as described in more detail herein.

[0036]

[0044] 5 illustrates RF clock signals RFCLK1 and RFCLK2 and a supply voltage waveform VREG_RF for generating the RF clock signals for a PMIC implementation without the capacitor array 420. As shown, RFCLK1 may have a rise time 502 during a clock cycle and a second rise time 504 during a subsequent clock cycle. As shown, the rise time 504 may be longer than the rise time 502 due to an increased undershoot of VREG_RF during a logic transition (e.g., rise time 504) of RFCLK1 caused by RFCLK2 being activated during the subsequent clock cycle. For example, ringing (e.g., oscillation) of VREG_RF may occur when one or more of the RFCLK1, RFCLK2, ..., RFCLKn signals transition from a logic low to a logic high, with the amount of undershoot associated with the ringing depending on the amount of RF clocks that are active and transitioning from a logic low to a logic high at the same time. 5, a relatively lower undershoot 506 may occur when only RFCLK1 is active, and a relatively higher undershoot 508 may occur when both RFCLK1 and RFCLK2 are active. The higher undershoot 508 results in a longer rise time 504, as well as a similar rise time 510 for RFCLK2. This variation in rise times 502, 504 may result in a phase shift in RFCLK1, which may adversely affect the performance of the RF device 4101 to which RFCLK1 is provided.

[0037]

[0045] As shown in Figure 4, an off-chip (e.g., off-PMIC 400) capacitive element 440 may be coupled to the output 416 of the power delivery circuitry 414. The capacitive element 440 (and associated routing) may have a parasitic inductance 444, which may cause ringing on VREG_RF, as described with reference to Figure 5. To reduce the ringing, a relatively large capacitive element (e.g., about 1 nF) may be implemented on the PMIC 400. However, including such a large capacitive element may result in higher cost and area for the PMIC.

[0038]

[0046] In some aspects of the disclosure, a capacitor array 420 may be coupled to the output 416 to reduce the amount of variation in the undershoot associated with VREG_RF, resulting in a reduced clock phase shift associated with the RF clock signal as described herein. In other words, instead of implementing relatively large capacitive elements on the PMIC to reduce ringing associated with VREG_RF, a capacitor array may be implemented with programmable capacitance configured to reduce the variation in the undershoot when different combinations of clock buffers are activated. The reduced variation in undershoot improves the phase shift associated with the clock signal without the implementation of relatively large on-chip capacitive elements, reducing cost and area consumption.

[0039]

[0047] 6 illustrates an example implementation of a capacitor array 420 in accordance with some aspects of the disclosure. As shown, the capacitor array 420 includes capacitive elements 6021, 6022, ..., 602 n , each of which includes a switch 6041, 6042, ..., 604 n , 6021, 6022, ..., 602 n At least one of the clock buffers 4061, 4062, ..., 406 may be implemented using a capacitor. nThe same amount of capacitive elements 6021, 6022, ..., 602 n , but the capacitor array 420 may be implemented with a different amount of capacitive elements than the clock buffers. The capacitor array 420 may be configured to couple a larger amount of capacitive elements to the output 416 when the first clock buffer is activated (e.g., because the first clock buffer has a higher load) compared to when the second clock buffer is activated. Capacitive elements 6021, 6022, ..., 602 n Each of the clock enable signals clk1_en, clk2_en, ..., clkn_en may be controlled via a respective one of the clock enable signals clk1_en, clk2_en, ..., clkn_en. The clock enable signals clk1_en, clk2_en, ..., clkn_en are also coupled to respective clock buffers 4061, 4062, ..., 4063, as shown. n , clk1_en, ..., clkn_en may be generated via the controller 230. In some aspects, the capacitive element 440 may have a lower capacitance compared to an implementation of a PMIC without the capacitor array 420. The capacitive element 440 may provide a baseline level of filtering when all switches of the capacitor array 420 are open.

[0040]

[0048] 7 illustrates RF clock signals RFCLK1 and RFCLK2 and a supply voltage waveform VREG_RF associated with a PMIC 400 implemented with a capacitor array 420 according to some aspects of the disclosure. As shown, with the implementation of the capacitor array 420, there is no or at least a reduced variation between the undershoot 506 and the undershoot 508 of VREG_RF. In other words, during a first clock cycle of RFCLK1, a capacitive element 6021 may be coupled to the output 416. During a second clock cycle of RFCLK1, both capacitive elements 6021, 6022 may be coupled to the output 416 since both RFCLK1 and RFCLK2 are active. Thus, the undershoot 508 is reduced to approximately the same level as the undershoot 506, thus reducing the undershoot variation between clock cycles, effectively reducing the phase shift associated with RFCLK1. The ringing associated with undershoot 506 may have a higher frequency than the ringing associated with undershoot 508 due to the varying amount of capacitive element coupled to output 416 .

[0041]

[0049] 8 illustrates an example implementation of the switches and capacitive elements of the capacitor array 420 according to some aspects of the disclosure. For example, the switch 6041 may be implemented with a transistor (e.g., an n-type metal-oxide-semiconductor (NMOS) transistor) and the capacitive element 6021 may be implemented using a transistor (e.g., a p-type metal-oxide-semiconductor (PMOS) transistor). For example, a gate of a PMOS transistor (e.g., the capacitive element 6021) may be coupled to the switch 6041, and a source and a drain of the PMOS transistor are coupled to a reference potential node (e.g., electrical ground). The transistor implementing the switch 6041 may have a source coupled to the output 416, a drain coupled to the capacitive element 6021, and a gate configured to receive a clock enable signal CLK1_enb (e.g., the inverse of CLK1_en).

[0042]

[0050] There may be a leakage current associated with the capacitive element 6021. Thus, while the switch 6041 is open, the voltage at the node 806 may decrease due to the leakage of the capacitive element 6021, causing a disturbance on VREG_RF when the switch 6041 is closed.

[0043]

[0051] In some aspects, a resistive element may be coupled in parallel with the switch 6041 in an attempt to compensate for leakage current associated with the capacitive element 6021. For example, the resistive element may be implemented using a transistor 808 (e.g., a PMOS transistor) having a source coupled to the output 416, a drain coupled to the capacitive element 6021, and a gate that may be biased to implement the resistive element. To compensate for the leakage current of the capacitive element 6021 and avoid (or at least reduce) a voltage drop at the node 806, the resistance of the resistive element (the on-resistance of the PMOS transistor) may be configured such that a current is supplied from the output 416 through the resistive element to the capacitive element 6021.

[0044]

[0052] 9 is a flow diagram illustrating example operations 900 for clock signal generation in accordance with some aspects of the disclosure. The operations 900 may be performed by a clock generation system, such as the clock generation system 401.

[0045]

[0053] The operations 900 begin at block 905 with a clock generation system including a plurality of clock generation circuits (e.g., clock buffers 4061, 4062, . . . , 406 n ), in block 910, the clock generation system generates one or more clock signals (e.g., RFCLK1, RFCLK2, ..., RFCLKn) from a clock signal (e.g., a pre-buffered clock signal generated by the pre-buffer circuit 402) via the one or more active clock generation circuits. In block 915, the clock generation system generates a supply voltage (e.g., VREG_RF) at an output (e.g., output 416) of a power supply circuit that is coupled (e.g., via the power supply circuit 414) to the power supply inputs of the multiple clock generation circuits.

[0046]

[0054] In block 920, the clock generation system may be configured to selectively generate a plurality of capacitive elements (e.g., capacitive elements 6021, 6022, ..., 6023) based on the amount of active clock generation circuitry. n ) to an output of the power supply circuit. For example, the amount of the plurality of capacitive elements coupled to the output of the power supply circuit may correspond to the amount of the one or more active clock generation circuits. In some aspects, the clock generation system may change the amount of the one or more active clock generation circuits and change the amount of the plurality of capacitive elements coupled to the output of the power supply circuit based on the changed amount of the one or more active clock generation circuits. That is, the amount of the plurality of capacitive elements may be changed such that an undershoot associated with a supply voltage is the same (e.g., within a margin of 30 mV) before and after changing the amount of the one or more active clock generation circuits.

[0047]

[0055] In some aspects, selectively coupling each of the plurality of capacitive elements includes selectively coupling each of the plurality of capacitive elements to an output of the power supply circuit using a switch (e.g., switches 6041, 6042, ..., 604 n ) In some implementations, at least one of the multiple capacitive elements may include a transistor (e.g., an NMOS transistor) having a gate coupled to a respective one of the switches, with the drain and source of the transistor coupled to a reference potential node (e.g., reference potential node 810). In some aspects, a resistive element (e.g., transistor 808) may be coupled in parallel with at least one of the switches. The resistance of the resistive element may be configured such that when the switch is open, a current across the resistive element corresponds to a leakage current of the capacitive element.

[0048]

[0056] In some aspects, the clock generation system may receive, via each clock generation circuit of the plurality of clock generation circuits, an enable signal (e.g., clock enable signals clk1_en, clk2_en, ..., clkn_en) configured to activate the clock generation circuit, and the switch is controlled based on a respective one of the enable signals. In some aspects, the clock generation system may receive, via at least one of the plurality of clock generation circuits, an enable signal (e.g., clock enable signals clk1_en, clk2_en, ..., clkn_en) configured to activate the clock generation circuit, and the switch is controlled based on a respective one of the enable signals. n ) may provide a respective one of the one or more clock signals. In some aspects, the inputs of multiple clock generation circuits may be coupled to the output of an oscillator (e.g., XO 404).

[0049]

[0057] Within this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the described feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling between two objects. For example, if object A physically contacts object B, and object B contacts object C, then object A and object C may still be considered to be coupled to each other even if object A and object C are not in direct physical contact with each other. For example, a first object may be coupled to a second object even if the first object never comes into direct physical contact with the second object. The terms "circuit" and "circuitry" are used broadly and are intended to include hardware implementations of both electrical devices and conductors that, when connected and configured, enable performance of the functions described in this disclosure, without limitation as to the type of electronic circuitry.

[0050]

[0058] The apparatus and methods described in the detailed description are illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as "elements"), which may be implemented using hardware, for example.

[0051]

[0059] One or more of the components, steps, features and / or functions shown herein may be rearranged and / or combined into a single component, step, feature or function, or performed in several components, steps or functions. Also, additional elements, components, steps and / or functions may be added without departing from the features disclosed herein. The apparatus, devices and / or components shown herein may be configured to perform one or more of the methods, features or steps described herein.

[0052]

[0060] It is understood that the specific order or hierarchy of steps in the disclosed methods is an example of an example process. Based on design preferences, it is understood that the specific order or hierarchy of steps in the methods may be rearranged. The accompanying method claims present elements of the various steps in a sample order, and are not limited to the specific order or hierarchy presented, unless specifically recited in the method claims.

[0053]

[0061] The above description is provided to enable those skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Thus, the claims are not limited to the aspects set forth herein, but are to be accorded the full scope consistent with the language of the claims, in which reference to an element in the singular does not mean "one and only one" unless so expressly stated, but rather means "one or more." Unless otherwise expressly stated, the term "some" refers to one or more. A phrase referring to "at least one of" a list of items refers to any combination of those items, including single members. As an example, "at least one of a, b, or c" is intended to cover at least a, b, c, ab, ac, bc, and abc, as well as any combination with multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other order of a, b, and c). All structural and functional equivalents of the elements of the various aspects described throughout this disclosure that are known or that later become known to those skilled in the art are expressly incorporated herein by reference and are encompassed by the claims. Moreover, nothing disclosed herein is made public, regardless of whether such disclosure is expressly recited in the claims. No claim element is to be construed under the provisions of 35 U.S.C. 112(f) unless the element is expressly recited using the phrase "means for" or, in the case of a method claim, unless the element is recited using the phrase "step for."

[0054]

[0062] It should be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

[0055]

[0063] The various operations of the methods described above may be performed by any suitable means capable of performing the corresponding functions. Those means may include various (one or more) hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs), or processors. Generally, where there are operations illustrated in the figures, those operations may have corresponding counterpart means-plus-function components with similar numbers. In some aspects, the means for activating may include a controller, such as controller 230. In some aspects, the means for generating may include a power supply circuit, such as power supply circuit 414. In some aspects, the means for selectively coupling may include a capacitor array, such as capacitor array 420.

[0056]

[0064] The various example logic blocks, modules, and circuits described in connection with this disclosure may be implemented or performed using a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but alternatively, the processor may be any commercially available processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0057]

[0065] If implemented in software, the functions may be stored on or transmitted over a computer-readable medium as one or more instructions or code. Software should be broadly construed to mean instructions, data, or any combination thereof, whether termed software, firmware, middleware, microcode, hardware description language, or otherwise. Computer-readable media includes both computer storage media and communication media, including any medium that facilitates transfer of a computer program from one place to another. A processor may be responsible for managing a bus and general processing, including the execution of software modules stored in a machine-readable storage medium. A computer-readable storage medium may be coupled to a processor such that the processor can read information from the storage medium and write information to the storage medium. Alternatively, the storage medium may be integral to the processor. By way of example, a machine-readable medium may include a transmission line, a carrier wave modulated by data, and / or a computer-readable storage medium with instructions stored thereon that is separate from a wireless node, all of which may be accessed by a processor via a bus interface. Alternatively or additionally, the machine-readable medium, or any portion thereof, may be integrated into the processor, such as may be a cache and / or a general-purpose register file. Examples of machine-readable storage media may include, by way of example, a RAM (random access memory), a flash memory, a ROM (read-only memory), a PROM (programmable read-only memory), an EPROM (erasable programmable read-only memory), an EEPROM (electrically erasable programmable read-only memory), a register, a magnetic disk, an optical disk, a hard drive, or other suitable storage media, or any combination thereof. The machine-readable medium may be embodied in a computer program product.

[0058]

[0066] A software module may comprise a single instruction, or many instructions, and may be distributed over several different code segments, among different programs, and across multiple storage media. A computer-readable medium may comprise several software modules. A software module includes instructions that, when executed by a device such as a processor, cause a processing system to perform various functions. A software module may include a transmitting module and a receiving module. Each software module may reside in a single storage device or be distributed across multiple storage devices. As an example, a software module may be loaded from a hard drive into RAM when a trigger event occurs. During execution of a software module, a processor may load some of the instructions into a cache to increase access speed. One or more cache lines may then be loaded into a general-purpose register file for execution by the processor. When referring to a function of a software module below, it will be understood that such function is implemented by a processor when executing instructions from that software module.

[0059]

[0067] Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared (IR), radio, and microwave, the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks typically reproduce data magnetically and discs reproduce data optically with lasers. Thus, in some aspects computer-readable medium may comprise non-transitory computer-readable medium (e.g., tangible media). Additionally, in other aspects computer readable media may comprise transitory computer readable media (eg, a signal). Combinations of the above should also be included within the scope of computer readable media.

Claims

1. 1. A circuit for generating a clock signal, comprising: a plurality of clock generation circuits configured to generate a plurality of clock signals from a clock signal; a power supply circuit having an output coupled to a power supply input of the plurality of clock generation circuits; coupled to the output of the power supply circuit; A plurality of capacitive elements; a switch coupled between each of the plurality of capacitive elements and the output of the power supply circuit; a capacitor array comprising: wherein the capacitor array is configured to selectively couple each of the plurality of capacitive elements to the output of the power supply circuit based on an amount of active one or more of the plurality of clock generation circuits.

2. 2. The circuit of claim 1, wherein the capacitor array is configured such that a quantity of the plurality of capacitive elements coupled to the output of the power supply circuit corresponds to the quantity of the one or more active clock generation circuits.

3. 2. The circuit of claim 1, wherein at least one of the plurality of capacitive elements comprises a transistor having a gate coupled to a respective one of the switches, the drain and source of the transistor being coupled to a reference potential node.

4. 2. The circuit of claim 1, wherein at least one of the plurality of capacitive elements comprises a capacitor coupled between a respective one of the switches and a reference potential node, and wherein the transistor preferably comprises an n-type metal-oxide-semiconductor (NMOS) transistor.

5. 2. The circuit of claim 1, further comprising a resistive element coupled in parallel with at least one of the switches, preferably the resistance of the resistive element being configured such that when the switch is open, a current across the resistive element corresponds to a leakage current of the capacitive element, preferably the resistive element being a transistor having a source coupled to the output, a drain coupled to the capacitive element, and a gate biased to implement the resistance.

6. 2. The circuit of claim 1, wherein each clock generation circuit of the plurality of clock generation circuits is configured to receive an enable signal configured to activate the clock generation circuit, and the switch is configured to be controlled based on a respective one of the enable signals, preferably the enable signals being provided by a controller, wherein the controller is configured to control which of the plurality of clock generation circuits are activated.

7. 2. The circuit of claim 1, wherein at least one of the plurality of clock generation circuits is configured to provide a respective one of the plurality of clock signals to a radio frequency (RF) front-end (RFFE) circuit.

8. 2. The circuit of claim 1, further comprising an oscillator, wherein inputs of the plurality of clock generation circuits are coupled to an output of the oscillator.

9. 1. A method for clock signal generation, comprising: activating one or more clock generation circuits of the plurality of clock generation circuits; generating one or more clock signals from the clock signal via the one or more active clock generation circuits; generating a supply voltage at an output of a power supply circuit coupled via the power supply circuit to power supply inputs of the plurality of clock generation circuits; selectively coupling each of a plurality of capacitive elements to the output of the power supply circuit based on an amount of the one or more active clock generation circuits, wherein selectively coupling each of the plurality of capacitive elements comprises controlling a switch coupled between each of the plurality of capacitive elements and the output of the power supply circuit. A method comprising:

10. A quantity of the plurality of capacitive elements coupled to the output of the power supply circuit corresponds to the quantity of the one or more active clock generation circuits, and preferably the method further comprises: Varying the amount of the one or more active clock generation circuits; Varying the amount of the plurality of capacitive elements coupled to the output of the power supply circuit based on the changed amount of the one or more active clock generation circuits. The method of claim 9 further comprising:

11. 11. The method of claim 10, wherein altering the amount of the one or more active clock generation circuits is performed by a controller providing an enabling signal to the clock generation circuits.

12. Varying the amount of the plurality of capacitive elements is performed by a controller providing an enabling signal to each switch coupled to a respective one of the plurality of capacitive elements; or 11. The method of claim 10, wherein the quantity of the plurality of capacitive elements is changed such that an undershoot associated with the supply voltage is the same before and after changing the quantity of the one or more active clock generation circuits.

13. The method of claim 9 or the circuit of claim 1, wherein each of the plurality of clock generation circuits comprises a clock buffer.

14. at least one of the plurality of capacitive elements comprises a transistor having a gate coupled to a respective one of the switches, the drain and source of the transistor being coupled to a reference potential node; or 10. The method of claim 9, wherein a resistive element is coupled in parallel with at least one of the switches, the resistance of the resistive element being configured such that when the switch is open, a current across the resistive element corresponds to a leakage current of the capacitive element.

15. 12. The method of claim 11, further comprising receiving, via each clock generation circuit of the plurality of clock generation circuits, an enable signal configured to activate the clock generation circuit, the switch being controlled based on a respective one of the enable signals.

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