Rich excitation response pair weak PUF circuit based on MOS tube leakage current

Abstract

The invention discloses a rich excitation response pair weak PUF circuit based on MOS tube leakage current, which comprises a first decoder, a second decoder, a third decoder, a fourth decoder, a first PUF array, a second PUF array, two transmission gate arrays and a shared head, each PUF array comprises 2q column units, q is an integer greater than 1, each column unit comprises 2p NMOS units, p is an integer greater than 1, and n is an integer greater than 1. Each NMOS unit comprises an NMOS tube, and the first PUF array and the second PUF array are respectively decoded by the first decoder, the third decoder, the second decoder and the fourth decoder on excitation signals. A certain NMOS unit in a certain column unit in the first PUF array can be compared with any one NMOS unit in any one column unit in the second PUF array to generate a final output response; the method has the advantages that the PUF entropy source utilization rate is increased by 2p + q times under the condition of keeping less hardware overhead, and the number of CRPs is remarkably increased.

Description

Technical Field

[0001] The present invention relates to a weak PUF circuit, and in particular to a weak PUF circuit based on a rich excitation response of a MOS tube leakage current. Background Art

[0002] With the rapid development of IoT technology, more and more IoT devices are connected to the network to form an IoT system, which brings unlimited possibilities to our production and life. Users can remotely access IoT devices through the Internet, control IoT devices, and realize communication between IoT devices and between users and IoT devices. The communication between IoT devices and between users and IoT devices is carried out on an open channel, which makes the data transmitted in the IoT system easy to be stolen by attackers. The encryption algorithm implemented by key generation technology is used as the cornerstone to ensure information security. The data transmitted in the IoT system is encrypted by the generated key to prevent data leakage or access by unauthorized users. However, traditional encryption methods need to store critical keys in non-volatile memories (NVM), which is unacceptable for IoT devices with limited costs and resources. In addition, the keys stored in NVM are also at risk of being physically attacked.

[0003] In order to deal with the above shortcomings, Physically Unclonable Function (PUF) technology came into being. PUF can generate feature information with randomness, uniqueness and anti-tampering characteristics by extracting random process deviations that are inevitably introduced during chip manufacturing, thereby achieving lightweight deployment of key generation. Researchers divide PUF into strong PUF circuits and weak PUF circuits based on whether there is PUF unit reuse in the process of generating challenge response pairs (CRP) by PUF. Since there is no reuse relationship between PUF units in weak PUF circuits, they cannot be modeled and attacked by machine learning algorithms, and weak PUF circuits become the first choice for generating high-security keys. However, traditional weak PUF circuits will cause the output response bits to flip under the influence of changes in the external working environment and internal thermal noise. At the same time, due to the low utilization rate of the entropy source of weak PUF circuits and the surge in the area of ​​weak PUF circuits caused by screening strategies, it is seriously difficult to deploy them in resource-constrained IoT devices.

[0004] Zhao et al. proposed a dual-entropy source weak PUF consisting of a two-transistor bias voltage generation circuit and a four-stage diode clamping circuit in the document "X. Zhao, C. Xie, Q. Zhao, and X. Pan, "ADual-Entropy-Superposed PUF With In-Cell Entropy Sign-Based Stabilization." IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(1), pp: 284-296.", which can only increase the number of CRPs by 2 times and increase the hardware overhead. Lu et al. proposed a 2D sequence-dependent PUF based on SRAM in the paper "L. Lu, and T. T. Kim," A Sequence-Dependent Configurable PUF Based on 6T SRAM for Enhanced Challenge Response Space." IEEE International Symposium on Circuits and Systems (ISCAS), 2019." by splitting the traditional SRAM structure. The PUF configures the order of SRAM cell selection (i.e., PUF cell). Each SRAM cell has a vertical bit line and a horizontal word line. Four SRAM cells are connected simultaneously using orthogonal word lines to generate one bit of data, thereby increasing the number of CRPs. However, the hardware overhead is large and the implementation is more complicated. Jeloka et al. proposed an SRAM PUF consisting of 6 transistors in the document "S.Jeloka, K.Supreet, M.Kaiyuan Yang, et al." ASequence Dependent Challenge-Response PUF using 28nm SRAM 6T BitCell." Symposium on VLSI Circuits, 2017, pp: C270-C271.". By selecting any two columns from the PUF array for comparison, the number of stimulus-response pairs can be expanded by an order of magnitude, but with a large hardware overhead. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a MOS tube leakage current-based rich stimulus response to weak PUF circuit with low hardware overhead while significantly increasing the number of CRPs.

[0006] The technical solution adopted by the present invention to solve the above technical problems is: a MOS tube leakage current based rich stimulus response to weak PUF circuit, including a first decoder, a second decoder, a third decoder, a fourth decoder, two PUF arrays, two transmission gate arrays and a shared head, each PUF array includes 2 q column units, q is an integer greater than 1, and each column unit includes 2 p NMOS units, p is an integer greater than 1, each NMOS unit includes an NMOS tube, the two PUF arrays are respectively referred to as the first PUF array and the second PUF array, and the two transmission gate arrays are respectively referred to as the first transmission gate array and the second transmission gate array; the first decoder is used to access the first group of p-bit excitation signals and decode them into 2 p bit row selection signal, output to the first PUF array, the first PUF array in the 2 p Under the control of the bit row selection signal, one NMOS unit in each column unit is selected to conduct and work in the subthreshold region to generate a 1-bit response output to the first transmission gate array, that is, the first PUF array generates a 2 q The second decoder is used to access the second group of p-bit excitation signals and decode them into 2 p The bit row selection signal is output to the second PUF array. The second PUF array is in the 2 p Under the control of the bit row selection signal, one NMOS unit in each column unit is selected and turned on to generate a 1-bit response output to the second transmission gate array, that is, the second PUF array generates 2 q The bit response is output to the second transmission gate array, and the third decoder is used to access the first group of q-bit excitation signals and decode them into 2 q The bit selection signal is output to the first transmission gate array, and the fourth decoder is used to access the second group of q-bit excitation signals and decode them into 2 q The bit selection signal is output to the second transmission gate array, and the first transmission gate array is used to output the bit selection signal to the second transmission gate array. q Under the control of the bit selection signal, the first PUF array is selected to output to the 2 q The 1-bit response in the bit response is output to the shared header, and the second transmission gate array is used to output the 2-bit response to the fourth decoder. q Under the control of the bit selection signal, the second PUF array is selected to output to the 2 qA 1-bit response in the PUF response is output to the shared header, and the shared header is used to compare the 1-bit response output by the first transmission gate array and the 1-bit response output by the second transmission gate array, and generate a final PUF response output according to the comparison result.

[0007] Compared with the prior art, the invention has the advantage that a weak PUF circuit is constructed by a first decoder, a second decoder, a third decoder, a fourth decoder, two PUF arrays (a first PUF array and a second PUF array), two transmission gate arrays and a shared header, each PUF array includes two q column units, q is an integer greater than 1, and each column unit includes 2 p NMOS units (i.e., PUF units), p is an integer greater than 1, each NMOS unit includes an NMOS tube, and by making the first group of p-bit excitation signals and the second group of p-bit excitation signals the same or different, the first group of q-bit excitation signals and the second group of q-bit excitation signals the same or different, under the decoding action of the first decoder and the third decoder on the excitation signals connected thereto, and under the decoding action of the second decoder and the fourth decoder on the excitation signals connected thereto, a certain NMOS unit in a certain column unit in the first PUF array can be compared with any NMOS unit in any column unit in the second PUF array, so as to output a final response, that is, a comparison is made between the first PUF array and the second PUF array having 2 q There are 2 columns in each column unit. p When there are NMOS units, the weak PUF circuit of the present invention uses the NMOS tube working in the subthreshold region as the entropy source to amplify the process deviation in the manufacturing process, improve the stability of the PUF, and use the one-to-many configuration of the entropy source to increase the number of stimulus response pairs from 2 to p+q Increase to (2 p+q ) 2 , achieving a PUF entropy source utilization rate increase of 2 p+q times, thus the weak PUF circuit of the present invention can significantly increase the number of CRPs while maintaining less hardware overhead.

[0008] Further, p=6, q=3, the first decoder and the second decoder each have 6 input terminals and 64 output terminals, the third decoder and the fourth decoder each have 3 input terminals and 8 output terminals, each of the transmission gate arrays has 8 input terminals, 8 selection terminals and 1 output terminal, each of the PUF arrays has 64 input terminals, 1 bias terminal and 8 output terminals, and the shared head has 1 enable terminal, 1 precharge terminal, two input terminals and one output terminal; the 64 output terminals of the first decoder and the first PUF array The 64 input terminals of the first PUF array are connected one by one, the 64 output terminals of the second decoder are connected one by one with the 64 input terminals of the second PUF array, the bias terminal of the first PUF array is connected with the bias terminal of the second PUF array, and the connection terminal is the bias terminal of the weak PUF circuit based on the rich excitation response of the MOS tube leakage current, which is used to access the bias signal VBB, and the bias signal VBB is used to make the NMOS tubes in the first PUF array and the second PUF array work in the subthreshold region, and the 8 output terminals of the third decoder are connected with the The eight selection ends of the first transmission gate array are connected one-to-one, the eight output ends of the first PUF array are connected one-to-one with the eight input ends of the first transmission gate array, the eight output ends of the fourth decoder are connected one-to-one with the eight selection ends of the second transmission gate array, the eight output ends of the second PUF array are connected one-to-one with the eight input ends of the second transmission gate array, the output ends of the first transmission gate array and the output ends of the second transmission gate array are connected one-to-one with the two input ends of the shared header; the six The input end, the three input ends of the third decoder, the six input ends of the second decoder and the three input ends of the fourth decoder constitute the 18-bit excitation end of the rich excitation response to the weak PUF circuit based on MOS tube leakage current, which is used to access the 18-bit excitation signal, the enable end of the shared head is the enable end of the rich excitation response to the weak PUF circuit based on MOS tube leakage current, which is used to access the enable signal, and the pre-charging end of the shared head is the pre-charging end of the rich excitation response to the weak PUF circuit based on MOS tube leakage current, which is used to access the pre-charging signal.

[0009] Further, in each PUF array, each column unit has 64 input terminals, bias terminals and output terminals, and in each column unit, each NMOS unit has an input terminal, a bias terminal and an output terminal. The NMOS tube of each NMOS unit is called a first NMOS tube, the gate of the first NMOS is the input terminal of the NMOS unit, the drain of the first NMOS is the bias terminal of the NMOS unit, the source of the first NMOS is the output terminal of the NMOS unit, and the input terminal of the jth NMOS unit is the The j-th input end of the column unit, j=1,2,…,64, the bias ends of 64 NMOS units are connected, and their connection ends are the bias ends of the column unit, and the output ends of 64 NMOS units are connected, and their connection ends are the output ends of the column unit; the i-th input ends of 8 column units are connected, and their connection ends are the i-th input end of the PUF array, i=1,2,…,64, the bias ends of 8 column units are connected, and their connection ends are the bias ends of the PUF array, and the output ends of 8 column units serve as 8 output ends of the PUF array.

[0010] Further, each transmission gate array includes 8 transmission gates, each transmission gate has a control end, an input end and an output end, the control ends of the 8 transmission gates serve as 8 selection ends of the transmission gate array, and the input ends of the 8 transmission gates serve as 8 input ends of the transmission gate array, wherein the control end of the kth transmission gate is the kth selection end of the transmission gate array, k=1,2,…,8, the input end of the kth transmission gate is the kth input end of the transmission gate array, and the output ends of the 8 transmission gates are connected, and their connection ends are the output ends of the transmission gate array.

[0011] Furthermore, each transmission gate includes a first inverter, a second NMOS tube and a first PMOS tube, the gate of the second NMOS tube is connected to the input end of the first inverter, and its connection end is the control end of the transmission gate, the gate of the first PMOS tube is connected to the output end of the first inverter, the source of the second NMOS tube is connected to the drain of the first PMOS tube, and its connection end is the output end of the transmission gate, and the drain of the second NMOS tube is connected to the source of the first PMOS tube, and its connection end is the input end of the transmission gate.

[0012] Further, the shared head includes a cross-coupling structure, a sensitive amplifier and an arbitrator, the cross-coupling structure has three input terminals, and the three input terminals are respectively referred to as the first input terminal, the second input terminal and the third input terminal, the sensitive amplifier has two input terminals, one enable terminal and two output terminals, the two input terminals are respectively referred to as the first input terminal and the second input terminal, the two output terminals are respectively referred to as the first output terminal and the second output terminal, the arbitrator has two input terminals and one output terminal, the two input terminals are respectively referred to as the first input terminal and the second input terminal, the first input terminal of the cross-coupling structure is connected to the first input terminal of the sensitive amplifier, and the connection terminal is the first input terminal of the shared head, the cross-coupling structure The third input end of the sense amplifier is connected to the second input end of the sense amplifier, and the connection end thereof is the second input end of the shared head, the second input end of the cross-coupling structure is the pre-charging end of the shared head, and the pre-charging signal connected to the pre-charging end of the shared head is used to control the cross-coupling structure to put it into a working state, the first output end of the sense amplifier is connected to the first input end of the arbitrator, the second output end of the sense amplifier is connected to the second input end of the arbitrator, the enable end of the sense amplifier is the enable end of the shared head, and the enable signal connected to the enable end of the shared head is used to control the sense amplifier to put it into a working state, and the output end of the arbitrator is the output end of the shared head.

[0013] Furthermore, the cross-coupling structure includes a second PMOS tube, a third PMOS tube, a fourth PMOS tube and a fifth PMOS tube, the gate of the second PMOS tube is connected to the gate of the fifth PMOS tube, and the connection end thereof is the second input end of the cross-coupling structure, the source of the second PMOS tube, the source of the third PMOS tube, the source of the fourth PMOS tube and the source of the fifth PMOS tube are all connected to the power supply voltage VDD, the drain of the second PMOS tube, the drain of the third PMOS tube and the gate of the fourth PMOS tube are connected, and the connection end thereof is the first input end of the cross-coupling structure, and the drain of the fourth PMOS tube, the drain of the fifth PMOS tube and the gate of the third PMOS tube are connected, and the connection end thereof is the third input end of the cross-coupling structure.

[0014] Further, the sensitive amplifier structure includes a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube and a seventh NMOS tube, the source of the sixth PMOS tube, the source of the seventh PMOS tube, the source of the eighth PMOS tube, the source of the ninth PMOS tube, the source of the tenth PMOS tube and the source of the eleventh PMOS tube are all connected to the power supply voltage VDD, the gate of the sixth PMOS tube, the gate of the tenth PMOS tube, the gate of the seventh NMOS, the gate of the ninth PMOS tube and the gate of the eleventh PMOS tube are connected, and the connection end is the enable end of the sensitive amplifier, the gate of the fifth NMOS tube is the first input end of the sensitive amplifier, and the gate of the sixth NMOS tube is the first input end of the sensitive amplifier. The second input end of the sense amplifier, the drain of the sixth PMOS tube, the drain of the seventh PMOS tube, the gate of the eighth PMOS tube, the drain of the third NMOS tube and the gate of the fourth NMOS tube are connected, and the connection end thereof is the first output end of the sense amplifier, the drain of the eighth PMOS tube, the drain of the ninth PMOS tube, the gate of the seventh PMOS tube, the drain of the fourth NMOS tube and the gate of the third NMOS tube are connected, and the connection end thereof is the second output end of the sense amplifier, the drain of the tenth PMOS tube, the source of the third NMOS tube and the drain of the fifth NMOS tube are connected, the drain of the eleventh PMOS tube, the source of the fourth NMOS tube and the drain of the sixth NMOS tube are connected, the source of the fifth NMOS tube, the source of the sixth NMOS tube and the drain of the seventh NMOS tube are connected, and the source of the seventh NMOS tube is grounded.

[0015] Furthermore, the arbitrator includes two two-input NAND gates, each of which has a first input terminal, a second input terminal and an output terminal. The two two-input NAND gates are respectively referred to as a first two-input NAND gate and a second two-input NAND gate. The first input terminal of the first two-input NAND gate is the first input terminal of the arbitrator unit, the second input terminal of the second two-input NAND gate is the second input terminal of the arbitrator unit, the second input terminal of the first two-input NAND gate is connected to the output terminal of the second two-input NAND gate, the output terminal of the first two-input NAND gate is connected to the first input terminal of the second two-input NAND gate, and the connection terminal thereof is the output terminal of the arbitrator unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A structural diagram of a weak PUF circuit based on a rich excitation response to MOS tube leakage current according to the present invention;

[0017] Figure 2 A structural diagram of a PUF array of a weak PUF circuit based on a rich excitation response of a MOS tube leakage current according to the present invention;

[0018] Figure 3 A structural diagram of a column unit of a weak PUF circuit based on a rich excitation response of a MOS tube leakage current according to the present invention;

[0019] Figure 4 A circuit diagram of an NMOS unit of a weak PUF circuit based on a rich excitation response of a MOS tube leakage current according to the present invention;

[0020] Figure 5 A structural diagram of a transmission gate array of a weak PUF circuit based on a rich excitation response of a MOS tube leakage current according to the present invention;

[0021] Figure 6 A circuit diagram of a transmission gate of a weak PUF circuit based on a rich excitation response of a MOS tube leakage current according to the present invention;

[0022] Figure 7 A structural diagram of a shared head of a weak PUF circuit based on a rich stimulus response of a MOS tube leakage current according to the present invention;

[0023] Figure 8 A circuit diagram of a cross-coupling structure of a weak PUF circuit based on a rich excitation response of a MOS tube leakage current according to the present invention;

[0024] Fig. 9 A structure diagram of a sensitive amplifier for a weak PUF circuit based on a rich excitation response of a MOS tube leakage current according to the present invention;

[0025] Fig.10 A circuit diagram of an arbiter for a weak PUF circuit based on a rich stimulus response of a MOS tube leakage current according to the present invention;

[0026] Fig.11 A layout of a weak PUF circuit based on a rich stimulus response to MOS tube leakage current of the present invention;

[0027] Fig.12 This is a diagram showing the influence of different VBBs on PUF stability and randomness based on MOS tube leakage current of the present invention;

[0028] Fig.13 A grayscale statistical diagram of the output response of a weak PUF circuit to a rich excitation response based on MOS tube leakage current according to the present invention;

[0029] Fig.14 It is an average grayscale statistical diagram of the output response of a weak PUF circuit to a rich excitation response based on MOS tube leakage current of the present invention;

[0030] Fig.15 The present invention provides a test diagram of the intra-chip Hamming distance and inter-chip Hamming distance of a weak PUF circuit based on a rich stimulus response of a MOS tube leakage current. DETAILED DESCRIPTION

[0031] The present invention is further described in detail below with reference to the accompanying drawings.

[0032] Embodiment 1: Figure 1 As shown, a MOS tube leakage current-based rich stimulus response to weak PUF circuit includes a first decoder, a second decoder, a third decoder, a fourth decoder, two PUF arrays, two transmission gate arrays and a shared header, each PUF array includes 2 q column units, q is an integer greater than 1, and each column unit includes 2 p NMOS units, p is an integer greater than 1, each NMOS unit includes an NMOS tube, the two PUF arrays are respectively referred to as the first PUF array and the second PUF array, and the two transmission gate arrays are respectively referred to as the first transmission gate array and the second transmission gate array; the first decoder is used to access the first group of p-bit excitation signals and decode them into 2 p bit row selection signal, output to the first PUF array, the first PUF array in the 2 p Under the control of the bit row selection signal, one NMOS unit in each column unit is selected to conduct and work in the subthreshold region to generate a 1-bit response output to the first transmission gate array, that is, the first PUF array generates a 2 q The second decoder is used to access the second group of p-bit excitation signals and decode them into 2 p The bit row selection signal is output to the second PUF array. The second PUF array is in the 2 p Under the control of the bit row selection signal, one NMOS unit in each column unit is selected and turned on to generate a 1-bit response output to the second transmission gate array, that is, the second PUF array generates 2 q The bit response is output to the second transmission gate array, and the third decoder is used to access the first group of q-bit excitation signals and decode them into 2 q The bit selection signal is output to the first transmission gate array, and the fourth decoder is used to access the second group of q-bit excitation signals and decode them into 2 q The bit selection signal is output to the second transmission gate array, and the first transmission gate array is used to output the second bit selection signal to the second transmission gate array. q Under the control of the bit selection signal, the first PUF array is selected to output to the 2 qThe 1-bit response in the bit response is output to the shared header, and the second transmission gate array is used to output the 2-bit response to the fourth decoder. q Under the control of the bit selection signal, the second PUF array is selected to output to the 2 q A 1-bit response in the bit response is output to the shared header, which is used to compare the 1-bit response QL output by the first transmission gate array and the 1-bit response QR output by the second transmission gate array, and generate a final PUF response R output according to the comparison result.

[0033] In this embodiment, p=6, q=3, the first decoder and the second decoder each have 6 input terminals and 64 output terminals, the third decoder and the fourth decoder each have 3 input terminals and 8 output terminals, each transmission gate array has 8 input terminals, 8 selection terminals and 1 output terminal, each PUF array has 64 input terminals, 1 bias terminal and 8 output terminals, and the shared header has 1 enable terminal, 1 precharge terminal, two input terminals and one output terminal; the 64 output terminals of the first decoder and the first PUF array are connected to each other. The 64 input terminals are connected one by one, the 64 output terminals of the second decoder are connected one by one with the 64 input terminals of the second PUF array, the bias terminal of the first PUF array is connected with the bias terminal of the second PUF array, and the connection terminal is a bias terminal of the weak PUF circuit based on the rich excitation response of the MOS tube leakage current, which is used to access the bias signal VBB, and the bias signal VBB is used to make the NMOS tubes in the first PUF array and the second PUF array work in the subthreshold region, and the 8 output terminals of the third decoder are connected with the first transmission The eight selection ends of the gate array are connected one-to-one, the eight output ends of the first PUF array are connected one-to-one with the eight input ends of the first transmission gate array, the eight output ends of the fourth decoder are connected one-to-one with the eight selection ends of the second transmission gate array, the eight output ends of the second PUF array are connected one-to-one with the eight input ends of the second transmission gate array, and the output ends of the first transmission gate array and the output ends of the second transmission gate array are connected one-to-one with the two input ends of the shared head; the six input ends of the first decoder, the three input ends of the third decoder, the six input ends of the second decoder and the three input ends of the fourth decoder constitute an 18-bit excitation end of the weak PUF circuit based on the rich excitation response of the MOS tube leakage current, which is used to access the 18-bit excitation signals C1 to C18, the enable end of the shared head is the enable end of the weak PUF circuit based on the rich excitation response of the MOS tube leakage current, which is used to access the enable signal EN, and the pre-charge end of the shared head is the pre-charge end of the weak PUF circuit based on the rich excitation response of the MOS tube leakage current, which is used to access the pre-charge signal PRE.

[0034] In this embodiment, by making the first group of p-bit excitation signals and the second group of p-bit excitation signals the same or different, and the first group of q-bit excitation signals and the second group of q-bit excitation signals the same or different, under the decoding action of the first decoder and the third decoder on the excitation signals connected thereto, and under the decoding action of the second decoder and the fourth decoder on the excitation signals connected thereto, a certain NMOS unit in a certain column unit in the first PUF array can be compared with any NMOS unit in any column unit in the second PUF array, thereby outputting a final response, that is, a certain NMOS unit in a certain column unit in the first PUF array and a certain NMOS unit in a certain column unit in the second PUF array. q There are 2 columns in each column unit. p When there are NMOS units, the number of excitation response pairs generated by the rich excitation response based on the leakage current of the MOS tube to the weak PUF circuit is (2 p+q ) 2 The traditional weak PUF circuit can only compare the NMOS units at the same position in the column units at the same position in the first PUF array and the second PUF array to output a response, that is, the traditional weak PUF circuit has 2 in its first PUF array and the second PUF array. q There are 2 columns in each column unit. p When there are two NMOS units, 2 p+q Thus, when the conventional weak PUF circuit also has two PUF arrays, and the two PUF arrays are exactly the same as the two PUF arrays in the weak PUF circuit with rich stimulus response pairs based on MOS tube leakage current of the present invention, the number of stimulus response pairs in the weak PUF circuit with rich stimulus response pairs based on MOS tube leakage current of the present invention is increased from 2 to 1. p+q Increase to (2 p+q ) 2 , achieving a PUF entropy source utilization rate increase of 2 p+q Therefore, the rich excitation response based on MOS tube leakage current of the present invention can significantly increase the number of CRPs for the weak PUF circuit while maintaining less hardware overhead.

[0035] Embodiment 2: This embodiment is basically the same as Embodiment 1, except that: in this embodiment, Figures 2 to 4As shown, in each PUF array, each column unit has 64 input terminals, bias terminals and output terminals. In each column unit, each NMOS unit has an input terminal, a bias terminal and an output terminal. The NMOS tube of each NMOS unit is called the first NMOS tube N1. The gate of the first NMOS is the input terminal of the NMOS unit, the drain of the first NMOS is the bias terminal of the NMOS unit, the source of the first NMOS is the output terminal of the NMOS unit, and the input terminal of the jth NMOS unit is the column unit. The j-th input terminal, j=1,2,…,64, the bias terminals of 64 NMOS units are connected, and their connection terminals are the bias terminals of the column units, and the output terminals of 64 NMOS units are connected, and their connection terminals are the output terminals of the column units; the i-th input terminals of 8 column units are connected, and their connection terminals are the i-th input terminals of the PUF array, i=1,2,…,64, the bias terminals of 8 column units are connected, and their connection terminals are the bias terminals of the PUF array, and the output terminals of 8 column units serve as 8 output terminals of the PUF array.

[0036] In this embodiment, in each PUF array, when the input terminal of a certain NMOS unit in a certain column unit is connected to a high level, in the NMOS unit, the first NMOS tube N1 operates in the subthreshold region under the action of the bias voltage VBB connected to its drain, and the first NMOS tube N1 generates a corresponding voltage signal and outputs it at its source, and the voltage signal is the extracted process deviation between transistors; in the first PUF array, a 64-bit row selection signal decoded by the first decoder is used to select an NMOS unit in the first PUF array to be turned on. Since the bias terminals of all NMOS units in the first PUF array are connected The bias ends of all NMOS units in the second PUF array are connected together, so that all NMOS tubes therein can be guaranteed to work in the subthreshold region, and the process deviation in the manufacturing process of the NMOS tube can be amplified. At the same time, in the second PUF array, a 64-bit row selection signal decoded by the second decoder is used to select an NMOS unit in the second PUF array to be turned on. Since the bias ends of all NMOS units in the second PUF array are connected together, it can be guaranteed that all NMOS tubes therein work in the subthreshold region, and the process deviation in the manufacturing process of the NMOS tube can be amplified. Therefore, the stability of the rich excitation response based on the leakage current of the MOS tube of the present invention to the weak PUF circuit can be improved.

[0037] Embodiment 3: This embodiment is basically the same as Embodiment 2, except that: in this embodiment, Figure 5As shown, each transmission gate array includes 8 transmission gates, each transmission gate has a control end, an input end and an output end, the control ends of the 8 transmission gates serve as 8 selection ends of the transmission gate array, and the input ends of the 8 transmission gates serve as 8 input ends of the transmission gate array, wherein the control end of the kth transmission gate is the kth selection end of the transmission gate array, k=1,2,…,8, the input end of the kth transmission gate is the kth input end of the transmission gate array, and the output ends of the 8 transmission gates are connected, and their connection ends are the output ends of the transmission gate array.

[0038] In this embodiment, Figure 6 As shown, each transmission gate includes a first inverter INV1, a second NMOS tube N2 and a first PMOS tube P1, the gate of the second NMOS tube N2 is connected to the input end of the first inverter INV1, and its connection end is the control end of the transmission gate, the gate of the first PMOS tube P1 is connected to the output end of the first inverter INV1, the source of the second NMOS tube N2 is connected to the drain of the first PMOS tube P1, and its connection end is the output end of the transmission gate, and the drain of the second NMOS tube N2 is connected to the source of the first PMOS tube P1, and its connection end is the input end of the transmission gate.

[0039] In this embodiment, when the control end of the transmission gate is connected to a high level 1, the second NMOS tube N2 and the first PMOS tube P1 are both turned on. At this time, the transmission gate is in a conducting state, and the signal connected to the input end of the transmission gate is transmitted to its output end through the second NMOS tube N2 and the first PMOS tube P1. When the control end of the transmission gate is connected to a low level 0, the second NMOS tube N2 and the first PMOS tube P1 are both turned off. At this time, the transmission gate is in a turned-off state and cannot transmit the signal connected to its input end to its output end.

[0040] Embodiment 4: This embodiment is basically the same as Embodiment 3, except that: in this embodiment, Figure 7As shown, the shared head includes a cross-coupling structure, a sensitive amplifier and an arbitrator. The cross-coupling structure has three input terminals, and the three input terminals are respectively referred to as the first input terminal, the second input terminal and the third input terminal. The sensitive amplifier has two input terminals, one enable terminal and two output terminals, and the two input terminals are respectively referred to as the first input terminal and the second input terminal. The two output terminals are respectively referred to as the first output terminal and the second output terminal. The arbitrator has two input terminals and one output terminal, and the two input terminals are respectively referred to as the first input terminal and the second input terminal. The first input terminal of the cross-coupling structure is connected to the first input terminal of the sensitive amplifier, and the connection terminal is the first input terminal of the shared head. The first input terminal of the cross-coupling structure is connected to the first input terminal of the arbitrator, the second output terminal of the cross-coupling structure is connected to the first input terminal of the arbitrator, the second output terminal of the cross-coupling structure is connected to the second input terminal of the arbitrator, and the enable terminal of the cross-coupling structure is connected to the enable terminal of the shared head. The enable signal PRE connected to the enable terminal of the shared head is used to control the cross-coupling structure to put it into a working state. The first output terminal of the cross-coupling structure is connected to the first input terminal of the arbitrator, the second output terminal of the cross-coupling structure is connected to the second input terminal of the arbitrator, the enable terminal of the cross-coupling structure is the enable terminal of the shared head, and the enable signal connected to the enable terminal of the shared head is used to control the cross-coupling structure to put it into a working state. The output terminal of the arbitrator is the output terminal of the shared head.

[0041] In this embodiment, Figure 8 As shown, the cross-coupling structure includes a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4 and a fifth PMOS tube P5, the gate of the second PMOS tube P2 is connected to the gate of the fifth PMOS tube P5, and the connection end thereof is the second input end of the cross-coupling structure, the source of the second PMOS tube P2, the source of the third PMOS tube P3, the source of the fourth PMOS tube P4 and the source of the fifth PMOS tube P5 are all connected to the power supply voltage VDD, the drain of the second PMOS tube P2, the drain of the third PMOS tube P3 and the gate of the fourth PMOS tube P4 are connected, and the connection end thereof is the first input end of the cross-coupling structure, the drain of the fourth PMOS tube P4, the drain of the fifth PMOS tube P5 and the gate of the third PMOS tube P3 are connected, and the connection end thereof is the third input end of the cross-coupling structure.

[0042] In the cross-coupling structure, when the pre-charge signal PRE connected to the second input terminal is at a low level of 0, the second PMOS tube P2 and the fifth PMOS tube P5 are both turned on. At this time, the signals connected to the first input terminal and the second input terminal are pulled to be equal to the power supply voltage VDD, and the third PMOS tube P3 and the fourth PMOS tube P4 are both turned off; when the pre-charge signal PRE connected to the second input terminal is at a high level of 1, the second PMOS tube P2 and the fifth PMOS tube P5 are both turned off. At this time, the leakage current connected to the first input terminal and the third input terminal is judged. If If the leakage current connected to the first input terminal is greater than the leakage current connected to the third input terminal, the fourth PMOS tube P4 is turned on, the signal connected to the first input terminal will be pulled to the power supply voltage VDD, and the third PMOS tube P3 will pull the signal connected to the third input terminal to be equal to the bias voltage VBB. If the leakage current connected to the first input terminal is less than the leakage current connected to the third input terminal, the third PMOS tube P3 is turned on, the signal connected to the third input terminal will be pulled to the power supply voltage VDD, and the fourth PMOS tube P4 will pull the signal connected to the third input terminal to be equal to the bias voltage VBB. Since each PMOS tube has a process deviation during manufacturing, the leakage currents of the first input terminal and the third input terminal of the cross-coupling structure will not be equal.

[0043] In this embodiment, Fig. 9As shown, the structure of the sensitive amplifier includes a sixth PMOS tube P6, a seventh PMOS tube P7, an eighth PMOS tube P8, a ninth PMOS tube P9, a tenth PMOS tube P10, an eleventh PMOS tube P11, a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5, a sixth NMOS tube N6 and a seventh NMOS tube N7. The source of the sixth PMOS tube P6, the source of the seventh PMOS tube P7, the source of the eighth PMOS tube P8, the source of the ninth PMOS tube P9, the source of the tenth PMOS tube P10 and the source of the eleventh PMOS tube P11 are all connected to the power supply voltage VDD. The gate of the sixth PMOS tube P6, the gate of the tenth PMOS tube P10, the gate of the seventh NMOS, the gate of the ninth PMOS tube P9 and the gate of the eleventh PMOS tube P11 are connected, and the connection end is the enable end of the sensitive amplifier. The gate of the fifth NMOS tube N5 is the first input end of the sensitive amplifier. The gate of the transistor N6 is the second input terminal of the sense amplifier, the drain of the sixth PMOS transistor P6, the drain of the seventh PMOS transistor P7, the gate of the eighth PMOS transistor P8, the drain of the third NMOS transistor N3 and the gate of the fourth NMOS transistor N4 are connected, and the connection end thereof is the first output terminal of the sense amplifier, the drain of the eighth PMOS transistor P8, the drain of the ninth PMOS transistor P9, the gate of the seventh PMOS transistor P7, the drain of the fourth NMOS transistor N4 and the gate of the third NMOS transistor N3 are connected, and the connection end thereof is the second output terminal of the sense amplifier, the drain of the tenth PMOS transistor P10, the source of the third NMOS transistor N3 and the drain of the fifth NMOS transistor N5 are connected, the drain of the eleventh PMOS transistor P11, the source of the fourth NMOS transistor N4 and the drain of the sixth NMOS transistor N6 are connected, the source of the fifth NMOS transistor N5, the source of the sixth NMOS transistor N6 and the drain of the seventh NMOS transistor N7 are connected, and the source of the seventh NMOS transistor N7 is grounded.

[0044] In the sense amplifier, when the enable signal connected to the enable terminal of the sense amplifier is at a low level of 0, the sense amplifier is in a pre-charging state, the sixth PMOS tube P6, the tenth PMOS tube P10, the ninth PMOS tube P9 and the eleventh PMOS tube P11 are all turned on, the seventh NMOS tube N7 is turned off, the seventh PMOS tube P7 is turned off, the eighth PMOS is turned off, the third NMOS and the fourth NMOS are both turned off, the fifth NMOS and the sixth NMOS are turned on or off according to the corresponding gate voltages, and since the sixth PMOS tube P6 is turned on, the first output terminal of the sense amplifier is charged to a high level, and since the ninth PMOS tube P9 is turned on, the second output terminal of the sense amplifier is also charged to a high level. When the enable signal connected to the enable end of the sense amplifier is high level 1, the sense amplifier is in an evaluation state, the sixth PMOS tube P6, the tenth PMOS tube P10, the ninth PMOS tube P9 and the eleventh PMOS tube P11 are all turned off, and the seventh NMOS tube N7 is turned on. When the input signal of the first input end of the sense amplifier is VBB and the signal of the second input end is VDD, the turn-on speed of the sixth NMOS tube N6 is faster than the turn-on speed of the fifth NMOS tube N5, and the discharge speed of the second output end of the sense amplifier is faster than the discharge speed of its first output end. Finally, the first output end of the sense amplifier will output a high level, and the second output end will output a low level. When the input signal of the first input end of the sense amplifier is VDD and the signal of the second input end is VBB, the turn-on speed of the fifth NMOS tube N5 is faster than the turn-on speed of the sixth NMOS tube N6, and the discharge speed of the first output end of the sense amplifier is faster than the discharge speed of its second output end. Finally, the second output end of the sense amplifier will output a high level, and the first output end will output a low level.

[0045] In this embodiment, Fig.10 As shown, the arbitrator includes two two-input NAND gates, each of which has a first input terminal, a second input terminal and an output terminal. The two two-input NAND gates are respectively referred to as a first two-input NAND gate U1 and a second two-input NAND gate U2. The first input terminal of the first two-input NAND gate U1 is the first input terminal of the arbitrator unit, the second input terminal of the second two-input NAND gate U2 is the second input terminal of the arbitrator unit, the second input terminal of the first two-input NAND gate U1 is connected to the output terminal of the second two-input NAND gate U2, the output terminal of the first two-input NAND gate U1 is connected to the first input terminal of the second two-input NAND gate U2, and the connection terminal thereof is the output terminal of the arbitrator unit.

[0046] In the arbiter, when the signal connected to the first input end of the first two-input NAND gate U1 is at a low level and the signal connected to the second input end of the second two-input NAND gate U2 is at a low level, no matter whether the signal connected to the second input end of the first two-input NAND gate U1 is at a high level or a low level, and no matter whether the signal connected to the first input end of the second two-input NAND gate U2 is at a high level or a low level, the signal outputted by the output end of the arbiter is at a high level; when the signal connected to the first input end of the first two-input NAND gate U1 is at a high level and the signal connected to the second input end of the second two-input NAND gate U2 is at a high level, the signal outputted by the output end of the arbiter remains unchanged in the previous state; when the signal connected to the first input end of the first two-input NAND gate U1 is at a high level and the signal connected to the second input end of the second two-input NAND gate U2 is at a high level, the signal outputted by the output end of the arbiter remains unchanged in the previous state; When it is low level, no matter whether the signal connected to the first input terminal of the second two-input NAND gate U2 is high level or low level, the signal outputted from the output terminal of the second two-input NAND gate U2 is high level. At this time, the signal connected to the second input terminal of the first two-input NAND gate U1 is also high level, and finally the signal outputted from the output terminal of the arbitrator is low level; when the signal connected to the first input terminal of the first two-input NAND gate U1 is low level and the signal connected to the second input terminal of the second two-input NAND gate U2 is high level, no matter whether the signal connected to the second input terminal of the first two-input NAND gate U1 is high level or low level, the signal outputted from the output terminal of the arbitrator is high level, then the signal connected to the first input terminal of the second two-input NAND gate U2 is also high level, and the signal outputted from the output terminal of the second two-input NAND gate U2 is low level.

[0047] In order to verify the performance of the MOS tube leakage current based rich stimulus response to weak PUF circuit of the present invention, the TSMC 65nm CMOS process is used to implement the MOS tube leakage current based rich stimulus response to weak PUF circuit of the present invention, and its layout is as follows: Fig.11 When p=6 and q=3, the overall layout area of ​​the MOS tube leakage current-based rich stimulus response to the weak PUF circuit of the present invention is 33.63 μm×48.68 μm, and the hardware overhead used is relatively small.

[0048] In order to verify the value of the bias voltage VBB input to the entropy source tube (i.e., the first NMOS tube in the NMOS unit of the column unit) of the PUF array when the rich excitation response based on the leakage current of the MOS tube of the present invention works at the best performance of the weak PUF circuit, the entropy source tube of the PUF array is tested when a 0.6V to 1V level is applied to the source, that is, the bias voltage VBB is tested when it is 0.6V, 0.65V, 0.7V, 0.75V, 0.8V, 0.85V, 0.9V, 0.95V and 1V. The test results are as follows: Fig.12As shown in the figure, when the bias voltage VBB increases from 0.6V to 0.8V, the same group of stimulus response pairs are tested 50 times repeatedly, and the average bit error rate drops from 1.31% to 0.25%, which is a decrease of 5.24 times. When the bias voltage VBB drops from 1V to 0.8V, the same group of stimulus response pairs are tested 50 times repeatedly, and the average bit error rate drops from 1.78% to 0.25%, which is a decrease of 7.12 times, and the randomness at 0.8V is also good. Therefore, the stability and randomness of the PUF circuit based on the MOS tube leakage current of the present invention are good when the bias voltage VBB is 0.8V.

[0049] Randomness indicates whether the PUF output response is randomly distributed, which can be intuitively reflected by a grayscale image. For a real sample of a MOS tube leakage current-based rich stimulus response to weak PUF circuit of the present invention, the bias voltage VBB is 0.8V, and 8192 groups of stimulus response pairs are randomly extracted. The obtained grayscale image is as follows: Fig.13 As shown, analysis Fig.13 It can be seen that the probability of the response being "1" is 50.01%, and the probability of the response being "0" is 49.99%, indicating that the rich excitation response based on MOS tube leakage current of the present invention has good randomness for the weak PUF circuit.

[0050] In addition, 20 samples of the MOS tube leakage current-based rich stimulus response weak PUF circuits of the present invention were repeatedly tested, with the bias voltage VBB set to 0.8V. 8192 groups of stimulus response pairs were randomly extracted from each sample of the MOS tube leakage current-based rich stimulus response weak PUF circuit. The average grayscale image obtained is shown in FIG. Fig.14 As shown, analysis Fig.14 It can be seen that the probability of the response being "1" is 49.86%, and the probability of the response being "0" is 50.14%, indicating that the rich excitation response based on MOS tube leakage current of the present invention has good randomness for the weak PUF circuit.

[0051] Uniqueness indicates the ability to distinguish different PUFs. Under the same stimulus, the output responses of multiple MOS tube leakage current-based rich stimulus responses of the present invention to the actual samples of weak PUF circuits are repeatedly tested. The bias voltage VBB is 0.8V, and the inter-chip Hamming distance is used for measurement. The intra-chip Hamming distance and inter-chip Hamming distance test diagram of the MOS tube leakage current-based rich stimulus response to the actual samples of weak PUF circuits are shown in FIG. Fig.15 As shown, analysis Fig.15 It can be seen that the expected value of the inter-chip Hamming distance is 49.848% and the standard deviation is 1.762%, both of which are close to the expected ideal value of 50% and the ideal value of the standard deviation of 0%. The rich excitation response based on the MOS tube leakage current of the present invention has good uniqueness for the weak PUF circuit.

[0052] In summary, the MOS tube leakage current-based rich stimulus response to weak PUF circuit of the present invention uses NMOS tubes working in the subthreshold region as entropy sources to amplify process deviations in the manufacturing process, improve the stability of PUF, and use a one-to-many configuration of entropy sources to increase the number of stimulus response pairs from 2 to 1. p+q Increase to (2 p+q ) 2 , achieving a PUF entropy source utilization rate increase of 2 p+q times, significantly increasing the number of CRPs while maintaining less hardware overhead, while also having better randomness and uniqueness.

Claims

1. A weak PUF circuit with rich stimulus response based on MOS tube leakage current, characterized in that It includes a first decoder, a second decoder, a third decoder, a fourth decoder, two PUF arrays, two transmission gate arrays and a shared head, each PUF array includes 2 q column units, q is an integer greater than 1, and each column unit includes 2 p NMOS units, p is an integer greater than 1, each NMOS unit includes an NMOS tube, the two PUF arrays are respectively referred to as the first PUF array and the second PUF array, and the two transmission gate arrays are respectively referred to as the first transmission gate array and the second transmission gate array; the first decoder is used to access the first group of p-bit excitation signals and decode them into 2 p bit row selection signal, output to the first PUF array, the first PUF array in the 2 p Under the control of the bit row selection signal, one NMOS unit in each column unit is selected to conduct and work in the subthreshold region to generate a 1-bit response output to the first transmission gate array, that is, the first PUF array generates a 2 q The second decoder is used to access the second group of p-bit excitation signals and decode them into 2 p The bit row selection signal is output to the second PUF array. The second PUF array is in the 2 p Under the control of the bit row selection signal, one NMOS unit in each column unit is selected and turned on to generate a 1-bit response output to the second transmission gate array, that is, the second PUF array generates 2 q The bit response is output to the second transmission gate array, and the third decoder is used to access the first group of q-bit excitation signals and decode them into 2 q The bit selection signal is output to the first transmission gate array, and the fourth decoder is used to access the second group of q-bit excitation signals and decode them into 2 q The bit selection signal is output to the second transmission gate array, and the first transmission gate array is used to output the bit selection signal to the second transmission gate array. q Under the control of the bit selection signal, the first PUF array is selected to output to the 2 q The 1-bit response in the bit response is output to the shared header, and the second transmission gate array is used to output the 2-bit response to the fourth decoder. q Under the control of the bit selection signal, the second PUF array is selected to output to the 2 q A 1-bit response in the PUF response is output to the shared header, and the shared header is used to compare the 1-bit response output by the first transmission gate array and the 1-bit response output by the second transmission gate array, and generate a final PUF response output according to the comparison result.

2. According to claim 1, a MOS tube leakage current based rich stimulus response to weak PUF circuit, characterized in that p=6, q=3, the first decoder and the second decoder each have 6 input terminals and 64 output terminals, the third decoder and the fourth decoder each have 3 input terminals and 8 output terminals, each of the transmission gate arrays has 8 input terminals, 8 selection terminals and 1 output terminal, each of the PUF arrays has 64 input terminals, 1 bias terminal and 8 output terminals, and the shared head has 1 enable terminal, 1 precharge terminal, two input terminals and one output terminal; the 64 output terminals of the first decoder and the 6 output terminals of the first PUF array The four input terminals are connected one-to-one, the 64 output terminals of the second decoder are connected one-to-one with the 64 input terminals of the second PUF array, the bias terminal of the first PUF array is connected with the bias terminal of the second PUF array, and the connection terminal is the bias terminal of the weak PUF circuit based on the rich excitation response of the MOS tube leakage current, which is used to access the bias signal VBB, and the bias signal VBB is used to make the NMOS tubes in the first PUF array and the second PUF array work in the subthreshold region, and the 8 output terminals of the third decoder are connected with the first The eight selection ends of the first transmission gate array are connected in one-to-one correspondence, the eight output ends of the first PUF array are connected in one-to-one correspondence with the eight input ends of the first transmission gate array, the eight output ends of the fourth decoder are connected in one-to-one correspondence with the eight selection ends of the second transmission gate array, the eight output ends of the second PUF array are connected in one-to-one correspondence with the eight input ends of the second transmission gate array, the output ends of the first transmission gate array and the output ends of the second transmission gate array are connected in one-to-one correspondence with the two input ends of the shared header; the six input ends of the first decoder are connected in one-to-one correspondence with the eight selection ends of the second transmission gate array, the eight output ends of the second PUF array are connected in one-to-one correspondence with the eight input ends of the second transmission gate array, and the output ends of the first transmission gate array and the output ends of the second transmission gate array are connected in one-to-one correspondence with the two input ends of the shared header; The input end, the three input ends of the third decoder, the six input ends of the second decoder and the three input ends of the fourth decoder constitute the 18-bit excitation end of the rich excitation response based on MOS tube leakage current for the weak PUF circuit, which is used to access the 18-bit excitation signal, the enable end of the shared head is the enable end of the rich excitation response based on MOS tube leakage current for the weak PUF circuit, which is used to access the enable signal, and the pre-charging end of the shared head is the pre-charging end of the rich excitation response based on MOS tube leakage current for the weak PUF circuit, which is used to access the pre-charging signal.

3. According to claim 2, a MOS tube leakage current based rich stimulus response to weak PUF circuit, characterized in that In each PUF array, each column unit has 64 input terminals, bias terminals and output terminals. In each column unit, each NMOS unit has an input terminal, a bias terminal and an output terminal. The NMOS tube of each NMOS unit is called a first NMOS tube. The gate of the first NMOS is the input terminal of the NMOS unit, the drain of the first NMOS is the bias terminal of the NMOS unit, the source of the first NMOS is the output terminal of the NMOS unit, and the input terminal of the jth NMOS unit is the gate of the column unit. The j-th input terminal of the element, j=1,2,…,64, the bias terminals of 64 NMOS units are connected, and their connection terminals are the bias terminals of the column units, and the output terminals of 64 NMOS units are connected, and their connection terminals are the output terminals of the column units; the i-th input terminals of 8 column units are connected, and their connection terminals are the i-th input terminals of the PUF array, i=1,2,…,64, the bias terminals of 8 column units are connected, and their connection terminals are the bias terminals of the PUF array, and the output terminals of 8 column units serve as 8 output terminals of the PUF array.

4. According to claim 2, a MOS tube leakage current based rich stimulus response to weak PUF circuit, characterized in that Each transmission gate array includes 8 transmission gates, each transmission gate has a control end, an input end and an output end, the control ends of the 8 transmission gates serve as 8 selection ends of the transmission gate array, and the input ends of the 8 transmission gates serve as 8 input ends of the transmission gate array, wherein the control end of the kth transmission gate is the kth selection end of the transmission gate array, k=1,2,…,8, the input end of the kth transmission gate is the kth input end of the transmission gate array, and the output ends of the 8 transmission gates are connected, and their connection ends are the output ends of the transmission gate array.

5. A MOS tube leakage current-based rich stimulus response to weak PUF circuit according to claim 4, characterized in that Each transmission gate includes a first inverter, a second NMOS tube and a first PMOS tube, the gate of the second NMOS tube is connected to the input end of the first inverter, and its connecting end is the control end of the transmission gate, the gate of the first PMOS tube is connected to the output end of the first inverter, the source of the second NMOS tube is connected to the drain of the first PMOS tube, and its connecting end is the output end of the transmission gate, and the drain of the second NMOS tube is connected to the source of the first PMOS tube, and its connecting end is the input end of the transmission gate.

6. A MOS tube leakage current-based rich stimulus response to weak PUF circuit according to claim 2, characterized in that The shared head includes a cross-coupling structure, a sensitive amplifier and an arbitrator. The cross-coupling structure has three input terminals, and the three input terminals are respectively referred to as the first input terminal, the second input terminal and the third input terminal. The sensitive amplifier has two input terminals, one enable terminal and two output terminals, and the two input terminals are respectively referred to as the first input terminal and the second input terminal. The two output terminals are respectively referred to as the first output terminal and the second output terminal. The arbitrator has two input terminals and one output terminal, and the two input terminals are respectively referred to as the first input terminal and the second input terminal. The first input terminal of the cross-coupling structure is connected to the first input terminal of the sensitive amplifier, and the connection terminal is the first input terminal of the shared head. The first input terminal of the cross-coupling structure is connected to the first input terminal of the sensitive amplifier, and the connection terminal is the first input terminal of the shared head. The three input terminals are connected to the second input terminal of the sensitive amplifier, and the connection terminal is the second input terminal of the shared head. The second input terminal of the cross-coupling structure is the pre-charging terminal of the shared head. The pre-charging signal connected to the pre-charging terminal of the shared head is used to control the cross-coupling structure to put it into a working state. The first output terminal of the sensitive amplifier is connected to the first input terminal of the arbitrator. The second output terminal of the sensitive amplifier is connected to the second input terminal of the arbitrator. The enable terminal of the sensitive amplifier is the enable terminal of the shared head. The enable signal connected to the enable terminal of the shared head is used to control the sensitive amplifier to put it into a working state. The output terminal of the arbitrator is the output terminal of the shared head.

7. A MOS tube leakage current-based rich stimulus response to weak PUF circuit according to claim 6, characterized in that The cross-coupling structure includes a second PMOS tube, a third PMOS tube, a fourth PMOS tube and a fifth PMOS tube, the gate of the second PMOS tube is connected to the gate of the fifth PMOS tube, and the connection end thereof is the second input end of the cross-coupling structure, the source of the second PMOS tube, the source of the third PMOS tube, the source of the fourth PMOS tube and the source of the fifth PMOS tube are all connected to the power supply voltage VDD, the drain of the second PMOS tube, the drain of the third PMOS tube and the gate of the fourth PMOS tube are connected, and the connection end thereof is the first input end of the cross-coupling structure, the drain of the fourth PMOS tube, the drain of the fifth PMOS tube and the gate of the third PMOS tube are connected, and the connection end thereof is the third input end of the cross-coupling structure.

8. A MOS tube leakage current-based rich stimulus response to weak PUF circuit according to claim 6, characterized in that The sensitive amplifier structure includes a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube and a seventh NMOS tube. The source of the sixth PMOS tube, the source of the seventh PMOS tube, the source of the eighth PMOS tube, the source of the ninth PMOS tube, the source of the tenth PMOS tube and the source of the eleventh PMOS tube are all connected to a power supply voltage VDD. The gate of the sixth PMOS tube, the gate of the tenth PMOS tube, the gate of the seventh NMOS tube, the gate of the ninth PMOS tube and the gate of the eleventh PMOS tube are connected, and the connection end thereof is the enable end of the sensitive amplifier. The gate of the fifth NMOS tube is the first input end of the sensitive amplifier. The gate of the sixth NMOS tube is the first input end of the sensitive amplifier. The second input terminal, the drain of the sixth PMOS tube, the drain of the seventh PMOS tube, the gate of the eighth PMOS tube, the drain of the third NMOS tube and the gate of the fourth NMOS tube are connected, and the connection end thereof is the first output terminal of the sensitive amplifier, the drain of the eighth PMOS tube, the drain of the ninth PMOS tube, the gate of the seventh PMOS tube, the drain of the fourth NMOS tube and the gate of the third NMOS tube are connected, and the connection end thereof is the second output terminal of the sensitive amplifier, the drain of the tenth PMOS tube, the source of the third NMOS tube and the drain of the fifth NMOS tube are connected, the drain of the eleventh PMOS tube, the source of the fourth NMOS tube and the drain of the sixth NMOS tube are connected, the source of the fifth NMOS tube, the source of the sixth NMOS tube and the drain of the seventh NMOS tube are connected, and the source of the seventh NMOS tube is grounded.

9. A MOS tube leakage current-based rich stimulus response to weak PUF circuit according to claim 6, characterized in that The arbitrator includes two two-input NAND gates, each of which has a first input terminal, a second input terminal and an output terminal. The two two-input NAND gates are respectively referred to as a first two-input NAND gate and a second two-input NAND gate. The first input terminal of the first two-input NAND gate is the first input terminal of the arbitrator unit, the second input terminal of the second two-input NAND gate is the second input terminal of the arbitrator unit, the second input terminal of the first two-input NAND gate is connected to the output terminal of the second two-input NAND gate, the output terminal of the first two-input NAND gate is connected to the first input terminal of the second two-input NAND gate, and the connection terminal thereof is the output terminal of the arbitrator unit.

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