A weak PUF circuit based on rich excitation response of MOS transistor drain current

Abstract

The application discloses a weak PUF circuit with rich excitation response based on MOS tube leakage current, comprising a first decoder, a second decoder, a third decoder, a fourth decoder, a first PUF array, a second PUF array, two transmission gate arrays and one shared header, each PUF array comprises two column units, q is an integer greater than 1, each column unit comprises two NMOS units, p is an integer greater than 1, each NMOS unit comprises an NMOS tube, under the decoding action of the first decoder, the third decoder and the second decoder, the fourth decoder on the excitation signal, a certain NMOS unit in a certain column unit in the first PUF array can be compared with any NMOS unit in any column unit in the second PUF array to generate a final output response, and the advantage is that the PUF entropy source utilization rate is improved by 2 times while the hardware overhead is kept small, and the number of CRPs is significantly improved. q p p+q ​​​

Description

Technical Field

[0001] This invention relates to weak PUF circuits, and more particularly to a weak PUF circuit with a rich excitation response based on MOS transistor leakage current. Background Technology

[0002] With the rapid development of IoT technology, more and more IoT devices are connecting to the network, forming IoT systems and bringing unlimited possibilities to our production and lives. Users can remotely access and control IoT devices via the Internet, enabling communication between IoT devices and between users and IoT devices. However, communication between IoT devices and between users and IoT devices occurs over open channels, making the data transmitted in the IoT system vulnerable to interception by attackers. Encryption algorithms implemented using key generation technology serve as the cornerstone of information security, encrypting the data transmitted in the IoT system with the generated key to prevent data leakage or unauthorized access. However, traditional encryption methods require storing critical keys in non-volatile memory (NVM), which is unacceptable for cost- and resource-constrained IoT devices. Furthermore, keys stored in NVM are also susceptible to physical attacks.

[0003] To address these shortcomings, Physically Unclonable Function (PUF) technology has emerged. PUFs extract random process variations unavoidable during chip manufacturing to generate characteristic information with randomness, uniqueness, and tamper-proof properties, enabling lightweight deployment of key generation. Researchers categorize PUFs into strong and weak PUF circuits based on whether PUF unit reuse exists during the generation of Challenge Response Pairs (CRPs). Since there is no reuse relationship between PUF units in weak PUF circuits, they cannot be modeled and attacked by machine learning algorithms, making them the preferred choice for generating highly secure keys. However, traditional weak PUF circuits are susceptible to output response bit flipping due to changes in the external operating environment and internal thermal noise. Furthermore, the low entropy source utilization of weak PUF circuits and the significant increase in circuit area caused by selection strategies severely increase the difficulty of deploying them in resource-constrained IoT devices.

[0004] In the paper “X. Zhao, C. Xie, Q. Zhao, and X. Pan, “ADual-Entropy-Superposed PUF With In-Cell Entropy Sign-Based Stabilization.” IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(1), pp: 284-296.”, Zhao et al. proposed a dual-entropy source weak PUF consisting of a two-transistor bias voltage generation circuit and a four-stage diode clamping circuit. This method can only increase the number of CRPs by a factor of 2 and increases the hardware overhead significantly. In the paper "L. Lu, and T. THKim, 'ASequence-Dependent Configurable PUF Based on 6T SRAM for Enhanced Challenge Response Space.' IEEE International Symposium on Circuits and Systems (ISCAS), 2019," Lu et al. proposed a 2D sequence-dependent PUF based on SRAM by decomposing the traditional SRAM structure. This PUF configures the order in which SRAM cells (i.e., PUF cells) are selected. Each SRAM cell has a vertical bit line and a horizontal word line. Four SRAM cells are connected simultaneously using orthogonal word lines to generate one bit of data, thereby increasing the number of CRPs. However, the hardware overhead is large and the implementation is relatively complex. In the paper “S. Jeloka, K. Supreet, M. Kaiyuan Yang, et al. A Sequence Dependent Challenge-Response PUF using 28nm SRAM 6T BitCell. Symposium on VLSI Circuits, 2017, pp: C270-C271.”, Jeloka et al. proposed an SRAM PUF consisting of 6 transistors forming an SRAM cell. By selecting any two columns from the PUF array for comparison, the number of stimulus-response pairs can be expanded by an order of magnitude, but this method uses a large amount of hardware overhead. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a weak PUF circuit with rich excitation response pair based on MOS transistor leakage current that significantly increases the number of CRPs while having low hardware overhead.

[0006] The technical solution adopted by this invention to solve the above-mentioned technical problems is as follows: a rich-excitation-response-pair weak-PUF circuit based on MOS transistor leakage current, comprising a first decoder, a second decoder, a third decoder, a fourth decoder, two PUF arrays, two transmission gate arrays, and a shared header, wherein each PUF array includes two... q There are 2 columns, where q is an integer greater than 1, and each column contains 2... p There are 1 NMOS cell, where p is an integer greater than 1. Each NMOS cell includes one NMOS transistor. The two PUF arrays are referred to as the first PUF array and the second PUF array, respectively. The two transmission gate arrays are referred to as the first transmission gate array and the second transmission gate array, respectively. The first decoder is used to receive the first group of p-bit excitation signals and decode them into 2... p The row selection signal is output to the first PUF array, and the first PUF array is in this 2 p Under the control of the row selection signal, one NMOS cell in each column is selected and turned on to operate in the subthreshold region, generating a 1-bit response output to the first transmission gate array, i.e., the first PUF array generates 2 bits. q The bit response is output to the first transmission gate array, and the second decoder is used to receive the second group of p-bit excitation signals and decode them into 2 bits. p The bit row selection signal is output to the second PUF array, and the second PUF array is in the 2 p Under the control of the row selection signal, one NMOS cell in each column cell is selected and turned on to generate a 1-bit response output to the second transmission gate array, that is, the second PUF array generates 2 bits. q The bit response is output to the second transmission gate array, and the third decoder is used to receive the first group of q-bit excitation signals and decode them into 2. q The bit selection signal is output to the first transmission gate array, and the fourth decoder is used to receive the second group of q-bit excitation signals and decode them into 2. q The bit selection signal is output to the second transmission gate array, and the first transmission gate array is used to select the bit selection signal at the output of the third decoder. q Under the control of the bit selection signal, the output of the first PUF array is selected to the 2nd position. q One bit of the response in the bit response is output to the shared header, and the second transmission gate array is used to output 2 bits from the fourth decoder. q Under the control of the bit selection signal, the second PUF array output is selected to its position 2. qOne bit of the response is output to the shared header, which is used to compare the one bit response output to the first transmission gate array and the one bit response output to the second transmission gate array, and generate the final PUF response output based on the comparison result.

[0007] Compared with the prior art, the advantage of the present invention is that a weak PUF circuit is constructed by using a first decoder, a second decoder, a third decoder, a fourth decoder, two PUF arrays (a first PUF array and a second PUF array), two transmission gate arrays, and a shared header. Each PUF array includes two... q There are 2 columns, where q is an integer greater than 1, and each column contains 2... p There are 2 NMOS cells (i.e., PUF cells), where p is an integer greater than 1. Each NMOS cell includes one NMOS transistor. By making the first set of p-bit excitation signals and the second set of p-bit excitation signals the same or different, and the first set of q-bit excitation signals and the second set of q-bit excitation signals the same or different, under the decoding actions of the first decoder, the third decoder, and the second decoder and the fourth decoder, a certain NMOS cell in a certain column of the first PUF array can be compared with any NMOS cell in any column of the second PUF array, thereby outputting the final response. That is, the first PUF array and the second PUF array have 2 NMOS cells (i.e., PUF cells), where p is an integer greater than 1. q There are 2 column cells, each column cell has 2 p In the case of one NMOS unit, the weak PUF circuit of this invention utilizes an NMOS transistor operating in the subthreshold region as an entropy source to amplify process deviations during manufacturing, improve PUF stability, and, by employing a one-to-many configuration of the entropy source, reduce the number of excitation response pairs from 2 p+q One upgraded to (2) p+q ) 2 One, achieving a PUF entropy source utilization rate improvement of 2 p+q The weak PUF circuit of the present invention can significantly increase the number of CRPs while maintaining less hardware overhead.

[0008] Furthermore, p=6, q=3, the first decoder and the second decoder each have 6 inputs and 64 outputs, the third decoder and the fourth decoder each have 3 inputs and 8 outputs, each transmission gate array has 8 inputs, 8 selectors and 1 output, each PUF array has 64 inputs, 1 bias and 8 outputs, and the shared header has 1 enable, 1 precharge, 2 inputs and 1 output; the 64 outputs of the first decoder are connected to the first PUF array. The 64 input terminals of the first PUF array are connected one-to-one with each other. The 64 output terminals of the second decoder are also connected one-to-one with the 64 input terminals of the second PUF array. The bias terminals of the first PUF array and the second PUF array are connected, and their connection terminals are the bias terminals of the rich-excitation response based on MOS transistor leakage current for the weak PUF circuit, used to input the bias signal VBB. The bias signal VBB is used to make the NMOS transistors in the first PUF array and the second PUF array operate in the subthreshold region. The 8 output terminals of the third decoder are connected to the... The eight select terminals of the first transmission gate array are connected one-to-one; the eight output terminals of the first PUF array are connected one-to-one with the eight input terminals of the first transmission gate array; the eight output terminals of the fourth decoder are connected one-to-one with the eight select terminals of the second transmission gate array; the eight output terminals of the second PUF array are connected one-to-one with the eight input terminals of the second transmission gate array; the output terminals of the first and second transmission gate arrays are connected one-to-one with the two input terminals of the shared header; the six input terminals of the first decoder... The input terminals, the three input terminals of the third decoder, the six input terminals of the second decoder, and the three input terminals of the fourth decoder constitute the 18-bit excitation terminal of the MOS transistor leakage current-based rich excitation response to weak PUF circuit, used to input an 18-bit excitation signal. The enable terminal of the shared head is the enable terminal of the MOS transistor leakage current-based rich excitation response to weak PUF circuit, used to input an enable signal. The pre-charge terminal of the shared head is the pre-charge terminal of the MOS transistor leakage current-based rich excitation response to weak PUF circuit, used to input a pre-charge signal.

[0009] Furthermore, in each PUF array, each column cell has 64 input terminals, bias terminals, and output terminals. Within each column cell, each NMOS cell has an input terminal, bias terminal, and output terminal. The NMOS transistor in each NMOS cell is referred to as the first NMOS transistor. The gate of the first NMOS transistor is the input terminal of the NMOS cell, the drain of the first NMOS transistor is the bias terminal of the NMOS cell, and the source of the first NMOS transistor is the output terminal of the NMOS cell. The input terminal of the j-th NMOS cell is... The j-th input terminal of the column cell, j = 1, 2, ..., 64, is connected to the bias terminals of the 64 NMOS cells, and its connection terminal is the bias terminal of the column cell. The output terminals of the 64 NMOS cells are also connected, and their connection terminals are the output terminals of the column cell. The i-th input terminal of the 8 column cells is connected, and its connection terminal is the i-th input terminal of the PUF array, i = 1, 2, ..., 64. The bias terminals of the 8 column cells are also connected, and their connection terminals are the bias terminals of the PUF array. The output terminals of the 8 column cells serve as the 8 output terminals of the PUF array.

[0010] Furthermore, each transmission gate array includes 8 transmission gates, each transmission gate having a control terminal, an input terminal, and an output terminal. The control terminals of the 8 transmission gates serve as the 8 selection terminals of the transmission gate array, and the input terminals of the 8 transmission gates serve as the 8 input terminals of the transmission gate array. Specifically, the control terminal of the k-th transmission gate is the k-th selection terminal of the transmission gate array, k = 1, 2, ..., 8, and the input terminal of the k-th transmission gate is the k-th input terminal of the transmission gate array. The output terminals of the 8 transmission gates are connected, and their connection terminal is the output terminal of the transmission gate array.

[0011] Furthermore, each transmission gate includes a first inverter, a second NMOS transistor, and a first PMOS transistor. The gate of the second NMOS transistor is connected to the input terminal of the first inverter, and its connection terminal is the control terminal of the transmission gate. The gate of the first PMOS transistor is connected to the output terminal of the first inverter. The source of the second NMOS transistor is connected to the drain of the first PMOS transistor, and its connection terminal is the output terminal of the transmission gate. The drain of the second NMOS transistor is connected to the source of the first PMOS transistor, and its connection terminal is the input terminal of the transmission gate.

[0012] Furthermore, the shared connector includes a cross-coupling structure, a sensitive amplifier, and an arbitrator. The cross-coupling structure has three input terminals, referred to as its first input terminal, second input terminal, and third input terminal. The sensitive amplifier has two input terminals, one enable terminal, and two output terminals, referred to as its first input terminal and second input terminal, and its two output terminals as its first output terminal and second output terminal, respectively. The arbitrator has two input terminals and one output terminal, referred to as its first input terminal and second input terminal, respectively. The first input terminal of the cross-coupling structure is connected to the first input terminal of the sensitive amplifier, and this connection terminal is the first input terminal of the shared connector. The third input terminal is connected to the second input terminal of the sensitive amplifier, and its connection terminal is the second input terminal of the shared head. The second input terminal of the cross-coupling structure is the pre-charge terminal of the shared head. The pre-charge signal connected to the pre-charge terminal of the shared head is used to control the cross-coupling structure to enter the working state. The first output terminal of the sensitive amplifier is connected to the first input terminal of the arbitrator. The second output terminal of the sensitive amplifier is connected to the second input terminal of the arbitrator. The enable terminal of the sensitive amplifier is the enable terminal of the shared head. The enable signal connected to the enable terminal of the shared head is used to control the sensitive amplifier to enter the working state. The output terminal of the arbitrator is the output terminal of the shared head.

[0013] Furthermore, the cross-coupling structure includes a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, and a fifth PMOS transistor. The gates of the second and fifth PMOS transistors are connected, and their connection terminals are the second input terminals of the cross-coupling structure. The sources of the second, third, fourth, and fifth PMOS transistors are all connected to the power supply voltage VDD. The drains of the second, third, and fourth PMOS transistors are connected, and their connection terminals are the first input terminals of the cross-coupling structure. The drains of the fourth and fifth PMOS transistors are connected, and their connection terminals are the third input terminals of the cross-coupling structure.

[0014] Furthermore, the sensitive amplifier structure includes a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor. The sources of the sixth, seventh, eighth, ninth, tenth, and eleventh PMOS transistors are all connected to the power supply voltage VDD. The gates of the sixth, tenth, seventh, ninth, and eleventh PMOS transistors are connected, and their connection terminals serve as the enable terminals of the sensitive amplifier. The gate of the fifth NMOS transistor is the first input terminal of the sensitive amplifier, and the gate of the sixth NMOS transistor is the enable terminal of the sensitive amplifier. The second input terminal of the amplifier is connected to the drain of the sixth PMOS transistor, the drain of the seventh PMOS transistor, the gate of the eighth PMOS transistor, the drain of the third NMOS transistor, and the gate of the fourth NMOS transistor, and its connection terminal is the first output terminal of the sensitive amplifier. The drain of the eighth PMOS transistor, the drain of the ninth PMOS transistor, the gate of the seventh PMOS transistor, the drain of the fourth NMOS transistor, and the gate of the third NMOS transistor are connected, and their connection terminal is the second output terminal of the sensitive amplifier. The drain of the tenth PMOS transistor, the source of the third NMOS transistor, and the drain of the fifth NMOS transistor are connected. The drain of the eleventh PMOS transistor, the source of the fourth NMOS transistor, and the drain of the sixth NMOS transistor are connected. The source of the fifth NMOS transistor, the source of the sixth NMOS transistor, and the drain of the seventh NMOS transistor are connected. The source of the seventh NMOS transistor is grounded.

[0015] Furthermore, the arbitrator includes two two-input NAND gates, each having a first input terminal, a second input terminal, and an output terminal. These two two-input NAND gates are referred to as the first two-input NAND gate and the second two-input NAND gate, respectively. The first input terminal of the first two-input NAND gate is the first input terminal of the arbitrator unit, and the second input terminal of the second two-input NAND gate is the second input terminal of the arbitrator unit. The second input terminal of the first two-input NAND gate is connected to the output terminal of the second two-input NAND gate, and the output terminal of the first two-input NAND gate is connected to the first input terminal of the second two-input NAND gate, with the connection point serving as the output terminal of the arbitrator unit. Attached Figure Description

[0016] Figure 1 This is a structural diagram of a weak PUF circuit with rich excitation response based on MOS transistor leakage current according to the present invention.

[0017] Figure 2 This is a structural diagram of a PUF array based on the rich excitation response of a weak PUF circuit with MOS transistor leakage current according to the present invention.

[0018] Figure 3 This is a structural diagram of a column cell in a weak PUF circuit based on the leakage current of a MOS transistor.

[0019] Figure 4 This is a circuit diagram of an NMOS cell with a rich excitation response to a weak PUF circuit based on the leakage current of a MOS transistor, according to the present invention.

[0020] Figure 5 This is a structural diagram of a transmission gate array for a weak PUF circuit with rich excitation response based on MOS transistor leakage current according to the present invention.

[0021] Figure 6 This is a circuit diagram of a transmission gate for a weak PUF circuit based on the rich excitation response of a MOS transistor leakage current according to the present invention.

[0022] Figure 7 This is a structural diagram of a shared header for a weak PUF circuit with a rich excitation response based on MOS transistor leakage current according to the present invention.

[0023] Figure 8 This is a circuit diagram of a cross-coupling structure for a weak PUF circuit based on the leakage current of a MOS transistor.

[0024] Figure 9 This is a structural diagram of a sensitive amplifier with a rich excitation response to a weak PUF circuit based on the leakage current of a MOS transistor, according to the present invention.

[0025] Figure 10 This is a circuit diagram of an arbitrator for a weak PUF circuit based on the leakage current of a MOS transistor.

[0026] Figure 11 This is a layout of a weak PUF circuit with a rich excitation response based on MOS transistor leakage current according to the present invention.

[0027] Figure 12 This is a diagram illustrating the influence of different VBB values ​​based on MOS transistor leakage current on the stability and randomness of the PUF according to the present invention.

[0028] Figure 13 This is a grayscale statistical diagram of the output response of a weak PUF circuit based on the rich excitation response of a MOS transistor leakage current according to the present invention.

[0029] Figure 14 This is an average grayscale statistical diagram of the output response of a weak PUF circuit based on the rich excitation response of a MOS transistor leakage current according to the present invention.

[0030] Figure 15 This is a test diagram of the intra-chip Hamming distance and inter-chip Hamming distance of a weak PUF circuit based on the rich excitation response of MOS transistor leakage current according to the present invention. Detailed Implementation

[0031] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0032] Example 1: As Figure 1 As shown, a rich-drive-response-pair (BRPF) weak-PUF circuit based on MOS transistor leakage current includes a first decoder, a second decoder, a third decoder, a fourth decoder, two PUF arrays, two transmission gate arrays, and a shared header. Each PUF array includes two... q There are 2 columns, where q is an integer greater than 1, and each column contains 2... p There are 1 NMOS cell, where p is an integer greater than 1. Each NMOS cell includes one NMOS transistor. The two PUF arrays are referred to as the first PUF array and the second PUF array, respectively. The two transmission gate arrays are referred to as the first transmission gate array and the second transmission gate array, respectively. The first decoder is used to receive the first group of p-bit excitation signals and decode them into 2... p The bit row selection signal is output to the first PUF array, and the first PUF array is in this 2 p Under the control of the row selection signal, one NMOS cell in each column is selected and turned on to operate in the subthreshold region, generating a 1-bit response output to the first transmission gate array, i.e., the first PUF array generates 2 bits. q The bit response output is sent to the first transmission gate array, and the second decoder is used to receive the second group of p-bit excitation signals and decode them into 2 bits. p The bit row selection signal is output to the second PUF array, and the second PUF array is in this 2 p Under the control of the row selection signal, one NMOS cell in each column is selected and turned on to generate a 1-bit response output to the second transmission gate array, that is, the second PUF array generates 2 bits. q The bit response is output to the second transmission gate array, and the third decoder is used to receive the first group of q-bit excitation signals and decode them into 2. q The bit selection signal is output to the first transmission gate array, and the fourth decoder is used to receive the second group of q-bit excitation signals and decode them into 2. q The bit selection signal is output to the second transmission gate array, and the first transmission gate array is used to select the 2 bits from the output of the third decoder. q Under the control of the bit selection signal, the first PUF array output is selected to its position 2. qOne bit of the response is output to the shared header, and the second transmission gate array is used to output the second bit of the fourth decoder. q Under the control of the bit selection signal, the second PUF array output is selected to its position 2. q One bit of the response is output to the shared header. The shared header is used to compare the one bit response QL output to it from the first transmission gate array and the one bit response QR output to it from the second transmission gate array, and to generate the final PUF response R output based on the comparison result.

[0033] In this embodiment, p=6, q=3, the first and second decoders each have 6 inputs and 64 outputs, the third and fourth decoders each have 3 inputs and 8 outputs, each transmission gate array has 8 inputs, 8 selectors, and 1 output, each PUF array has 64 inputs, 1 bias, and 8 outputs, and the shared header has 1 enable, 1 precharge, 2 inputs, and 1 output; the 64 outputs of the first decoder are connected to the first PUF array... The 64 input terminals of the first decoder are connected one-to-one with each other, and the 64 output terminals of the second decoder are connected one-to-one with the 64 input terminals of the second PUF array. The bias terminals of the first and second PUF arrays are connected, and their connection terminals are bias terminals for the weak PUF circuit based on the rich excitation response of MOS transistor leakage current, used to input the bias signal VBB. The bias signal VBB is used to make the NMOS transistors in the first and second PUF arrays operate in the subthreshold region. The 8 output terminals of the third decoder are connected to the first transmission... The eight select terminals of the gate array are connected one-to-one. The eight output terminals of the first PUF array are connected one-to-one with the eight input terminals of the first transmission gate array. The eight output terminals of the fourth decoder are connected one-to-one with the eight select terminals of the second transmission gate array. The eight output terminals of the second PUF array are connected one-to-one with the eight input terminals of the second transmission gate array. The output terminals of the first and second transmission gate arrays are connected one-to-one with the two input terminals of the shared head. The six input terminals of the first decoder, the three input terminals of the third decoder, the six input terminals of the second decoder, and the three input terminals of the fourth decoder constitute an 18-bit excitation terminal for the MOSFET leakage current-based rich excitation response to the weak PUF circuit, used to input 18-bit excitation signals C1 to C18. The enable terminal of the shared head is the enable terminal for the MOSFET leakage current-based rich excitation response to the weak PUF circuit, used to input the enable signal EN. The pre-charge terminal of the shared head is the pre-charge terminal for the MOSFET leakage current-based rich excitation response to the weak PUF circuit, used to input the pre-charge signal PRE.

[0034] In this embodiment, by making the first group of p-bit excitation signals and the second group of p-bit excitation signals the same or different, and the first group of q-bit excitation signals and the second group of q-bit excitation signals the same or different, under the decoding actions of the first decoder and the third decoder, and under the decoding actions of the second decoder and the fourth decoder, a certain NMOS cell in a certain column of the first PUF array can be compared with any NMOS cell in any column of the second PUF array, thereby outputting the final response, that is, the first PUF array and the second PUF array have 2 q There are 2 column cells, each column cell has 2 p When there are NMOS cells, the number of excitation response pairs generated by the rich excitation response based on the leakage current of the MOS transistor and the weak PUF circuit of the present invention is (2) p+q ) 2 Traditional weak PUF circuits can only compare NMOS cells at the same position in the same column cells of the first and second PUF arrays to output a response. That is, traditional weak PUF circuits have 2 NMOS cells in their first and second PUF arrays. q There are 2 column cells, each column cell has 2 p With one NMOS cell, 2 can be generated p+q There are two excitation response pairs; thus, when a conventional weak PUF circuit also has two PUF arrays, and these two PUF arrays are exactly the same as the two PUF arrays in the excitation response pair-rich weak PUF circuit based on MOS transistor leakage current of the present invention, the number of excitation response pairs in the excitation response pair-rich weak PUF circuit based on MOS transistor leakage current of the present invention is increased from 2 to 1000 compared to the conventional weak PUF circuit. p+q One upgraded to (2) p+q ) 2 One, achieving a PUF entropy source utilization rate improvement of 2 p+q Therefore, the rich excitation response based on MOS transistor leakage current of the present invention can significantly increase the number of CRPs while maintaining less hardware overhead.

[0035] Example 2: This example is basically the same as Example 1, except that: in this example, as Figures 2 to 4As shown, in each PUF array, each column cell has 64 input terminals, bias terminals, and output terminals. Within each column cell, each NMOS cell has an input terminal, bias terminal, and output terminal. The NMOS transistor in each NMOS cell is referred to as the first NMOS transistor N1. The gate of the first NMOS transistor is the input terminal of the NMOS cell, the drain of the first NMOS transistor is the bias terminal, and the source of the first NMOS transistor is the output terminal. The input terminal of the j-th NMOS cell is the column cell's... The j-th input terminal (j = 1, 2, ..., 64) is connected to the bias terminals of 64 NMOS cells, and its connection terminal is also the bias terminal of the column cell. The output terminals of the 64 NMOS cells are also connected to the output terminals of the column cell. The ith input terminal of the 8 column cells is connected to the ith input terminal of the PUF array (i = 1, 2, ..., 64). The bias terminals of the 8 column cells are also connected to the bias terminals of the PUF array. The output terminals of the 8 column cells serve as the 8 output terminals of the PUF array.

[0036] In this embodiment, in each PUF array, when the input terminal of a certain NMOS cell in a certain column is connected to a high level, the first NMOS transistor N1 in that NMOS cell operates in the subthreshold region under the bias voltage VBB connected to its drain. The first NMOS transistor N1 generates a corresponding voltage signal and outputs it at its source. This voltage signal represents the extracted process deviation between transistors. In the first PUF array, the 64-bit row select signal decoded by the first decoder selects one NMOS cell in the first PUF array to be turned on. Since the bias terminals of all NMOS cells in the first PUF array are connected... By connecting them together, it is possible to ensure that all NMOS transistors within it operate in the subthreshold region, amplifying process deviations during NMOS transistor manufacturing. Simultaneously, in the second PUF array, the 64-bit row select signal decoded by the second decoder selects one NMOS cell in the second PUF array to conduct. Since the bias terminals of all NMOS cells in the second PUF array are connected together, it is possible to ensure that all NMOS transistors within it operate in the subthreshold region, amplifying process deviations during NMOS transistor manufacturing. Thus, the stability of the rich excitation response based on MOS transistor leakage current of this invention for weak PUF circuits can be improved.

[0037] Example 3: This example is basically the same as Example 2, except that: in this example, as Figure 5As shown, each transmission gate array includes 8 transmission gates. Each transmission gate has a control terminal, an input terminal, and an output terminal. The control terminals of the 8 transmission gates serve as the 8 selection terminals of the transmission gate array, and the input terminals of the 8 transmission gates serve as the 8 input terminals of the transmission gate array. The control terminal of the k-th transmission gate is the k-th selection terminal of the transmission gate array, k = 1, 2, ..., 8. The input terminal of the k-th transmission gate is the k-th input terminal of the transmission gate array. The output terminals of the 8 transmission gates are connected, and their connection terminal is the output terminal of the transmission gate array.

[0038] In this embodiment, as Figure 6 As shown, each transmission gate includes a first inverter INV1, a second NMOS transistor N2, and a first PMOS transistor P1. The gate of the second NMOS transistor N2 is connected to the input terminal of the first inverter INV1, and its connection terminal is the control terminal of the transmission gate. The gate of the first PMOS transistor P1 is connected to the output terminal of the first inverter INV1. The source of the second NMOS transistor N2 is connected to the drain of the first PMOS transistor P1, and its connection terminal is the output terminal of the transmission gate. The drain of the second NMOS transistor N2 is connected to the source of the first PMOS transistor P1, and its connection terminal is the input terminal of the transmission gate.

[0039] In this embodiment, when the control terminal of the transmission gate is connected to a high level 1, both the second NMOS transistor N2 and the first PMOS transistor P1 are turned on. At this time, the transmission gate is in the on state, and the signal input to the transmission gate is transmitted to its output terminal through the second NMOS transistor N2 and the first PMOS transistor P1. When the control terminal of the transmission gate is connected to a low level 0, both the second NMOS transistor N2 and the first PMOS transistor P1 are turned off. At this time, the transmission gate is in the off state and cannot transmit the signal input to its output terminal.

[0040] Example 4: This example is basically the same as Example 3, except that: in this example, as Figure 7As shown, the shared connector includes a cross-coupled structure, a sensitive amplifier, and an arbiter. The cross-coupled structure has three input terminals, referred to as its first input terminal, second input terminal, and third input terminal. The sensitive amplifier has two input terminals, one enable terminal, and two output terminals, referred to as its first input terminal and second input terminal, and its two output terminals as its first output terminal and second output terminal, respectively. The arbiter has two input terminals and one output terminal, referred to as its first input terminal and second input terminal, respectively. The first input terminal of the cross-coupled structure is connected to the first input terminal of the sensitive amplifier, and this connection terminal is the first terminal of the shared connector. The third input terminal of the cross-coupled structure is connected to the second input terminal of the sensitive amplifier, and its connection terminal is the second input terminal of the shared head. The second input terminal of the cross-coupled structure is the pre-charge terminal of the shared head. The pre-charge signal PRE connected to the pre-charge terminal of the shared head is used to control the cross-coupled structure to put it into working state. The first output terminal of the sensitive amplifier is connected to the first input terminal of the arbitrator, and the second output terminal of the sensitive amplifier is connected to the second input terminal of the arbitrator. The enable terminal of the sensitive amplifier is the enable terminal of the shared head. The enable signal connected to the enable terminal of the shared head is used to control the sensitive amplifier to put it into working state. The output terminal of the arbitrator is the output terminal of the shared head.

[0041] In this embodiment, as Figure 8 As shown, the cross-coupled structure includes a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, and a fifth PMOS transistor P5. The gate of the second PMOS transistor P2 and the gate of the fifth PMOS transistor P5 are connected, and their connection point is the second input terminal of the cross-coupled structure. The sources of the second PMOS transistor P2, the third PMOS transistor P3, the fourth PMOS transistor P4, and the fifth PMOS transistor P5 are all connected to the power supply voltage VDD. The drains of the second PMOS transistor P2, the third PMOS transistor P3, and the gate of the fourth PMOS transistor P4 are connected, and their connection point is the first input terminal of the cross-coupled structure. The drains of the fourth PMOS transistor P4, the fifth PMOS transistor P5, and the gate of the third PMOS transistor P3 are connected, and their connection point is the third input terminal of the cross-coupled structure.

[0042] In this cross-coupled structure, when the pre-charge signal PRE connected to its second input terminal is low (0), both the second PMOS transistor P2 and the fifth PMOS transistor P5 are turned on. At this time, the signals connected to its first and second input terminals are pulled up to equal the power supply voltage VDD, and the third PMOS transistor P3 and the fourth PMOS transistor P4 are turned off. When the pre-charge signal PRE connected to its second input terminal is high (1), both the second PMOS transistor P2 and the fifth PMOS transistor P5 are turned off. At this time, the magnitude of the leakage current connected to its first and third input terminals is determined. If... If the leakage current at the first input terminal is greater than the leakage current at the third input terminal, then the fourth PMOS transistor P4 will conduct, pulling the signal at the first input terminal to the power supply voltage VDD. The third PMOS transistor P3 will pull the signal at the third input terminal to equal the bias voltage VBB. If the leakage current at the first input terminal is less than the leakage current at the third input terminal, then the third PMOS transistor P3 will conduct, pulling the signal at the third input terminal to the power supply voltage VDD. The fourth PMOS transistor P4 will pull the signal at the third input terminal to equal the bias voltage VBB. Due to manufacturing variations in each PMOS transistor, the leakage currents at the first and third input terminals of the cross-coupled structure will not be equal.

[0043] In this embodiment, as Figure 9As shown, the sensitive amplifier structure includes a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, an eleventh PMOS transistor P11, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, and a seventh NMOS transistor N7. The sources of the sixth PMOS transistor P6, the seventh PMOS transistor P7, the eighth PMOS transistor P8, the ninth PMOS transistor P9, the tenth PMOS transistor P10, and the eleventh PMOS transistor P11 are all connected to the power supply voltage VDD. The gates of the sixth PMOS transistor P6, the tenth PMOS transistor P10, the seventh NMOS transistor P8, the ninth PMOS transistor P9, and the eleventh PMOS transistor P11 are connected, and their connection terminals are the enable terminals of the sensitive amplifier. The gate of the fifth NMOS transistor N5 is the first input terminal of the sensitive amplifier. The sixth NMOS transistor... The gate of transistor N6 is the second input terminal of the sensitive amplifier. The drain of the sixth PMOS transistor P6, the drain of the seventh PMOS transistor P7, the gate of the eighth PMOS transistor P8, the drain of the third NMOS transistor N3, and the gate of the fourth NMOS transistor N4 are connected, and their connection terminal is the first output terminal of the sensitive amplifier. The drain of the eighth PMOS transistor P8, the drain of the ninth PMOS transistor P9, the gate of the seventh PMOS transistor P7, the drain of the fourth NMOS transistor N4, and the gate of the third NMOS transistor N3 are connected, and their connection terminal is the second output terminal of the sensitive amplifier. The drain of the tenth PMOS transistor P10, the source of the third NMOS transistor N3, and the drain of the fifth NMOS transistor N5 are connected. The drain of the eleventh PMOS transistor P11, the source of the fourth NMOS transistor N4, and the drain of the sixth NMOS transistor N6 are connected. The source of the fifth NMOS transistor N5, the source of the sixth NMOS transistor N6, and the drain of the seventh NMOS transistor N7 are connected. The source of the seventh NMOS transistor N7 is grounded.

[0044] In this sensitive amplifier, when the enable signal connected to the enable terminal of the sensitive amplifier is low (0), the sensitive amplifier is in a pre-charge state. The sixth PMOS transistor P6, the tenth PMOS transistor P10, the ninth PMOS transistor P9, and the eleventh PMOS transistor P11 are all turned on, the seventh NMOS transistor N7 is turned off, the seventh PMOS transistor P7 is turned off, the eighth PMOS transistor is turned off, the third NMOS transistor and the fourth NMOS transistor are both turned off, and the fifth NMOS transistor and the sixth NMOS transistor are turned on or off according to the corresponding gate voltage. Since the sixth PMOS transistor P6 is turned on, the first output terminal of the sensitive amplifier is charged to a high level. Since the ninth PMOS transistor P9 is turned on, the second output terminal of the sensitive amplifier is also charged to a high level. When the enable signal connected to the enable terminal of the sensitive amplifier is high (1), the sensitive amplifier is in evaluation state. The sixth PMOS transistor P6, the tenth PMOS transistor P10, the ninth PMOS transistor P9, and the eleventh PMOS transistor P11 are all turned off, while the seventh NMOS transistor N7 is turned on. When the input signal at the first input terminal of the sensitive amplifier is VBB and the signal at the second input terminal is VDD, the turn-on speed of the sixth NMOS transistor N6 is faster than that of the fifth NMOS transistor N5. The discharge speed at the second output terminal of the sensitive amplifier is faster than that at its first output terminal. Finally, the first output terminal of the sensitive amplifier will output a high level, and the second output terminal will output a low level. When the input signal at the first input terminal of the sensitive amplifier is VDD and the signal at the second input terminal is VBB, the turn-on speed of the fifth NMOS transistor N5 is faster than that of the sixth NMOS transistor N6. The discharge speed at the first output terminal of the sensitive amplifier is faster than that at its second output terminal. Finally, the second output terminal of the sensitive amplifier will output a high level, and the first output terminal will output a low level.

[0045] In this embodiment, as Figure 10 As shown, the arbitrator includes two two-input NAND gates. Each two-input NAND gate has a first input terminal, a second input terminal, and an output terminal. The two two-input NAND gates are referred to as the first two-input NAND gate U1 and the second two-input NAND gate U2, respectively. The first input terminal of the first two-input NAND gate U1 is the first input terminal of the arbitrator unit, and the second input terminal of the second two-input NAND gate U2 is the second input terminal of the arbitrator unit. The second input terminal of the first two-input NAND gate U1 and the output terminal of the second two-input NAND gate U2 are connected. The output terminal of the first two-input NAND gate U1 and the first input terminal of the second two-input NAND gate U2 are connected, and the connection terminal is the output terminal of the arbitrator unit.

[0046] In this arbitrator, when the signal connected to the first input terminal of the first two-input NAND gate U1 is low and the signal connected to the second input terminal of the second two-input NAND gate U2 is low, regardless of whether the signal connected to the second input terminal of the first two-input NAND gate U1 is high or low, and regardless of whether the signal connected to the first input terminal of the second two-input NAND gate U2 is high or low, the output signal of the arbitrator is high. When the signal connected to the first input terminal of the first two-input NAND gate U1 is high and the signal connected to the second input terminal of the second two-input NAND gate U2 is high, the output signal of the arbitrator remains unchanged from the previous state. When the signal connected to the first input terminal of the first two-input NAND gate U1 is high and the signal connected to the second input terminal of the second two-input NAND gate U2 is low, the output signal of the arbitrator remains unchanged from the previous state. When the signal is low, regardless of whether the signal connected to the first input terminal of the second two-input NAND gate U2 is high or low, the output signal of the second two-input NAND gate U2 is high. At this time, the signal connected to the second input terminal of the first two-input NAND gate U1 is also high, and finally the output signal of the arbitrator is low. When the signal connected to the first input terminal of the first two-input NAND gate U1 is low and the signal connected to the second input terminal of the second two-input NAND gate U2 is high, regardless of whether the signal connected to the second input terminal of the first two-input NAND gate U1 is high or low, the output signal of the arbitrator is high. Then the signal connected to the first input terminal of the second two-input NAND gate U2 is also high, and the output signal of the second two-input NAND gate U2 is low.

[0047] To verify the performance of the rich-drive response based on MOSFET drain current for a weak PUF circuit, the circuit was implemented using TSMC 65nm CMOS technology, as shown in the layout below. Figure 11 As shown. When p=6 and q=3, the overall layout area of ​​the rich-excitation response circuit based on MOS transistor leakage current with weak PUF is 33.63μm×48.68μm, and the hardware overhead is relatively small.

[0048] To verify the optimal performance of the rich-excitation response based on MOS transistor leakage current in this invention for a weak PUF circuit, the bias voltage VBB input to the entropy source transistor (i.e., the first NMOS transistor in the NMOS cell of the column unit) of the PUF array was tested with various performance indicators when a bias voltage VBB of 0.6V to 1V was applied to the source of the PUF array. Specifically, the tests were conducted with bias voltages VBB of 0.6V, 0.65V, 0.7V, 0.75V, 0.8V, 0.85V, 0.9V, 0.95V, and 1V. The test results are as follows: Figure 12As shown, when the bias voltage VBB increases from 0.6V to 0.8V, the average bit error rate (BER) decreases from 1.31% to 0.25% after 50 repeated tests on the same set of stimulus response pairs, a decrease of 5.24 times. When the bias voltage VBB decreases from 1V to 0.8V, the average BER decreases from 1.78% to 0.25% after 50 repeated tests on the same set of stimulus response pairs, a decrease of 7.12 times. Furthermore, the randomness at 0.8V is also good. Therefore, the stability and randomness of the PUF circuit based on MOS transistor leakage current with a rich stimulus response pair bias voltage VBB of this invention are good at 0.8V.

[0049] Randomness indicates whether the PUF output response is randomly distributed, which can be visually reflected using a grayscale image. For a sample of the present invention's PUF circuit with rich excitation response pairs based on MOS transistor leakage current, with a bias voltage VBB of 0.8V, 8192 excitation response pairs were randomly extracted, and the resulting grayscale image is shown below. Figure 13 As shown, analysis Figure 13 It can be seen that the probability of a response of "1" is 50.01% and the probability of a response of "0" is 49.99%, indicating that the rich excitation response based on MOS transistor leakage current of the present invention has good randomness for weak PUF circuits.

[0050] Furthermore, 20 prototype weak PUF circuits based on MOS transistor leakage current based on the present invention were repeatedly tested, with a bias voltage VBB of 0.8V. For each prototype weak PUF circuit based on MOS transistor leakage current based on the present invention, 8192 sets of excitation-response pairs were randomly extracted, and the resulting average grayscale images are shown below. Figure 14 As shown, analysis Figure 14 It can be seen that the probability of a response of "1" is 49.86% and the probability of a response of "0" is 50.14%, indicating that the rich excitation response based on MOS transistor leakage current of the present invention has good randomness for weak PUF circuits.

[0051] Uniqueness refers to the ability to distinguish different PUFs. Under the same excitation, the output response of multiple prototype weak PUF circuits based on the rich excitation response of the MOS transistor leakage current based on this invention was repeatedly tested. The bias voltage VBB was 0.8V, and the inter-chip Hamming distance was used for measurement. The test graphs of the intra-chip Hamming distance and inter-chip Hamming distance of the prototype weak PUF circuit based on the rich excitation response of the MOS transistor leakage current based on this invention are shown in the figure. Figure 15 As shown, analysis Figure 15 It can be seen that the expected value of the inter-chip Hamming distance is 49.848%, and the standard deviation is 1.762%. Both are close to the ideal value of 50% and the ideal value of 0% of the standard deviation, indicating that the rich excitation response based on MOS transistor leakage current of this invention has good uniqueness for weak PUF circuits.

[0052] In summary, the MOSFET leakage current-based rich-excitation-response-pair weak PUF circuit of this invention utilizes an NMOS transistor operating in the subthreshold region as an entropy source to amplify process deviations during manufacturing, thereby improving the stability of the PUF. Furthermore, by employing a one-to-many configuration of the entropy source, the number of excitation-response pairs is increased from 2... p+q One upgraded to (2) p+q ) 2 One, achieving a PUF entropy source utilization rate improvement of 2 p+q This method significantly increases the number of CRPs while maintaining relatively low hardware overhead, and also exhibits good randomness and uniqueness.

Claims

1. A rich-excitation-response-pair weak PUF circuit based on MOS transistor leakage current, characterized in that... It includes a first decoder, a second decoder, a third decoder, a fourth decoder, two PUF arrays, two transmission gate arrays, and a shared header. Each PUF array includes two... q There are 2 columns, where q is an integer greater than 1, and each column contains 2... p There are 1 NMOS cell, where p is an integer greater than 1. Each NMOS cell includes one NMOS transistor. The two PUF arrays are referred to as the first PUF array and the second PUF array, respectively. The two transmission gate arrays are referred to as the first transmission gate array and the second transmission gate array, respectively. The first decoder is used to receive the first group of p-bit excitation signals and decode them into 2... p The bit row selection signal is output to the first PUF array, and the first PUF array is in this 2 p Under the control of the row selection signal, one NMOS cell in each column is selected and turned on to operate in the subthreshold region, generating a 1-bit response output to the first transmission gate array, i.e., the first PUF array generates 2 bits. q The bit response is output to the first transmission gate array, and the second decoder is used to receive the second group of p-bit excitation signals and decode them into 2 bits. p The bit row selection signal is output to the second PUF array, and the second PUF array is in the 2 p Under the control of the row selection signal, one NMOS cell in each column is selected and turned on to generate a 1-bit response output to the second transmission gate array, that is, the second PUF array generates 2 q The bit response is output to the second transmission gate array, and the third decoder is used to receive the first group of q-bit excitation signals and decode them into 2. q The bit selection signal is output to the first transmission gate array, and the fourth decoder is used to receive the second group of q-bit excitation signals and decode them into 2. q The bit selection signal is output to the second transmission gate array, and the first transmission gate array is used to select the bit selection signal at the output of the third decoder. q Under the control of the bit selection signal, the output of the first PUF array is selected to the 2nd position. q One bit of the response in the bit response is output to the shared header, and the second transmission gate array is used to output 2 bits from the fourth decoder. q Under the control of the bit selection signal, the second PUF array output is selected to its position 2. q One bit of the response is output to the shared header, which is used to compare the one bit response output to the first transmission gate array and the one bit response output to the second transmission gate array, and generate the final PUF response output based on the comparison result.

2. The weak PUF circuit with rich excitation response based on MOS transistor leakage current according to claim 1, characterized in that... p=6, q=3, the first decoder and the second decoder each have 6 inputs and 64 outputs, the third decoder and the fourth decoder each have 3 inputs and 8 outputs, each transmission gate array has 8 inputs, 8 selectors and 1 output, each PUF array has 64 inputs, 1 bias and 8 outputs, and the shared header has 1 enable, 1 precharge, 2 inputs and 1 output; the 64 outputs of the first decoder are connected to the 6 inputs of the first PUF array. The four input terminals of the second decoder are connected one-to-one. The 64 output terminals of the second decoder are connected one-to-one with the 64 input terminals of the second PUF array. The bias terminals of the first PUF array and the second PUF array are connected, and their connection terminals are the bias terminals of the rich-excitation response based on MOS transistor leakage current for the weak PUF circuit, used to input the bias signal VBB. The bias signal VBB is used to make the NMOS transistors in the first PUF array and the second PUF array operate in the subthreshold region. The eight output terminals of the third decoder are connected to the first... The eight select terminals of the first transmission gate array are connected one-to-one; the eight output terminals of the first PUF array are connected one-to-one with the eight input terminals of the first transmission gate array; the eight output terminals of the fourth decoder are connected one-to-one with the eight select terminals of the second transmission gate array; the eight output terminals of the second PUF array are connected one-to-one with the eight input terminals of the second transmission gate array; the output terminals of the first and second transmission gate arrays are connected one-to-one with the two input terminals of the shared header; the six input terminals of the first decoder... The input terminals, the three input terminals of the third decoder, the six input terminals of the second decoder, and the three input terminals of the fourth decoder constitute the 18-bit excitation terminal of the MOS transistor leakage current-based rich excitation response to weak PUF circuit, used to input an 18-bit excitation signal. The enable terminal of the shared head is the enable terminal of the MOS transistor leakage current-based rich excitation response to weak PUF circuit, used to input an enable signal. The pre-charge terminal of the shared head is the pre-charge terminal of the MOS transistor leakage current-based rich excitation response to weak PUF circuit, used to input a pre-charge signal.

3. A weak PUF circuit with rich excitation response based on MOS transistor leakage current according to claim 2, characterized in that... In each PUF array, each column cell has 64 input terminals, bias terminals, and output terminals. Within each column cell, each NMOS cell has an input terminal, bias terminal, and output terminal. The NMOS transistor in each NMOS cell is referred to as the first NMOS transistor. The gate of the first NMOS transistor is the input terminal of the NMOS cell, the drain of the first NMOS transistor is the bias terminal of the NMOS cell, and the source of the first NMOS transistor is the output terminal of the NMOS cell. The input terminal of the j-th NMOS cell is the column cell... The j-th input terminal of the 8 column cells, j = 1, 2, ..., 64, is connected to the bias terminals of the 64 NMOS cells, and its connection terminal is the bias terminal of the column cell. The output terminals of the 64 NMOS cells are also connected, and their connection terminals are the output terminals of the column cell. The i-th input terminal of the 8 column cells is connected, and its connection terminal is the i-th input terminal of the PUF array, i = 1, 2, ..., 64. The bias terminals of the 8 column cells are also connected, and their connection terminals are the bias terminals of the PUF array. The output terminals of the 8 column cells serve as the 8 output terminals of the PUF array.

4. A rich-excitation-response weak PUF circuit based on MOS transistor leakage current according to claim 2, characterized in that... Each transmission gate array includes 8 transmission gates. Each transmission gate has a control terminal, an input terminal, and an output terminal. The control terminals of the 8 transmission gates serve as the 8 selection terminals of the transmission gate array, and the input terminals of the 8 transmission gates serve as the 8 input terminals of the transmission gate array. The control terminal of the k-th transmission gate is the k-th selection terminal of the transmission gate array, k = 1, 2, ..., 8. The input terminal of the k-th transmission gate is the k-th input terminal of the transmission gate array. The output terminals of the 8 transmission gates are connected, and their connection terminal is the output terminal of the transmission gate array.

5. A rich-excitation-response-pair weak PUF circuit based on MOS transistor leakage current according to claim 4, characterized in that... Each transmission gate includes a first inverter, a second NMOS transistor, and a first PMOS transistor. The gate of the second NMOS transistor is connected to the input terminal of the first inverter, and its connection terminal is the control terminal of the transmission gate. The gate of the first PMOS transistor is connected to the output terminal of the first inverter. The source of the second NMOS transistor is connected to the drain of the first PMOS transistor, and its connection terminal is the output terminal of the transmission gate. The drain of the second NMOS transistor is connected to the source of the first PMOS transistor, and its connection terminal is the input terminal of the transmission gate.

6. A rich-excitation-response-pair weak PUF circuit based on MOS transistor leakage current according to claim 2, characterized in that... The shared connector includes a cross-coupling structure, a sensitive amplifier, and an arbitrator. The cross-coupling structure has three input terminals, referred to as its first input terminal, second input terminal, and third input terminal. The sensitive amplifier has two input terminals, one enable terminal, and two output terminals, referred to as its first input terminal and second input terminal, and its two output terminals as its first output terminal and second output terminal, respectively. The arbitrator has two input terminals and one output terminal, referred to as its first input terminal and second input terminal, respectively. The first input terminal of the cross-coupling structure is connected to the first input terminal of the sensitive amplifier, and this connection point is the first input terminal of the shared connector. The three input terminals are connected to the second input terminal of the sensitive amplifier, and their connection terminals are the second input terminals of the shared head. The second input terminal of the cross-coupling structure is the pre-charge terminal of the shared head. The pre-charge signal connected to the pre-charge terminal of the shared head is used to control the cross-coupling structure to enter the working state. The first output terminal of the sensitive amplifier is connected to the first input terminal of the arbitrator. The second output terminal of the sensitive amplifier is connected to the second input terminal of the arbitrator. The enable terminal of the sensitive amplifier is the enable terminal of the shared head. The enable signal connected to the enable terminal of the shared head is used to control the sensitive amplifier to enter the working state. The output terminal of the arbitrator is the output terminal of the shared head.

7. A rich-excitation-response-pair weak PUF circuit based on MOS transistor leakage current according to claim 6, characterized in that... The cross-coupling structure includes a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, and a fifth PMOS transistor. The gates of the second and fifth PMOS transistors are connected, and their connection point is the second input terminal of the cross-coupling structure. The sources of the second, third, fourth, and fifth PMOS transistors are all connected to the power supply voltage VDD. The drains of the second, third, and fourth PMOS transistors are connected, and their connection point is the first input terminal of the cross-coupling structure. The drains of the fourth and fifth PMOS transistors are connected, and their connection point is the third input terminal of the cross-coupling structure.

8. A rich-excitation-response weak PUF circuit based on MOS transistor leakage current according to claim 6, characterized in that... The sensitive amplifier structure includes a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor. The sources of the sixth, seventh, eighth, ninth, tenth, and eleventh PMOS transistors are all connected to the power supply voltage VDD. The gates of the sixth, tenth, seventh, ninth, and eleventh PMOS transistors are connected, and their connection point serves as the enable terminal of the sensitive amplifier. The gate of the fifth NMOS transistor is the first input terminal of the sensitive amplifier, and the gate of the sixth NMOS transistor is the third input terminal of the sensitive amplifier. The six PMOS transistors, the seventh PMOS transistor, the eighth PMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are connected to each other, and this connection point is the first output terminal of the sensitive amplifier. The eighth PMOS transistor, the ninth PMOS transistor, the seventh PMOS transistor, the fourth NMOS transistor, and the third NMOS transistor are connected to each other, and this connection point is the second output terminal of the sensitive amplifier. The tenth PMOS transistor, the third NMOS transistor, and the fifth NMOS transistor are connected to each other. The eleventh PMOS transistor, the fourth NMOS transistor, and the sixth NMOS transistor are connected to each other. The fifth NMOS transistor, the sixth NMOS transistor, and the seventh NMOS transistor are connected to each other. The source of the seventh NMOS transistor is grounded.

9. A rich-excitation-response-pair weak PUF circuit based on MOS transistor leakage current according to claim 6, characterized in that... The arbitrator includes two two-input NAND gates, each having a first input, a second input, and an output. These two two-input NAND gates are referred to as the first two-input NAND gate and the second two-input NAND gate, respectively. The first input of the first two-input NAND gate is the first input of the arbitrator unit, and the second input of the second two-input NAND gate is the second input of the arbitrator unit. The second input of the first two-input NAND gate is connected to the output of the second two-input NAND gate, and the output of the first two two-input NAND gate is connected to the first input of the second two-input NAND gate, with the connection point serving as the output of the arbitrator unit.

Images