An LDO circuit with switchable power supply terminals

Abstract

The present application discloses an LDO circuit with a switchable power supply terminal, which includes an error amplifier EA. The error amplifier EA is connected to a chip output module and a chip input module through transmission gates TG1 and TG2 respectively. The output module and the input module have the same structure, and both include a control unit, a switching unit, and a voltage unit. In the same module: the control unit controls the switch of the switching unit under the action of a control signal. When the switching unit is turned off, the corresponding transmission gate of this module is turned on, enabling the error amplifier EA to communicate with this module, and the output voltage generated by the voltage unit of this module serves as the output of the LDO. When the switching unit is turned on, the corresponding transmission gate of this module is turned off, disconnecting the error amplifier EA from this module, and the voltage unit of this module is turned off. The present invention can achieve the switching of the LDO power supply terminal with only one error amplifier, effectively saving chip area.

Description

Technical Field

[0001] The present invention belongs to the technical field of LDO circuits and relates to an LDO circuit with a switchable power supply terminal. Background Art

[0002] In a power management chip, it is possible to choose whether to supply power to the internal LDO (low dropout regulator) from the input terminal or the output terminal. To save power consumption, different power supply terminals can be selected for the LDO in different situations through a corresponding algorithm. At this time, the LDO needs to have the function of switching the power supply terminal.

[0003] The traditional method is to make two LDOs on the chip, using the input terminal and the output terminal as the power supply terminals respectively. After specifying the power supply terminal, the LDO under the other power supply terminal is turned off. The disadvantage of this method is that two independent LDOs are required. Since the layout area of the LDO is generally large, this method wastes chip area and has a high cost. Summary of the Invention

[0004] To solve the deficiencies in the prior art, the present application provides an LDO circuit with a switchable power supply terminal.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] An LDO circuit with a switchable power supply terminal, characterized in that:

[0007] The circuit includes an error amplifier EA, and the error amplifier EA is connected to the chip output module and the chip input module through transmission gates TG1 and TG2 respectively;

[0008] The output module and the input module have the same structure, and both include a control unit, a switch unit, and a voltage unit;

[0009] In the same module:

[0010] The control unit controls the switch of the switch unit under the action of a control signal:

[0011] When the switch unit is turned off, the corresponding transmission gate of this module is turned on, so that the error amplifier EA is connected to this module, and the output voltage generated by the voltage unit of this module is used as the output of the LDO;

[0012] When the switch unit is turned on, the corresponding transmission gate of this module is turned off, so that the error amplifier EA is disconnected from this module, and the voltage unit of this module is turned off;

[0013] The control signal of the output module is OFF_SYS, and the control signal of the input module is OFF_PMID.

[0014] The present invention further includes the following preferred solutions:

[0015] Preferably, in the output module, the control unit includes a high-voltage transistor MS1, resistors R1 and R2;

[0016] The gate of the high-voltage transistor MS1 is connected to the control signal OFF_SYS and the voltage unit, the source is grounded, and the drain is connected to one end of R2 and the switch unit of this module. The other end of R2 is connected to one end of R1, and the other end of R1 is connected to the switch unit of this module.

[0017] Preferably, in the output module, the switch unit includes a low-voltage transistor MS2;

[0018] The source of the MS2 is connected to the SYS terminal, the gate is connected to the connection point of R1 and R2, and the drain is connected to the transmission gate TG1 and the voltage unit of this module.

[0019] Preferably, the switch unit is provided with a protection unit, and the protection unit includes a Zener diode Z1. The negative electrode of the Zener diode Z1 is connected to the SYS terminal, and the positive electrode is connected to the gate of the low-voltage transistor MS2.

[0020] Preferably, in the output module, the voltage unit includes a high-voltage transistor MP1 and a low-voltage transistor MR1;

[0021] The source of the MP1 is connected to the source of the MS2, the gate is connected to the drain of the MS2 and the transmission gate TG1, and the drain is connected to the drain of the MR1;

[0022] The gate of the MR1 is connected to the control signal OFF_SYS, and the source is the output terminal REGN of the LDO.

[0023] Preferably, a diode is connected between the source and the drain of the high-voltage transistor MP1. The source is connected to the cathode of the diode, and the drain is connected to the anode of the diode;

[0024] A diode is connected between the source and the drain of the low-voltage transistor MR1. The source is connected to the cathode of the diode, and the drain is connected to the anode of the diode.

[0025] Preferably, the MR1 is a PMOS.

[0026] Preferably, when it is required to be powered by the output terminal SYS terminal of the chip, OFF_SYS is at a low level and OFF_PMID is at a high level;

[0027] When it is required to be powered by the input terminal PMID terminal of the chip, OFF_SYS is at a high level and OFF_PMID is at a low level.

[0028] Preferably, in the output module, that is, on the SYS side, when OFF_SYS is at a high level, the gate voltage of MS2 is the voltage divided by R1 and R2. By setting the resistance ratio of R1 and R2, MS2 is in a fully conducting state when SYS is at its lowest level.

[0029] Preferably, the output module and the input module have the same structure, and the corresponding units in the modules are composed of components of the same model.

[0030] The beneficial effects achieved by this application are as follows:

[0031] The present invention can achieve the switching of the LDO power supply terminal with only one error amplifier, effectively saving chip area. Description of the Drawings

[0032] Figure 1 It is a structural diagram of an LDO circuit with a switchable power supply terminal. Detailed Embodiments

[0033] The following further describes this application with reference to the drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and should not be used to limit the protection scope of this application.

[0034] An LDO circuit with a switchable power supply terminal according to the present invention includes an error amplifier EA, and the error amplifier EA is respectively connected to a chip output module and a chip input module through transmission gates TG1 and TG2;

[0035] The output module and the input module have the same structure, and both include a control unit, a switch unit, and a voltage unit;

[0036] In the same module:

[0037] The control unit controls the switch of the switch unit under the action of a control signal:

[0038] When the switch unit is turned off, the corresponding transmission gate of this module is turned on, connecting the error amplifier EA to this module, and the output voltage generated by the voltage unit of this module is used as the output of the LDO;

[0039] When the switch unit is turned on, the corresponding transmission gate of this module is turned off, disconnecting the error amplifier EA from this module, and the voltage unit of this module is turned off;

[0040] The control signal of the output module is OFF_SYS, and the control signal of the input module is OFF_PMID.

[0041] During specific implementation, the output module and the input module have the same structure, and the corresponding units in the modules are composed of components of the same model, as Figure 1 shown. Figure 1Among them, PMID and SYS are the input and output terminals of the chip respectively, REGN is the output terminal of the LDO, and OFF_SYS and OFF_PMID are control signals respectively. EA is an error amplifier; MS1, MS3, MP1, and MP2 are high-voltage transistors, and TG1 and TG2 are transmission gates; MS2, MS4, MR1, and MR2 are low-voltage transistors, where MR1 and MR2 are PMOS, and Z1 and Z2 are Zener diodes.

[0042] Combined with Figure 1 , the output module is used to introduce the control unit, switch unit, and voltage unit. Specifically:

[0043] In the output module, the control unit includes the high-voltage transistor MS1, resistors R1 and R2;

[0044] The gate of the high-voltage transistor MS1 is connected to the control signal OFF_SYS and the voltage unit, the source is grounded, the drain is connected to one end of R2 and the switch unit of this module, the other end of R2 is connected to one end of R1, and the other end of R1 is connected to the switch unit of this module.

[0045] The switch unit includes the low-voltage transistor MS2;

[0046] The source of the MS2 is connected to the SYS terminal, the gate is connected to the connection point of R1 and R2, and the drain is connected to the transmission gate TG1 and the voltage unit of this module;

[0047] The protection unit includes the Zener diode Z1. The negative pole of the Zener diode Z1 is connected to the SYS terminal, and the positive pole is connected to the gate of the low-voltage transistor MS2.

[0048] The voltage unit includes the high-voltage transistor MP1 and the low-voltage transistor MR1;

[0049] The source of the MP1 is connected to the source of the MS2, the gate is connected to the drain of the MS2 and the transmission gate TG1, and the drain is connected to the drain of the MR1;

[0050] The gate of the MR1 is connected to the control signal OFF_SYS, and the source is the output terminal REGN of the LDO.

[0051] A diode is connected between the source and the drain of the high-voltage transistor MP1. The source is connected to the cathode of the diode, and the drain is connected to the anode of the diode;

[0052] A diode is connected between the source and the drain of the low-voltage transistor MR1. The source is connected to the cathode of the diode, and the drain is connected to the anode of the diode.

[0053] The MR1 is a PMOS.

[0054] When it is required to be powered by the output terminal SYS of the chip, OFF_SYS is at a low level and OFF_PMID is at a high level. The working principle is as follows:

[0055] On the PMID side, OFF_PMID is at a high level. Therefore, the gate voltage of MS4 is the voltage division result of R3 and R4. By setting a reasonable ratio of R3 to R4, it is possible to ensure that MS4 is in a fully conducting state even when PMID is at its lowest. The function of Z2 is to protect the gate of MS4 when PMID is relatively high.

[0056] The conduction of MS4 turns off MP2. At the same time, TG2 turns off, disconnecting the output terminal of EA from the gate of MP2 to ensure that the output terminal of EA is not affected. MR2 turns off to ensure that when PMID is lower than REGN, current does not flow from REGN to PMID.

[0057] On the SYS side, since OFF_SYS is at a low level, MS2 turns off. At the same time, TG1 conducts. Therefore, the gate signal of MS2 is controlled by EA at this time; MR1 conducts, so the output voltage generated by the power transistor MP1 is used as the REGN output.

[0058] When it is required to be powered by the input terminal PMID of the chip, OFF_SYS is at a high level and OFF_PMID is at a low level. The working principle is the same as above and will not be elaborated here.

[0059] It should be noted that the specific implementation circuits of TG1 and TG2 change with different EA structures. Figure 1 The TG in is only a schematic diagram used to represent the connection relationship between the EA output and the gates of MP1 and MP2.

[0060] The applicant of the present invention has made a detailed description and illustration of the embodiments of the present invention in combination with the accompanying drawings of the specification. However, those skilled in the art should understand that the above embodiments are only the preferred implementation schemes of the present invention. The detailed description is only to help readers better understand the spirit of the present invention, rather than a limitation on the protection scope of the present invention. On the contrary, any improvement or modification made based on the spirit of the present invention should fall within the protection scope of the present invention.

Claims

1. An LDO circuit with a switchable power supply terminal, characterized in that: The circuit includes an error amplifier EA, and the error amplifier EA is connected to a chip output module and a chip input module through transmission gates TG1 and TG2 respectively; The output module and the input module have the same structure, and both include a control unit, a switch unit, and a voltage unit; In the same module: The control unit controls the switch of the switch unit under the action of a control signal: When the switch unit is turned off, the corresponding transmission gate of this module is turned on, so that the error amplifier EA is connected to this module, and the output voltage generated by the voltage unit of this module is used as the output of the LDO; When the switch unit is turned on, the corresponding transmission gate of this module is turned off, so that the error amplifier EA is disconnected from this module, and the voltage unit of this module is turned off; The control signal of the output module is OFF_SYS, and the control signal of the input module is OFF_PMID.

2. The LDO circuit with a switchable power supply terminal according to claim 1, characterized in that: In the output module, the control unit includes a high-voltage transistor MS1, resistors R1 and R2; The gate of the high-voltage transistor MS1 is connected to the control signal OFF_SYS and the voltage unit, the source is grounded, the drain is connected to one end of R2 and the switch unit of this module, the other end of R2 is connected to one end of R1, and the other end of R1 is connected to the switch unit of this module.

3. The LDO circuit with a switchable power supply terminal according to claim 2, characterized in that: In the output module, the switch unit includes a low-voltage transistor MS2; The source of the MS2 is connected to the SYS terminal, the gate is connected to the connection point of R1 and R2, and the drain is connected to the transmission gate TG1 and the voltage unit of this module.

4. The LDO circuit with a switchable power supply terminal according to claim 3, characterized in that: The switch unit is provided with a protection unit, and the protection unit includes a Zener diode Z1. The negative electrode of the Zener diode Z1 is connected to the SYS terminal, and the positive electrode is connected to the gate of the low-voltage transistor MS2.

5. The LDO circuit with a switchable power supply terminal according to claim 3, characterized in that: In the output module, the voltage unit includes a high-voltage transistor MP1 and a low-voltage transistor MR1; The source of the MP1 is connected to the source of the MS2, the gate is connected to the drain of the MS2 and the transmission gate TG1, and the drain is connected to the drain of the MR1; The gate of the MR1 is connected to the control signal OFF_SYS, and the source is the output terminal REGN of the LDO.

6. The LDO circuit with a switchable power supply terminal according to claim 5, characterized in that: A diode is connected between the source and the drain of the high-voltage transistor MP1, the source is connected to the cathode of the diode, and the drain is connected to the anode of the diode; A diode is connected between the source and the drain of the low-voltage transistor MR1, the source is connected to the cathode of the diode, and the drain is connected to the anode of the diode.

7. The LDO circuit with a switchable power supply terminal according to claim 6, characterized in that: The MR1 is a PMOS.

8. The LDO circuit with a switchable power supply terminal according to claim 6, characterized in that: When power is required to be supplied from the output terminal SYS of the chip, OFF_SYS is at a low level and OFF_PMID is at a high level; When power is required to be supplied from the input terminal PMID of the chip, OFF_SYS is at a high level and OFF_PMID is at a low level.

9. An LDO circuit with a switchable power supply terminal according to claim 8, characterized in that: In the output module, that is, on the SYS side, when OFF_SYS is at a high level, the gate voltage of MS2 is the voltage division result of R1 and R2. By setting the resistance ratio of R1 and R2, MS2 is in a fully conducting state when SYS is at its lowest.

10. An LDO circuit with a switchable power supply terminal according to any one of claims 1-8, characterized in that: The output module and the input module have the same structure, and the corresponding units in the modules are composed of components of the same model.

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