Quick latch based on logic isolation

Abstract

The invention relates to a fast latch based on logic isolation. The fast latch comprises a transmission gate module which adopts a plurality of transmission gates controlled by clock signals to transmit input signals to corresponding generation nodes. The generation module is used for generating a feedback node signal by adopting a plurality of mutually connected phase inverters; the feedback module is used for receiving feedback node signals and feeding back each feedback node signal to a corresponding generation node by adopting a cross feedback loop, and in a normal working state, when a clock signal is at a high level, the fast latch works in a transparent mode; when the clock CLK is at a low level, enabling the fast latch to work in a holding mode; and when a single node or double nodes are overturned, the quick latch is self-repaired. According to the latch, logic isolation is realized through a cross feedback loop, and soft errors can be repaired and correct data can be stored even if a radiation event occurs; the fast latch can provide complete DNU elasticity, and has a faster speed and a smaller area.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to a fast latch based on logic isolation. Background Art

[0002] In the continuous development process of deep submicron complementary metal oxide semiconductor (CMOS) technology, the feature size of transistors has been continuously reduced. Although this trend has brought significant advantages in reducing chip cost, power consumption, and improving performance, it has also made digital circuits more sensitive to soft errors caused by radiation. In harsh radiation environments such as space, high-altitude aircraft, and some ground radiation environments, high-energy particles (including neutrons, α particles, protons, electrons, and heavy ions, etc.) bombard the sensitive areas of semiconductor devices, generating a large number of electron-hole pairs. Under the action of the electric field and concentration gradient, these electron-hole pairs drift and diffuse respectively, and are collected by the source or drain, thereby generating transient voltage pulses at the node, namely single event transient (SET). When the collected charge is too much and the pulse intensity exceeds the flip threshold, it will cause the stored data to flip, resulting in a soft error, that is, single event upset (SEU). Among them, single node upset (SNU) and double node upset (DNU) are common radiation-induced soft errors, which pose a serious threat to the stability of digital circuits. With the continuous progress of integrated circuit technology, the spacing between transistors, node capacitance, and power supply voltage have been continuously reduced, making the critical charge of the circuit smaller and smaller, and the proportion of single particle multiple node upsets (such as DNU or triple node upset TNU) caused by charge sharing effect larger and larger. In modern complex integrated circuits, any single particle flip in any module may cause the electronic device to execute errors or even system crashes. Therefore, a storage module that can tolerate single particle multi-point flips is very critical for constructing high-reliability large-scale integrated circuits.

[0003] Existing radiation-hardened latches have certain limitations in terms of cost and robustness. Although the traditional triple modular redundancy (TMR) design can achieve single-event upset (SEU) tolerance, the area and power consumption costs are extremely high. Other latches such as FERST, LEST, RFC, etc. have deficiencies in terms of delay, area, or sensitivity to the high-impedance state (HIS). For double-event upset (DEU) hardening designs, multi-mode redundancy requires a large number of redundant branches, increasing the design complexity and resource consumption. Moreover, some designs have high power consumption in the transparent operation mode or cannot completely solve the DEU problem caused by the charge sharing mechanism. In addition, some advanced latches mainly have the following problems: First, they cannot provide complete triple-node upset (TNU) tolerance because there is at least one counterexample: if three nodes are simultaneously hit by high-energy particles, the latch will output an incorrect value in the latched mode. Second, they cannot provide SET filtering. When a SET propagates from the upstream logic gate to the input of the latch, it can reach the output of the latch, that is, in the transparent mode, the latch cannot filter SET. Third, they cannot provide both complete TNU tolerance and SET filtering simultaneously. Summary of the Invention

[0004] Based on this, it is necessary to provide a fast latch based on logic isolation to address the above technical problems.

[0005] A fast latch based on logic isolation, the fast latch comprising: a transmission gate module, a generation module, and a feedback module.

[0006] The transmission gate module is configured to transmit an input signal to a corresponding generation node by using a plurality of transmission gates controlled by a clock signal.

[0007] The generation module is configured to connect the input ends of a plurality of inverters to each other in sequence, connect the connection point of every two inverters to the corresponding generation node, and each inverter generates a feedback node signal and transmits it to the input end of the feedback module; wherein the number of transmission gates is the same as the number of inverters. The feedback module is configured to receive the feedback node signal and feedback each feedback node signal to the corresponding generation node by using a cross-feedback loop composed of PMOS transistors and NMOS transistors; in the normal operating state, when the clock signal is at a high level, the fast latch operates in the transparent mode; when the clock CLK is at a low level, the fast latch operates in the hold mode; it is also configured to limit the influence of double-node perturbations and achieve fast self-recovery through a feedback mechanism when double-node perturbations occur; the feedback module adjusts the aspect ratio of the PMOS transistors and NMOS transistors to keep the output voltage within a set range and avoid error propagation.

[0008] In one embodiment, the transmission gate module includes six transmission gates; the input ends of all the transmission gates are used to receive an input signal, the control ends of all the transmission gates are connected to a clock signal, and the output end of each transmission gate is connected to a corresponding generation node.

[0009] In one embodiment, the generation module includes six inverters with the same structure; each inverter includes a pull-up branch and a pull-down branch connected to each other. The input end of the pull-up branch is the first input end, the input end of the pull-down branch is the second input end, and the connection point of the pull-up branch and the pull-down branch is the output end of the inverter.

[0010] The second input end of the first inverter is connected to the first input end of the second inverter and then connected to generation node A. The second input end of the second inverter is connected to the first input end of the third inverter and then connected to generation node B, and so on until the sixth inverter. The second input end of the sixth inverter is connected to the first input end of the first inverter and then connected to generation node Q.

[0011] The output ends of the six inverters are respectively connected to feedback nodes A1, B1, C1, D1, E1, and Q1.

[0012] In one embodiment, the pull-up branch of the inverter includes a PMOS transistor, and the pull-down branch includes an NMOS transistor.

[0013] In the first inverter: the source of the PMOS transistor is connected to voltage VDD, the gate of the PMOS transistor is connected to generation node A, and the drains of the PMOS transistor and the NMOS transistor are connected and then connected to feedback node A1; the source of the NMOS transistor is connected to ground GND, and the gate of the NMOS transistor is connected to generation node B.

[0014] In one embodiment, the feedback module includes: six FCE units with the same structure. Each FCE unit includes a first pull-up branch and a first pull-down branch based on two input ends. The two input ends of the first pull-up branch are respectively the first input end and the second input end of the FCE unit, and the two input ends of the first pull-down branch are respectively the third input end and the fourth input end of the FCE unit; the connection point of the first pull-up branch and the first pull-down branch is the output end of the FCE unit. The four input terminals of the first FCE unit are respectively connected to the feedback nodes B1, C1, D1, and E1. The four input terminals of the second FCE unit are respectively connected to the feedback nodes C1, D1, E1, and Q1. The four input terminals of the third FCE unit are respectively connected to the feedback nodes D1, E1, Q1, and A1. The four input terminals of the fourth FCE unit are respectively connected to the feedback nodes E1, Q1, A1, and B1. The four input terminals of the fifth FCE unit are respectively connected to the feedback nodes Q1, A1, B1, and C1. The four input terminals of the sixth FCE unit are respectively connected to the feedback nodes A1, B1, C1, and D1. The output terminals of the six FCE units are respectively connected to the generation nodes A, B, C, D, E, and Q.

[0015] In one embodiment, the FCE unit includes: a first pull-up branch and a first pull-down branch. The first pull-up branch includes: a second PMOS transistor and a third PMOS transistor. The first pull-down branch includes: a second NMOS transistor and a third NMOS transistor.

[0016] In the first FCE unit: the gates of the second PMOS transistor and the third PMOS transistor of the first pull-up branch are respectively connected to the feedback nodes B1 and C1. The source of the second PMOS transistor is connected to the voltage VDD. The drain of the second PMOS transistor is connected to the drain of the third PMOS transistor. The source of the third PMOS transistor is connected to the source of the second NMOS transistor and then connected to the generation node A. The gates of the second NMOS transistor and the third NMOS transistor are respectively connected to the feedback nodes connected to the nodes D1 and E1. The drain of the second NMOS transistor is connected to the drain of the third NMOS transistor. The source of the third NMOS transistor is connected to GND.

[0017] The above-mentioned fast latch based on logic isolation, the fast latch includes: a transmission gate module, a generation module, and a feedback module. The transmission gate module is used to transmit the input signal to the corresponding generation node by a plurality of transmission gates controlled by a clock signal. The generation module is used to generate feedback node signals by a plurality of interconnected inverters. The feedback module is used to receive the feedback node signals and feedback each feedback node signal to the corresponding generation node by a cross-feedback loop. In the normal operating state, when the clock signal is high, the fast latch operates in the transparent mode; when the clock CLK is low, the fast latch operates in the hold mode; in the presence of single-node flip or double-node flip, the fast latch self-repairs. The latch realizes logic isolation through a cross-feedback loop, can repair soft errors and save correct data even when a radiation event occurs; the fast latch can provide complete DNU resilience, has a faster speed, less area, and the minimum PDAP. Description of the Drawings

[0018] Figure 1Composition block diagram of a fast latch based on logical isolation in an embodiment; Figure 2 Schematic diagram of the principle of the generation module in an embodiment; Figure 3 Schematic diagram of the principle of the feedback module in an embodiment; Figure 4 Single - event upset fault injection waveform diagram of a fast latch based on logical isolation in another embodiment; Figure 5 Double - event upset fault injection waveform diagram of a fast latch based on logical isolation in another embodiment. Detailed implementation manners

[0019] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0020] In one embodiment, as Figure 1 shown, a fast latch based on logical isolation is provided. The fast latch includes: a transmission gate module 10, a generation module 20, and a feedback module 30.

[0021] The transmission gate module 10 is used to transmit an input signal to a corresponding generation node by a plurality of transmission gates controlled by a clock signal.

[0022] Specifically, the transmission gate module 10 (Transport Gate module) is composed of transmission gates TG1 - TG6 controlled by a clock signal CLK, and the input signal is D_IN. The transmission gates are respectively connected to nodes A, B, C, D, E, Q. The clock signal CLK generates NCK through an inverter to jointly control the conduction / cut - off of the transmission gates, so as to realize the transmission of the input signal D_IN to each node.

[0023] The generation module 20 is used to connect the input ends of a plurality of inverters to each other in sequence, connect the connection point of every two inverters to a corresponding generation node, and each inverter generates a feedback node signal and transmits it to the input end of the feedback module 30; where the number of transmission gates is the same as the number of inverters.

[0024] Specifically, the generator module 20 includes logic gate circuits, such as inverters G-INV6, G-INV1, etc. (inverters G-INV), as well as inverter G-2AND (two-input AND gate) and inverter G-3AND (three-input AND gate). Nodes A, B, C, D, E, Q, etc. are interconnected. For example, the input of inverter G-INV6 is E1 and the output is Q; the input of inverter G-INV1 is A and the output is connected to other logic gates to jointly implement the signal generation and processing functions.

[0025] The feedback module 30 is used to receive the feedback node signals and feedback each feedback node signal to the corresponding generation node through a cross-feedback loop composed of PMOS and NMOS transistors; in the normal working state, when the clock signal is high, the fast latch operates in the transparent mode; when the clock CLK is low, the fast latch operates in the hold mode; it is also used to limit the impact of double-node disturbances and achieve fast self-recovery through a feedback mechanism when double-node disturbances occur; the feedback module adjusts the aspect ratios of the PMOS and NMOS transistors to keep the output voltage within a set range and avoid error propagation.

[0026] It can quickly detect and recover errors, improve the robustness and reliability of the latch, while reducing the area overhead and delay. In a variety of DNU scenarios, the feedback module performs excellently, ensuring the stable operation of the latch in a radiation environment.

[0027] Specifically, the feedback module 30 (Feedback module): includes FCE units 1, 2, 3, 4, 5, and 6. The units are interconnected through nodes B1, C1, D1, E1, Q1, etc. For example, the input of FCE unit 1 is the signal of generation node A, and the output is connected to nodes B1, C1, etc. of FCE unit 2; the input of FCE unit 3 is the signal of generation node C, and the output interacts with other FCE units, and finally outputs Q through FCE unit 6 to form a feedback logic link to achieve signal feedback processing.

[0028] In the normal working state: When the clock signal CLK is high, transmission gates TG1 - TG6 are all turned on, and the input signal D_IN charges generation nodes A, B, C, D, E, Q, and generation nodes A, B, C, D, E, Q generate feedback node signals A1, B1, C1, D1, E1, Q1 through the generator module. At this time, the fast latch operates in the transparent mode. The direct path from D_IN to Q can reduce the propagation delay.

[0029] In the hold mode, the clock signal CLK is at a low level, and the transmission gates TG1 - TG6 are all closed. The input signal D_IN has no impact on the internal nodes. The internal nodes are mutually feedback, thus maintaining the correct logic. The inverter G - INV generates the voltage of the feedback node, and the FCE unit maintains the generated node voltage. Therefore, the feedback loop of the fast latch can keep the voltages of all internal nodes at the correct logic. Next, the self - recovery principle of the proposed DNUSH latch for SNU / SEDNU in the hold mode is discussed. The latch is symmetrically designed, so any two generated nodes or any two feedback nodes have the same properties.

[0030] In the above - mentioned fast latch based on logic isolation, the fast latch includes: a transmission - gate module, a generation module, and a feedback module. The transmission - gate module is used to transmit the input signal to the corresponding generated node by a plurality of transmission gates controlled by the clock signal. The generation module is used to generate the feedback - node signal by a plurality of interconnected inverters; the feedback module is used to receive the feedback - node signal and feedback each feedback - node signal to the corresponding generated node by a cross - feedback loop. In the normal operating state, when the clock signal is at a high level, the fast latch operates in the transparent mode; when the clock CLK is at a low level, the fast latch operates in the hold mode; in the presence of single - node flip or double - node flip, the fast latch self - repairs. This latch realizes logic isolation through a cross - feedback loop, can repair soft errors and save correct data even when a radiation event occurs; this fast latch can provide complete DNU resilience, has a faster speed, less area, and the minimum PDAP.

[0031] In one embodiment, the transmission - gate module includes 6 transmission gates; the input ends of all transmission gates are used to receive the input signal, the control ends of all transmission gates are connected to the clock signal, and the output end of each transmission gate is connected to a corresponding generated node.

[0032] In one embodiment, as Figure 2 shown, the generation module includes 6 inverters with the same structure; each inverter includes a pull - up branch and a pull - down branch connected to each other. The input end of the pull - up branch is the first input end, the input end of the pull - down branch is the second input end, and the connection point of the pull - up branch and the pull - down branch is the output end of the inverter.

[0033] The second input end of the first inverter is connected to the first input end of the second inverter and then connected to the generated node A. The second input end of the second inverter is connected to the first input end of the third inverter and then connected to the generated node B, and so on until the sixth inverter. The second input end of the sixth inverter is connected to the first input end of the first inverter and then connected to the generated node Q.

[0034] The output terminals of six inverters are respectively connected to the feedback nodes A1, B1, C1, D1, E1, and Q1.

[0035] In one embodiment, the pull-up branch of the inverter includes a PMOS transistor, and the pull-down branch includes an NMOS transistor.

[0036] In the first inverter: the source of the PMOS transistor is connected to the voltage VDD, the gate of the PMOS transistor is connected to the generating node A, the drain of the PMOS transistor and the drain of the NMOS transistor are connected and then connected to the feedback node A1; the source of the NMOS transistor is connected to the ground GND, and the gate of the NMOS transistor is connected to the generating node B.

[0037] In a specific embodiment, the generating module includes 6 inverters G-INV, and each inverter G-INV includes a pull-up branch and a pull-down branch. Among them, the pull-up branch includes a PMOS transistor, and the pull-down branch includes an NMOS transistor. The gate of the PMOS transistor in the pull-up branch is the first input terminal of the inverter, the gate of the NMOS transistor in the pull-down branch is the second input terminal of the inverter, and the connection point of the drain of the PMOS transistor in the pull-up branch and the drain of the NMOS transistor in the pull-down branch is the output terminal of the inverter.

[0038] Inverter G-INV1 includes PMOS transistor P1 and NMOS transistor N1; inverter G-INV2 includes PMOS transistor P2 and NMOS transistor N2; inverter G-INV3 includes PMOS transistor P3 and NMOS transistor N3; inverter G-INV4 includes PMOS transistor P4 and NMOS transistor N4; inverter G-INV5 includes PMOS transistor P5 and NMOS transistor N5; inverter G-INV6 includes PMOS transistor P6 and NMOS transistor N6.

[0039] The source of PMOS transistor P1 is connected to VDD, the gate of PMOS transistor P1 is connected to generation node A, and the drain of PMOS transistor P1 is connected to feedback node A1; the source of PMOS transistor P2 is connected to VDD, the gate of PMOS transistor P2 is connected to generation node B, and the drain of PMOS transistor P2 is connected to feedback node B1; the source of PMOS transistor P3 is connected to VDD, the gate of PMOS transistor P3 is connected to generation node C, and the drain of PMOS transistor P3 is connected to feedback node C1; the source of PMOS transistor P4 is connected to VDD, the gate of PMOS transistor P4 is connected to generation node D, and the drain of PMOS transistor P4 is connected to feedback node D1; the source of PMOS transistor P5 is connected to VDD, the gate of PMOS transistor P5 is connected to generation node E, and the drain of PMOS transistor P5 is connected to node feedback E1; the source of PMOS transistor P6 is connected to VDD, the gate of PMOS transistor P6 is connected to generation node F, and the drain of PMOS transistor P6 is connected to feedback node Q1; the source of NMOS transistor N1 is connected to ground GND, the gate of NMOS transistor N1 is connected to generation node B, and the drain of NMOS transistor N1 is connected to feedback node A1; the source of NMOS transistor N2 is connected to ground GND, the gate of NMOS transistor N2 is connected to generation node C, and the drain of NMOS transistor N2 is connected to feedback node B1; the source of NMOS transistor N3 is connected to ground GND, the gate of NMOS transistor N3 is connected to generation node D, and the drain of NMOS transistor N3 is connected to feedback node C1; the source of NMOS transistor N4 is connected to ground GND, the gate of NMOS transistor N4 is connected to generation node E, and the drain of NMOS transistor N4 is connected to feedback node D1; the source of NMOS transistor N5 is connected to ground GND, the gate of NMOS transistor N5 is connected to generation node Q, and the drain of NMOS transistor N5 is connected to feedback node E1; the source of NMOS transistor N6 is connected to ground GND, the gate of NMOS transistor N5 is connected to generation node A, and the drain is connected to feedback node Q1.

[0040] In one embodiment, as Figure 3 shown, the feedback module includes: 6 FCE units with the same structure, and each FCE unit includes a first pull-up branch and a first pull-down branch based on two input terminals; the two input terminals of the first pull-up branch are respectively the first input terminal and the second input terminal of the FCE unit, and the two input terminals of the first pull-down branch are respectively the third input terminal and the fourth input terminal of the FCE unit; the connection point of the first pull-up branch and the first pull-down branch is the output terminal of the FCE unit. The four input terminals of the first FCE unit are respectively connected to feedback nodes B1, C1, D1, and E1. The four input terminals of the second FCE unit are respectively connected to feedback nodes C1, D1, E1, and Q1. The four input terminals of the third FCE unit are respectively connected to feedback nodes D1, E1, Q1, and A1. The four input terminals of the fourth FCE unit are respectively connected to feedback nodes E1, Q1, A1, and B1. The four input terminals of the fifth FCE unit are respectively connected to feedback nodes Q1, A1, B1, and C1. The four input terminals of the sixth FCE unit are respectively connected to feedback nodes A1, B1, C1, and D1. The output terminals of the six FCE units are respectively connected to generation nodes A, B, C, D, E, and Q.

[0041] In one embodiment, the FCE unit includes: a first pull-up branch and a first pull-down branch. The first pull-up branch includes: PMOS transistor P7 and PMOS transistor P13. The first pull-down branch includes: NMOS transistor N7 and NMOS transistor N13.

[0042] In the first FCE unit: The gates of PMOS transistor P7 and PMOS transistor P13 in the first pull-up branch are respectively connected to feedback nodes B1 and C1. The source of PMOS transistor P7 is connected to voltage VDD. The drain of PMOS transistor P7 is connected to the drain of PMOS transistor P13. The source of PMOS transistor P13 is connected to the source of NMOS transistor N7 and then connected to generation node A. The gates of NMOS transistor N7 and NMOS transistor N13 are respectively connected to the feedback nodes connected to nodes D1 and E1. The drain of NMOS transistor N7 is connected to the drain of NMOS transistor N13. The source of NMOS transistor N13 is connected to GND.

[0043] In a specific embodiment, the feedback module includes: 6 FCE units with the same structure. Each FCE unit includes two PMOS transistors and two NMOS transistors. FCE unit 1 includes PMOS transistor P7, PMOS transistor P13, NMOS transistor N7, and NMOS transistor N13. Among them, PMOS transistor P7 and PMOS transistor P13 constitute the first pull-up branch of FCE unit 1. The gates of PMOS transistor P7 and PMOS transistor P13 are respectively the first input terminal and the second input terminal of FCE unit 1, and are respectively connected to feedback nodes B1 and C1. NMOS transistor N7 and NMOS transistor N13 constitute the first pull-down branch of FCE unit 1. The gates of NMOS transistor N7 and NMOS transistor N13 are respectively the third input terminal and the fourth input terminal of FCE unit 1, and are respectively connected to feedback nodes D1 and E1. The source of PMOS transistor P13 is connected to the source of NMOS transistor N7 and then used as the output terminal of FCE unit 1, and the output terminal of FCE unit 1 is connected to generation node A. The composition and connection method of FCE units 2 to 6 are the same as those of FCE unit 1.

[0044] such as Figure 3As shown, the gate of PMOS transistor P7 is connected to feedback node B1, the source of PMOS transistor P7 is connected to VDD, and the drain of PMOS transistor P7 is connected to the source of PMOS transistor P13. The gate of PMOS transistor P8 is connected to feedback node C1, the source of PMOS transistor P8 is connected to VDD, and the drain of PMOS transistor P8 is connected to the source of PMOS transistor P14. The gate of PMOS transistor P9 is connected to feedback node D1, the source of PMOS transistor P9 is connected to VDD. The drain of PMOS transistor P9 is connected to the source of PMOS transistor P15. The gate of PMOS transistor P10 is connected to feedback node E1, the source of PMOS transistor P10 is connected to VDD, and the drain of PMOS transistor P10 is connected to the source of PMOS transistor P16. The gate of PMOS transistor P11 is connected to feedback node Q1, the source of PMOS transistor P11 is connected to VDD, and the drain of PMOS transistor P11 is connected to the source of PMOS transistor P17. The gate of PMOS transistor P12 is connected to feedback node A1, the source of PMOS transistor P12 is connected to VDD, and the drain of PMOS transistor P12 is connected to the source of PMOS transistor P18. The 18 MOS transistors in the second part (lower half): The gate of PMOS transistor P13 is connected to feedback node C1, the source of PMOS transistor P13 is connected to the drain of P7, and the drain of PMOS transistor P13 is connected to generation node A. The gate of PMOS transistor P14 is connected to feedback node D1, the source of PMOS transistor P14 is connected to the drain of PMOS transistor P8, and the drain of PMOS transistor P14 is connected to generation node B. The gate of PMOS transistor P15 is connected to feedback node E1, the source of PMOS transistor P15 is connected to the drain of P9, and the drain of PMOS transistor P15 is connected to node C. The gate of PMOS transistor P16 is connected to feedback node Q1, the source of PMOS transistor P16 is connected to the drain of PMOS transistor P10, and the drain of PMOS transistor P16 is connected to generation node D. The gate of PMOS transistor P17 is connected to feedback node A1, the source of PMOS transistor P17 is connected to the drain of PMOS transistor P11, and the drain of PMOS transistor P17 is connected to node E.The gate of PMOS transistor P18 is connected to feedback node B1, the source of PMOS transistor P18 is connected to the drain of P12, and the drain of PMOS transistor P18 is connected to generation node F. The gate of NMOS transistor N7 is connected to feedback node D1, the source of NMOS transistor N7 is connected to the drain of NMOS transistor N13, and the drain of NMOS transistor N7 is connected to generation node A. The gate of NMOS transistor N8 is connected to feedback node E1, the source of NMOS transistor N8 is connected to the drain of NMOS transistor N14, and the drain of NMOS transistor N8 is connected to generation node B. The gate of NMOS transistor N9 is connected to feedback node Q1, the source of NMOS transistor N9 is connected to the drain of NMOS transistor N15, and the drain of NMOS transistor N9 is connected to generation node C. The gate of NMOS transistor N10 is connected to feedback node A1, the source of NMOS transistor N10 is connected to the drain of NMOS transistor N16, and the drain of NMOS transistor N10 is connected to node D. The gate of NMOS transistor N11 is connected to feedback node B1, the source of NMOS transistor N11 is connected to the drain of NMOS transistor N17, and the drain of NMOS transistor N11 is connected to generation node E. The gate of NMOS transistor N12 is connected to feedback node C1, the source of NMOS transistor N12 is connected to the drain of NMOS transistor N18, and the drain of NMOS transistor N12 is connected to generation node Q. The gate of NMOS transistor N13 is connected to feedback node E1, the source of NMOS transistor N13 is connected to ground (GND), and the drain is connected to the source of NMOS transistor N7. The gate of NMOS transistor N14 is connected to feedback node Q1. The source is connected to ground (GND), and the drain of NMOS transistor N13 is connected to the source of NMOS transistor N8. The gate of NMOS transistor N15 is connected to feedback node A1, the source of NMOS transistor N15 is connected to ground (GND), and the drain of NMOS transistor N15 is connected to the source of NMOS transistor N9. The gate of NMOS transistor N16 is connected to feedback node B1, the source of NMOS transistor N16 is connected to ground (GND), and the drain of NMOS transistor N16 is connected to the source of NMOS transistor N10.The gate of NMOS transistor N17 is connected to feedback node C1, the source of NMOS transistor N17 is connected to ground (GND), and the drain of NMOS transistor N17 is connected to the source of NMOS transistor N11. The gate of NMOS transistor N18 is connected to feedback node D1, the source of NMOS transistor N18 is connected to ground (GND), and the drain of NMOS transistor N18 is connected to the source of NMOS transistor N12.

[0045] Analyze the DNU self-repair ability of the latch proposed in this application based on logic isolation from the single-node flip (SNU) and double-node flip (DNU) situations of the latch.

[0046] (1) Anti-single-node flip First, discuss the situation of single-node flip. Due to the symmetry of the latch structure and the charge collection characteristics of the stacked NMOS structure, the number of node discussion situations is greatly reduced. Therefore, representative nodes will be selected below.

[0047] There are only 2 situations for SNU, namely the generation node flips and the feedback node flips: SN1: The feedback node (A1, B1, C1, D1, E1 or Q1) flips. Since both the pull-up branch and the pull-down branch of the FCE cell have two inputs, the flip of a single feedback node (such as feedback node A1) will only keep the FCE cell in HIS. Then, the faulty feedback node is repaired by the inverter G-INV.

[0048] SN2: The generation node (A, B, C, D, E or Q) flips. Each generation node (such as generation node A) serves as an input to the pull-up branch of one inverter G-INV (such as inverter G-INV1) and an input to the pull-down branch of another inverter G-INV (such as inverter G-INV6). Therefore, the flip of a single generation node only affects the output of one inverter G-INV. For example, when generation node A fluctuates from 0 V to 1.2 V, inverter G-INV1 remains in HIS (high-impedance state), and both the pull-up branch and the pull-down branch of inverter G-INV6 are conducting, causing the feedback node Q1 to be disturbed. As described in SN1, the disturbance of a single feedback node does not cause the output of the FCE cell to be disturbed. There is no direct path between FCE cell 1 and generation node A, so the disturbance of generation node A does not affect FCE cell 1. Therefore, generation node A is repaired, and feedback node Q1 is repaired through inverter G-INV6. That is, the flip of a single feedback node does not cause incorrect logic propagation. The above discussion shows that the latch can self-repair from all SNUs.

[0049] Figure 4Waveform diagram of single - event upset fault injection for a fast latch based on logic isolation.

[0050] (2)Case of double - event upset Due to the symmetric characteristics of the fast latch based on logic isolation, there are a total of 13 combinations for DNU: For the generating nodes A, B, C, D, E, Q, according to their relative positions, there are 5 combinations. If the generating node A is selected as a reference, there are the following 5 different combinations: {A, B}, {A, C}, {A, D}, {A, E}, {A, Q}. Similarly, there are 6 combinations of generating nodes and feedback nodes. If the generating node A is selected as a reference: {A, A1}, {A, B1}, {A, C1}, {A, D1}, {A, E1}, {A, Q1}. There are only 2 combinations for the feedback nodes, namely adjacent feedback nodes and non - adjacent feedback nodes. This is because the flipping of two non - adjacent feedback nodes does not affect the operation of the FCE unit. Therefore, the two combinations of the feedback nodes are selected as {A1, B1} and {A1, D1}. Since the inverting amplifier G - INV and the pull - up and pull - down branches of the FCE unit have opposite sensitivities to the input perturbation, each of the following DNU examples is analyzed in two sub - cases where the input signal D_IN is logic 1 and logic 0.

[0051] (a)DN1: {A, B} is perturbed.

[0052] 1) The generating nodes A and B flip from logic 1 to logic 0. The output of the inverting amplifier G - INV1 (i.e., the feedback node A1) flips from logic 0 to logic 1. Both the pull - up and pull - down branches of the inverting amplifier G - INV2 are turned on, and the feedback node B1 flips from logic 0 to 0.7 V. The pull - down branch of the FCE unit 4 is turned on, and the output of the FCE unit 4 (i.e., the generating node D) fluctuates to 1.0 V, which can be regarded as still maintaining the original logic; the pull - up branch of the FCE unit 6 is turned off, making the FCE unit 6 in a high - impedance state, and the output of the FCE unit 6 (i.e., the generating node Q) remains unchanged and is not affected by the feedback node A1 and the feedback node B1. The generating node A is restored by the FCE unit 1, the generating node B is restored by the FCE unit 2, and then the feedback node A1 is restored through the inverting amplifier G - INV1, and the inverting amplifier G - INV2 repairs the feedback node B1.

[0053] 2) A and B flip from logic 0 to logic 1. The feedback node A1 flips, and the output of the inverting amplifier G - INV6 (i.e., the feedback node Q1) flips to 0.2 V. The output of the FCE unit 5 (i.e., the generating node E) fluctuates to 0.2 V. The restoration of the generating nodes A and B is the same as in the case of DN1 1), and the restoration that appeared in 1) will not be repeated in 2). The feedback node Q1 is restored by the inverting amplifier G - INV6.

[0054] (b)DN2: {A, C} is perturbed.

[0055] 1) The generated nodes A and C flip from logic 1 to logic 0. The feedback nodes A1 and C1 flip to 0.7 V. The feedback nodes A1 and C1 are not adjacent in sequence and do not jointly serve as the input of the pull-up branch or the pull-down branch in the circuit, so they have no impact on the FCE unit. The generated node A is restored by the FCE unit 1, and the generated node C is restored by the FCE unit 3. The feedback node A1 is restored by the inverter G-INV1, and the feedback node C1 is restored by the inverter G-INV3.

[0056] 2) The generated nodes A and C flip from logic 0 to logic 1. The feedback nodes B1 and Q1 flip from 0 V to 0.2 V. The feedback nodes B1 and Q1 are not adjacent in sequence and have no impact on the FCE unit. The feedback node B1 is restored by the inverter G-INV2, and the feedback node Q1 is restored by the inverter G-INV6.

[0057] (c)DN3: {A, D} is perturbed.

[0058] 1) The generated nodes A and D flip to logic 0. It means that the generated node A will flip to logic 0 only when the input D_IN is 1, which will not be elaborated later. A1 and D1 flip from 0 V to 0.7 V. A1 and D1 are not adjacent in sequence and have no impact on the FCE unit. The generated node A is restored by the FCE unit 1, and the generated node D is restored by the FCE unit 4. The feedback node A1 is restored by the inverter G-INV1, and the feedback node D1 is restored by the inverter G-INV4.

[0059] 2) The generated nodes A and D flip to logic 1. It means that the generated node A will flip to logic 1 only when the input D_IN is 0. C1 and Q1 flip from 0 V to 0.2 V. The feedback nodes C1 and Q1 are not adjacent in sequence and have no impact on the FCE unit. The feedback node C1 is restored by the inverter G-INV3, and the feedback node Q1 is restored by the inverter G-INV6.

[0060] (d)DN4: {A, E} is perturbed.

[0061] 1) The generated nodes A and E flip to logic 0. The feedback nodes A1 and E1 flip from 0 V to 0.7 V. A1 and E1 are not adjacent in sequence and have no impact on the FCE unit. The generated node A is restored by the FCE unit 1, and the generated node E is restored by the FCE unit 5. The feedback node A1 is restored by the inverter G-INV1, and the feedback node E1 is restored by the inverter G-INV5.

[0062] 2) The generating nodes A and E are flipped to logic 1. The feedback nodes D1 and Q1 are flipped from 0 V to 0.2 V. The feedback nodes D1 and Q1 are not adjacent in sequence and have no impact on the FCE unit. The feedback node D1 is restored by the inverter G-INV4, and the feedback node Q1 is restored by the inverter G-INV6.

[0063] (e) DN5: {A, Q} is perturbed. This situation is the same as DN1.

[0064] 1) The generating nodes A and Q are flipped to logic 0. The feedback node Q1 is flipped, and the output of the inverter G-INV1 (i.e., the feedback node A1) is flipped to 0.7 V. The feedback nodes A1 and Q1 turn on both the pull-up branch and the pull-down branch of the FCE unit 3, causing the generating node C to fluctuate from 1.2 V to 1.0 V. The generating node C can be regarded as still maintaining the original logic. The generating node A is restored by the FCE unit 1, the generating node Q is restored by the FCE unit 6. The feedback node A1 is restored by the inverter G-INV1, and the feedback node Q1 is restored by the inverter G-INV6.

[0065] 2) The generating nodes A and Q are flipped to logic 1. The feedback node Q1 is flipped, and the output of the inverter G-INV5 (i.e., the feedback node E1) is flipped to 0.2 V. The feedback nodes E1 and Q1 cause the output of the FCE unit 4 (i.e., the generating node D) to fluctuate from 0 V to 0.2 V. The generating node D can be regarded as still maintaining the original logic. The feedback node E1 is restored by the inverter G-INV5, and the feedback node Q1 is restored by the inverter G-INV6.

[0066] DN6: {A, A1} is perturbed. Since the perturbation of {A, B} will cause a logic error in A1, the self-recovery of the DN1 example means that the DN6 example can be self-recovered.

[0067] (f) DN7: {A, B1} is perturbed.

[0068] 1) The generating node A is flipped to logic 0, and the feedback node B1 is flipped to logic 1. It means that the feedback node will be flipped to logic 1 only when the input D_IN is 1, which will not be elaborated later. The output A1 of the inverter G-INV1 is flipped to 0.7 V. The perturbations of the feedback nodes A1 and B1 cause the output of the FCE unit 4 (i.e., the generating node D) to fluctuate to 1.0 V. The generating node D can be regarded as still maintaining the original logic. The generating node A is restored by the FCE unit 1, the feedback node A1 is restored by the inverter G-INV1, and B1 is restored by the inverter G-INV2.

[0069] 2) The generating node A flips to logic 1, and the feedback node B1 flips to logic 0. The output Q1 of the inverter G-INV6 flips to 0.2 V. The feedback nodes Q1 and B1 are not adjacent in sequence and do not affect the FCE unit. The feedback node Q1 is restored by the inverter G-INV6.

[0070] (g)DN8: {A, C1} is disturbed.

[0071] 1) The generating node A flips to logic 0, and the feedback node C1 flips to logic 1. The output A1 of the inverter G-INV1 flips to 0.7 V. The feedback nodes A1 and C1 are not adjacent in sequence and do not affect the FCE unit. The generating node A is restored by the FCE unit 1, the feedback node A1 is restored by the inverter G-INV1, and the feedback node C1 is restored by the inverter G-INV3.

[0072] 2) The generating node A flips to logic 1, and the feedback node C1 flips to logic 0. The output (i.e., the feedback node Q1) of the inverter G-INV6 flips to 0.2 V. The feedback nodes Q1 and C1 are not adjacent in sequence and do not affect the FCE unit. The feedback node Q1 is restored by the inverter G-INV6.

[0073] (h)DN9: {A, D1} is disturbed.

[0074] 1) It flips to logic 0, and the feedback node D1 flips to logic 1. The output A1 of the inverter G-INV1 flips to 0.7 V. The feedback nodes A1 and D1 are not adjacent in sequence and do not affect the FCE unit. The generating node A is restored by the FCE unit 1, the feedback node A1 is restored by the inverter G-INV1, and the feedback node D1 is restored by the inverter G-INV4.

[0075] 2) The generating node A flips to logic 1, and the feedback node D1 flips to logic 0. The output (i.e., the feedback node Q1) of the inverter G-INV6 flips to 0.2 V. The feedback nodes Q1 and D1 are not adjacent in sequence and do not affect the FCE unit. The feedback node Q1 is restored by the inverter G-INV6.

[0076] (i)DN10: {A, E1} is disturbed.

[0077] 1) The generating node A flips to logic 0, and E1 flips to logic 1. The output (i.e., the feedback node A1) of the inverter G-INV1 flips to 0.7 V. The feedback nodes A1 and E1 are not adjacent in sequence and do not affect the FCE unit. The generating node A is restored by the FCE unit 1, the feedback node A1 is restored by the inverter G-INV1, and the feedback node E1 is restored by the inverter G-INV5.

[0078] 2) The generating node A flips to logic 1, and the feedback node E1 flips to logic 0. The output Q1 of the inverter G-INV6 flips to 0.2 V. The perturbations of the feedback nodes E1 and Q1 cause the output of the FCE cell 4 (i.e., the generating node D) to fluctuate to 0.2 V, and the generating node D can be regarded as still maintaining the original logic. The feedback node Q1 is restored by the inverter G-INV6.

[0079] (j)DN11: {A, Q1} is perturbed.

[0080] 1) The generating node A flips to logic 0, and the feedback node Q1 flips to logic 1. The output of the inverter G-INV1 (i.e., the feedback node A1) flips to 0.7 V. The perturbations of the feedback nodes A1 and Q1 cause the output of the FCE cell 3 (i.e., the generating node C) to fluctuate to 1.0 V, and the generating node C can be regarded as still maintaining the original logic. The generating node A is restored by the FCE cell 1, the feedback node A1 is restored by the inverter G-INV1, and the feedback node Q1 is restored by the inverter G-INV6.

[0081] 2) The generating node A flips to logic 1, and the feedback node Q1 flips to logic 0. Since only the feedback node Q1 flips among the feedback nodes, it can be seen from the example of SN2 that the perturbation of the feedback node Q1 does not affect each module of the FCE cell. The feedback node Q1 is restored by the inverter G-INV6.

[0082] (k)DN12: {A1, B1} is perturbed.

[0083] 1) A1 and B1 flip to logic 1. The perturbations of A1 and B1 cause the output of the FCE cell 4 (i.e., the generating node D) to fluctuate to 0.2 V. The perturbation of the generating node D causes the output of the inverter G-INV4 (i.e., the feedback node D1) to fluctuate to 0.2 V, which can be regarded as still maintaining the original logic. The feedback node A1 is restored by the inverter G-INV1, the feedback node B1 is restored by the inverter G-INV2, and the generating node D is restored by the FCE cell 4.

[0084] 2) The feedback nodes A1 and B1 flip to logic 0. The perturbations of the feedback nodes A1 and B1 cause the output of the FCE cell 4 (i.e., the generating node Q) to fluctuate to 0.7 V. The perturbation of the generating node Q causes the output of the inverter G-INV5 (i.e., the feedback node E1) to fluctuate to 1.1 V, which can be regarded as still maintaining the original logic. The generating node Q is restored by the FCE cell 5.

[0085] (l)DN13: {A1, D1} is perturbed. A1 and D1 are not adjacent in sequence and do not jointly serve as the inputs of the pull-up branch or the pull-down branch in the circuit, so they do not affect the FCE cell.

[0086] Figure 5Waveform diagram of double - node flip - flop fault injection for a fast latch based on logical isolation.

[0087] Due to the high symmetry of the fast latch proposed in this application, the remaining node pairs can all be represented by the above 13 examples by moving the positions of the inverter G - INVs and FCE units. The above discussion shows that the fast latch proposed in this application can self - repair from all possible DNU.

[0088] The technical features of the above - mentioned embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above - mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0089] The above - described embodiments only represent several implementation manners of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this application. It should be noted that for those of ordinary skill in the art, without departing from the concept of this application, several deformations and improvements can still be made, and these all belong to the protection scope of this application. Therefore, the protection scope of this application should be subject to the appended claims.

Claims

1. A fast latch based on logic isolation, characterized in that: The fast latch comprises: a transmission gate module, a generation module and a feedback module; The transmission gate module is used to transmit the input signal to the corresponding generation node using a plurality of transmission gates controlled by a clock signal; The generating module is used to sequentially connect the input ends of several inverters to each other, connect the connection point of every two inverters to the corresponding generating node, each inverter generates a corresponding feedback node signal, and transmits the feedback node signal to the input end of the feedback module; wherein the number of the transmission gates is the same as the number of the inverters, The feedback module is used to receive the feedback node signal and use a cross feedback loop composed of a PMOS tube and an NMOS tube to feed back each feedback node signal to the corresponding generation node; under normal working conditions, when the clock signal is at a high level, the fast latch works in a transparent mode; when the clock CLK is at a low level, the fast latch works in a holding mode; it is also used to limit the impact of the dual-node disturbance through a feedback mechanism and achieve rapid self-recovery when a dual-node disturbance occurs; the feedback module adjusts the width-to-length ratio of the PMOS tube and the NMOS tube to keep the output voltage within a set range to avoid error propagation.

2. The fast latch based on logic isolation according to claim 1, characterized in that: The transmission gate module includes 6 transmission gates; The input ends of all transmission gates are used to receive input signals, the control ends of all transmission gates are connected to the clock signal, and the output end of each transmission gate is connected to a corresponding generation node.

3. The fast latch based on logic isolation according to claim 1, characterized in that: The generating module includes 6 inverters of the same structure; each inverter includes a pull-up branch and a pull-down branch connected to each other, the input end of the pull-up branch is the first input end, the input end of the pull-down branch is the second input end, and the connection point between the pull-up branch and the pull-down branch is the output end of the inverter; The second input terminal of the first inverter is connected to the first input terminal of the second inverter and then connected to the generation node A. The second input terminal of the second inverter is connected to the first input terminal of the third inverter and then connected to the generation node B. This process is analogous to the sixth inverter. The second input terminal of the sixth inverter is connected to the first input terminal of the first inverter and then connected to the generation node Q. The output ends of the six inverters are connected to the feedback nodes A1, B1, C1, D1, E1, and Q1 respectively.

4. The fast latch based on logic isolation according to claim 3, characterized in that: The pull-up branch of the inverter includes a PMOS tube, and the pull-down branch includes an NMOS tube; In the first inverter: the source of the PMOS tube is connected to the voltage VDD, the gate of the PMOS tube is connected to the generation node A, the drain of the PMOS tube is connected to the drain of the NMOS tube and then connected to the feedback node A1; the source of the NMOS tube is connected to the ground GND, and the gate of the NMOS tube is connected to the generation node B.

5. The fast latch based on logic isolation according to claim 1, characterized in that: The feedback module comprises: 6 FCE units of the same structure, each FCE unit comprises a first pull-up branch and a first pull-down branch based on two input terminals; the two input terminals of the first pull-up branch are respectively the first input terminal and the second input terminal of the FCE unit, the two input terminals of the first pull-down branch are respectively the third input terminal and the fourth input terminal of the FCE unit; the connection point of the first pull-up branch and the first pull-down branch is the output terminal of the FCE unit, The four input ends of the first FCE unit are connected to the feedback nodes B1, C1, D1, and E1 respectively, the four input ends of the second FCE unit are connected to the feedback nodes C1, D1, E1, and Q1 respectively, the four input ends of the third FCE unit are connected to the feedback nodes D1, E1, Q1, and A1 respectively, the four input ends of the fourth FCE unit are connected to the feedback nodes E1, Q1, A1, and B1 respectively, the four input ends of the fifth FCE unit are connected to the feedback nodes Q1, A1, B1, and C1 respectively, and the four input ends of the sixth FCE unit are connected to the feedback nodes A1, B1, C1, and D1 respectively; the output ends of the six FCE units are connected to the generation nodes A, B, C, D, E, and Q respectively.

6. The fast latch based on logic isolation according to claim 5, characterized in that: The FCE unit includes: a first pull-up branch and a first pull-down branch, the first pull-up branch includes: a second PMOS tube and a third PMOS tube; the first pull-down branch includes: a second NMOS tube and a third NMOS tube; In the first FCE unit: the gates of the second PMOS tube and the third PMOS tube of the first pull-up branch are connected to the feedback nodes B1 and C1 respectively, the source of the second PMOS tube is connected to the voltage VDD, the drain of the second PMOS tube is connected to the drain of the third PMOS tube, the source of the third PMOS tube is connected to the source of the second NMOS tube and then connected to the generation node A, the gates of the second NMOS tube and the gates of the third NMOS tube are connected to the feedback node and connected to the nodes D1 and E1 respectively, the drain of the second NMOS tube is connected to the drain of the third NMOS tube, and the source of the third NMOS tube is connected to GND.

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