A clock gating circuit and a clock gating circuit implementation method

Abstract

The present application provides a clock gating circuit and a method for implementing the clock gating circuit. The clock gating circuit includes: a state machine, a triple-module redundant latch circuit and a logic gate circuit; the state machine is used to generate a control state signal according to a state jump triggered by an input control signal, and input the triple-module redundant latch circuit; the triple-module redundant latch circuit is used to latch the control state signal according to the input previous-stage clock signal, and output the latch signal to the logic gate circuit; the logic gate circuit is used to perform an AND operation on the latch signal and the previous-stage clock signal to generate and output a clock control signal. In the present application, the state machine and triple-module redundant technology are applied to the clock gating circuit to enhance the ability of the clock gating circuit to resist radiation.

Description

Technical Field

[0001] The present application relates to the technical field of chip design, and in particular to a clock gating circuit and a method for implementing the clock gating circuit. Background Art

[0002] With the development of chip design technology and manufacturing technology, large-scale system on a chip (SoC) has become the mainstream of chip development, quickly occupying the market, and is widely used in various fields, such as aviation and aerospace.

[0003] In the aerospace field, SoCs used in spacecraft are susceptible to single-particle effects due to the presence of complex radiation particles and rays in the space environment where the spacecraft is located. Among them, the clock gating circuit, which is the upper control circuit of the chip clock structure, will produce single-particle upsets and single-particle transient pulses once it is affected by radiation particles and rays, thereby affecting the downstream subsystems and their registers controlled by it, causing large-scale upsets or even damage, thereby affecting the performance of the SoC chip. Therefore, higher requirements are placed on the radiation resistance of the clock gating circuit. Summary of the invention

[0004] The present application provides a clock gating circuit and a clock gating circuit implementation method to enhance the radiation resistance of the clock gating circuit.

[0005] In the first aspect, the present application provides a clock gating circuit, including: a state machine, a three-module redundant latch circuit and a logic gate circuit; wherein the state machine is used to generate a control state signal according to a state transition triggered by an input control signal, and input the control state signal into the three-module redundant latch circuit; wherein the control signal is a multi-bit signal, and the control state signal is a single-bit signal; the three-module redundant latch circuit is used to latch the control state signal according to an input previous stage clock signal, and output the latch signal to the logic gate circuit; the previous stage clock signal is a clock signal generated by the upper stage circuit before inputting the clock gating circuit. The logic gate circuit is used to perform an AND operation on the latch signal and the previous stage clock signal, generate and output a clock control signal, and the clock control signal is used to select the next stage clock signal.

[0006] In some possible embodiments, the state machine includes: a state processing module and a state machine voter; the state processing module is used to determine the working state of the state machine according to the input control signal, and output a working state signal corresponding to the working state to the state machine voter; wherein the working state signal is a multi-bit state signal; the state machine voter is used to vote on the working state signal and output the first voting result as the control state signal. When the radiation effect causes a single-bit jump in the working state signal, the voter can shield this single-bit error, thereby maintaining the correct output value.

[0007] In some possible embodiments, the state processing module is used to determine the working state of the state machine as a first working state when the control signal is a first value, and output a first working state signal corresponding to the first working state; when the control signal is a second value, determine the working state of the state machine as a second working state, and output a second working state signal corresponding to the second working state; wherein each bit of the first value is different from each bit of the second value, so as to prevent the control signal from having an irradiation effect, triggering a bit change, and causing the state machine to erroneously change its working state.

[0008] In some possible implementations, the first working state is used to indicate that the clock gating circuit is in an initial state and / or the clock gating circuit is in a closed state; the second working state is used to indicate that the clock gating circuit is in an open state.

[0009] In some possible implementations, the state processing module is further used to determine the working state of the state machine as a third working state when the working state of the state machine is not the first working state and the second working state, and output a third working state signal corresponding to the third working state, wherein the third working state is different from the first working state, and the third working state is different from the second working state. By changing the control signal, it is possible to jump back from the third working state to the first working state or the second working state, thereby preventing the state machine from being locked due to bit jumps caused by the radiation effect.

[0010] In some possible implementations, a triple-module redundant latch circuit includes: a triple-module redundant latch and a latch voter; wherein the triple-module redundant latch is used to latch the control state signal according to the previous stage clock signal, generate a signal to be voted and output it to the latch voter; the latch voter is used to vote on the signal to be voted and output the second voting result as a latch signal.

[0011] In some possible implementations, a triple-module redundant latch is used to output the first latch signal at the current moment as a signal to be voted on when the current stage clock signal is a third value; and to output the second latch signal at the previous moment as a signal to be voted on when the current stage clock signal is a fourth value; the third value is different from the fourth value.

[0012] In some possible implementations, the triple modular redundant latch includes: a latch based on back-to-back inverters, a latch based on dual interlocked memory cells, or a latch based on a triple modular redundant nested structure.

[0013] In some possible implementations, the logic gate circuit is an AND gate circuit.

[0014] In a second aspect, the present application provides a method for implementing a clock gating circuit, which is applied to a clock gating circuit as described in the first aspect and any one of its possible implementations, including: generating a control state signal according to a state transition triggered by an input control signal, wherein the control signal is a multi-bit signal and the control state signal is a single-bit signal; latching the control state signal according to an input previous-stage clock signal to generate a latch signal, wherein the previous-stage clock signal is a clock signal generated by an upper-level circuit before the clock gating circuit; performing an AND operation on the latch signal and the previous-stage clock signal to generate a clock control signal, and the clock control signal is used to select a subsequent-stage clock signal.

[0015] In some possible implementations, a control state signal is generated based on a state jump triggered by an input control signal, including: determining the working state of the state machine based on the input control signal; voting on the working state signal corresponding to the working state, and outputting the first voting result as the control state signal, wherein the working state signal is a multi-bit state signal.

[0016] In some possible implementations, the working state of the state machine is determined based on an input control signal, including: when the control signal is a first value, the working state of the state machine is determined to be a first working state; or, when the control signal is a second value, the working state of the state machine is determined to be a second working state; wherein each bit of the first value is different from each bit of the second value.

[0017] In some possible implementations, the first working state is used to indicate that the clock gating circuit is in an initial state and / or the clock gating circuit is in a closed state; the second working state is used to indicate that the clock gating circuit is in an open state.

[0018] In some possible implementations, determining the working state of the state machine based on an input control signal also includes: when the working state of the state machine is not the first working state and the second working state, determining the working state of the state machine as a third working state, the third working state is different from the first working state, and the third working state is different from the second working state.

[0019] In some possible implementations, the control state signal is latched according to the input previous-stage clock signal to generate a latched signal, including: latching the control state signal according to the previous-stage clock signal to generate a signal to be voted; voting on the signal to be voted, and determining the second voting result as the latched signal.

[0020] In some possible implementations, the control state signal is latched according to the previous stage clock signal to generate a pending vote signal, including: when the current stage clock signal is a third value, the first latched signal at the current moment is determined as the pending vote signal; when the current stage clock signal is a fourth value, the second latched signal at the previous moment is determined as the pending vote signal; the third value is different from the fourth value.

[0021] Compared with the prior art, the technical solution provided by this application has the following beneficial effects:

[0022] In the present application, by applying the state machine and triple-module redundancy technology to the clock gating circuit, the clock gating circuit can resist the single particle effect caused by space radiation, thereby enhancing the radiation resistance of the clock gating circuit.

[0023] In addition, by extending the original single-bit clock gating enable signal to multiple bits, the risk of enable signal flipping is reduced, and the radiation resistance of clock gating is further enhanced.

[0024] It should be understood that the above general description and the following detailed description are only exemplary and explanatory and do not limit the scope of protection of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of the structure of a clock gating circuit in an embodiment of the present application;

[0026] Figure 2 A schematic diagram of a possible implementation of a latch in an embodiment of the present application;

[0027] Figure 3 Schematic diagram of another clock gating circuit structure in an embodiment of the present application;

[0028] Figure 4 A schematic diagram of a possible working mode of the clock gating circuit in an embodiment of the present application;

[0029] Figure 5 A schematic diagram of another possible implementation of the latch in the embodiment of the present application;

[0030] Figure 6 This is a timing diagram of the clock gating circuit of an embodiment of the present application. DETAILED DESCRIPTION

[0031] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present invention. However, it should be clear to those skilled in the art that the present invention may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present invention.

[0032] In order to illustrate the technical solution described in this application, a specific embodiment is provided below for illustration.

[0033] With the development of chip design technology and manufacturing technology, large-scale system on a chip (SoC) has become the mainstream of chip development, quickly occupying the market, and is widely used in various fields, such as aviation and aerospace.

[0034] At the same time, with the increasing shortage of energy, how to reduce the power consumption of electronic products has become an important issue in SoC design. Large-scale SoCs are generally composed of multiple clock domains, forming a complex clock network that connects and controls subsystems with different functions. In other words, if the various subsystems or modules of the chip can be turned off by controlling the gating of the clock network, the purpose of reducing the power consumption of the chip can be achieved. Therefore, a clock gating circuit is designed. The principle is that the processor can achieve the gating of the top-level clock of each clock source or each clock domain by controlling the level value of the enable signal in the clock gating circuit, and distribute the gated clock signal to each subsystem or module of the chip, indicating to turn on the required module or turn off the temporarily unneeded module, thereby realizing the control of different functional subsystems and saving the overall power consumption of the chip.

[0035] For example, Figure 1 FIG. 1 is a schematic diagram of the structure of a clock gating circuit in an embodiment of the present application. Figure 1 As shown, the clock gating circuit 10 may include: a latch 11 and an AND gate 12 .

[0036] First, some possible implementations of the latch 11 are introduced.

[0037] In some possible implementations, the latch 11 may include three pins (denoted as pin A, pin CK, and pin S). It should be understood that pin A may be used as a signal input terminal of the latch 11, and an enable control signal (denoted as EN_0) is input into the latch 11 from pin A; pin CK may be used as a clock signal input terminal of the latch 11, and a previous stage clock signal (denoted as CLK) is input into the latch 11 from pin CK; pin S may be used as a signal output terminal of the latch 11, and a latch signal (denoted as Q) is output from pin S.

[0038] Exemplarily, the latch 11 in the clock gating circuit 10 may be an RS latch, a D latch, or the like.

[0039] In some possible implementations, Figure 2 A schematic diagram of a possible implementation of the latch in the embodiment of the present application, see Figure 2 As shown, latch 11 may be an RS latch, and the RS latch may include two inverters (recorded as inverter 11a and inverter 11b) and a logic circuit. When the RS latch is applied to a clock gating circuit, according to the preset logic of the latch circuit, the RS latch continuously inputs and outputs data during the effective period of the control signal. For example, when CLK is at a low level, the trigger latch 11 is in a transparent period, and the signal at the input end continuously outputs the latch.

[0040] Combine the following Figure 2 The structural schematic diagram shown briefly describes the working process of the latch 11 in the clock gating circuit 10.

[0041] The previous-stage clock signal CLK is input into latch 11. When the previous-stage clock signal CLK is at a low level, latch 11 is triggered into a transparent period, and the enable control signal EN_0 is input into latch 11 for latching, generating a latch signal Q output; when the previous-stage clock signal CLK is at a high level, latch 11 is triggered into a holding period, and latch 11 keeps the output signal of the previous moment unchanged.

[0042] For example, when the clock signal CLK=0 (i.e., CLK is at a low level), Q changes with the change of EN_0. If EN_0=1, then Q=EN_0=1; if EN_0=0, then Q=EN_0=0. At the next moment, CLK changes from 0 to 1 (i.e., CLK changes from a low level to a high level), the current value of EN_0 (EN_0=1) is latched immediately, and the output Q=EN_0=1. During the entire period when CLK is 1, Q remains unchanged (i.e., Q_0=1). When CLK changes to 0 again, the latch is canceled, and Q changes with the change of EN_0 again.

[0043] Furthermore, some possible implementations of the AND gate 12 are introduced.

[0044] In the embodiment of the present application, the AND gate 12 can be used to perform AND operations on various currently input signals and output the signals after the operations.

[0045] In some possible implementations, the AND gate 12 may include three pins (denoted as pin S1, pin CK1, and pin CK2). It should be understood that the pin S1 may be used as a signal input terminal, and the latch signal Q is input into the AND gate 12 from the pin S1; the pin CK1 may be used as a clock signal input terminal, and the previous stage clock signal CLK is input into the AND gate 12 from the pin CK1; the pin CK2 may be used as a signal output terminal, and the clock control signal (denoted as CLK_O) is output from the pin CK2.

[0046] Exemplarily, assuming that Q=1, CLK=1, then CLK_O=1; Q=1, CLK=0, then CLK_O=0.

[0047] Combine the following Figure 1 and Figure 2 The structural schematic diagram shown in FIG. 1 briefly describes the working process of the clock gating circuit by using a specific example.

[0048] In one implementation, assuming that the previous-stage clock signal CLK input to the latch 11 is at a low level and the enable control signal EN_0 is at a high level, the latch 11 outputs a latch signal Q equal to EN_0 which is at a high level, the latch signal Q and the previous-stage clock signal CLK are input to the AND gate 12, and the AND gate 12 outputs the clock control signal CLK_O; or, the previous-stage clock signal CLK input to the latch 11 is at a low level, the enable control signal EN_0 of the input latch 11 is at a low level, the latch 11 outputs a latch signal Q equal to EN_0 which is at a low level, the latch signal Q is at a low level, and the subsequent clock is turned off.

[0049] In another implementation, assume that the previous clock signal CLK input to the latch 11 changes from a low level to a high level, the latch 11 latches the current signal and keeps the latch signal Q unchanged until the previous clock signal CLK changes to a low level, at which time the latch releases the current latch state.

[0050] From the above, we can see that if Figure 1 The clock gating circuit shown is applied to the SoC in the spacecraft. Then, due to the complex radiation particles and rays in the space environment where the spacecraft is located, the latch 11 is easily affected. Once the latch 11 is affected, a single event effect occurs, which will generate an erroneous latch signal, thereby affecting the downstream subsystems controlled by the clock gating circuit 10, causing large-scale errors, and further affecting the performance of the SoC.

[0051] In order to solve the above problems, an embodiment of the present application provides another clock gating circuit, which can be applied to aerospace vehicles, such as spacecraft, rockets, space stations, satellites, space probes, etc.

[0052] Figure 3FIG. 1 is a schematic diagram of another clock gating circuit structure in an embodiment of the present application, see Figure 3 As shown, the clock gating circuit 20 may include: a state machine 21, a triple-module redundant latch circuit 22, and an AND gate circuit 23. The state machine 21 and the triple-module redundant latch circuit 22 are applied on the basis of the clock gating circuit 10, so that the clock gating circuit 20 can resist the single particle effect caused by space radiation, thereby enhancing the radiation resistance of the clock gating circuit 20. Further, the state machine 21 can output a control state signal with good stability according to the state selection triggered by the multi-bit enable signal, so as to ensure the stable operation of the subsequent circuit, thereby greatly improving the radiation resistance of the clock gating circuit 20.

[0053] In some possible implementations, the state machine 21 may include two pins (recorded as pin 21a and pin 21b), pin 21a may be used as a signal input terminal, and pin 21b may be used as a signal output terminal; the triple-mode redundant latch circuit 22 may include two pins (recorded as pin 22a and pin 22b), pin 22a may be used as a signal input terminal, and pin 22b may be used as a signal output terminal; and the AND gate circuit 23 may include three pins (recorded as pin 23a, pin 23b, and pin 23c), pin 23a may be used as a signal input terminal, pin 23b may be used as a clock signal input terminal, and pin 23c may be used as a signal output terminal. It should be understood that pin 21b is connected to pin 22a, and pin 22b is connected to pin 23a.

[0054] First, some possible implementations of the state machine 21 are introduced.

[0055] In one embodiment, the state machine 21 is used to generate a control state signal (denoted as EN) according to the state transition triggered by the input control signal (denoted as CTRL), and input it into the triple-module redundant latch circuit 22. It should be understood that the control signal CTRL is input into the state machine 21 by pin 21a, and the control state signal EN is output by pin 21b. The state machine 21 can be various devices that implement the logic circuit of the embodiment of the present application. For example: programmable logic device, etc. The control signal CTRL can be a multi-bit signal, which can be determined by the upper control register according to the requirements and resources of the application. Exemplarily, the control signal can be a 4-bit signal, for example: CTRL[3:0]; the control signal can be an 8-bit signal, for example: CTRL[7:0]. The control state signal EN is a single-bit signal (0 or 1).

[0056] In some possible implementations, the state machine 21 may include a state processing module 211 and a state ticket decider 212. The state processing module 211 is used to determine the working state of the state machine 21 according to the input control signal CTRL, and output a working state signal corresponding to the working state to the state ticket decider 212; the state ticket decider 212 is used to vote on the working state signal and output the first voting result as the control state signal EN.

[0057] In some possible implementations, the state processing module 211 may include two working states, a first working state (denoted as Z1) and a second working state (denoted as Z2). The first working state Z1 may be used to indicate that the clock gating circuit 20 is in an initial state and / or the clock gating circuit 20 is in a closed state; the second working state Z2 may be used to indicate that the clock gating circuit 20 is in an open state. The values ​​of each bit of the working state signal corresponding to the first working state and the working state signal corresponding to the second working state are different. It should be understood that the working state signal may be a multi-bit state signal with a width of at least 2 bits. Then, the working state signal corresponding to the first working state may be 111, and the working state signal corresponding to the second working state may be 000.

[0058] In some possible implementations, the state processing module 211 may also include three working states, namely, a first working state Z1, a second working state Z2, and a third working state (denoted as Z3). The first working state Z1 may be used to indicate that the clock gating circuit 20 is in an initial state and / or the clock gating circuit 20 is in a closed state; the second working state Z2 may be used to indicate that the clock gating circuit 20 is in an open state; the third working state Z3 may be used to indicate an error state, which is not used under normal circumstances. Once a single-particle flip occurs in the working state signal corresponding to the first working state Z1 or the second working state Z2, a value change occurs in a certain bit of the working state signal, triggering a jump to the third working state Z3. The values ​​of each bit of the working state signal corresponding to the first working state Z1 and the working state signal corresponding to the second working state Z2 are different; the working state signal corresponding to the third working state Z3 is different from the value of the working state signal corresponding to the first working state Z1, and the working state signal corresponding to the third working state Z3 is different from the value of the working state signal corresponding to the second working state Z2. Exemplarily, the working state signal corresponding to the first working state Z1 may be 111, the working state signal corresponding to the second working state Z2 may be 000, and the working state signal corresponding to the third working state Z3 may be 010.

[0059] In some possible implementations, the state processing module 211 may determine the working state of the state machine 21 in the following manner: when the control signal CTRL is a first value (denoted as A), the working state of the state machine 21 is determined as the first working state Z1; or, when the control signal CTRL is a second value (denoted as B), the working state of the state machine 21 is determined as the second working state Z2; wherein each bit of the first value A is different from each bit of the second value B. It should be understood that CTRL can be a multi-bit signal, then the first value A and the second value B can also be multi-bit signals, both of which have a width of at least 2 bits. Exemplarily, CTRL can be 4 bits, i.e. [3:0], then A can be 1111, and B can be 0000.

[0060] In some possible implementations, the state processing module 211 may also determine the working state of the state machine 21 in the following manner: when the working state of the state machine is not the first working state and the second working state, the working state of the state machine 21 is determined to be the third working state Z3. It should be understood that CTRL can be a multi-bit signal, and the working state signal corresponding to the third working state Z3 can also be a multi-bit signal, and the width is at least 2 bits. Exemplarily, CTRL can be 4 bits, that is, [3:0], and the working state signal corresponding to the first working state Z1 can be 111, the working state signal corresponding to the second working state Z2 can be 000, and the working state signal corresponding to the third working state Z3 can be all values ​​except 111 and 000.

[0061] In some possible implementations, the state processing module 211 outputs a working state signal corresponding to the working state to the state ticket decider 212, which may include outputting a working state signal corresponding to the working state at the current moment. The working state at the current moment may include the first working state Z1 and / or the second working state Z2, but does not include all other states. This setting ensures that the erroneous working state signal caused by the occurrence of a single particle upset will not be introduced into the state ticket decider 212, and thus will not cause errors in subsequent clocks.

[0062] Exemplarily, when the current working state is the first working state Z1, the state processing module 211 outputs a working state signal corresponding to the first working state Z1 to the state ticket decider 212; when the current working state is the third working state Z3, the state processing module 211 does not output a working state signal corresponding to the working state.

[0063] In some possible implementations, Figure 4 This is a schematic diagram of a possible working mode of the state processing module in the embodiment of the present application, see Figure 4As shown, assuming that the state processing module 211 is working, it can include the first working state Z1, the second working state Z2 and the third working state Z3, wherein the working state signal corresponding to the first working state Z1 can be 000; the working state signal corresponding to the second working state Z2 can be 111; and the working state signal corresponding to the third working state Z3 can be all values ​​different from 000 and 111. Set the first value A=00001111, when the 8-bit control signal CTRL is equal to the first value A, the current working state of the state machine 21 is determined to be the first working state Z1, and the state processing module 211 outputs the working state signal 000 corresponding to the first working state Z1 to the state machine 212. Set the second value B=11110000, when the 8-bit control signal CTRL is equal to the second value B, the current working state of the state machine 21 is determined to be the second working state Z2, and the state processing module 211 outputs the working state signal 111 corresponding to the second working state Z2 to the state machine 212.

[0064] Furthermore, the state processing module 211 outputs a working state signal corresponding to the working state to the state ticket decider 212 in the following situations, but not limited to:

[0065] First, the state processing module 211 is outputting the working state signal (000) corresponding to the first working state Z1 according to the currently input control signal CTRL. At the next moment, when the control signal CTRL is the second value B (11110000), the working state of the state machine 21 is determined to be the second working state Z2, and the state processing module 211 will output the working state signal (111) corresponding to the second working state Z2.

[0066] Second, the state processing module 211 is outputting the working state signal (111) corresponding to the second working state Z2 according to the currently input control signal CTRL. At the next moment, when the control signal CTRL is the first value A (00001111), the working state of the state machine 21 is determined to be the first working state Z1, and the state processing module 211 will output the working state signal (000) corresponding to the first working state Z1.

[0067] The third type is that the state machine 21 is affected by the radiation effect and an erroneous third working state Z3 appears, and the state processing module 211 does not output the working state signal corresponding to the third working state Z3 (that is, all signals except 111 or 000). At the next moment, when the control signal CTRL is the first value A (00001111), the working state of the state machine 21 is determined to be the first working state Z1, and the state processing module 211 will output the working state signal (000) corresponding to the first working state Z1, that is, the state machine 21 can switch from the third working state Z3 to the first working state Z1. Alternatively, at the next moment, when the control signal CTRL is the second value B (11110000), the working state of the state machine 21 is determined to be the second working state Z2, and the state processing module 211 will output the working state signal (111) corresponding to the second working state Z2. That is, the state machine 21 can switch from the third working state Z3 to the second working state Z2. That is to say, the working state signal corresponding to the third working state Z3 will not be output by the state processing module 211 to the state ticket decider 212 .

[0068] It should be noted that the state machine 21 has an erroneous third working state Z3, which means that the first working state Z1 or the second working state Z2 in the state machine 21 is affected by the space environment, and a single particle flip occurs, thereby generating an erroneous third working state Z3. For example, the working state signal (000) corresponding to the first working state Z1 has a single particle flip and jumps to the working state signal (010), and the working state signal (010) corresponds to the third working state Z3. The working state signal (010) will not be output by the state processing module 211 to the state ticket decider 212.

[0069] It can be seen that in the third case, the third working state Z3 can be triggered by the control signal CTRL to jump back to the first working state Z1 or the second working state Z2, thereby realizing the soft error correction function of the current state value of the state machine.

[0070] In some possible implementations, the status signal decider 212 may be used to vote on the working status signal, and output the first voting result as the control state signal EN. It should be understood that the voting logic of the status signal decider 212 may be to select the signal represented by the majority of bits in the working status signal as the voting result. For example, the working status signal 111 is input into the status signal decider 212, and the status signal decider 212 selects the value of the majority of bits in 111 (i.e., 1), obtains the first voting result of 1, and outputs the first voting result (i.e., 1) as the control state signal EN.

[0071] The working process of the state machine 21 is described below with reference to a specific example.

[0072] Assume that the control signal CTRL (such as 1111) triggers the state processing module 211 to select the state and determines that the current state is the first working state Z1, and the working state signal corresponding to the first working state Z1 is 111. 111 is input to the state ticket decider 212 for voting, and the output control state signal EN is 1.

[0073] Furthermore, some possible embodiments of the triple-module redundant latch circuit 22 are introduced.

[0074] In one embodiment, the triple-module redundant latch circuit 22 can be used to latch the control state signal EN according to the input previous stage clock signal CLK, and output the latch signal (denoted as Q) to the AND gate circuit 23. The previous stage clock signal CLK is a clock signal generated by the upper stage circuit before inputting the clock gating circuit 20. The latch signal Q is a single-bit signal.

[0075] It should be understood that the control state signal EN is input into the triple-module redundant latch circuit 22 via the pin 22a, and the latch signal Q is output via the pin 22b.

[0076] In some possible implementations, the triple-module redundant latch circuit 22 may include: a triple-module redundant latch 221 and a latch voter 222. The triple-module redundant latch 221 is used to latch the control state signal EN according to the previous clock signal CLK, and the triple-module redundant latch 221 generates a signal to be voted and outputs it to the latch voter 222. The signal to be voted is a single-bit signal (i.e., 0 or 1).

[0077] In some possible implementations, the triple-module redundant latch 221 may include three latches (denoted as latch S1, latch S2, and latch S3). Latch S1, latch S2, and latch S3 are used to latch the control state signal EN according to the previous clock signal CLK, and generate pending vote signals (denoted as pending vote signal Q21, pending vote signal Q22, pending vote signal Q23), respectively. Latch S1, latch S2, and latch S3 work independently, and the results are independent of each other. Latch S1, latch S2, and latch S3 have exactly the same structure. Exemplarily, latch S1, latch S2, and latch S3 may be implemented as follows Figure 2 The latch of the structure shown may also be a latch based on a triple modular redundant nested structure.

[0078] In some possible implementations, the latch S1 may have three pins (recorded as pin CK1, pin D1, and pin Q1). It should be understood that the pin CK1 may be used as a clock signal input terminal, and the previous stage clock signal CLK is input into the latch S1 through the pin CK1; the pin D1 may be used as a signal input terminal, and the control state signal EN is input into the latch S1 through the pin D1; the pin Q1 may be used as a signal output terminal, and the pending vote signal Q21 is output from the pin Q1.

[0079] In some possible implementations, latch S2 may have three pins (recorded as pin CK2, pin D2, and pin Q2). It should be understood that pin CK2 may be used as a clock signal input terminal, and the previous stage clock signal CLK is input into latch S2 from pin CK1; pin D2 may be used as a signal input terminal, and the control state signal EN is input into latch S2 from pin D2; pin Q2 may be used as a signal output terminal, and the pending vote signal Q22 is output from pin Q2.

[0080] In some possible implementations, the latch S3 may have three pins (recorded as pin CK3, pin D3, and pin Q3). It should be understood that the pin CK3 can be used as a clock signal input terminal, and the previous clock signal CLK is input into the latch S3 from the pin CK1; the pin D3 can be used as a signal input terminal, and the control state signal EN is input into the latch S3 from the pin D1; the pin Q2 can be used as a signal output terminal, and the pending vote signal Q23 is output from the pin Q3.

[0081] In some possible implementations, Figure 5 FIG. 1 is a schematic diagram of another possible implementation of the latch in the embodiment of the present application, see Figure 5 As shown, the latch S1 can be a latch based on a dual interlocked storage unit. Compared with a simple RS latch or a D latch, the latch S1 based on a dual interlocked storage unit has multiple nodes. A single node is affected by radiation particles and causes a flip, which does not affect other nodes. Therefore, the latch S1 based on a dual interlocked storage unit has better radiation resistance.

[0082] It can be understood that the working process of the latch S1 is as follows: the control state signal EN is input into the latch S1, the latch S1 is latched under the control of the previous clock signal CLK, and the pending decision signal Q21 is output.

[0083] Then, the working process of the triple-module redundant latch 221 is: the control state signal EN is copied three times, and under the control of the previous stage clock signal CLK, it is input into latch S1, latch S2 and latch S3 for latching respectively, and latch S1, latch S2 and latch S3 output the pending vote signal Q21, the pending vote signal Q22 and the pending vote signal Q23.

[0084] In some possible implementations, the triple-module redundant latch 221 can be used to output the first latch signal at the current moment as the signal to be voted when the current clock signal CLK is a third value; and to output the second latch signal at the previous moment as the signal to be voted when the current clock signal CLK is a fourth value; the third value is different from the fourth value.

[0085] It should be understood that the third value can be 0, that is, when the previous stage clock signal CLK is at a low level, the three-module redundant latch 221 is in a transparent period, the control state signal EN is input to the latch S1, and latching is performed under the control of the low-level previous stage clock signal CLK, generating a latch signal Q and outputting it; the fourth value can be 1, that is, when the previous stage clock signal CLK input to the three-module redundant latch 221 is at a high level, the latch S1 is triggered to be in a holding period, and the latch S1 keeps the output signal of the previous moment unchanged.

[0086] Exemplarily, when CLK is 0, if EN=0, then Q=EN=0; if EN=1, then Q=EN=1.

[0087] In some possible implementations, the latch voting device 222 can be used to vote on the signal to be voted, and output the second voting result as the latch signal Q. The voting logic of the latch voting device 222 can be to select the signal represented by the majority of the signals to be voted as the voting result. For example: if the signals to be voted output by the three-mode latch 221 are 1, 1, and 0 respectively, then the second voting result is the signal represented by the majority of the signals to be voted (1), and therefore, the output latch signal Q is 1.

[0088] The above triple-module redundant latch circuit 22 is described below with reference to a specific example.

[0089] Assuming that the control state signal EN is 1, three copies are made and input into the triple-module redundant latch circuit 22, which latches under the control of the previous stage clock signal CLK. When the previous stage clock signal CLK is 0, the triple-module redundant latch circuit 22 outputs three signals to be latched (all 1), and the latch voting device 222 votes on the three signals to be latched, and the output latch signal Q is 1.

[0090] Furthermore, some possible implementations of the AND gate circuit 23 are introduced.

[0091] In one embodiment, the AND gate circuit 23 can be used to perform an AND operation on the latch signal Q and the previous clock signal CLK to generate and output the clock control signal CLK_O. The clock control signal CLK_O can be used as an input clock for a subsequent clock network or subsystem. The AND gate circuit 23 can be any logic circuit that can implement an AND operation. For example, the AND gate circuit 23 can be an AND gate.

[0092] It should be understood that the latch signal Q is input into the AND gate circuit 23 via the pin 23a, the previous stage clock signal CLK is input into the AND gate circuit 23 via the pin 23b, and the latch signal Q is output via the pin 23c.

[0093] Assume that the latch signal Q=1 and the previous stage clock signal CLK=1, then the clock control signal CLK_O=1; and assume that the latch signal Q=0 and the previous stage clock signal CLK=1, then the clock control signal CLK_O=0.

[0094] The clock gating circuit 20 is described below with reference to a specific example. Figure 3 , Figure 4 and Figure 5 It can be seen that the control signal CTRL is input to the state machine 21, triggering the state machine 21 to output the state control signal EN; the state control signal EN and the previous stage clock signal CLK are input to the triple-mode redundant latch circuit 22, and the triple-mode redundant latch circuit 22 outputs the latch signal Q. The latch signal Q and the previous stage clock signal CLK are input to the AND gate circuit 23, which outputs the clock control signal CLK_O.

[0095] Assume that the current control signal CTRL value is 111111, 111111 is input to the state machine 21, and the trigger state is selected as the second working state Z2. Then the state processing module 211 determines the working state signal (111) corresponding to the second working state and outputs it to the state ticket decider 212. The state ticket decider 212 votes on the working state signal 111 and outputs the state control signal EN as 1. The state control signal EN is input to the three-mode redundant latch circuit 22. The three-mode redundant latch circuit 22 latches the state control signal EN under the control of the previous stage clock signal CLK. Among them, if the previous stage clock signal CLK is a low level, the output latch signal Q=EN=1 is output. If the previous stage clock signal CLK is a high level, the output latch signal Q remains unchanged and continues to be 1. The latch signal Q and the previous stage clock signal CLK are input to the AND gate circuit 23, and the AND gate circuit 23 outputs the clock control signal CLK_O. Among them, when Q=1, if CLK=0, the output is CLK_O=0; if CLK=1, the output is CLK_O=1.

[0096] At the next moment, the control signal CTRL value is the first value 000000, 000000 is input to the state machine 21, and the current working state is determined to be the first working state Z1. Then the state processing module 211 determines the working state signal (000) corresponding to the first working state and outputs it to the state ticket decider 212. The state ticket decider 212 votes on the working state signal 000, and the output state control signal EN is 0. When the state control signal EN is 0, the entire clock gating is closed, and the subsequent clocks are all 0.

[0097] In the embodiments of the present application, a state machine is applied to a clock gating circuit. Through the selection of the working state, the state machine can avoid the incorrect transmission of control signals caused by single-event effects to the subsequent circuit, and achieve a stable output of the state control signal applied to the latch circuit. At the same time, the triple modular redundancy technology is applied to the latch circuit in the clock gating circuit to implement a hardened latch, and then a stable latch signal is output. It can be seen that in the clock gating circuit in the embodiments of the present application, through the state machine and the triple modular redundant latch circuit, the single-event effects caused by space radiation can be effectively resisted, and thus the radiation resistance of the clock gating circuit is enhanced.

[0098] In addition, the original single-bit clock gating enable signal is extended to multiple bits, and at the same time, a hardened latch structure is adopted to resist the risk of the enable signal flipping caused by space radiation, thereby enhancing the radiation resistance of the clock gating.

[0099] Figure 6 This is the timing diagram of the clock gating circuit in the embodiments of the present application. As Figure 6 shown, it includes: the waveforms of the pre-stage clock signal CLK, the control bus signal (denoted as CTRL[N:0]), the control state signal EN, the latch signal (denoted as Q), and the clock control signal CLK_O.

[0100] Among them, the waveform of the pre-stage clock signal CLK alternates between high level and low level, representing different states of the pre-stage clock signal CLK.

[0101] Working stage of the state machine: The control bus signal CTRL[N:0] is input into the state machine. After state selection and voting, the control state signal EN is generated. Therefore, the waveform of the control bus signal CTRL[N:0] will propagate to the control state signal EN after several clock cycles, making the control state signal EN have a waveform similar to that of the control bus signal CTRL[N:0].

[0102] Working stage of the triple modular redundant latch circuit: Under the control of the pre-stage clock signal CLK, the control state signal EN is input into the triple modular redundant latch circuit for signal latching and voting to generate the latch signal Q. When the pre-stage clock signal CLK is at a low level, the latch is enabled to generate the latch signal Q at the current moment. When the pre-stage clock signal CLK is at a high level, the latch maintains the latch signal Q at the previous moment. That is to say, as Figure 6 shown, when the pre-stage clock signal CLK drops to a low level, the latch is enabled, and the latch signal Q starts to rise at the falling edge of the pre-stage clock signal CLK, obtaining a waveform the same as the current control state signal EN; at the next moment, the pre-stage clock signal CLK starts to rise to a high level, and the latch maintains the latch signal Q at the previous moment, that is, the waveform of the latch signal Q remains unchanged, maintaining the waveform state at the previous moment.

[0103] Logic gate circuit working stage: the previous stage clock signal CLK and the latch signal Q perform an AND operation in the logic gate circuit to generate and output the clock control signal CLK_O. When the previous stage clock signal CLK and the latch signal Q are at a high level, the waveform of the clock control signal CLK_O is a high level; when the previous stage clock signal CLK and the latch signal Q are at a low level, the waveform of the clock control signal CLK_O is a low level. Since the previous stage clock signal CLK has a delay of the combinational circuit compared with the latch signal Q, the AND operation of the previous stage clock signal CLK and the latch signal Q does not introduce glitches. Finally, when the latch signal Q is at a high level, the clock control signal CLK_O has the same frequency and a slightly delayed phase relationship with the previous stage clock signal CLK; when the latch signal Q is at a low level, the clock control signal CLK_O outputs a low level, shutting down the clocks of the subsequent clock network and circuit modules, saving power consumption.

[0104] From the analysis of the above waveforms, it can be seen that by applying the state machine and triple-mode redundancy technology in the clock gating circuit, the stable output of the lower-level clock control signal can be achieved, thereby greatly reducing the impact of the single-particle effect on the clock gating circuit and enhancing the anti-radiation function of the clock gating circuit.

[0105] Compared with some clock gating circuits, the clock gating circuit structure of the embodiment of the present application has a large area overhead, but because the clock gating circuit is only used at the top level of each clock domain network, the demand is not large. Therefore, compared with the area of ​​the entire SoC, the additional area overhead brought by the clock gating circuit of the embodiment of the application does not cause a burden on the design and manufacture of the SoC. On the contrary, the clock gating circuit in the embodiment of the application has good radiation resistance performance, which can ensure the stable performance of the SoC, thereby ensuring the stability of the clock network of the aerospace device and avoiding large-scale bursts of soft errors.

[0106] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application is described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features can be replaced. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A clock gating circuit, It is characterized in that include: State machine, triple-module redundant latch circuit and logic gate circuit; wherein, The state machine is used to generate a control state signal according to a state transition triggered by an input control signal, and input the control state signal into the triple-module redundant latch circuit; the control signal is a multi-bit signal, and the control state signal is a single-bit signal; The triple-module redundant latch circuit is used to latch the control state signal according to the input previous stage clock signal, and output the latch signal to the logic gate circuit; the previous stage clock signal is a clock signal generated by the upper stage circuit before being input into the clock gating circuit; The logic gate circuit is used to perform an AND operation on the latch signal and the previous-stage clock signal to generate and output a clock control signal, wherein the clock control signal is used to select a subsequent-stage clock signal; The state machine comprises: a state processing module and a state ticket decider; the state processing module is used to determine the working state of the state machine according to the input control signal, and output a working state signal corresponding to the working state to the state ticket decider; wherein the working state signal is a multi-bit state signal; the state ticket decider is used to vote on the working state signal, and output a first voting result as the control state signal; The state processing module is used to determine the working state of the state machine as a first working state when the control signal is a first value, and output a first working state signal corresponding to the first working state; when the control signal is a second value, determine the working state of the state machine as a second working state, and output a second working state signal corresponding to the second working state; wherein each bit of the first value is different from each bit of the second value.

2. The clock gating circuit according to claim 1, It is characterized in that The first working state is used to indicate that the clock gating circuit is in an initial state and / or the clock gating circuit is in a closed state; the second working state is used to indicate that the clock gating circuit is in an open state.

3. The clock gating circuit according to claim 1, It is characterized in that The state processing module is also used to determine the working state of the state machine as a third working state when the working state of the state machine is neither the first working state nor the second working state, and output a third working state signal corresponding to the third working state, wherein the third working state is different from the first working state, and the third working state is different from the second working state.

4. The clock gating circuit according to claim 1, It is characterized in that The triple-module redundant latch circuit comprises: a triple-module redundant latch and a latch voting device; wherein, The triple-module redundant latch is used to latch the control state signal according to the previous clock signal, generate a signal to be voted and output it to the latch voter; The latch voting device is used to vote on the signal to be voted and output the second voting result as the latch signal.

5. The clock gating circuit according to claim 4, It is characterized in that The triple-module redundant latch is used to output the first latch signal at the current moment as the signal to be voted when the previous-stage clock signal is the third value; and to output the second latch signal at the previous moment as the signal to be voted when the previous-stage clock signal is the fourth value; the third value is different from the fourth value.

6. The clock gating circuit according to claim 4, It is characterized in that The triple-module redundant latch includes: a latch based on back-to-back inverters, a latch based on dual interlocked storage cells, or a latch based on a triple-module redundant nested structure.

7. The clock gating circuit according to claim 1, It is characterized in that The logic gate circuit is an AND gate circuit.

8. A method for implementing a clock gating circuit, It is characterized in that Applicable to the clock gating circuit according to any one of claims 1 to 7; the method comprises: Generate a control state signal according to a state transition triggered by an input control signal, wherein the control signal is a multi-bit signal and the control state signal is a single-bit signal; latching the control state signal according to an inputted previous stage clock signal to generate a latched signal, wherein the previous stage clock signal is a clock signal generated by an upper stage circuit before the clock gating circuit; Performing an AND operation on the latch signal and the previous-stage clock signal to generate a clock control signal, wherein the clock control signal is used to select a subsequent-stage clock signal; The step of generating a control state signal according to a state transition triggered by an input control signal includes: determining the working state of the state machine according to the input control signal; voting on the working state signal corresponding to the working state, and outputting the first voting result as the control state signal, wherein the working state signal is a multi-bit state signal; Determining the working state of the state machine according to the input control signal includes: when the control signal is a first value, determining the working state of the state machine as a first working state; or, when the control signal is a second value, determining the working state of the state machine as a second working state; wherein each bit of the first value is different from each bit of the second value.

9. The method according to claim 8, It is characterized in that The first working state is used to indicate that the clock gating circuit is in an initial state and / or the clock gating circuit is in a closed state; the second working state is used to indicate that the clock gating circuit is in an open state.

10. The method according to claim 8, It is characterized in that The step of determining the working state of the state machine according to the input control signal further includes: When the working state of the state machine is neither the first working state nor the second working state, the working state of the state machine is determined to be a third working state, which is different from the first working state and different from the second working state.

11. The method according to claim 8, It is characterized in that The step of latching the control state signal according to the inputted previous clock signal to generate a latch signal comprises: According to the previous stage clock signal, the control state signal is latched to generate a pending voting signal; The signal to be voted is voted, and a second voting result is determined as the latch signal.

12. The method according to claim 11, It is characterized in that The step of latching the control state signal according to the previous stage clock signal to generate a pending voting signal comprises: When the previous-stage clock signal is the third value, the first latch signal at the current moment is determined as the signal to be voted on; when the previous-stage clock signal is the fourth value, the second latch signal at the previous moment is determined as the signal to be voted on; the third value is different from the fourth value.

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