High voltage stacked transistor amplifier

Abstract

Various aspects of integrated amplifiers, integrated amplifier layouts, and amplifier packaging structures are described. In one embodiment, the amplifier has an amplifier cell and a biasing network coupled to a common-gate transistor in the amplifier cell. The amplifier cell includes a common-source transistor and a common-gate transistor in a cascoded relationship, at least one of the common-source transistor and the common-gate transistor includes a field plate. Among other advantages, the amplifiers described herein can be biased at relatively high voltages without compromising reliability, performance, and without requiring additional off-chip components, such as biasing networks of resistors and inductors, and still operate like a single common-source transistor.

Description

[Background technology]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Non-provisional Patent Application No. 17 / 219,118, filed March 31, 2021, which is incorporated by reference in its entirety.

[0002] The semiconductor industry continues to see a demand for lower cost and smaller size integrated devices, especially monolithic microwave integrated circuits (MMICs). MMIC devices include integrated circuits (ICs) designed to operate at microwave frequencies. MMIC devices may be used for power amplification, mixing, and high frequency switching, among other operations. The semiconductor industry also continues to see a demand for higher voltage and higher power integrated devices, including high voltage, high power MMIC power amplifiers.

[0003] The common-source amplifier is one of the basic single-stage field-effect transistor (FET) amplifier technologies. In a common-source FET amplifier, the input signal is provided at the gate terminal of the FET amplifier and the output signal is provided at the drain of the FET amplifier. The source terminal of the FET amplifier is not utilized for either the input or output terminal; the source terminal is considered the "common" terminal. In bipolar junction transistors, similar circuit topologies are commonly referred to as transconductance amplifiers or voltage amplifiers. Summary of the Invention

[0004] Various aspects of an integrated amplifier, an integrated amplifier layout, and an amplifier packaging structure are described. In one embodiment, the amplifier has an amplifier cell and a biasing network. The amplifier cell includes a common source transistor and a common gate transistor in a cascoded relationship, at least one of the common source transistor and the common gate transistor includes a field plate. The biasing network is coupled to the common gate transistor in the amplifier cell. The drain of the common source transistor may also be electrically coupled to the source of the common gate transistor in the cascoded relationship. In some cases, the amplifier cell may further include a second common gate transistor, a third common gate transistor, or more common gate transistors. In one aspect of the embodiment, a stabilization capacitor may be coupled between an output for the amplifier and a gate of the common gate transistor. The capacitance of the stabilization capacitor may maintain a positive real output impedance for the amplifier over an operating frequency for the amplifier.

[0005] In another aspect, the gate of the common-gate transistor may be coupled to a biasing node of a biasing network. The biasing network may include a resistor voltage divider network coupled between an output for the amplifier, the amplifier cell, and a ground for the amplifier. The gate of the common-gate transistor may be coupled to the biasing node along the resistor voltage divider network. The biasing network, in another aspect of the embodiments, may include an inductor coupled in series with the resistor voltage divider network. The biasing network may further include a supply transistor. The gate of the supply transistor may be coupled to the biasing node along the resistor voltage divider network, and the gate of the common-gate transistor may be coupled to a source of the supply transistor.

[0006] In another aspect of the embodiments, the amplifier cell may further include a resistor-capacitor network coupled between the gate of the common-gate transistor and a ground for the amplifier. The resistor-capacitor network may provide a high frequency ground at the gate of the common-gate transistor. The amplifier may further include a stabilizing resistor coupled between the amplifier cell and the biasing network.

[0007] The amplifier may further include a second amplifier cell. The second amplifier cell may include a second common source transistor and a second common gate transistor in a cascoded relationship. The second amplifier cell may be arranged in parallel with the amplifier cell at the output of the amplifier. A biasing network may be coupled to the amplifier cell and the second amplifier cell for biasing both the amplifier cell and the second amplifier cell. The output of the amplifier cell may be directly coupled to the output of the second amplifier cell.

[0008] A stabilizing resistor may be coupled between the input of the amplifier cell and the input of the second amplifier cell. A stabilizing resistor may be coupled between the amplifier cell and the biasing network. A first stabilizing resistor may be coupled between the amplifier cell and the biasing network, and a second stabilizing resistor may be coupled between the amplifier cell and the second amplifier cell.

[0009] The amplifier may further include a second biasing network, and the gate of the common-gate transistor and the gate of the second common-gate transistor are both coupled to the biasing network and the second biasing network. The amplifier may further include a bias interconnect feed line. The biasing network may be coupled at a first end of the bias interconnect feed line, and the second biasing network may be coupled at a second end of the bias interconnect feed line. The amplifier may further include a stabilization resistor coupled between the amplifier cell and the biasing network at the first end of the bias interconnect feed line, a second stabilization resistor coupled between the amplifier cell and the second amplifier cell along the bias interconnect feed line, and a third stabilization resistor coupled between the second amplifier cell and the second biasing network at the second end of the bias interconnect feed line.

[0010] The power handling capacity of the amplifier may be greater than 400 W in one embodiment, and the operating supply voltage for the amplifier may be greater than 50 V. The amplifier may be capable of operating in other power ranges and under other operating supply voltages.

[0011] In another embodiment, an amplifier may include an amplifier cell, a stabilizing capacitor coupled between an output for the amplifier and a gate of the second transistor, and a biasing network for the amplifier cell. The amplifier cell includes a first transistor and a second transistor. The capacitance of the stabilizing capacitor may maintain a positive real output impedance for the amplifier over an operating frequency for the amplifier. The biasing network is coupled between the output of the amplifier and a gate for the second transistor. The first transistor may be a common source transistor, the second transistor may be a common gate transistor, and the first and second transistors may be coupled in a cascoded relationship. In another aspect, at least one of the first and second transistors includes a field plate.

[0012] The biasing network may include a resistor voltage divider network coupled between the output, the amplifier cell, and a ground for the amplifier. The biasing network may further include a supply transistor. A gate of the supply transistor may be coupled to the biasing node along the resistor voltage divider network, and a gate of the second transistor may be coupled to a source of the supply transistor. The amplifier cell may further include a resistor-capacitor network coupled between the gate of the second transistor and a ground for the amplifier. The amplifier may further include a stabilizing resistor coupled between the amplifier cell and the biasing network.

[0013] In another aspect of the embodiments, the amplifier may include a second amplifier cell. The second amplifier cell may be arranged in parallel with the amplifier cell with respect to the output. The biasing network may be coupled to the amplifier cell and the second amplifier cell for biasing both the amplifier cell and the second amplifier cell. The amplifier may further include a second biasing network. The biasing network and the second biasing network may be coupled to the amplifier cell and the second amplifier cell for biasing both the amplifier cell and the second amplifier cell.

[0014] In another embodiment, an integrated amplifier implemented on a semiconductor die includes an amplifier cell including a common source transistor and a common gate transistor in a cascoded relationship. The common gate transistor has a plurality of contacts formed on the semiconductor die. The integrated amplifier further includes a stabilization capacitor coupled between an output for the integrated amplifier and a gate of the common gate transistor. The stabilization capacitor may be formed between the plurality of contacts of the common gate transistor on the semiconductor die.

[0015] In another aspect of the embodiments, the stabilization capacitor includes a plurality of stabilization capacitors distributed among a plurality of contacts of the common-gate transistor. The stabilization capacitors may be distributed along an interconnection feed finger extending between the plurality of contacts of the common-gate transistor. The stabilization capacitor may include multiple stabilization capacitors, and the stabilization capacitors may be distributed along a plurality of interconnection feed fingers extending between the contacts of the common-gate transistor.

[0016] In another aspect of the embodiments, the common source transistor and the common gate transistor may be formed in a side-by-side arrangement on a semiconductor die. The common source transistor and the common gate transistor may be arranged in a side-by-side arrangement on the semiconductor die. The common source transistor and the common gate transistor may be arranged in a side-by-side arrangement on the semiconductor die with a bias interconnect supply line extending between the common source transistor and the common gate transistor.

[0017] The integrated amplifier may further include a biasing network for the amplifier cell, and a bias interconnect feed line coupled between the biasing network and the amplifier cell, the bias interconnect feed line extending between and separating the common source and common gate transistors in side-by-side arrangement on the semiconductor die.

[0018] The amplifier cell may further include a resistor-capacitor network for the common-gate transistor. The resistor-capacitor network may be coupled between the gate of the common-gate transistor and ground for the integrated amplifier. The resistor of the resistor-capacitor network may be formed in-line with and coupled to a bias interconnect supply line. The resistor-capacitor network may be coupled from the gate of the common-gate transistor to the source of the common-source transistor through a bias interconnect supply line that extends between and separates the common-source and common-gate transistors. The capacitor of the resistor-capacitor network may comprise a metal feature for the source of the common-source transistor.

[0019] In another embodiment, an integrated amplifier implemented on a semiconductor die includes an amplifier cell, a biasing network for the amplifier cell, and a bias interconnect feed line coupled between the biasing network and the amplifier cell. The amplifier cell may include a first transistor in juxtaposed relationship with a second transistor on the semiconductor die. The bias interconnect feed line may extend between and separate the first and second transistors on the semiconductor die.

[0020] The integrated amplifier may further include a stabilization capacitor coupled between the output for the integrated amplifier and the gate of the second transistor. The stabilization capacitor may be formed on the semiconductor die between the contacts of the second transistor. The stabilization capacitor may be distributed along interconnect feed fingers extending between the contacts of the second transistor.

[0021] The amplifier cell may further include a resistor-capacitor network for the second transistor. The resistor-capacitor network may be coupled between the gate of the second transistor and ground for the integrated amplifier. The resistor-capacitor network may be coupled from the gate of the second transistor to the source of the first transistor through a bias interconnect supply line that extends between and separates the first and second transistors. The resistor of the resistor-capacitor network may be formed in-line with and coupled to the bias interconnect supply line. The capacitor of the resistor-capacitor network may comprise a metal feature for the source of the first transistor.

[0022] In another aspect of the embodiments, the integrated amplifier may further include a second amplifier cell. The second amplifier cell may include a third transistor disposed on the semiconductor die in juxtaposition with the fourth transistor. A bias interconnect supply line may extend between and isolate the third and fourth transistors. The integrated amplifier may further include an isolation resistor coupled between the amplifier cell and the second amplifier cell. The isolation resistor may be formed and coupled in-line with the bias interconnect supply line.

[0023] In another embodiment, an integrated amplifier implemented on a semiconductor die has an amplifier cell and a biasing network for the amplifier cell. The biasing network includes two common drain transistors, two current source transistors, and a bias node located between the two common drain transistors and the two current source transistors. The two common drain transistors may have different channel widths, and the two current source transistors may have different channel widths. The gates of the two common drain transistors may be coupled to each other. The gates of the two current source transistors may be coupled to each other.

[0024] In another aspect of the embodiments, the integrated amplifier may further include a resistor voltage divider network coupled between the output for the amplifier cell and the gate of the two common drain transistors. The integrated amplifier may further include a capacitor coupled between the gate of the two common drain transistors and the bias node.

[0025] In another embodiment, a packaged amplifier device includes a device package with an input lead, an output lead, and a ground lead, a first integrated amplifier mounted on a first semiconductor die secured within the device package, a second integrated amplifier mounted on a second semiconductor die secured within the device package, and bond wires coupled between the first and second semiconductor die, and an output of the first integrated amplifier may be coupled in parallel with an output of the second integrated amplifier within the device package.

[0026] The packaged amplifier device may further include a third integrated amplifier mounted on a third semiconductor die secured within the device package. An output of the third integrated amplifier may be coupled in parallel with an output of the first integrated amplifier and an output of the second integrated amplifier within the device package. The packaged amplifier device may further include a bond wire coupled between the second and third semiconductor dies. The packaged amplifier device may further include a third semiconductor die with a first capacitor, a fourth semiconductor die with a second capacitor, and a bond wire coupled between the third and fourth semiconductor dies.

[0027] In another aspect of the embodiments, the power handling capacity of the packaged amplifier device may be greater than 2,000 W and the operating supply voltage for the packaged amplifier device may be greater than 50 V. The packaged amplifier may operate under other power ranges and other operating supply voltages.

[0028] In another embodiment, the packaged amplifier device includes a device package with package leads and an integrated amplifier mounted on a semiconductor die. The package leads may comprise three package leads disposed within a case. The semiconductor die may be secured within the device package. The integrated amplifier includes an amplifier cell. The amplifier cell includes a common source transistor and a common gate transistor in a cascoded relationship, and a biasing network is provided for the amplifier cell. An output for the integrated amplifier may be coupled to an output lead of the three package leads, and an input for the integrated amplifier may be coupled to an input lead of the three package leads.

[0029] In another aspect of the embodiments, the packaged amplifier device may further include a second integrated amplifier mounted on a second semiconductor die secured within the device package. An output of the integrated amplifier may be coupled in parallel with an output of the second integrated amplifier within the device package, and a bond wire may be coupled between the semiconductor die and the second semiconductor die. The packaged amplifier device may further include a second semiconductor die. The second semiconductor die may include a capacitor, and the second semiconductor die may be coupled to the integrated amplifier within the device package. In another aspect of the embodiments, the output lead may include a conductive flange of the device package, the semiconductor may be secured to the conductive flange using solder, and the second semiconductor die may be secured to the conductive flange using epoxy.

[0030] In another embodiment, a packaged amplifier device includes a device package having an input lead, an output lead, and a ground lead, a first integrated amplifier mounted on a first semiconductor die secured within the device package, a first bond wire coupled between an output bond pad and the output lead of the first integrated amplifier, and a second integrated amplifier mounted on a second semiconductor die secured within the device package, a second bond wire coupled between the output bond pad and the output lead of the second integrated amplifier, such that an output of the first integrated amplifier is coupled in parallel with an output of the second integrated amplifier, the packaged amplifier device further including a third bond wire coupled between the first semiconductor die and the second semiconductor die.

[0031] The packaged amplifier device further includes a third semiconductor die including a capacitor, a fourth bond wire coupled between the input lead and an input bond pad of the third semiconductor die, and a fifth bond wire coupled between an output bond pad of the third semiconductor die and an input bond pad of the first integrated amplifier.

[0032] Aspects of the present disclosure can be better understood with reference to the following drawings. It should be noted that elements in the figures are not necessarily drawn to scale, emphasis instead being placed upon illustrating the principles of the embodiments. In the drawings, like reference characters indicate the same or corresponding elements throughout the several views, but do not necessarily refer to the same elements. [Brief description of the drawings]

[0033] [Figure 1] FIG. 2 illustrates an example amplifier stage according to various embodiments described herein. [Diagram 2] FIG. 2 illustrates another example amplifier stage with a stabilizing capacitor in accordance with various embodiments described herein. [Diagram 3]FIG. 1 illustrates another example amplifier stage having a biasing network including a choke coil in accordance with various embodiments described herein. [Figure 4] FIG. 2 illustrates another example amplifier stage with a biasing network including a bias supply transistor in accordance with various embodiments described herein. [Diagram 5] FIG. 2 illustrates another example amplifier stage with bias stabilization resistors in accordance with various embodiments described herein. [Figure 6] FIG. 1 illustrates another example amplifier stage including an additional transistor breaker in accordance with various embodiments described herein. [Figure 7] FIG. 2 illustrates another example amplifier stage with bias stabilization resistors in accordance with various embodiments described herein. [Figure 8] FIG. 2 illustrates an example stacked amplifier in accordance with various embodiments described herein. [Figure 9] FIG. 2 illustrates an exemplary semiconductor die layout of a stacked amplifier in accordance with various embodiments described herein. [Figure 10] FIG. 10 illustrates a region of the layout shown in FIG. 9 in accordance with various embodiments described herein. [Figure 11] FIG. 11 is an enlarged view of an area indicated in FIG. 10 in accordance with various embodiments described herein. [Figure 12] FIG. 11 is another enlarged view of the area shown in FIG. 10 in accordance with various embodiments described herein. [Figure 13] FIG. 1 illustrates a packaged amplifier device in accordance with various embodiments described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] For certain applications, there is a need to develop radio frequency (RF) semiconductor amplifier devices that can operate at relatively high supply voltages. High supply voltages are utilized to achieve high output power, high gain, and high efficiency while also operating with high load impedances. The use of high load impedances also results in less matching losses at RF frequencies.

[0035] However, operating a semiconductor amplifier device at higher voltages can potentially reduce reliability due to higher peak electric field strengths and higher junction temperatures for the transistor amplifiers in the device. One approach to addressing these reliability issues is to use transistor circuit topologies that drop the supply voltage around two, three, or more transistors. In this type of circuit topology, the direct current (DC) voltage distributed to each of the transistors does not exceed the maximum rated voltage of any of the individual transistors. This approach can effectively reduce the peak electric field strengths and junction temperatures between the transistors. For example, with a cascode transistor circuit topology, the operating supply voltage can be doubled without increasing the peak electric field strengths or junction temperatures of the individual transistors.

[0036] In one transistor circuit topology scheme, for simplicity, the transistor circuit requires only the connections for a simple common-source transistor, and the transistor circuit behaves like such a simple common-source transistor. Such a circuit topology has a gate terminal, a drain terminal, and a ground terminal, and in this case no additional terminals or connections are used for biasing the circuit or for other purposes. The transistor circuit topology can also operate at high supply voltages without sacrificing reliability, performance, or requiring additional components, including off-chip components such as biasing networks of resistors and inductors.

[0037] One challenge in distributing the voltage drop using several transistor circuit topologies is maintaining stable operation. Among other approaches, stabilization resistors may be coupled in series with RF ground capacitors implemented on common-gate transistors in a cascode transistor circuit topology. However, stabilization resistors and resistor-capacitor networks may not be sufficient to ensure stabilization in all cases. For example, in circuits using transistors with field plates or with very small gate to drain capacitances, stabilization resistors and resistor-capacitor networks may not be sufficient to ensure stability over the entire range of operating voltages and frequencies.

[0038] In the above technical context, the embodiments described herein relate to a novel stackable transistor circuit topology for high voltage amplifiers. Some novel features and novel aspects of the embodiments are described at the circuit level, device layout level, and device packaging level. In one aspect, the amplifiers described herein can be biased at a relatively high voltage and still behave like a single common source transistor without sacrificing reliability, performance, or requiring additional off-chip components.

[0039] The amplifiers described herein require only one input, one output, and one ground terminal, even when several stacked transistor circuits are arranged in parallel for high power capacity. The stability of the integrated amplifier device is improved by both on-chip features and inter-chip features within the device's package. The packaged amplifier device does not require additional external biasing or additional off-chip components. These and several other aspects of the embodiments are described in more detail below.

[0040] FIG. 1 illustrates an amplifier stage 10 according to various embodiments described herein. As with the other amplifier stages illustrated in FIGS. 2-7, amplifier stage 10 is provided as a representative example of a high voltage transistor amplifier designed to be capable of stable operation at a relatively high operating supply voltage. The description of FIG. 1 is not exhaustive, and amplifier stage 10 may include other components not illustrated. Additionally, one or more components illustrated in FIG. 1 may be omitted in some cases. Amplifier stage 10 may be formed in a variety of ways, such as using separate components, as an integrated circuit device formed on one or more semiconductor dies, or as a combination of separate components and integrated circuit devices. Amplifier stage 10 may also be packaged in a suitable semiconductor package with or without other components, which will be described in more detail below.

[0041] In one embodiment, the transistors of amplifier stage 10 (and other transistors described herein) may be formed from Group III-V element semiconductor materials, including Group III nitrides (nitrides based on aluminum (Al), gallium (Ga), indium (In), and alloys thereof (AlGaIn)), gallium arsenide (GaAs), indium phosphide (InP), indium gallium phosphide (InGaP), aluminum gallium arsenide (AlGaAs), and combinations thereof. In other cases, the transistors of amplifier stage 10 may be formed from Group IV element semiconductor materials, including silicon (Si), germanium (Ge), and combinations thereof. When embodied as an integrated device, amplifier stage 10 may be formed using any suitable sequence of steps in a semiconductor manufacturing process.

[0042] As shown in Figure 1, amplifier stage 10 includes an input 12, an output 14, an amplifier cell 20, a biasing network 30, and a stabilization network 40. Amplifier cell 20 includes a common-source transistor 22 and a common-gate transistor 24. Common-source transistor 22 and common-gate transistor 24 are coupled in a cascode connection relationship. Biasing network 30 includes resistors 32, 34 arranged in a series connected voltage divider, and stabilization network 40 includes a capacitor 42 and a resistor 44.

[0043] A gate terminal of transistor 22 is coupled to input 12, a source terminal of transistor 22 is coupled to ground for amplifier stage 10, and a drain terminal of transistor 22 is coupled to a source of transistor 24. A drain of transistor 24 is coupled to output 14, and a gate of transistor 24 is coupled to ground through a stabilization network 40. A biasing network 30 is coupled between the output 14, amplifier cell 20, and ground for amplifier stage 10. A gate of transistor 24 is coupled to a bias node 36 of biasing network 30, which is located between resistors 32 and 34.

[0044] Transistors 22 and 24 may be embodied as enhancement mode field effect transistors (FETs), although other types of transistors may be utilized. Thus, when the gate of transistor 22 is grounded, transistor 22 (and amplifier stage 10) is designed to conduct no (or substantially no) current because the potential at the gate of transistor 22 is less than the pinch-off voltage. In one embodiment, transistors 22 and 24 may be embodied as Group III-V semiconductor FET devices of any suitable size (e.g., gate width), although the concepts described herein may be utilized with transistors made of other semiconductor materials.

[0045] Transistor 22 may include one or more field plates, e.g., a source-connected field plate, a gate-connected field plate, or both a source-connected field plate and a gate-connected field plate. Similarly, transistor 24 may include a source-connected field plate, a gate-connected field plate, or both a source-connected field plate and a gate-connected field plate. In other cases, transistors 22 and 24 do not include field plates. Transistors 22 and 24 may be matched (or substantially matched) in terms of size and power handling capabilities in one embodiment, although transistors 22 and 24 may be unequal in size relative to one another. Other aspects of transistors 22 and 24 are described in more detail below.

[0046] In operation, an operating supply voltage may be applied to the output 14 of the amplifier stage 10, and an RF input signal may be applied to the input 12 of the amplifier stage 10. In this condition, the amplifier cell 20 amplifies the RF input signal received at the input 12 and provides an amplified output signal at the output 14. The operating supply voltage of the amplifier stage 10 may be relatively high, for example, 50-150V or more, although lower potentials may be used in some cases. As a specific example, the operating supply voltage of the amplifier stage 10 may be 80V, 90V, 100V, 110V, 120V, 130V or more. The overall power handling capacity of the amplifier stage 10 may vary based on the size of the transistors 22, 24, among other factors. The power handling capacity of the amplifier stage 10 may vary based on the size of the transistors 22, 24, among other factors. With larger transistors 22, 24, the power handling capacity of the amplifier stage 10 may be large. Several stages similar to amplifier stage 10 may also be stacked together and coupled in parallel.

[0047] During operation of amplifier stage 10, biasing network 30 distributes and applies the operating supply voltage to transistors 22 and 24. The values ​​of resistors 32 and 34 are preferably selected so that the voltage at the source of transistor 24 is substantially equal to one-half the operating supply voltage applied to output 14. That is, when transistor 22 is turned off (i.e., when the gate voltage of transistor 22 is less than the pinch-off voltage of transistor 22), biasing network 30 distributes and applies the full operating supply voltage of amplifier stage 10 evenly (or substantially evenly) to transistors 22 and 24. Biasing network 30 helps maintain the drain-source voltages of transistors 22 and 24 within the maximum voltage ratings for these devices, even when the operating supply voltage for amplifier stage 10 is relatively high.

[0048] In one embodiment, the resistances of the resistors 32, 34 may be identical or nearly identical to each other, although the resistance of each of the resistors 32, 34 may vary compared to each other. The resistors 32, 34 may be of relatively high impedance, for example, resistances in the kilo-ohm or multi-kilo-ohm range. Using a high impedance for the resistors 32, 34 can avoid power losses and improve the overall efficiency of the amplifier stage 10. However, if a relatively large current needs to be delivered to bias the amplifier cell 20, the resistance of the resistors 32, 34 may be low. If the amplifier stage 10 is formed as an integrated device, the resistors 32, 34 may also be integrated on the same semiconductor die that contains the transistors 22, 24, thereby eliminating the need for external biasing or other off-chip components.

[0049] One concern for stable operation of the amplifier stage 10 is how the output impedance of the amplifier stage 10 (i.e., looking at the output 14) changes over the operating range of the amplifier stage 10. The operating supply voltage and operating frequency of the amplifier stage 10 are two operating factors that affect the stability of the amplifier stage 10, among others. Additionally, the transistors 22, 24 may optionally include a source field plate. Transistors that include a source field plate may exhibit a decreasing intrinsic drain-gate capacitance at high operating voltages. Thus, the transistor 24 may exhibit a low intrinsic drain-gate capacitance at high operating supply voltages. This condition may create a negative real output impedance at the output 14 under some operating conditions, which may cause the transistor 24 to become unstable. When tested with an RF input signal from 500 MHz to 50 GHz, the amplifier stage 10 was found to exhibit an increasing negative real output impedance when the operating supply voltage is gradually increased, especially at high operating supply voltages and high operating frequencies.

[0050] The stabilization network 40 can help avoid unstable operation of the amplifier stage 10. The stabilization network 40 includes a resistor-capacitor network coupled between the gate of the transistor 24 and the ground of the amplifier stage 10. In the embodiment shown in FIG. 1, the stabilization network 40 includes a capacitor 42 and a resistor 44 coupled in series. The capacitor 42 and the resistor 44 may be modified compared to the exemplary arrangement shown in FIG. 1. For example, the resistor 44 may be directly coupled to the gate of the transistor 24, and the capacitor 42 may be coupled between the resistor 44 and the ground for the amplifier stage 10. The stabilization network 40 may include other resistor-capacitor networks, as appropriate.

[0051] Capacitor 42 may be utilized to increase the stability of amplifier stage 10 over the operating conditions of amplifier stage 10. Resistor 44 may also be utilized to increase the stability of amplifier stage 10 over the operating frequency range of amplifier stage 10. The capacitance of capacitor 42 may be selected, for example, to a value between 0.2 pF / mm and 0.10 pF / mm, although other capacitances may be used. In one case, the capacitance of capacitor 42 was selected to be 0.6 pF to test the operation of amplifier stage 10. The resistance of resistor 44 may be selected, for example, to a value between 1 Ωmm and 200 Ωmm, although other resistances may be used.

[0052] The resistance of resistor 44 was varied from 10 Ω to 100 Ω over an operating frequency range of 500 MHz to 50 GHz and an operating supply voltage range of 25 V to over 100 V. It was found that amplifier stage 10 exhibits increased stability at higher values ​​of resistor 44. The performance of amplifier stage 10 is suitable to allow amplification of a wide range of input frequencies over a wide range of operating supply voltages while presenting a good output impedance at output 14. However, amplifier stage 10 can in some cases exhibit a negative real output impedance, especially at higher operating frequencies and supply voltages, even with a relatively high value of resistor 44.

[0053] Referring to another aspect, FIG. 2 shows amplifier stage 50 with an additional stabilizing capacitor 60. Amplifier stage 50 shown in FIG. 2 is similar to amplifier stage 10 shown in FIG. 1, but further includes stabilizing capacitor 60. Stabilizing capacitor 60 may be utilized to address the reduction of the intrinsic drain-gate capacitance of transistors with field plates at high operating voltages. Stabilizing capacitor 60 is coupled between the drain and gate of transistor 24. The capacitance of capacitor 60 may be selected to a value of, for example, 0.01 pF / mm to 0.5 pF / mm, although other capacitances may be used. The capacitance of capacitor 60 may be selected based on the operating supply voltage for amplifier stage 10, the size of transistor 24, the type and size of any field plate (if any) used with transistor 24, and other factors. In one case, the capacitance of capacitor 60 was selected to be 0.25 pF to test the operation of amplifier stage 50.

[0054] Over an operating frequency range of 500 MHz to 50 GHz and an operating supply voltage range of 100V or greater, the performance of amplifier stage 50 is suitable to enable amplification of a wide range of input frequencies over a wide range of operating supply voltages while presenting good output impedance at output 14. When capacitor 60 was selected to be 0.25 pF, amplifier stage 50 only exhibited a positive real output impedance even at relatively high operating frequencies and supply voltages (including 50 GHz and 100V, respectively).

[0055] Other aspects of the embodiments include modifications of the biasing network 30 shown in Figures 1 and 2. The series connected voltage divider provided by resistors 32, 34 in the biasing network 30 may exhibit drawbacks in some operating conditions. For example, when the operating supply voltage is increasing, the biasing network 30 conducts relatively more current, thereby reducing efficiency. The RF impedance of the biasing network 30 also loads the transistor 24. One approach to addressing these concerns is shown in Figure 3.

[0056] FIG. 3 illustrates an amplifier stage 70 in which a biasing network 80 includes a choke coil 82. The amplifier stage 70 illustrated in FIG. 3 is similar to the amplifier stage 50 illustrated in FIG. 2, but further includes a choke coil 82 as part of the biasing network 80. The choke coil 82 may be utilized to provide a larger RF impedance to the biasing network 80 as compared to the biasing network 30. The resistances of the resistors 32, 34 may also be increased together to provide a larger DC impedance to the biasing network 80. The performance of the amplifier stage 70 is suitable to enable amplification of a wide range of input frequencies with relatively high efficiency over a wide range of operating supply voltages, especially at high operating supply voltages.

[0057] However, amplifier stage 70 may also exhibit drawbacks for certain applications and operating conditions. For example, choke 82 is an extra component that may limit the overall bandwidth of amplifier stage 70. It may be necessary to implement choke 82 as an off-chip component, which may be undesirable for certain applications. It may be difficult for biasing network 80 to provide a sufficiently large forward gate current to transistor 24 under high RF drive because high resistances are selected for resistors 32, 34. One approach to addressing these concerns is shown in FIG. 4.

[0058] FIG. 4 illustrates an amplifier stage 90 in which a biasing network 92 includes a bias supply transistor 94. The amplifier stage 90 illustrated in FIG. 4 is similar to the amplifier stage 50 illustrated in FIG. 2, however, the biasing network 92 provides certain improvements over the biasing networks 30 and 80, particularly at higher operating supply voltages and RF drives. As illustrated in FIG. 4, the drain of the bias supply transistor 94 is coupled to the output 14. The source of the transistor 94 is coupled to a resistor 96, which is coupled to ground for the amplifier stage 90. The gate of the transistor 94 is coupled to the bias node 36 between the resistors 32 and 34. Additionally, the gate of the transistor 24 is coupled to a bias node 98 at the source of the transistor 94, rather than being coupled to the bias node 36.

[0059] Transistor 94 may be embodied as a FET transistor formed using the same semiconductor materials and manufacturing steps used to form transistors 22 and 24. However, transistor 94 may have significantly smaller dimensions (e.g., channel width) than transistors 22 and 24 because transistor 94 is not utilized as an amplifier. For example, transistor 94 may be approximately 40-80 times smaller than transistors 22 and 24 (i.e., approximately 1 / 40-1 / 80 the size of transistors 22 and 24).

[0060] Transistor 94 presents both a high RF impedance and a high DC impedance at output 14. At the same time, transistor 94 can efficiently deliver current to transistor 24 even at high operating supply voltages and under high RF drive. Also, high resistances can be selected for resistors 32, 34 without adversely affecting their ability to deliver drive current to transistor 24. By way of example, resistors 32, 34 may be selected in the range of several hundred kilohms.

[0061] 5 illustrates another exemplary amplifier stage 90A that includes bias stabilization resistor 45. Amplification stage 90A is similar to amplifier stage 90 shown in FIG. 4, but further includes bias stabilization resistor 45. Bias stabilization resistor 45 is coupled between a bias node 98 at the source of bias supply transistor 94 and the gate of transistor 24.

[0062] The above concepts can be extended to accommodate even higher operating supply voltages. Figure 6 shows an amplifier stage 100 that includes an additional transistor stage that can accommodate higher operating supply voltages. Amplifier stage 100 includes an input 12, an output 14, an amplifier cell 110, a biasing network 120, a first stabilization network 130, a second stabilization network 140, a first stabilization capacitor 160, and a second stabilization capacitor 162.

[0063] The amplifier cell 110 includes a common-source transistor 112, a first common-gate transistor 114, and a second common-gate transistor 116 in a cascode arrangement. The biasing network 120 includes resistors 121-123, a first bias supply transistor 124, a second bias supply transistor 125, and a resistor 126 arranged in a series connected voltage divider. The first stabilization network 130 includes a capacitor 131 and a resistor 132, and the second stabilization network 140 includes a capacitor 141 and a resistor 142.

[0064] The gate terminal of transistor 112 is coupled to the input 12, the source terminal of transistor 112 is coupled to ground for the amplifier stage 100, and the drain terminal of transistor 112 is coupled to the source of transistor 114. The drain of transistor 114 is coupled to the source of transistor 116, and the gate of transistor 114 is coupled to ground through a first stabilization network 130. The drain of transistor 116 is coupled to the output 14, and the gate of transistor 116 is coupled to ground through a second stabilization network 140. A biasing network 120 is coupled between the output 14, the amplifier cell 110, and ground for the amplifier stage 100. For biasing purposes, the gate of transistor 116 is coupled to a bias node at the source of transistor 124 in biasing network 30, and the gate of transistor 114 is coupled to a bias node at the source of transistor 125 in biasing network 30.

[0065] Transistors 112, 114, and 116 may be embodied as enhancement mode FETs for use as a highly efficient power amplifier, although other types of transistors may be used. Thus, when the gate of transistor 112 is grounded, transistor 112 (and amplifier stage 100) is designed to conduct no (or substantially no) current because the potential at the gate of transistor 112 is less than the pinch-off voltage. Transistors 112, 114, and 116 may be embodied as Group III-V semiconductor FET devices of any suitable size (e.g., gate width), although the concepts described herein may be utilized with transistors formed of other semiconductor materials.

[0066] Transistors 112, 114, and 116 may include one or more field plates, e.g., a source-connected field plate, a gate-connected field plate, or both a source-connected field plate and a gate-connected field plate. In other cases, transistors 112, 114, and 116 do not include field plates. Transistors 112, 114, and 116 may be matched (or substantially matched) in size and power handling capability in one embodiment, although transistors 112, 114, and 116 may vary in size compared to each other. Transistors 112, 114, and 116 may vary in size compared to the transistors of amplifier cell 20 shown in Figures 1-4. In some cases, the sum of the sizes of transistors 112, 114, and 116 may be greater than the sum of the sizes of transistors 22 and 24. In other cases, the sum of the sizes of transistors 112, 114, and 116 may be less than the sum of the sizes of transistors 22 and 24. Overall, amplifier stage 100 may be designed for use with high operating supply voltages because the operating supply voltage applied at output 14 may be distributed across transistors 112, 114, and 116.

[0067] In operation, an operating supply voltage may be applied to output 14 of amplifier stage 100, and an RF input signal may be applied to input 12 of amplifier stage 100. In this state, amplifier stage 100 amplifies the RF input signal received at input 12 and provides an amplified output signal at output 14. The operating supply voltage of amplifier stage 100 may be higher than the operating supply voltage of amplifier stage 10, since amplifier stage 100 includes more transistors than amplifier cells 20. For example, the operating supply voltage of amplifier stage 10 may be 100-150V or higher, although amplifier stage 100 is not limited to use over any particular voltage range. In particular embodiments, the operating supply voltage of amplifier stage 10 may be 100V, 110V, 120V, 130V, 140V, 150V or higher. In some cases, the gain and total power handling capacity of amplifier stage 100 may be higher than the gain and total power handling capacity of amplifier stage 10. Amplification stage 100 may also be connected in parallel with one, two, three, four or more amplification stages of the same (or similar design) to further increase power handling capacity.

[0068] During operation of the amplifier stage 100, the biasing network 120 distributes an operating supply voltage to the transistors 112, 114, and 116. The values ​​of the resistors 121, 122, and 123 may be selected such that the voltage at the source of the transistor 116 is substantially equal to two-thirds (2 / 3) of the operating supply voltage applied to the output 14. The resistors 121, 122, and 123 may also be selected such that the voltage at the source of the transistor 114 is substantially equal to one-third (1 / 3) of the operating supply voltage applied to the output 14. In one embodiment, the resistances of the resistors 121, 122, and 123 may be identical or nearly identical to one another, although the resistances of each of the resistors 121, 122, and 123 may vary compared to one another. The resistors 121, 122, 123 may be of relatively high impedance, for example resistance in the hundreds of kilohms range. The use of high impedance resistors 121, 122, 123 may avoid power losses and improve the overall efficiency of the amplifier stage 100.

[0069] Amplifier stage 100 may utilize stabilizing capacitors 160, 162 to address the reduction of the intrinsic drain-gate capacitance of transistors with field plates at relatively high operating voltages. A first stabilizing capacitor 160 is coupled between the source of transistor 116 and the gate of transistor 114. A second stabilizing capacitor 162 is coupled between the drain and gate of transistor 116. The capacitances of stabilizing capacitors 160, 162 may be selected based on the operating supply voltage for amplifier stage 100, the size of transistors 114, 116, the type and size of any field plates (if any) used with transistors 114, 116, and other factors.

[0070] 7 illustrates another exemplary amplifier stage 100A including a first bias stabilizing resistor 133 and a second bias stabilizing resistor 143. The amplifier stage 100A is similar to the amplifier stage 100 illustrated in FIG. 6, but further includes resistors 133 and 143. The first bias stabilizing resistor 133 is coupled between the source of the second bias supply transistor 125 and the gate of the transistor 114. The second bias stabilizing resistor 143 is coupled between the source of the first bias supply transistor 124 and the gate of the transistor 116.

[0071] FIG. 8 illustrates an exemplary stacked amplifier 200 for various embodiments described herein. The stacked amplifier 200 is provided as a representative example of a high-voltage stacked transistor amplifier designed for stable operation at a relatively high operating supply voltage and a relatively high power capacity. The description of FIG. 8 is not exhaustive, and the stacked amplifier 200 may include other components not shown in FIG. 8. Additionally, one or more components shown in FIG. 8 may be omitted in some cases. The stacked amplifier 200 may be formed in various ways, such as using separate components, as an integrated circuit device formed on one or more substrates, or as a combination of separate components and integrated circuit devices. In a preferred embodiment, the stacked amplifier 200 is formed and implemented on a single semiconductor die. The stacked amplifier 200 may also be packaged in a suitable semiconductor device package with or without other components, which will be described in more detail below.

[0072] The stacked amplifier 200 includes, among other things, amplifier stages 210-214 arranged in a parallel configuration between the input and output of the stacked amplifier 200. Each of the amplifier stages 210-214 is similar to the amplifier stage 90A shown in FIG. 5. In other cases, the stacked amplifier 200 can be formed using amplifier stages 10, 50, 70, 90, 100, or 100A. Although five amplifier stages 210-214 are shown in FIG. 8, the stacked amplifier 200 is not limited to any particular number of amplifier stages. In other cases, the stacked amplifier 200 can include six, seven, eight or more amplifier stages in a stacked parallel arrangement, with FIG. 9 showing an exemplary layout of six amplifier stages. Alternatively, the stacked amplifier 200 may have four or fewer amplifier stages, or may omit one or more of the amplifier stages 210-214.

[0073] The stacked amplifier 200 further includes, among other things, a number of inputs 220-224 coupled to the inputs of the amplifier stages 210-214, respectively. Isolation resistors 230-233 are coupled between the inputs 220-224 as shown in Figure 8 to stabilize the operation (and potential) of the amplifier stages 210-214 relative to one another. The isolation resistors 230-233 may have a relatively small resistance, for example, less than 100 Ω, less than 50 Ω, or less than 10 Ω, although any suitable resistance may be used.

[0074] The stacked amplifier 200 further includes an output 226, with all of the outputs of the amplifier stages 210-214 being coupled to the output 226. The stacked amplifier 200 further includes stitch pads 227, 228 and stitch resistors 237, 238. The stitch pads 227, 228 may be used to electrically couple the stacked amplifier 200 to another stacked amplifier in parallel, as will be described in more detail below. The stitch resistors 237, 238 are similar to the isolation resistors 230-233. As will be described with reference to FIG. 8 below, the inputs 220-224 may be embodied as bond pads for anchoring bond wires for electrical connections. The output 226 and stitch pads 227, 228 may also be embodied as bond pads for anchoring bond wires.

[0075] The stacked amplifier 200 further includes a biasing network 240. The biasing network 240 provides a bias voltage on a bias node 258, which is coupled to each of the amplifier stages 211-214 via isolation resistors 261-264 along a bias interconnect feed line 260. Thus, the biasing network 240 provides a bias voltage to the transistor 24 in the amplifier stage 210, and the biasing network 240 also provides a bias voltage to each of the amplifier stages 211-214, among other ways of thinking. In some cases, the stacked amplifier 200 may include two or more biasing networks similar to the biasing network 240. With reference to FIG. 8, for example, the stacked amplifier 200 may include an additional biasing network above the amplifier 214 (e.g., above the plane of the drawing), which may also be coupled to the bias interconnect feed line 260.

[0076] The biasing network 240 includes resistors 241, 242, resistor 243, transistors 250-253, and capacitor 245 arranged in a voltage divider. The source of transistor 250 is coupled to output 226 via resistor 243. The drain of transistor 250 is coupled to the source of transistor 251, the drain of which is coupled to bias node 258 and the source of transistor 252. The drain of transistor 252 is coupled to the source of transistor 253, the drain of which is coupled to ground for stacked amplifier 200. The gates of transistors 250, 251 are both coupled to capacitor 245, which is also coupled to bias node 258. The gates of transistors 252, 253 are both coupled to ground for stacked amplifier 200.

[0077] Like the other biasing networks described herein, biasing network 240 is designed so that the voltage at the source of transistor 24 is half the operating supply voltage applied to output 226 when transistor 22 is turned off. The values ​​of resistors 241-243 may be selected to achieve the correct bias voltage at bias node 258 for that equal (or substantially equal) voltage bias between transistors 22 and 24. Thus, when transistor 22 is turned off (i.e., when the gate voltage of transistor 22 is lower than the pinch-off voltage for transistor 22), biasing network 240 distributes substantially the full operating supply voltage equally to transistors 22 and 24. In addition, capacitor 245 provides a low RF impedance at the gate-source junction of transistor 251. Capacitor 245 prevents forward conduction of transistors 250 and 251 under the RF voltage swing at the output of amplifier stage 210. Thus, capacitor 245 helps maintain a constant DC voltage at node 258 over the RF input and output power ranges for amplifier stage 210 .

[0078] Biasing network 240 is designed for particular stability and efficiency when used with high operating supply voltages, such as from about 80 V to 150 V or higher. At high operating supply voltages, the junction temperature of transistors 250-253 may be a concern, and transistors 250-253 are designed to account for and avoid damaging junction temperatures.

[0079] Transistors 250 and 251 are connected as a common drain or source follower, and transistors 252 and 253 are connected as current sources. In operation, the current flowing through transistor 250 is the same as the current flowing through transistor 251, and the current flowing through transistor 252 is the same as the current flowing through transistor 253. Nearly half of the total operating supply voltage applied at output 226 is dropped across transistors 250 and 251, and nearly half of that voltage is dropped across transistors 252 and 253.

[0080] However, the voltage drops across transistors 250 and 251 are not necessarily the same. In one design, the voltage drop across transistor 250 is greater than the voltage drop across transistor 251 because the drain-source voltage across transistor 251 is approximately the pinch-off voltage of transistor 251. The bulk (and balance) of the voltages across the pair of transistors 250 and 251 is dropped across transistor 250. Similarly, the voltage drops across transistors 252 and 253 are not necessarily the same. The voltage drop across transistor 252 is greater than the voltage drop across transistor 253 because the drain-source voltage across transistor 253 is approximately the pinch-off voltage of transistor 253. The bulk (and balance) of the voltages across the pair of transistors 252 and 253 is dropped across transistor 252. Thus, the power handling of transistors 250 and 252 is greater than the power handling of transistors 251 and 253, and the junction temperatures of transistors 250 and 252 are of great concern.

[0081] Taking into account the above-mentioned operational concerns, the size (e.g., total gate width) of transistor 250 may be larger than the size of transistor 251, and the size of transistor 252 may be larger than the size of transistor 253. Thus, the current density in transistor 251 may be larger than the current density in transistor 250, and the current density in transistor 253 may be larger than the current density in transistor 252. The junction temperatures of transistors 250-253 are still maintained within suitable operating parameters because the total power handling of each of transistors 250-253 is balanced with its respective size. Additional aspects of transistors 250-253 and biasing network 240 are described below with reference to FIG. 11.

[0082] In operation, an operating supply voltage may be applied to the output 226 of the stacked amplifier 200, and the same RF input signal may be applied to each of the inputs 220-224. In this state, the amplifier stages 210-214 amplify the RF input signal and provide an amplified output signal at the output 226. The operating supply voltage of the stacked amplifier 200 may be relatively high, for example, 50-150V or more. When implemented on a semiconductor die, the total power handling capacity of the stacked amplifier 200 may be, as one example, 400W-600W depending on the number of amplifier stages, the size of the die, the layout density on the die, and other factors. As a specific example, the power handling capacity of the stacked amplifier 200 may be 400W, 450W, 500W, 550W, 600W or more. However, the total power handling capacity of the stacked amplifier 200 is not limited to any particular range. Multiple stacked amplifiers similar to stacked amplifier 200, each formed and packaged on a separate semiconductor die, may also be arranged together in a single semiconductor package to reach even higher power ratings. An embodiment in which several stacked amplifiers are packaged together in a single semiconductor package is described below with reference to FIG.

[0083] Referring to another aspect, FIG. 9 illustrates an example semiconductor die layout 300 for stacked amplifier 200. Layout 300 is provided as a representative example of how stacked amplifier 200 shown in FIG. 8 can be arranged on semiconductor die 301. The description of FIG. 9 is not exhaustive, and layout 300 may have other features not shown in FIG. 9. Additionally, one or more layout features shown in FIG. 9 may be omitted in some cases. Semiconductor die 301 may include a Si substrate, a silicon carbide (SiC) substrate, or another suitable substrate having a gallium nitride material deposited on the substrate. Transistors and other active devices may be formed in the gallium nitride material. In other cases, semiconductor die 301 may have a Si substrate, and transistors and other active devices may be formed in the Si substrate. However, the concepts described herein are not limited to the use of any particular variety of substrates or semiconductor materials, and such concepts may be extended to be used with a wide variety of semiconductor materials.

[0084] 9, amplifier stages 210-215 are positioned or stacked in a side-by-side arrangement from left to right on the page. Transistors 22 and 24 of amplifier stage 210 are also positioned in a side-by-side arrangement from bottom to top on the page. Biasing network 240 is positioned to the left of amplifier stage 210, and a similar biasing network 270 is positioned to the right of amplifier stage 215. Bias interconnect feed line 260 extends across layout 300 from biasing network 240 to biasing network 270 and separates transistors 22 and 24 from each other.

[0085] When implemented on a semiconductor die 301, the total power handling capacity of the stacked amplifier 200 may be, by way of example, 400W to 600W, depending on the size of the die 301, the layout density on the die 301 (e.g., the number and dimensions of the amplifier stages 210-215), and other factors. The semiconductor die 301 may be connected in parallel to additional dies containing many stacked amplifiers in one device package to achieve high power handling.

[0086] Figure 9 also shows a number of bond pads around the periphery of layout 300. Inputs 220-225 for amplifier stages 210-215 are shown as bond pads in Figure 9. Inputs 220-225 are electrically isolated by isolation resistors 230-234. Output 226 for amplifier stages 210-215 is also shown as a bond pad. No isolation resistors are incorporated between the outputs of each of amplifier stages 210-215 and the bond pad for output 226 in the embodiment shown in Figure 9. Instead, the outputs of amplifier stages 210-215 are all directly coupled to the bond pad for output 226.

[0087] Stitch pads 227 and 228 are also shown as bond pads on the left side of layout 300 in FIG. 9. Stitch resistor 237 separates stitch pad 227 from the bond pad for input 220. Similarly, stitch resistor 238 separates stitch pad 228 from the bond pad for output 226. Layout 300 further includes stitch pads 227A and 228A on the right side, which are similar to stitch pads 227 and 228. Stitch pads 227, 228, 227A, and 228A can be used to electrically couple semiconductor die 301 to one or two other semiconductor dies that include stacked amplifiers similar to stacked amplifier 200. The other semiconductor dies may be positioned in a side-by-side relationship with semiconductor die 301 in a device package. Bond wires can be used to couple stitch pads 227, 228, 227A, and 228A to similar stitch pads on other semiconductor dies. An embodiment in which several stacked amplifiers are packaged together in a single semiconductor device package is described below with reference to FIG.

[0088] Figure 10 illustrates a region of the layout 300 shown in Figure 9 according to various embodiments described herein. The features of the layout 300 illustrated in Figures 10 and 11 and 12 are representative and not drawn to scale. Individual features described below may vary in size and shape compared to the features illustrated without departing from the spirit and advantages of the embodiments.

[0089] From left to right on the page, the bond pad for input 220 is electrically coupled to the gate of transistor 22. Transistor 22 is positioned in a side-by-side arrangement with transistor 24, with bias interconnect supply line 260 extending between and isolating transistors 22 and 24. Biasing network 240 is centered above transistors 22 and 24. A number of metal interconnects 302 extend from the drain of transistor 22, over (or under) bias interconnect supply line 260, to the source of transistor 24. The drain of transistor 24 is electrically coupled to the bond pad for output 226.

[0090] 10, the layout of transistor 22 includes interdigitated source features 310, gate features 312, and drain features 314. The source features 310, gate features 312, and drain features 314 extend in multiple rows within layout 300. Although not individually visible in FIG. 10, source features 310 may include a source contact disposed on a top surface of semiconductor die 301, with a source metal feature (e.g., a source metal layer, a source field plate, or a portion of a source field plate, etc.) contacting a surface of semiconductor die 301 in a source region of transistor 22. Gate feature 312 may include a gate contact disposed on a top surface of semiconductor die 301, with a gate metal feature (e.g., a gate metal layer, a gate field plate, or a portion of a gate field plate, etc.) contacting a surface of semiconductor die 301 in a gate region of transistor 22. The drain feature 314 may include a drain contact provided on the top surface of the semiconductor die 301, with a drain metal feature (e.g., a drain metal layer, a drain field plate, or a portion of a drain field plate, etc.) in contact with the surface of the semiconductor die 301 in the drain region of the transistor 22.

[0091] The layout of transistor 24 includes interdigitated drain features 320, gate features 312, and source features 324. Drain features 320, gate features 312, and source features 324 extend in multiple rows within layout 300. Although not individually visible in FIG. 10, drain feature 320 may include a drain contact disposed on a top surface of semiconductor die 301, with a drain metal feature (e.g., a drain metal layer, a drain field plate, or a portion of a drain field plate, etc.) contacting a surface of semiconductor die 301 in a drain region of transistor 24. Gate feature 322 may include a gate contact disposed on a top surface of semiconductor die 301, with a gate metal feature (e.g., a gate metal layer, a gate field plate, or a portion of a gate field plate, etc.) contacting a surface of semiconductor die 301 in a gate region of transistor 24. The source feature 324 may include a source contact provided on the top surface of the semiconductor die 301, with a source metal feature (e.g., a source metal layer, a source field plate, or a portion of a source field plate, etc.) in contact with the surface of the semiconductor die 301 within the four-source region of the transistor 24.

[0092] Other components of stacked amplifier 200 are also shown in layout 300. In particular, capacitor 42 and resistor 44 are shown coupled between the gate of transistor 24 and ground. Additionally, stabilization capacitor 60 is shown coupled between the drain and gate of transistor 24. As will be explained in more detail below, capacitor 42, resistor 44, and stabilization capacitor 60 are each distributed among various features of transistors 22, 24 in layout 300 (between two features, and between three or more features).

[0093] FIG. 11 is an expanded view of the location area shown in FIG. 10. FIG. 11 includes a depiction of biasing network 240. Biasing network 240 provides a bias voltage to bias node 258, which is coupled along bias interconnect feed line 260 through isolation resistor 261 to, among other things, transistor 24. Biasing network 240 includes, among other components, resistors 241, 242, transistors 250-253, and capacitor 245 arranged in a voltage divider. Biasing network 240 is designed to be capable of operating at high operating supply voltages, for example, at operating supply voltages of about 80V to 150V or more. At high operating supply voltages, junction temperatures of transistors 250-253 may be a concern, and transistors 250-253 are designed to account for and avoid damaging junction temperatures.

[0094] Transistors 250 and 251 are connected as a common drain or source follower, and transistors 252 and 253 are connected as current sources. In operation, the current flowing through transistor 250 is the same as the current flowing through transistor 251, and the current flowing through transistor 252 is the same as the current flowing through transistor 253. Nearly half of the total operating supply voltage of biasing network 240 is dropped across transistors 250 and 251, and nearly half of that voltage is dropped across transistors 252 and 253.

[0095] However, the voltage drops across transistors 250 and 251 are not necessarily the same. The voltage drop across transistor 250 is greater than the voltage drop across transistor 251 because the drain-source voltage across transistor 251 is approximately the pinch-off voltage of transistor 251. The bulk (and balance) of the voltage drops across transistor 250. Similarly, the voltage drops across transistors 252 and 253 are not necessarily the same. The voltage drop across transistor 252 is greater than the voltage drop across transistor 253 because the drain-source voltage across transistor 253 is approximately the pinch-off voltage of transistor 253. The bulk (and balance) of the voltage drops across transistor 252. Thus, the power handled by transistors 250 and 252 is greater than the power handled by transistors 251 and 253, and the junction temperatures of transistors 250 and 252 are of major concern.

[0096] Taking into account the above-mentioned operational concerns, the size of transistor 250 (e.g., measured over a gate width "W1" of all gate fingers in transistor 250) is greater than the size of transistor 251. Similarly, the size of transistor 252 (e.g., measured over a gate width "W2" of all gate fingers in transistor 252) is greater than the size of transistor 253. Thus, the current density of transistor 251 is greater than the current density of transistor 250, and the current density of transistor 253 is greater than the current density of transistor 252. The junction temperatures of transistors 250-253 are still maintained within suitable operating parameters because the total power handling of each of transistors 250-253 is balanced with its respective size.

[0097] As discussed above, biasing network 240 provides a bias voltage across bias node 258. The bias voltage is coupled along bias interconnect supply line 260 to, among other things, transistor 24. A number of resistors are coupled or inserted in-line along bias interconnect supply line 260 as part of layout 300. For example, isolation resistor 261 is inserted in-line along bias interconnect supply line 260. Other isolation resistors 262-264 (see FIG. 8), not visible in FIG. 11, are also inserted between amplifier stages 210-215 along bias interconnect supply line 260.

[0098] Additionally, resistor 44 is coupled along bias interconnect supply line 260 between bias interconnect supply line 260 and capacitor 42. Capacitor 42 and resistor 44 are components of stabilization network 40, which is coupled between the gate of transistor 24 and ground (see FIGS. 5 and 8). In layout 300, bias interconnect supply line 260 separates transistors 22 and 24 (particularly separating the contacts of these transistors from one another), but stabilization network 40 for transistor 24 is coupled from the gate of transistor 24 across bias interconnect supply line 260 to a feature of transistor 22.

[0099] 11, capacitor 42 is positioned at and partially integrated with the source metal feature of transistor 22. The source of transistor 22 is coupled to ground through in-source via 330. In-source via 330 passes through semiconductor die 301 and electrically couples the source metal layer of transistor 22, located on the top side of semiconductor die 301, to a metal ground plane, located on the back side of semiconductor die 301.

[0100] Capacitor 42 is formed as a metal-insulator-metal (MIM) capacitor on semiconductor die 301, and includes a bottom metal layer, a dielectric layer on the bottom metal layer, and a source metal layer on the dielectric layer. By way of example, the dielectric layer of capacitor 42 may be silicon nitride (Si3N4), silicon dioxide, tantalum pentoxide (Ta2O5), silicon oxynitride (SiO x N y ), or other suitable dielectric. The source metal layer of transistor 22 is electrically coupled to a ground metal plane located on the rear side of semiconductor die 301 by in-source vias 330. Referring back to FIG. 10, resistors 44 are shown distributed along bias interconnect feed line 260 into a number of isolated resistive elements. Capacitors 42 are also shown distributed between source features 310 of transistor 22.

[0101] Resistor 44, isolation resistor 261, and other resistors formed on semiconductor die 301 may be formed using nichrome, tantalum nitride, tungsten silicide, or other suitable materials. Resistors may also be formed as bulk resistors via implanted or diffused dopants, or otherwise. Locating resistor 44 and isolation resistor 261, among others, with bias interconnect supply line 260 provides a compact and efficient way to integrate the components of amplifier stage 210 in layout 300. Similarly, locating capacitor 42 with the source metal layer of transistor 22 also provides a compact and efficient way to integrate the components of amplifier stage 210 in layout 300.

[0102] Figure 12 is another expanded view of the area shown in Figure 10. Figure 12 shows isolation resistors 261, 262 inserted in-line along bias interconnect feed line 260. Because resistor 44 is formed from resistors 44A-44C, the dispersive nature of resistor 44 is also shown in Figure 12. Similarly, because capacitor 42 is formed from capacitors 42A-42C, the dispersive nature of capacitor 42 is also shown in Figure 12.

[0103] Additional features of bias interconnect feed line 260 are also shown in Figure 12. In particular, bias interconnect feed line 260 is also coupled to bias feed line fingers 260A, 260B that extend laterally between contacts of transistor 24 in the same direction as the channel width of transistor 24. Because stabilization capacitor 60 is formed by capacitors 60A-60F (see Figure 8), the dispersive nature of such stabilization capacitor 60 is also shown in Figure 12.

[0104] Capacitors 60A-60C are formed by bias feed line finger 260A as a single-sided metal layer, a layer of dielectric deposited on bias feed line finger 260A, and another metal layer deposited on the dielectric layer, and are coupled to the drain of transistor 24 and the bond pad of output 226. Capacitors 60D-60F are formed by bias feed line finger 260B as a single-sided metal layer, a layer of dielectric deposited on bias feed line finger 260B, and another metal layer deposited on the dielectric layer, and are coupled to the drain of transistor 24 and the bond pad of output 226. Thus, stabilization capacitors 60 are formed on semiconductor die 301 between the contacts of transistor 24. The distribution of stabilization capacitors 60 between the contacts of transistor 24 provides a compact and efficient way to integrate the components of amplifier stage 210 in layout 300.

[0105] FIG. 13 illustrates a packaged amplifier device 400 according to various embodiments described herein. The depiction of the packaged amplifier device 400 in FIG. 13 is representative and not drawn to scale. Individual features described below may vary in size and shape compared to the features shown without departing from the spirit and advantages of the embodiments. The packaged amplifier device 400 includes multiple semiconductor dies secured within a semiconductor package 410. The semiconductor package 410 may be embodied as a ceramic air cavity package, a polymer overmolded air cavity package, or a similar air cavity package. However, the device packaging concepts described below are not limited to use with any particular type of semiconductor package, and other types of packages may be used.

[0106] The semiconductor package 410 has a conductive flange 411, a frame 412, and leads 420-422. The leads 420-422 are conductive and may be used for input and output signals. The conductive flange 411 may be made of copper, molybdenum, copper-molybdenum laminate, or other material with suitable conductive and thermal properties. The conductive flange 411 may be secured to a printed circuit board or other area connectable to a larger circuit using solder, screws, or other fasteners. Because the conductive flange 411 is conductive, it may be considered another lead of the semiconductor package 410 and is typically utilized as a ground lead. The conductive flange 411 may have eyelets for fasteners, as shown in FIG. 13. The eyelets may be omitted in other cases, such as when solder is used to secure the conductive flange 411 to a printed circuit board or other substrate.

[0107] Frame 412 encloses an air cavity within semiconductor package 410, and a top surface 430 of conductive flange 411 is exposed within frame 412. Multiple columns 440-443 of semiconductor dies are secured within frame 412 to top surface 430 of conductive flange 411. As shown in FIG. 13, column 440 includes semiconductor die 301 (see also FIG. 9) and semiconductor dies 451 and 452. Among other semiconductor dies 301, 451, and 452 in columns 441-443 may each be secured to top surface 430 using thermal epoxy, solder (e.g., gold-tin preform), a combination thereof, or other suitable means. In one embodiment, semiconductor die 301 is secured to top surface 430 using gold-tin preform solder, and semiconductor dies 451 and 452 are secured to top surface 430 using thermal epoxy.

[0108] The semiconductor die 301 includes the stacked amplifier 200 described herein. Both of the semiconductor dies 451 and 452 have one or more capacitors to provide input impedance matching. In some cases, one or both of the semiconductor dies 451 and 452 may further include a resistor to form a resistor-capacitor network to provide input impedance matching. The semiconductor dies 451 and 452 may be utilized together to provide fundamental and second harmonic termination, control, and input impedance matching for the stacked amplifier 200. Depending on the need for input impedance matching, the semiconductor die 451 may be omitted, the semiconductor die 452 may be omitted, or both the semiconductor dies 451 and 452 may be omitted.

[0109] Each of columns 441-443 further includes a semiconductor die similar to semiconductor die 301, 451, and 452. Columns 441-443 are coupled in parallel to one another between input lead 420 and output lead 421. Thus, packaged amplifier device 400 includes four stacked amplifiers in columns 440-443, including stacked amplifier 200 implemented on semiconductor die 301, and three additional stacked amplifiers that may be similar to stacked amplifier 200 (i.e., matching size, number of active devices, ratio of active devices, etc.).

[0110] After the group of semiconductor dies 480 are secured to the semiconductor package 410, the semiconductor dies are electrically coupled to the input leads 420, to each other, and to the output leads 421, as shown in FIG. 13. In particular, bond wires 460 are coupled between the input leads 420 and bond pads on the semiconductor die 452. Bond wires 461 are coupled between the bond pads on the semiconductor die 452 and the bond pads on the semiconductor die 451. Bond wires 462 are coupled between the bond pads on the semiconductor die 451 and the bond pads on the semiconductor die 301. Additionally, bond wires 463 are coupled between the bond pads on the semiconductor die 301 and the output leads 421. The bond wires 462 are coupled from the die 451 to the bond pads for the inputs 220-225 of the stacked amplifier 200 (see FIG. 9). A bond wire 463 is coupled from the bond pad for the output 226 of the stacked amplifier 200 to the output lead 421. Any suitable type and number of bond wires may be used, for example, 1.5 mil thick gold bond wires.

[0111] Additional bond wires may also be used to electrically couple semiconductor dies 301, 451, and 452 in column 440 to corresponding semiconductor dies in column 441. For example, bond wire 470 may be coupled between stitch pad 228A (see FIG. 9) on semiconductor die 301 and a similar stitch pad on the semiconductor die on the right side of FIG. 13. Similarly, bond wire 471 may be coupled between stitch pad 227A (see FIG. 9) on semiconductor die 301 and a similar stitch pad on the semiconductor die on the right side of FIG. 13. Bond wire 472 may be coupled between a stitch pad on semiconductor die 451 and a similar stitch pad on the semiconductor die on the right side of FIG. 13. Additionally, bond wire 473 may be coupled between a stitch pad on semiconductor die 452 and a similar stitch pad on the semiconductor die on the right side of FIG. Additional bond wires may also be used to couple the semiconductor die in column 441 to the semiconductor die in column 442, and to couple the semiconductor die in column 442 to the semiconductor die in column 443. In this manner, the respective potentials at certain circuit nodes in group semiconductor die 480 may be matched and related to one another, thereby helping to maintain the stability of packaged amplifier device 400.

[0112] Viewing packaged amplifier device 400 as a whole, group of semiconductor dies 480 collectively operate as a single three-terminal active device. In particular, semiconductor die 480 operates as a single common-source transistor amplifier, with input lead 420 acting as a gate input, output lead 421 acting as a drain output, and flange 411 acting as a common source. Packaged amplifier device 400 may further include group of semiconductor dies 490 similar to semiconductor die 480 but electrically coupled between input lead 422, output lead 423, and flange 411. Group of semiconductor dies 490 together may also operate as another single three-terminal active device of packaged amplifier device 400. Semiconductor die 480 and semiconductor die 490 together may be used to potentially form a D-mode amplifier, although other circuit configurations may be used.

[0113] In other cases, packaged amplifier device 400 may omit group of semiconductor dies 490, input lead 422, and output lead 423. In this case, packaged amplifier device 400 may appear as a single three-terminal active device having or consisting of only three terminals or package leads. In still other cases, packaged amplifier device 400 may have additional columns of semiconductor dies coupled together within group of semiconductor dies 480, group of semiconductor dies 490, or both groups. Additionally, packaged amplifier device 400 may have additional leads and groups of additional dies, and other variations are within the scope of the present embodiments.

[0114] A ceramic, polymeric, or other lid (not shown) may be placed on or in frame 412 after all of the semiconductor dies are secured in place and wire bonded, and the lid may be secured or sealed in place using an adhesive, bond, or other means. In some cases, the lid may be hermetically sealed to frame 412, and semiconductor package 410 may be a hermetically sealed package.

[0115] The packaged amplifier device 400 provides a solution for high voltage stacked transistor amplifiers without the need for off-chip components such as biasing networks of resistors and inductors. The packaged amplifier device 400 can also operate at high supply voltages by design without sacrificing reliability or performance. The packaged amplifier device 400 has a stacked amplifier 200 on a semiconductor die 301 along with seven additional similar amplifiers in the embodiment shown in FIG. 13. The additional stacked amplifiers may be combined in parallel using a larger package. Thus, the total power handling capacity of the packaged amplifier device 400 can reach 2,000-4,000W or more. Particular examples of the total power handling capacity of the packaged amplifier device 400 may be 2,000W, 2,500W, 3,000W, 3,500W, 4,000W or more, although lower power handling capacities using fewer stacked amplifiers are also possible.

[0116] The amplifier stages and stacked amplifiers described herein consistent with the concepts described herein can be simulated as many circuit elements in software. For example, the amplifier stages 10, 50, 70, 90, 90A, 100, 100A can be simulated on one or more computing devices. Similarly, the stacked amplifier 200 can be simulated on one or more computing devices. One or more aspects of a semiconductor manufacturing process can be simulated, such as dopant distribution, stress distribution, device geometry, and other aspects of the manufacturing process used to form the amplifier. Simulation of the manufacturing process can be used to model one or more individual operating characteristics of the transistors and other elements (e.g., resistors, inductors, capacitors, etc.) of the amplifier.

[0117] One or more operating characteristics of the amplifier, such as gain bandwidth, stability, noise figure (NF), and other characteristics, may also be simulated. Simulation may be used to model the characteristics of the semiconductor devices (e.g., transistors) and other elements (e.g., resistors, inductors, capacitors, etc.) of the amplifier. Thus, the amplifier may be simulated using one or more circuit simulators, semiconductor device modeling, semiconductor process simulation, or related technology computer-aided design (TCAD) software tools.

[0118] Each circuit element, when simulated using software, may be embodied as a module or list of code associated with certain parameters to simulate that circuit element. Software for simulating a circuit element may include program instructions embodied in the form of, for example, source code, including human readable statements written in a programming language, or machine code, including machine instructions recognizable by a processor in a suitable execution system, for example, a computer system or other system. Each circuit element, when embodied in hardware, may represent a circuit or multiple electrically interconnected circuits.

[0119] The one or more computing devices may execute software for simulating, among other things, the circuit elements forming the distributed amplifier described herein. The computing devices may include at least one processing circuit. Such processing circuitry may include, for example, one or more processors and one or more storage or memory devices coupled to a local interface. The local interface may include, for example, a data bus with associated address / control bus or any suitable bus structure.

[0120] A storage or memory device may store data or components executable by a processor of a processing circuit. For example, data associated with one or more circuit elements of a distributed amplifier may be stored in one or more storage devices and associated for processing by one or more processors in a computing device. Similarly, software for simulating circuit elements and / or other components may be stored in one or more storage devices and executable by one or more processors in a computing device.

[0121] The transistors described herein may include one or more field plates, e.g., a source-connected field plate, a gate-connected field plate, or both a source-connected field plate and a gate-connected field plate. Although FET transistors are described above, the concepts described herein may be utilized with bipolar-connected transistors, and the amplifier cells described herein may be implemented using bipolar-connected transistors. Among other types of FET transistors, the transistors described herein may be formed as high electron mobility transistors (HEMTs), pseudomorphic high electron mobility transistors (pHEMTs), metamorphic high electron mobility transistors (mHEMTs), and laterally diffused metal oxide semiconductor transistors (LDMOSs) that can be used as highly efficient power amplifiers.

[0122] The transistors described herein can be formed using a wide variety of semiconductor materials and semiconductor fabrication processes. Examples of semiconductor materials include silicon (Si) and germanium (Ge), Group IV element semiconductor materials including compounds thereof, aluminum (Al), gallium (Ga), and indium (In), and Group III element semiconductor materials including compounds thereof. The semiconductor transistor amplifiers can be constructed, in certain examples, from Group III-V direct bandgap semiconductor technology, since the high bandgaps and electron mobilities offered by these devices provide, among other advantages, high electron velocities and high breakdown voltages. Thus, in some embodiments, the present concepts can be utilized in Group III-V direct bandgap active semiconductor devices, such as Group III nitrides (nitrides based on aluminum (Al)-, gallium (Ga)-, indium (In)-, and their alloys (AlGaIn)), GaAs, InP, InGaP, AlGaAs, and the like. However, the principles and concepts may also be applied to transistors and other active devices made from other semiconductor materials.

[0123] The concepts described herein may be embodied in GaN-on-Si (GaN formed on Si) transistors and devices, GaN-on-SiC transistors and devices, and other types of semiconductor materials. As used herein, the phrase "gallium nitride material" or GaN semiconductor material refers to any of gallium nitride and its alloys, such as aluminum gallium nitride (Al GaN), among others. x Ga (1‐x) N), indium gallium nitride (In y Ga (1‐y) N), Aluminum Indium Gallium Nitride (Al x In y Ga (1‐x‐y) N), gallium arsenide phosphide (GaAs a P b N (1‐a‐b) ), Aluminum Indium Gallium Phosphide (Al x In y Ga(1‐x‐y) As a P b N (1‐a‐b) ). Typically, arsenic and / or phosphorous, if present, are in low concentrations (e.g., less than 5 weight percent). The term "gallium nitride" or GaN semiconductor refers directly to gallium nitride and does not include its alloys.

[0124] The above-described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments, and features described in various embodiments may be interchangeable where possible. In the above description, many specific details are provided to fully understand the embodiments of the present disclosure. However, as will be understood by those skilled in the art, the technical solutions of the present disclosure may be implemented without one or more of the specific details, or may employ other methods, other components, other materials, etc. In other cases, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring the aspects of the present disclosure.

[0125] Although relative terms such as "top", "bottom", "upper", "lower", "top", "bottom", "right", and "left" may be used to describe the relative spatial relationship of certain structural features, these terms are used merely for convenience as directions in the examples. It should be understood that if the device is turned upside down, the "upper" component becomes the "lower" component. When a structure or feature is described as being "located on" (or formed on) another structure or feature, such structure may be located directly on (i.e., in contact with) the other structure without any other intervening structures or features between the structure and the other structure. When a structure or feature is described as being "located on" (or formed on) another structure or feature, such structure may be positioned over the other structure with or without the intervening structures or features between them. When two components are described as being "coupled" to one another, the components may be electrically coupled to one another with or without the other components being electrically coupled and intervening between them. When two components are described as being "directly coupled" to one another, the components may be electrically coupled to one another with no other components electrically coupled between them.

[0126] As used in the original specification, the terms "a," "an," "the," and "said" are used to indicate the presence of one or more elements and components. As used in the original specification, the terms "comprise," "include," "have," "contain," and variations thereof are used in an open-ended manner, unless otherwise specified, in addition to the listed elements, components, etc., and these terms may include or include additional elements, components, etc. Terms such as "first," "second," etc. are used merely as labels and not as limitations on the number of objects.

[0127] Although the embodiments have been described in detail herein, such description is illustrative. The features of the embodiments described herein are representative, and in alternative embodiments, certain features and elements may be added or omitted. In addition, modifications of the aspects of the embodiments described herein may be made by those skilled in the art without departing from the spirit and scope of the present invention as set forth in the claims, and the scope of the present invention should be accorded the broadest interpretation to include modifications and equivalent structures.

Claims

1. 1. An amplifier comprising: an amplifier cell including a common-source transistor and a common-gate transistor in a cascode-connected relationship, at least one of the common-source transistor and the common-gate transistor including a field plate; The amplifier further comprising a biasing network coupled to the common-gate transistor in the amplifier cell.

2. 2. The amplifier of claim 1, further comprising a stabilizing capacitor coupled between an output for said amplifier and the gate of said common-gate transistor.

3. 3. The amplifier of claim 2, wherein the capacitance of said stabilizing capacitor maintains a positive real output impedance of said amplifier over operating frequencies for said amplifier.

4. 2. The amplifier of claim 1, wherein the gate of said common-gate transistor is coupled to a bias node of said biasing network.

5. 2. The amplifier of claim 1, wherein the biasing network comprises a resistor voltage divider network coupled between an output for the amplifier, the amplifier cell, and a ground for the amplifier.

6. 6. The amplifier of claim 5, wherein the gate of said common-gate transistor is coupled to a bias node along said resistor voltage divider network.

7. 6. The amplifier of claim 5, wherein the biasing network further comprises an inductor coupled in series with the resistor voltage divider network.

8. the biasing network further comprises a source transistor; a gate of the source transistor coupled along the resistor voltage divider network to a bias node; 6. The amplifier of claim 5, wherein the gate of said common gate transistor is coupled to the source of said source transistor.

9. 2. The amplifier of claim 1, wherein the drain of said common source transistor is electrically coupled to the source of said common gate transistor in said cascode connection.

10. 2. The amplifier of claim 1, wherein said amplifier cell further comprises a second common-gate transistor.

11. the amplifier cell further includes a resistor-capacitor network coupled between the gate of the common-gate transistor and ground for the amplifier; 2. The amplifier of claim 1, wherein the resistor-capacitor network provides a high frequency ground at the gate of the common-gate transistor.

12. 2. The amplifier of claim 1, further comprising a ballast resistor coupled between said amplifier cell and said biasing network.

13. 10. The amplifier of claim 1, wherein the power handling capacity of the amplifier is greater than 400W.

14. 10. The amplifier of claim 1, wherein an operating supply voltage for the amplifier is greater than 50V.

15. a second amplifier cell including a second common-source transistor and a second common-gate transistor in a cascode connection relationship; At the output of the amplifier, the second amplifier cell is arranged in parallel with the amplifier cell; The amplifier of claim 1 , wherein the biasing network is coupled to the amplifier cell and to the second amplifier cell for biasing both the amplifier cell and the second amplifier cell.

16. 16. The amplifier of claim 15, wherein the output of the amplifier cell is directly coupled to the output of the second amplifier cell.

17. 16. The amplifier of claim 15, further comprising a ballast resistor coupled between an input of the amplifier cell and an input of the second amplifier cell.

18. 16. The amplifier of claim 15, further comprising a ballast resistor coupled between the amplifier cell and the biasing network.

19. a first ballast resistor coupled between the amplifier cell and the biasing network; 16. The amplifier of claim 15, further comprising a second ballast resistor coupled between the amplifier cell and the second amplifier cell.

20. 16. The amplifier of claim 15, further comprising a second biasing network, wherein a gate of said common-gate transistor and a gate of said second common-gate transistor are both coupled to said biasing network and to said second biasing network.

21. a bias interconnect feed line; the biasing network is coupled at a first end of the bias interconnect feed line; 21. The amplifier of claim 20, wherein the second biasing network is coupled at a second end of the bias interconnect feed line.

22. a ballast resistor coupled between the amplifier cell and the biasing network at the first end of the bias interconnect feed line; a second ballast resistor coupled along the bias interconnect feed line between the amplifier cell and the second amplifier cell; 22. The amplifier of claim 21, further comprising a third ballast resistor coupled between the second amplifier cell and the second biasing network at the second end of the bias interconnect feed line.

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