Resistive Memory Device for Matrix-Vector Multiplication

Abstract

A device for performing matrix-vector multiplication of a matrix and a vector, the device comprising a memory crossbar array comprising: a plurality of row lines; a plurality of column lines; and a plurality of junctions disposed between the plurality of row lines and the plurality of column lines. Each junction comprises a programmable resistance element and an access element for accessing the programmable resistance element. The memory crossbar array further comprises one or more write-assist wires and one or more corresponding arrays of a plurality of switching elements. The write-assist wires are connectable to the plurality of column lines via the plurality of switching elements.

Description

[Technical field]

[0001] Cognitive computing is a promising technology that derives intelligence and knowledge from huge amounts of data. Current cognitive computers are usually based on the Von Neumann architecture, where the computing and memory units are separated. Cognitive computing is inherently data-centric and requires the rapid movement of huge amounts of data back and forth. Since the Von Neumann architecture is rather inefficient for such tasks, it is becoming increasingly clear that other architectures are desirable to build efficient cognitive computers, especially those where memory and logic somehow coexist. Summary of the Invention [Means for solving the problem]

[0002] According to one aspect, the disclosure is embodied as a device for performing matrix-vector multiplication of a matrix and a vector. The device includes a memory crossbar array including a plurality of row lines; a plurality of column lines; and a plurality of junctions disposed between the plurality of row lines and the plurality of column lines. Each junction includes a programmable resistance element and an access element for accessing the programmable resistance element. The memory crossbar array further includes one or more write-assist wires and one or more corresponding arrays of a plurality of switching elements. The write-assist wires are connectable to the plurality of column lines via the plurality of switching elements.

[0003] The device is configured to perform the write operation by applying programming signals to a subset of the row lines to program conductance values ​​of the resistive elements for the matrix-vector multiplication; and turning on the one or more write assist wires during the write operation with the one or more arrays of switching elements, thereby providing one or more shunt paths for the programming signals during the write operation.

[0004] According to another aspect, there is provided a design structure tangibly embodied in a machine-readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising a device according to the above aspect.

[0005] According to another aspect, there is provided a method for performing a matrix-vector multiplication by the device of the above aspect, the method including: performing the write operation by applying programming signals to a subset of the row lines to program conductance values ​​of the resistive elements for the matrix-vector multiplication; and turning on, with the one or more arrays of switching elements, the one or more write assist wires during the write operation, thereby providing one or more shunt paths for the programming signals during the write operation.

[0006] Embodiments of the present disclosure will be described in more detail below, by way of illustrative and non-limiting examples, with reference to the accompanying drawings, in which: [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a simplified schematic block diagram of a device for performing matrix-vector multiplication according to one embodiment of the present disclosure. [Diagram 2] FIG. 2 illustrates an example of matrix-vector multiplication according to one embodiment of the present disclosure. [Diagram 3]FIG. 3 illustrates an exemplary implementation of a scalar multiplication to be performed by a phase change memory cell. [Figure 4] FIG. 4 is a schematic diagram showing the current / voltage characteristics of material components of a phase change memory cell. [Diagram 5] FIG. 5 shows a schematic diagram of a memory crossbar array according to one embodiment of the present disclosure. [Figure 6] FIG. 6 illustrates the write operation of the iterative matrix programming scheme for a memory crossbar array. [Figure 7] FIG. 7 illustrates a read operation of the iterative programming scheme for a memory crossbar array. [Figure 8] FIG. 8 illustrates the matrix-vector multiplication operations performed by the memory crossbar array. [Figure 9] FIG. 9 illustrates a (M / L) programming sequence through a crossbar array according to one embodiment of the present disclosure. [Figure 10] FIG. 10 illustrates a matrix-vector multiplication performed in a memory crossbar array. [Figure 11] FIG. 11 shows a block diagram of an exemplary design flow. [Figure 12] FIG. 12 shows a flow chart diagram illustrating method steps of a method for performing matrix-vector multiplication with a memory crossbar array. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Cognitive computing is a promising technology for deriving intelligence and knowledge from huge amounts of data. Current cognitive computers are usually based on the von Neumann architecture, where the computing and memory units are separated. Cognitive computing is inherently data-centric and requires the rapid movement of huge amounts of data back and forth. Since the von Neumann architecture is rather inefficient for such tasks, it is becoming increasingly clear that other architectures are desirable for building efficient cognitive computers, especially those where memory and logic somehow coexist.

[0009] Memcomputing is an important non-von Neumann approach being investigated. Key elements in this novel computing paradigm are high-density, low-power, configurable-state, programmable, and non-volatile memory devices.

[0010] A fundamental computational primitive is matrix-vector multiplication. This primitive is of particular interest because it forms the basis of several linear algebraic operations and is one of the most commonly used mathematical operations in science and engineering. Matrices are usually represented by two-dimensional arrays of matrix elements, and vectors by one-dimensional arrays of vector elements. Matrices can be thought of as arrays of vectors. Thus, matrix-vector multiplication can be generalized to matrix-matrix multiplication and to vector-vector multiplication.

[0011] However, many challenges remain in performing accurate matrix-vector operations in an efficient manner in arrays of memory devices.

[0012] Thus, there is a need for new and improved main computing devices, particularly main computing devices that can perform matrix-vector multiplication.

[0013] With reference to FIGS. 1-12, some general aspects and terminology of embodiments of the present disclosure are described.

[0014] According to an embodiment of the present disclosure, a resistive element may be defined as an element whose electrical resistance can be changed by applying an electrical programming signal to the resistive element. The resistive element may be specifically embodied as a resistive memory element. The electrical programming signal may be, for example, a current flowing through the resistive memory element or a voltage applied to the resistive memory element. The current or voltage or a combination thereof may be applied to the resistive memory element, for example, in the form of a pulse. As a result, the electrical resistance of a resistive memory element depends on the history of the current previously flowing through the resistive memory element or the history of the electrical signal applied to the resistive memory element or a combination of these histories.

[0015] Resistive memory elements are based on a physical phenomenon occurring in materials whose resistance changes under the action of an electric current or an electric field. The change is usually non-volatile and reversible. Several classes of resistive memory elements are known, ranging from metal oxides to chalcogenides. A typical resistive memory element is a metal / insulator / metal structure, where the metal component acts as the electrode and the insulator is the resistive switching material (e.g., a chalcogenide). These resistive memory elements show good performance in terms of power consumption, possible integration density, retention, and durability.

[0016] The embodiments of the present disclosure provide a method for performing inexact, fast matrix-vector multiplication. The result of this multiplication may be preferably used in an algorithm that does not require high precision for the multiplication task. Such an algorithm that may be used for post-processing the result of the multiplication according to the embodiments of the present disclosure is, for example, the algorithm disclosed by Klavik et al., "Changing Computing Paradigms Towards Power Efficiency," Proc. Royal Society A., 2014. The multiplication performed according to the embodiments of the present disclosure may be fast, low power, and scalable to matrix sizes of 10000x10000 or more.

[0017] Implementations of the present disclosure may provide significant power or speed advantages, or a combination thereof, compared to traditional von Neumann approaches where data must be shuttled between a central processing unit (CPU) and memory.

[0018] Because matrix-vector multiplication can be generalized to matrix-matrix multiplication and vector-vector multiplication, devices and methods according to embodiments of the present disclosure can also be used to perform matrix-matrix multiplication and vector-vector multiplication.

[0019] FIG. 1 is a simplified schematic block diagram of a device 100 for performing matrix-vector multiplication. The device 100 comprises a resistive memory 10 having a plurality of programmable resistive elements. Moreover, a signal generator 11 is provided. The signal generator 11 is configured to apply electrical programming signals to the resistive elements of the resistive memory 10. The signal generator 11 comprises a circuit for programming resistive memory cells during a data writing or programming operation so that a matrix-vector multiplication can be performed. The row and column lines may also be denoted as word lines and bit lines. The signal generator 11 is configured to receive a matrix A as an input and to apply programming signals to the resistive elements to program their conductance values ​​for the matrix-vector multiplication.

[0020] The conductance values ​​represent the matrix values ​​of the matrix to be multiplied with the vector.

[0021] Additionally, the device 100 includes a read circuit 12 configured to read resistance values ​​of the resistive elements during a data read operation. The device 100 is configured to apply read voltages to rows of a memory crossbar array. The read voltages represent vector elements of a vector to be multiplied with the matrix. The device is further configured to read current values ​​of columns of the memory array. The current values ​​represent resultant values ​​of vector elements of a resultant vector of the multiplication.

[0022] The device 100 further comprises a control circuit 13 configured to control the signal generator 11 and the readout circuit 12 .

[0023] The resistive memory 10 may generally be any of the possible types of resistive memory described above. In particular, the resistive memory 10 may be a phase change memory (PCM) or a resistive random access memory (RRAM). In the following, it is assumed that the resistive memory 10 is embodied as a PCM. The resistive memory 10 thus comprises a number of PCM cells as resistive memory elements. The PCM cells of the memory 10 may have s=2 or s>2 programmable resistance states, in the latter case providing multilevel operation. The s programmable resistance states correspond to different relative proportions of amorphous and crystalline phases in the PCM material of the cell. These states may include a fully amorphous RESET state of high resistance, a fully crystalline SET state of low resistance, and a number of intermediate states corresponding to increasing amounts of crystalline phases in the amorphous PCM material. The s programmable cell states are typically defined in terms of a predefined reference value or range of values ​​of a resistance metric used for read detection by the read circuit 12.

[0024] To perform a matrix-vector multiplication, the PCM cell is programmed according to an embodiment in a kind of write operation. More specifically, the signal generator 11 applies voltages to the cell via the column and row lines such that the resulting programming signals set the cell to a state (conductance value) that represents the matrix element of the matrix to be multiplied with the vector. In a read operation, a (low) read voltage is applied to the column or row lines. The resulting row or column line current values ​​are then read / measured to obtain the resulting vector.

[0025] 2 illustrates an example of matrix multiplication according to an embodiment of the present disclosure, which uses Ohm's law and Kirchhoff's law in a resistive memory crossbar array.

[0026] Following the illustrated example, let a matrix A of size 3x3 be multiplied with a vector x, and the result be a product or result vector b:

number

[0027] Therefore, matrix A has the matrix element A 11 , A 21 and A 31 The first column consists of matrix elements A 12 , A 22 and A 32 The second column consists of the matrix element A 13 , A 23 and A 33 The vector x includes vector elements x1, x2, and x3.

[0028] For such multiplication of a matrix A having size 3x3, the resistive memory 10 comprises a memory crossbar array 200 of corresponding size 3x3.

[0029] The memory crossbar array 200 comprises three row lines 201, 202 and 203 and three column lines 204, 205 and 206. The three row lines 201, 202 and 203 are disposed above the three column lines 204, 205 and 206, which are shown in dotted lines. More specifically, the row lines 201, 202 and 203 extend in a first xy-plane and the three column lines extend in a second xy-plane, where the first xy-plane is disposed in a vertical z-direction from the second xy-plane.

[0030] The three row lines 201, 202, and 203 and the three column lines 204, 205, and 206 are connected to each other via vertical junctions 210. The junctions 210 extend in the vertical z direction between an upper intersection 211a of the row lines 201 to 203 and a lower intersection 211b of the column lines 204 to 206.

[0031] Each junction 210 consists of a series arrangement of a resistive memory element and a transistor, although for ease of illustration the transistor is not shown in FIG.

[0032] More specifically, the memory crossbar array 200 includes nine resistive memory elements embodied as PCM cells. 11 , R 12 and R 13 and row line 202 includes resistive memory element R 21 , R 22 and R 23 and row line 203 includes resistive memory element R 31 , R 32 , and R 33 It is equipped with:

[0033] To perform the matrix-vector multiplication of the above matrices, the signal generator 11 applies programming signals, in particular current pulses, to the resistive memory elements and thereby programs the conductance values ​​for the matrix-vector multiplication.

[0034] More specifically, the conductance value of the resistive memory element represents the matrix value of the matrix-vector multiplication. 11 The conductance of is the matrix value A 11 The resistive memory element R 12 The conductance of is the matrix value A 12 or, more generally, the conductance of the resistive memory Rij is programmed to the corresponding matrix value Aij.

[0035] Read circuit 12 then applies read voltages to column lines 204, 205 and 206. More specifically, read circuit 12 applies read voltage X1 to column line 204, read voltage X2 to column line 205, and read voltage X3 to column line 206. The read voltages thus represent the vector values ​​of the vector of the matrix-vector multiplication.

[0036] Moreover, the read circuit 12 reads current values ​​on row lines 201, 202 and 203. As an example, the read circuit 12 reads a current value b1 from row line 201, which is the sum of three multiplications:

number

[0037] Thus, read circuit 12 reads current value b2 from row line 202 and current value b3 from row line 203. The current values ​​represent the resulting values ​​of the vector elements of product vector b.

[0038] In a corresponding manner, readout circuitry 12 may apply read voltages to row lines 201, 202 and 203, and may read out current values ​​on column lines 204, 205 and 206 and perform a transpose matrix-vector multiplication.

[0039] 3 illustrates an exemplary implementation of a scalar multiplication that may be performed by a PCM cell 300. Such scalar multiplication forms the basis of the matrix-vector multiplication performed in accordance with embodiments of the present disclosure.

number

number

[0040] In this equation, α is a time-dependent conductance variation parameter, and f is a function, specifically a polynomial function, that approximates the current-voltage characteristic of the PCM cell 300. The PCM cell 300 is adapted to vary the effective conductance G by an iterative program and verification procedure. n Next, the read circuit 12 is programmed to a read voltage V n is applied, and a current I n Finally, the current I n is transformed inversely to give the value that represents the result of scalar multiplication.

number

[0041] According to a preferred embodiment, an averaging of the results over the K memory elements / PCM cells is performed.

[0042] 4 is a schematic diagram showing the current / voltage (and therefore resistance) characteristics of the material components of the memory cell 300 of FIG. 3. The solid lines show the change in current versus voltage for a PCM material starting from a fully crystalline SET state (upper curve) and also starting from a fully amorphous RESET state (lower curve). These two curves reflect the large (typically three orders of magnitude) change in resistivity between the crystalline and amorphous phases. The amorphous phase exhibits nonlinear characteristics with a threshold switching phenomenon that is electric field induced. At a certain threshold voltage V TH At , this phase switches to a very low "ON-state" resistance corresponding to a crystalline PCM material. The cell programming (write) voltage is selected to be above this threshold voltage as shown.

[0043] As can be seen from FIG. 4, the current in the read mode is a slightly non-linear function of the voltage.

[0044] 5 shows a schematic diagram of a memory crossbar array 500 according to one embodiment of the present disclosure. The memory crossbar array 500 includes a number of row lines RL, a number of column lines CL, and a number of junctions 30 including a series arrangement of a programmable resistance element R and a transistor T as an access element. The transistor T may be specifically embodied as a MOSFET.

[0045] The memory crossbar array 500 further comprises a plurality of vertical access lines AL, where each of the plurality of vertical access lines AL is connected to a respective array of resistive memory elements R. More particularly, each vertical access line AL is connected to the gate of the access transistor T of a corresponding column line CL. Thus, by providing an appropriate control signal, i.e., a selection signal, to one or more of the plurality of vertical access lines AL, all resistive memory elements R connected to a respective access line AL can be simultaneously turned on or off, i.e., selected or deselected.

[0046] The memory crossbar array 500 further comprises write assist wires 40 and a corresponding array 50 of switching elements 51. The switching elements 51 may be embodied as transistors, in particular MOSFET transistors. The array 50 further comprises access wires 52 for accessing the write assist wires 40, in other words for turning on the write assist wires 40. More particularly, the access wires 52 are connected to the gates of the transistors 51. The sources and drains of the transistors 51 are arranged between the write assist wires 40 and the column lines CL of the memory crossbar array 500. Thus, the write assist wires 40 can be connected to a number of column lines CL via the switching elements / transistors 51. More particularly, by providing an appropriate control signal, in other words a select signal, to the access wires 52, the transistors 51 may be switched on / turned on, so that the write assist wires 40 can be electrically connected to the column lines CL, in other words the write assist wires 40 can be turned on. When transistor 51 is switched off / turned off, write assist wire 40 is also turned off, i.e., not electrically connected to column line CL. Write assist wire 40 provides a shunt path for programming signals during a write operation, which will be described in more detail with reference to Figures 6 and 7.

[0047] 6 and 7 illustrate iterative matrix programming of the memory crossbar array 500 of FIG.

[0048] 6 illustrates the programming process. More specifically, the control circuit 13 may apply a select signal to select, for example, the left column line CL 610 of the memory crossbar array 500. This can be done by sending a select signal S to the left access line AL 620.

[0049] Signal generator 11, under the control of control circuitry 13, can then apply a programming signal PS, specifically a write voltage in the form of a write pulse, to one or more of the row lines RL. Although in FIG. 6 only one write pulse is shown applied as the programming signal PS to the lower row line RL 630 of memory crossbar array 500, in general the programming signal may be applied to a subset of the row lines. The programming signal is applied to program the conductance values ​​of resistive elements for subsequent matrix-vector multiplications performed in memory crossbar array 500.

[0050] Depending on the embodiment, the information to be written by the write pulse may be encoded in the amplitude of the write pulse or in the length of the write pulse.

[0051] During the write operation, the write assist wire 40 is turned on by the switching array 50. More specifically, a control / select signal is applied to the access wire 52, and thereby to the gate of the transistor 51, thereby switching the transistor 51 and electrically connecting the write assist wire 40 to the column line CL 610. As a result, the programming signal PS causes a programming current PC to flow from the row line RL 630 through the resistive element R 641, the transistor T 642, the column line CL 610, and the transistor 51 to the write assist wire 40. Thus, a shunt path 70 is provided for the programming current PC during a write operation.

[0052] The write operation shown in FIG. 6 can be performed by single shot programming or by iterative programming.

[0053] In iterative programming, in the first step, a write operation is performed as shown in Figure 6. Then, in the next step, the result of the write operation is verified by a read operation.

[0054] 7 illustrates such a read operation of the iterative programming scheme for the memory crossbar array 500 of FIG. 5. In the case of the read operation, the control circuit 13 applies a selection signal S to the access line AL 620. A read signal RS, in particular a read voltage, is then applied to the column line CL 610. As a result, a read current I 読み取り can be measured by the integrator circuit 60 of the row line RL, and the resistance values ​​of the selected three resistive elements R of the left column line CL 610 can be determined. The write-assist wires 40 are turned off for the read operation.

[0055] This iterative process can be repeated as desired or necessary until the desired resistance value for the selected resistive element R is achieved.

[0056] According to other embodiments of the present disclosure, the iterative programming may also be performed with a variable read voltage, which may, for example, take advantage of the voltage dependence of the conductance of a resistive memory element.

[0057] FIG. 8 is a diagram illustrating the matrix-vector multiplication operations performed by memory crossbar array 500 of FIG.

[0058] For the matrix-vector multiplication, all access lines AL are selected. This can be done by the control circuit 13 by sending a selection signal S to all access lines AL. The matrix-vector multiplication can then be performed by applying a read signal RS, in particular a voltage pulse, in parallel to the column lines CL. The input of the calculation, in this example the vector value of the matrix-vector multiplication, can be encoded as the amplitude of a voltage pulse applied to the column lines, or as the time duration of the voltage pulse, or as a sequence of binary voltage pulses. The result of the calculation is converted by an integration unit 60 into a read current I 読み取り Or the read current I 読み取り is obtained by measuring the integral of over a fixed time.

[0059] The write-assist wire 40 is turned off for the corresponding read operation.

[0060] 9 illustrates a (M / L) programming sequence for a memory crossbar array 900 according to one embodiment of the present disclosure. The memory crossbar array 900 includes a number M of row lines RL, a number of column lines CL, and a number of junctions 30 including a series arrangement of programmable resistance elements R and access transistors T as access elements.

[0061] M is an integer and indicates the total number of row lines of the memory crossbar array 900. The memory crossbar array 900 is divided into M / L segments, where L is also an integer, and each of the M / L segments includes L row lines RL and assigned write assist wires 40. In the illustrated example of FIG. 9, the memory crossbar array 900 includes N segments S1, S2, ..., SN, where three segments S1, S2 and S3 are shown in detail. Each of the N segments includes L=3 row lines RL with assigned write assist wires 40 and corresponding arrays 50 including switching elements / transistors 51 and access wires 52. The memory crossbar array 900 further includes a plurality of vertical access lines AL connected to the gates of the access transistors T of the corresponding column lines CL.

[0062] The memory crossbar array 900 may be used to program at least M / L resistive elements in one column line CL of the plurality of column lines in parallel during a write operation. In other words, at least one resistive element in the column line of each segment may be programmed in parallel. In the example of FIG. 9, a programming signal PS is applied to the lower row lines 930 of the segments S1, S2, and S3. For the programming, the write assist wire 40 is turned on. More specifically, a control / selection signal is applied to the access wire 52, and thereby to the gate of the transistor 51, thereby switching the transistor 51 and electrically connecting the write assist wire 40 to the left column line CL 910. Moreover, the control circuit 13 applies a selection signal to select the left column line CL 910 of the memory crossbar array 900. This may be performed by sending a selection signal S to the left access line AL 920. As a result, in each of the segments S1, S2 and S3 (and possibly further segments S4, ..., SN), the programming signal PS causes a programming current PC to flow from the row line 930, through the resistive element 941, the transistor 942, the column line 910 and the transistor 51 to the write assist wire 40. Thus, in each of the segments S1, S2, S3, ..., SN, a shunt path 70 is provided for the programming current PC during a write / programming operation. Thus, the memory crossbar array 900 enables parallel programming.

[0063] According to an embodiment, the signal generator 13 may be configured to program multiple resistive elements per segment in parallel if the programming signal / programming current is low enough. More specifically, each shunt path 70 serves as a common current path for all resistive elements in a row of the segment, and thus the maximum programming current is limited by the maximum current that the column line of the segment can carry. However, due to the M / L write assist wires 40, the programming current of each column line is reduced by the number of segments, i.e., by a factor L / M. In other words, the multiple segments distribute the programming current of each column line to the N segments S1, S2, S3, ..., SN by the write assist wires 40.

[0064] FIG. 10 illustrates a matrix-vector multiplication performed in the memory crossbar array 900 of FIG.

[0065] For the matrix-vector multiplication, all access lines AL are selected. This can be done by the control circuit 13 by sending a selection signal S to all access lines AL. The matrix-vector multiplication can then be performed with a complexity of O(1) by applying a read signal RS, in particular a voltage pulse, in parallel to the column lines CL. The input of the calculation, in this example the vector values ​​of the matrix-vector multiplication, can be encoded as the amplitude of a voltage pulse applied to the column lines, or as the time duration of the voltage pulse, or as a sequence of binary voltage pulses. The result of the calculation is converted by an integration unit 60 into a read current I 読み取り or read current I 読み取り The integral of x is obtained by measuring x over a fixed time. The write-assist wire 40 is turned off for the corresponding read operation. According to an embodiment, the device may perform multiple runs for the matrix-vector multiplication and perform averaging of the result values ​​of the multiple runs.

[0066] According to an embodiment, the read circuit 12 may apply positive and negative read voltages as a read signal RS to the column lines CL of the memory crossbar array 900 .

[0067] Instead of applying the read voltage to the column lines CL, the read circuit 12 may apply the read voltage to the row lines RL of the memory crossbar array 900 according to an embodiment, whereby a transpose matrix-vector multiplication may be performed by the memory crossbar array 900. According to such an embodiment, the result of the matrix-vector multiplication may be obtained by measuring a read current or an integral of the read current over a fixed time by an integration unit disposed at the column lines CL.

[0068] FIG. 11 is a block diagram of an exemplary design flow 1100 used, for example, in semiconductor IC logic design, simulation, testing, layout, and manufacturing. The design flow 1100 includes a process, machine, or mechanism, or combination thereof, for processing a design structure or device to generate a logical or other functionally equivalent representation of the design structure or device or combination thereof described above and shown, for example, in FIGS. 1-10. The design structure processed or generated, or processed and generated, by the design flow 1100 may be encoded on a machine-readable transmission medium or storage medium to include data or instructions, or combinations thereof, that, when executed on a data processing system or otherwise processed, generate a logical, structural, mechanical, or other functionally equivalent representation of a hardware component, circuit, device, or system. The machine includes, but is not limited to, any machine used in an IC design process, for example, designing, manufacturing, or simulating a circuit, component, device, or system. For example, the machine may include a lithography machine, a machine or device for generating a mask (e.g., an electron beam writing device), or a combination thereof, a computer or device for simulating a design structure, any device used in a manufacturing or testing process, or any machine for programming a functionally equivalent representation of a design structure into any medium (e.g., a machine for programming a programmable gate array).

[0069] The design flow 1100 may vary depending on the type of representation being designed. For example, a design flow 1100 for building an application specific IC (ASIC) may be different than a design flow 1100 for designing a standard component, or for implementing the design on a programmable array, such as an Altera 登録商標 Inc. or Xilinx 登録商標The design flow 1100 may differ from that provided by Inc. for creating an instance in a programmable gate array (PGA) or field programmable gate array (FPGA).

[0070] 11 illustrates a plurality of such design structures, such as those described above, preferably including an input design structure 1120 that is processed by design process 1110. Design structure 1120 may be a logical simulation design structure that is generated and processed by design process 1110 to generate a logically equivalent functional representation of a hardware device. Design structure 1120 may also, or alternatively, comprise data or program instructions, or a combination thereof, that when processed by design process 1110, generates a functional representation of a physical structure of a hardware device. Whether representing functional or structural or a combination thereof design features, design structure 1120 may be generated using electronic computer-aided design (ECAD), such as electronic computer-aided design as implemented by a core developer / designer. When encoded on a machine-readable data transmission medium, gate array, or storage medium, design structure 1120 may be accessed and processed by one or more hardware or software modules, or combinations thereof, in design process 1110 to simulate or otherwise functionally represent electronic components, circuits, electronic or logic modules, devices, devices, or systems, such as those shown in Figures 1-10. Thus, design structure 1120 may include files or other data structures that, when processed by a design or simulation data processing system, functionally simulate or otherwise represent circuits or other levels of a hardware logic design, such as those files or other data structures described above that contain human or machine or human and machine readable source code, compiled structures, and computer executable code structures.Such data structures may include hardware-description language (HDL) design entities or other data structures that are compliant or compatible with, or compliant and compatible with, low-level HDL design languages ​​(e.g., Verilog and VHDL), or high-level design languages ​​(e.g., C or C++), or a combination of such design languages.

[0071] Design process 1110 preferably uses and incorporates hardware or software modules or combinations thereof to synthesize, translate, or otherwise process design / simulation functional equivalents of components, circuits, devices, or logic structures shown in FIGS. 1-10 to generate netlist 1180, which may include design structures, such as design structure 1120. Netlist 1180 may include, for example, compiled or otherwise processed data structures representing lists of wires, discrete components, logic gates, control circuits, I / O devices, and models, etc., that describe connections to other elements and circuits in an integrated circuit design. Netlist 1180 may be synthesized using an iterative process in which netlist 1180 is resynthesized one or more times depending on the design specifications and parameters of the device. As with other design structure types described herein, netlist 1180 may be stored on a machine-readable data storage medium or programmed into a programmable gate array. The medium may be a non-volatile storage medium, such as a magnetic or optical disk drive, a programmable gate array, a compact flash, or a memory device. 登録商標 , or other flash memory. Additionally or alternatively, the medium may be system or cache memory, buffer space, or electrically or optically conductive devices and materials over which data packets may be transmitted and intermediately stored over the Internet or other networking suitable means.

[0072] The design process 1110 may include hardware and software modules for processing various input data structure types, such as those mentioned above, including netlist 1180. Such data structure types may, for example, be present in library elements 1130 and may comprise a set of commonly used elements, circuits, and devices, such as those mentioned above, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.). The data structure types may further include design specifications 1140, feature data 1150, verification data 1160, design rules 1170, and test data files 1185, which may include input test patterns, output test results, and other test information. The design process 1110 may further include standard mechanical design processes, such as stress analysis; thermal analysis; mechanical event simulation; and process simulation for operations, such as casting, molding, and die pressing. Those of ordinary skill in the art of mechanical design can appreciate the range of possible mechanical design tools and applications that may be used in design process 1110 without departing from the scope and spirit of the present disclosure. Design process 1110 may also include modules for performing standard circuit design processes, such as timing analysis, verification, design rule checking, and place and route operations.

[0073] The design process 1110 uses and incorporates logical and physical design tools, such as HDL compilers and simulation model building tools, to process the design structure 1120 along with any additional mechanical design or data (if applicable) and some or all of the illustrated supporting data structures to generate a second design structure 1190. The design structure 1190 resides on a storage medium or programmable gate array in a data format (e.g., IGES, DXF, Parasolid XT, JT, DRG, or information stored in any other suitable format for storing or rendering such mechanical design structures) used for the exchange of mechanical device and structure data. Like the design structure 1120, the design structure 1190 preferably includes one or more files, data structures, or other computer-encoded data or instructions that reside on a transmission medium or data storage medium and that, when processed by an ECAD system, generate a logical or other functionally equivalent form of one or more of the embodiments of the present disclosure shown in FIGS. 1-10. In one embodiment, design structure 1190 may include a compiled executable HDL simulation model that functionally simulates the devices shown in FIGS.

[0074] Design structure 1190 may also use a data format used for the exchange of integrated circuit layout data or symbolic data formats (e.g., information stored in GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure 1190 may include information, such as symbol data, map files, test data files, design content files, manufacturing data, layout parameters, wires, metal levels, vias, shapes, data for routing through a manufacturing line, and other possible data required by a manufacturer or other designer / developer to manufacture the devices or structures described above and shown in FIGS. 1-10. Design structure 1190 may then proceed to stage 1195, where, for example, design structure 1190 may proceed to tape-out, be released for manufacturing, be released to a mask house, be sent to another design house, or be sent back to the customer.

[0075] 12 illustrates a flow chart diagram of method steps of a method for performing matrix-vector multiplication of a matrix and a vector, which may be performed, for example, by memory crossbar array 500 of FIG. 5 or memory crossbar array 900 of FIG.

[0076] The method begins at step 1210 .

[0077] In step 1220, control circuitry 13 turns on one or more write-assist wires during a write operation via one or more arrays of switching elements.

[0078] In step 1230, signal generator 11 applies programming signals to a subset of the row lines to program the conductance values ​​of resistive elements for the matrix-vector multiplication.

[0079] In step 1240, control circuit 13 turns off the one or more write-assist wires.

[0080] In step 1250, the method ends.

[0081] The description of various embodiments of the present invention has been presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used in this specification have been selected to best explain the principles of the embodiments, practical applications, or technical improvements to the technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0082] In general, modifications described for one embodiment may be applied to other embodiments, where appropriate.

Claims

1. 1. A device for performing matrix-vector multiplication of a matrix and a vector, the device comprising: a memory crossbar array; The memory crossbar array comprises: Multiple row lines; Multiple column lines; a plurality of junctions disposed between the plurality of row lines and the plurality of column lines, each junction comprising a programmable resistance element and an access element for accessing the programmable resistance element; and one or more write-assist wires and one or more corresponding arrays of switching elements, wherein the write-assist wires are connectable to the column lines via the switching elements; It is equipped with wherein the device is applying programming signals to a subset of the plurality of row lines to program conductance values ​​of the resistive elements for the matrix-vector multiplication; and Turning on the one or more write assist wires during a write operation with the one or more arrays of the plurality of switching elements, thereby providing one or more shunt paths for the programming signal during the write operation. and performing the write operation by The device.

2. the device comprising: read circuitry configured to apply a read voltage to the column lines of the memory crossbar array; and The current read out from the row lines of the memory crossbar array The device of claim 1 , comprising:

3. the memory crossbar array is divided into a plurality of segments; each segment of the plurality of segments comprising a plurality of row lines; and each of the plurality of segments having an assigned write assist wire from the one or more write assist wires; The device of claim 1 .

4. the memory crossbar array having M row lines; the memory crossbar array is divided into M / L segments, where M and L are integers, and each segment of the M / L segments comprises L row lines and an assigned write-assist wire of the one or more write-assist wires. The device of claim 1 .

5. The device of claim 4 , wherein the device is configured to program at least M / L devices in parallel on one of the plurality of column lines during the write operation.

6. the conductance values ​​represent the matrix values ​​of the matrix-vector multiplication; the read voltages represent vector values ​​of the vectors of the matrix-vector multiplication; and the current is a resultant value of a vector element of a product vector of the matrix-vector multiplication; The device of claim 2 .

7. The device of claim 1 , wherein the junction comprises a series arrangement of a resistive element and an access transistor.

8. The device of claim 1 , wherein the write-assist wires are arranged parallel to the row lines.

9. The device of claim 1 , wherein the switching element is embodied as a transistor.

10. The device of claim 1 , wherein the read voltage information is encoded as a duration of a read voltage pulse or a voltage level of a read voltage pulse, or a combination thereof.

11. The device of claim 1 , wherein the read voltage information is encoded as a sequence of binary voltage pulses.

12. the device comprising: performing multiple runs for the matrix-vector multiplication; and Average the results of the multiple runs The device of claim 1 , configured to:

13. The resistive element is Phase change memory (PCM) elements; Conductive bridge resistive memory element; Metal oxide resistive random access memory (RRAM) elements; Magnetoresistive random access memory (MRAM) elements; Ferroelectric random access memory (FeRAM) devices; an optical memory element; and A system device comprising a combination of transistors, resistors, capacitors and / or inductors that jointly emulate the behavior of a resistive memory element The device of claim 1 , wherein the device is one of:

14. 10. The device of claim 1, wherein the device comprises a signal generator configured to program the conductance value of the resistive element by an iterative program and verify procedure.

15. The device of claim 2 , wherein the read circuitry is configured to apply positive and negative read voltages to the column lines of the memory crossbar array.

16. 3. The device of claim 2, wherein the read circuitry is configured to apply read voltages to the row lines of the memory crossbar array to perform a transpose matrix-vector multiplication.

17. 1. A method for designing, manufacturing, or testing an integrated circuit, comprising: hardware description language (HDL) code encoded on a machine-readable medium, the HDL code comprising: when executed on a simulation data processing system, causing the simulation data processing system to simulate an electronic circuit for performing matrix-vector multiplication of a matrix and a vector, the electronic circuit comprising a memory crossbar array; The memory crossbar array comprises: Multiple row lines; Multiple column lines; a plurality of junctions disposed between the plurality of row lines and the plurality of column lines, each junction comprising a programmable resistance element and an access element for accessing the programmable resistance element; and one or more write-assist wires and one or more corresponding arrays of switching elements, wherein the write-assist wires are connectable to the column lines via the switching elements; It is equipped with wherein the electronic circuit is applying programming signals to a subset of the plurality of row lines to program conductance values ​​of the resistive elements for the matrix-vector multiplication; and Turning on the one or more write assist wires during a write operation with the one or more arrays of the plurality of switching elements, thereby providing one or more shunt paths for the programming signal during the write operation. and performing the write operation by The HDL code.

18. the device comprising: read circuitry configured to apply a read voltage to the column lines of the memory crossbar array; and The current read out from the row lines of the memory crossbar array 20. The HDL code of claim 17, comprising:

19. the memory crossbar array is divided into a plurality of segments; each segment of the plurality of segments comprising a plurality of row lines; and each segment of the plurality of segments having an assigned write assist wire; 18. The HDL code of claim 17.

20. 1. A method for performing matrix-vector multiplication of a matrix and a vector by a memory crossbar array, the memory crossbar array comprising: Multiple row lines; Multiple column lines; a plurality of junctions disposed between the plurality of row lines and the plurality of column lines, each junction comprising a programmable resistance element and an access element for accessing the programmable resistance element; and one or more write-assist wires and one or more corresponding arrays of switching elements, wherein the write-assist wires are connectable to the column lines via the switching elements; It is equipped with wherein the method comprises: performing the write operation by applying programming signals to a subset of the plurality of row lines to program conductance values ​​of the resistive elements for the matrix-vector multiplication; and Turning on the one or more write assist wires during a write operation with the one or more arrays of the plurality of switching elements, thereby providing one or more shunt paths for the programming signal during the write operation. The method comprising:

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