Semiconductor device

Abstract

To provide a semiconductor device which performs calculation by using a transistor having a large S value or operation in a subthreshold region of the transistor.SOLUTION: The transistor includes an oxide semiconductor layer having a channel formation region, a gate electrode having a region overlapping with the oxide semiconductor layer with an insulating layer interposed therebetween, and a first conductive layer having a region overlapping with the oxide semiconductor layer with a ferroelectric layer interposed therebetween. In particular, the ferroelectric layer has a crystal, and the crystal has a crystal structure that exhibits ferroelectricity.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a transistor, a semiconductor device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof. [Background technology]

[0003] In recent years, the development of semiconductor devices has progressed, and LSIs, CPUs, and memories are mainly used. A CPU is a collection of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) separated from a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0004] BACKGROUND ART Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0005] Furthermore, technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has been attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors have also attracted attention as other materials.

[0006] Furthermore, it is known that transistors using oxide semiconductors have extremely low leakage current in a non-conducting state. For example, a low-power CPU that utilizes the low leakage current characteristic of transistors using oxide semiconductors has been disclosed (see Patent Document 1). Also, for example, a memory device that can retain stored data for a long period of time by utilizing the low leakage current characteristic of transistors using oxide semiconductors has been disclosed (see Patent Document 2).

[0007] Furthermore, in recent years, with the trend toward smaller and lighter electronic devices, there has been an increasing demand for higher density integrated circuits, and there is also a demand for improved productivity in semiconductor devices including integrated circuits.

[0008] Currently, there is active development in artificial intelligence (AI), particularly in the development of integrated circuits that mimic the workings of the human brain. These integrated circuits incorporate the workings of the brain as electronic circuits, and have circuits that correspond to the "neurons" and "synapses" of the human brain. For this reason, such integrated circuits are sometimes called "neuromorphic," "brain-morphic," or "brain-inspired." These integrated circuits have a non-von Neumann architecture, and are expected to be able to perform parallel processing with significantly less power consumption than von Neumann architectures, which consume more power as processing speed increases.

[0009] An information processing model that mimics a neural network with "neurons" and "synapses" is called an artificial neural network (ANN). By using an artificial neural network, it is possible to make inferences with accuracy comparable to or even exceeding that of humans. In a neural network, the main operation is the weighted sum of neuron outputs, i.e., the sum-of-products operation.

[0010] Non-Patent Document 1 proposes a multiply-and-accumulate circuit using nonvolatile memory elements. In this multiply-and-accumulate circuit, each memory element utilizes the subthreshold operation of a transistor having silicon in its channel region to output a current corresponding to the multiplication of data corresponding to a multiplier stored in the memory element and input data corresponding to a multiplicand. This enables calculations using analog values. Furthermore, data corresponding to a multiply-and-accumulate operation is obtained by summing the currents output by the memory elements in each column. Because this multiply-and-accumulate circuit has internal memory elements, it is possible to avoid reading and writing data from and to external memory during multiplication or addition. This reduces the number of data transfers due to reads and writes, which is expected to reduce power consumption. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-257187 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-151383 [Non-patent literature]

[0012] [Non-Patent Document 1] X. Guo et al., “Fast, Energy-Efficient, Robust, and Reproducible Mixed-Signal Neuromorphic Classifier Based on Embedded NOR Flash Memory Technology” IEDM2017, pp.151-154. Summary of the Invention [Problem to be solved by the invention]

[0013] When performing analog calculations using the subthreshold region of a transistor, a wide subthreshold region and a large S value are required to ensure a range of voltages within which the circuit performing the analog calculations can operate.

[0014] Generally, transistors are developed with the aim of achieving good characteristics. Good characteristics here include high reliability and a rapid transition from the off state to the on state, i.e., a small S value. While it is possible to achieve a transistor with poor characteristics, i.e., a large S value, by using semiconductors, insulating films, etc. containing many defects and / or impurities, such transistors generally have poor reliability and are not practical for use in circuits. Furthermore, it is not common to develop transistors that are reliable, have good characteristics, and have a large S value.

[0015] Furthermore, in a transistor using silicon in the active layer, the current flows at a constant level in the off state, so the subthreshold region is not very wide.

[0016] Transistors using oxide semiconductors are known to have extremely low leakage current in the off-state, which means that they have a wide subthreshold region. While the use of this wide subthreshold region for analog computing has been studied, a larger S value is required to ensure a sufficient margin for circuit operation.

[0017] An object of one embodiment of the present invention is to provide a highly reliable transistor having a large S value.An object of one embodiment of the present invention is to provide a semiconductor device that performs calculations by utilizing operation of a transistor in a subthreshold region.An object of one embodiment of the present invention is to provide a semiconductor device with a wide subthreshold region.An object of one embodiment of the present invention is to provide a novel transistor or a novel semiconductor device.

[0018] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and other problems. Note that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems. [Means for solving the problem]

[0019] One embodiment of the present invention is a transistor including: an oxide semiconductor layer having a channel formation region; a gate electrode having a region overlapping with the oxide semiconductor layer with an insulating layer interposed therebetween; and a first conductive layer having a region overlapping with the oxide semiconductor layer with a ferroelectric layer interposed therebetween, wherein the ferroelectric layer has crystals, and the crystals have a crystal structure that exhibits ferroelectricity.

[0020] Another embodiment of the present invention is a semiconductor device including: a first transistor including a first oxide semiconductor layer having a channel formation region, a first insulating layer, a first gate electrode having a region overlapping with the first oxide semiconductor layer with the first gate insulating layer interposed therebetween, and a first conductive layer having a region overlapping with the first oxide semiconductor layer with the ferroelectric layer interposed therebetween; and a second transistor including a second oxide semiconductor layer having a channel formation region, a second insulating layer, a second gate electrode having a region overlapping with the second oxide semiconductor layer with the second gate insulating layer interposed therebetween, and a ferroelectric layer, wherein the second transistor does not have a conductive layer that is in contact with the ferroelectric layer and overlaps with the second oxide semiconductor layer with the ferroelectric layer interposed therebetween, and the ferroelectric layer has a crystal, and the crystal has a crystal structure that exhibits ferroelectricity.

[0021] Alternatively, one embodiment of the present invention includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor, in which a gate of the first transistor and a gate of the second transistor are electrically connected to a first wiring, one of a source or a drain of the first transistor and one of a source or a drain of the third transistor are electrically connected to a second wiring, the other of the source or the drain of the first transistor is electrically connected to a gate of the third transistor, one of a source or a drain of the second transistor and one of a source or a drain of the fourth transistor are electrically connected to a third wiring, and the other of the source or the drain of the second transistor is electrically connected to a gate of the fourth transistor. a gate of the third transistor is connected to a first wiring via a first capacitor, and a gate of the fourth transistor is connected to the first wiring via a second capacitor; the third transistor and the fourth transistor each include a first oxide semiconductor layer having a channel formation region, a first gate electrode having a region overlapping with the first oxide semiconductor layer via a first gate insulating layer, and a conductive layer having a region overlapping with the first oxide semiconductor layer via a ferroelectric layer; the first transistor and the second transistor each include a second oxide semiconductor layer having a channel formation region, a second gate electrode having a region overlapping with the second oxide semiconductor layer via a second gate insulating layer, and a ferroelectric layer; the ferroelectric layer has crystals, and the crystals have a crystal structure that exhibits ferroelectricity.

[0022] In the above aspect, the ferroelectric layer preferably contains one or both of hafnium and zirconium as a material having ferroelectricity.

[0023] In the above aspect, polarization is generated in the ferroelectric layer by applying an electric field between the first conductive layer and the oxide semiconductor layer.

[0024] Alternatively, one embodiment of the present invention includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor, in which a gate of the first transistor and a gate of the second transistor are electrically connected to a first wiring, one of a source or a drain of the first transistor and one of a source or a drain of the third transistor are electrically connected to a second wiring, and the other of the source or the drain of the first transistor is electrically connected to the gate of the third transistor. One of the source or drain of the second transistor and one of the source or drain of the fourth transistor are electrically connected to a third wiring, the other of the source or drain of the second transistor is electrically connected to a gate of the fourth transistor, the gate of the third transistor is connected to the first wiring via a first capacitance, and the gate of the fourth transistor is connected to the first wiring via a second capacitance, and the S value of the third transistor and the S value of the fourth transistor are larger than the S value of the first transistor.

[0025] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, an electronic component in which a chip is housed in a package, etc. are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices or may include semiconductor devices.

[0026] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0027] As an example of the case where X and Y are electrically connected, one or more elements (e.g., switches, transistors, capacitance elements, inductors, resistance elements, diodes, display devices, light-emitting devices, loads, etc.) that enable the electrical connection between X and Y can be connected between X and Y.

[0028] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase signal amplitude or current, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0029] When it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or circuit between them).

[0030] Furthermore, for example, it can be expressed as follows: "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as follows: "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0031] Note that even when independent components are shown electrically connected in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both wiring and an electrode. Therefore, the term "electrically connected" in this specification also includes such cases where one conductive film has the functions of multiple components.

[0032] Furthermore, in this specification and the like, a "resistance element" can be, for example, a circuit element having a resistance value higher than 0Ω, or a wiring having a resistance value higher than 0Ω. Therefore, in this specification and the like, a "resistance element" is intended to include a wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, and the like. Therefore, the term "resistance element" can sometimes be replaced with terms such as "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," and "region having a resistance value" can sometimes be replaced with terms such as "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value can be replaced with a resistance value of 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0033] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a wiring region having a capacitance value higher than 0 F, a parasitic capacitance, a gate capacitance of a transistor, etc. Therefore, in this specification, a "capacitive element" is intended to include a circuit element including a pair of electrodes and a dielectric between the electrodes. Furthermore, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can sometimes be replaced with terms such as "capacitance." Conversely, the term "capacitance" can sometimes be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." Furthermore, the term "pair of electrodes" in "capacitance" can be replaced with "pair of conductors," "pair of conductive regions," "pair of regions," etc. The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. It can also be, for example, 1 pF or more and 10 μF or less.

[0034] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms source and drain may be interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the structure of the transistor, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as a first gate, and the other of the gate or backgate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification and the like.

[0035] The S value is the gate voltage required to increase the current between the source electrode and the drain electrode (subthreshold current) by one order of magnitude. Generally, the smaller the S value, the steeper the slope of the subthreshold current with respect to the gate voltage, which is considered to be a good characteristic with excellent switching characteristics.

[0036] For example, in this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used as an example of a transistor. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the breakdown voltage (reliability) of the transistor. Furthermore, when operating in the saturation region, the multi-gate structure can provide a voltage-current characteristic with a flat slope, whereby the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing a voltage-current characteristic with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0037] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a circuit diagram shows one resistor, this includes two or more resistors electrically connected in series. For example, when a circuit diagram shows one capacitor, this includes two or more capacitors electrically connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors electrically connected in series, with the gates of the transistors electrically connected to each other. Similarly, when a circuit diagram shows one switch, this includes two or more transistors electrically connected in series or parallel, with the gates of the transistors electrically connected to each other.

[0038] Furthermore, in this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, device structure, etc. Furthermore, a terminal, a wiring, etc. can be referred to as a node.

[0039] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0040] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not refer to specific potentials. A "high-level potential" means a potential that is more positive than a "low-level potential," and a "low-level potential" means a potential that is more negative than a "high-level potential." Furthermore, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0041] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, a statement that "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, vacuum, etc.). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current flow and is expressed as a negative current amount. Therefore, in this specification, etc., unless otherwise specified regarding the positive or negative sign of the current (or the direction of current), a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0042] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0043] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0044] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below, and being in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0045] Furthermore, in this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, in some cases or depending on the situation, terms such as "film" and "layer" may not be used and may be interchanged with other terms. For example, the terms "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, for example, the terms "insulating layer" and "insulating film" may be interchanged with the term "insulator."

[0046] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" in some cases.

[0047] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, terms such as "signal" may be changed to the term "potential."

[0048] In this specification and the like, the term "impurities" in semiconductors refers to, for example, elements other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities can cause, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements (excluding oxygen and hydrogen).

[0049] In this specification, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has the function of controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. Therefore, a switch may have two or more terminals for passing a current in addition to a control terminal. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific type as long as it can control a current.

[0050] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to, for example, a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited, or a state in which current can flow between the source electrode and drain electrode. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0051] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0052] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. [Effects of the Invention]

[0053] According to one embodiment of the present invention, a highly reliable transistor having a large S value can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that performs calculations by utilizing operation of a transistor in a subthreshold region can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having a wide subthreshold region can be provided. Alternatively, according to one embodiment of the present invention, a novel transistor or a novel semiconductor device can be provided.

[0054] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief explanation of the drawings]

[0055] [Figure 1] 1A and 1B are cross-sectional views showing examples of the structure of a transistor according to a semiconductor device. [Figure 2] FIG. 2 is a circuit diagram showing a configuration example of a product-sum operation circuit related to the semiconductor device. [Figure 3] FIG. 3 is a timing chart showing an example of the operation of the semiconductor device. [Figure 4] FIG. 4 is an explanatory diagram showing the operating state during the period T1 to T2. [Figure 5] FIG. 5 is an explanatory diagram showing the operating state during the period T3 to T4. [Figure 6] FIG. 6 is an explanatory diagram showing the operating state after the period T5. [Figure 7] FIG. 7 is a timing chart showing an example of the operation of the semiconductor device. [Figure 8]FIG. 8 is an explanatory diagram showing the operating state during the period T6 to T7. [Figure 9] FIG. 9 is an explanatory diagram showing the operating state during the period T8 to T9. [Figure 10] FIG. 10 is an explanatory diagram showing the operating state after the period T10. [Figure 11] 11A and 11B are cross-sectional views showing examples of the structure of a transistor relating to a semiconductor device. [Figure 12] FIG. 12A is a diagram illustrating the classification of IGZO crystal structures, FIG. 12B is a diagram illustrating the XRD spectrum of crystalline IGZO, and FIG. 12C is a diagram illustrating the electron microbeam diffraction pattern of crystalline IGZO. [Figure 13] 13A to 13H are diagrams showing electronic devices. [Figure 14] Fig. 14A is a diagram showing an Id-Vg curve obtained by device simulation, and Fig. 14B is a diagram showing an enlarged portion of Fig. 14A. Fig. 14C is a diagram showing S values ​​calculated at each Id, with Id in Fig. 14B plotted on the horizontal axis. DETAILED DESCRIPTION OF THE INVENTION

[0056] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0057] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0058] In this specification and the like, the configurations shown in each embodiment can be combined as appropriate with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate with each other.

[0059] In addition, the content (or even part of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (or even part of the content) described in that embodiment and another content (or even part of the content) described in one or more other embodiments.

[0060] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0061] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and at least one figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0062] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0063] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m,n]" may be added to the reference numeral. Also, when an identification symbol such as "_1", "[n]", "[m,n]" is added to the reference numeral in the drawings, etc., the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0064] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0065] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention will be described.

[0066] <Configuration example of semiconductor device> The semiconductor device described in this embodiment is, as an example, a transistor having a TGSA (Trench Gate Self Align) structure as shown in FIG. 1 . The transistor also has a conductive layer 103 on the back channel side, and an insulating film between the conductive layer 103 and a semiconductor layer 130. The insulating film includes a ferroelectric layer 120. Here, the side of the semiconductor layer 130 closer to the gate electrode 160 is referred to as the front channel side, and the side farther from the gate electrode is referred to as the back channel side. The transistor structure is not limited to the TGSA structure, and so-called top gate structure, bottom gate structure, etc. may also be adopted. In these structures, the conductive layer 103 and the ferroelectric layer 120 may be provided on the back channel side. For the ferroelectric layer 120, a material that can exhibit ferroelectricity may be used in a state in which ferroelectricity is exhibited.

[0067] As a material that can have ferroelectricity, for example, hafnium oxide is preferable. Alternatively, as a material that can have ferroelectricity, zirconium oxide, hafnium zirconium oxide (HfZrO XMetal oxides such as J1 (where X is a real number greater than 0) can be used. Alternatively, a material that can have ferroelectricity can be a material in which hafnium oxide is doped with element J1 (here, element J1 is one or more selected from zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.). Here, the atomic ratio of hafnium atoms to element J1 can be set appropriately, and for example, the atomic ratio of hafnium atoms to element J1 can be set to 1:1 or close to 1:1. Alternatively, a material that can have ferroelectricity can be a material in which zirconium oxide is doped with element J2 (here, element J2 is one or more selected from hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.). The ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately. For example, the ratio of the number of zirconium atoms to the number of atoms of element J2 may be set to 1:1 or close to 1:1. Furthermore, as a material that can have ferroelectricity, lead titanate (PbTiO X Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0068] Furthermore, materials that can have ferroelectricity include aluminum scandium nitride (Al 1-a Sc a N b(where a is a real number greater than 0 and less than 0.5, and b is 1 or a value close to 1; hereinafter, simply referred to as AlScN), Al-Ga-Sc nitride, Ga-Sc nitride, etc. can be used. Furthermore, as a material that can have ferroelectricity, a metal nitride having elements Ma1, Ma2, and nitrogen can be used. Here, element Ma1 is one or more elements selected from aluminum (Al), gallium (Ga), indium (In), etc. Furthermore, the element Ma2 is one or more selected from boron (B), scandium (Sc), yttrium (Y), lanthanides (lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu)), actinides (15 elements from actinium (Ac) to lawrencium (Lr)), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), and the like. The ratio of the number of atoms of element Ma1 to the number of atoms of element Ma2 can be set appropriately. Metal oxides containing element Ma1 and nitrogen may exhibit ferroelectricity even without containing element Ma2. Ferroelectric materials include the above-mentioned metal nitrides to which element Ma3 has been added. The element Ma3 is one or more elements selected from the group consisting of magnesium (Mg), calcium (Ca), strontium (Sr), zinc (Zn), cadmium (Cd), and the like. The ratio of the number of atoms of element Ma1, the number of atoms of element Ma2, and the number of atoms of element Ma3 can be set appropriately. Because the above-mentioned metal nitrides contain at least a Group 13 element and nitrogen, a Group 15 element, the metal nitrides are sometimes referred to as Group III-V ferroelectrics or Group III nitride ferroelectrics.

[0069] Moreover, as a material that can have ferroelectricity, perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, GaFeO3 with a κ-alumina structure, and the like can be used.

[0070] Furthermore, the material capable of exhibiting ferroelectricity can be, for example, a mixture or compound of multiple materials selected from the materials listed above. Alternatively, the material capable of exhibiting ferroelectricity can be a layered structure of multiple materials selected from the materials listed above. The crystal structure and electrical properties of the materials listed above may vary depending not only on the film formation conditions but also on various processes. Therefore, in this specification, the above-mentioned materials are referred to not only as ferroelectrics but also as materials capable of exhibiting ferroelectricity. Furthermore, the term "ferroelectric" also includes materials capable of exhibiting ferroelectricity. In this specification, even if a material capable of exhibiting ferroelectricity is referred to as a material that is not explicitly referred to as a material capable of exhibiting ferroelectricity, it will be treated as an insulator.

[0071] As a material that can have ferroelectricity, hafnium oxide or a material containing hafnium oxide and zirconium oxide (typically HfZrOx) is suitable because it can have ferroelectricity even when processed into a thin film of several nm.

[0072] Alternatively, aluminum scandium nitride (AlScN) is suitable as a material that can have ferroelectricity because it can be formed by sputtering, and the impurity concentration in the film can be reduced or a dense film can be formed. When aluminum scandium nitride (AlScN) is used as a material that can have ferroelectricity, it is expected to form a highly reliable film.

[0073] The thickness of the layer of the ferroelectric material can be 1 nm or more, preferably 2 nm or more, and more preferably 5 nm or more. A thickness that does not cause leakage current is more preferable. The thickness of the layer of the ferroelectric material is preferably a thickness that allows application of an electric field sufficient to generate polarization. For example, the thickness can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less. That is, the thickness of the layer of the ferroelectric material can be in the range of 2 nm to 30 nm, more preferably 5 nm to 15 nm. By setting the thickness of the ferroelectric material to the above range, it is possible to achieve a thin film and exhibit ferroelectricity. In this specification, a layer of a ferroelectric material may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. In this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0074] In addition, HfZrO is a material that can have ferroelectric properties. X When using a ferroelectric material, it is preferable to form the film using atomic layer deposition (ALD), particularly thermal ALD. Furthermore, when using thermal ALD to form a film of a material that can have ferroelectricity, it is preferable to use a material that does not contain hydrocarbons (also called hydrocarbon, HC) as a precursor. If the material that can have ferroelectricity contains either or both of hydrogen and carbon, this may inhibit the crystallization of the material that can have ferroelectricity. Therefore, as described above, it is preferable to use a precursor that does not contain hydrocarbons to reduce the concentration of either or both of hydrogen and carbon in the material that can have ferroelectricity. For example, a chlorine-based material can be used as a precursor that does not contain hydrocarbons. Furthermore, as a material that can have ferroelectricity, a material containing hafnium oxide and zirconium oxide (HfZrO x), HfCl4 and / or ZrCl4 may be used as the precursor. On the other hand, a dopant (typically silicon, carbon, etc.) for controlling the polarization state may be added to a material that may have ferroelectricity. In this case, one method for adding carbon as a dopant may be to use a formation method using a material containing hydrocarbon as the precursor.

[0075] When a film is formed using a material that can have ferroelectricity, impurities in the film, in this case at least one of hydrogen, hydrocarbon, and carbon, are thoroughly removed, thereby forming a film having high-purity intrinsic ferroelectricity. The film having high-purity intrinsic ferroelectricity and the high-purity intrinsic oxide semiconductor shown in the embodiment described later have very high compatibility in manufacturing processes. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.

[0076] Furthermore, it is preferable that the impurity concentration of the material capable of having ferroelectricity is low. In particular, it is preferable that the concentrations of hydrogen (H) and carbon (C) are low. Specifically, the hydrogen concentration of the material capable of having ferroelectricity is 5×10 20 atoms / cm 3 Less than 1×10 is preferred 20 atoms / cm 3 The carbon concentration of the material that can have ferroelectricity is preferably 5×10 or less. 19 atoms / cm 3 Less than 1×10 is preferred 19 atoms / cm 3 The following is more preferred:

[0077] In addition, HfZrO is a material that can have ferroelectric properties. X When using hafnium oxide and zirconium oxide, it is preferable to use a thermal ALD method to alternately form films of hafnium oxide and zirconium oxide in a 1:1 ratio.

[0078] Furthermore, when a film of a material that may have ferroelectricity is formed using a thermal ALD method, the oxidizing agent may be H2O or O3. However, the oxidizing agent for the thermal ALD method is not limited to these. For example, the oxidizing agent for the thermal ALD method may include one or more selected from O2, O3, N2O, NO2, H2O, and H2O2.

[0079] Furthermore, the crystal structure of the ferroelectric material is not particularly limited as long as it exhibits ferroelectricity. For example, the crystal structure of the ferroelectric material may be one or more selected from cubic, tetragonal, orthorhombic, and monoclinic systems. An orthorhombic crystal structure is particularly preferred for ferroelectric materials because it exhibits ferroelectricity. A layer for enhancing crystallinity may be formed before forming the ferroelectric material. For example, when HfZrOx is used as the ferroelectric material, the layer for enhancing crystallinity may be a metal oxide such as hafnium oxide or zirconium oxide, or hafnium or zirconium. When AlScN is used as the ferroelectric material, the layer for enhancing crystallinity may be a metal nitride such as aluminum nitride or scandium nitride, or aluminum or scandium. Alternatively, the ferroelectric material may have a composite structure having an amorphous structure and a crystalline structure. For example, HfZrO is a material that can have ferroelectricity. X When using a material containing an O phase in its crystal structure, ferroelectricity is exhibited.

[0080] The ferroelectric layer 120 may be a laminate of a layer 122 of a material that may exhibit ferroelectricity and an insulator. For example, as shown in FIG. 1 , the ferroelectric layer 120 may be configured such that a layer 122 of a material that may exhibit ferroelectricity and an insulating layer 124, which is a first insulating layer, are provided in this order between the conductive layer 103 and the semiconductor layer 130. Alternatively, the ferroelectric layer 120 may be configured such that a second insulating layer and a layer 122 of a material that may exhibit ferroelectricity are provided in this order between the conductive layer 103 and the semiconductor layer 130. Alternatively, the ferroelectric layer 120 may be configured such that a second insulating layer, a layer 122 of a material that may exhibit ferroelectricity, and a first insulating layer (insulating layer 124) are provided in this order between the conductive layer 103 and the semiconductor layer 130.

[0081] The insulating material used for the first insulating layer (insulating layer 124) and the second insulating layer may be a paraelectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride. The insulator can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The sputtering method is particularly preferable when an oxide semiconductor is used for the semiconductor layer 130 because the amount of hydrogen absorbed as an impurity in the deposited film is small.

[0082] ALD methods include thermal ALD, which uses only thermal energy to react precursors and reactants, and plasma-enhanced ALD (PEALD), which uses plasma-excited reactants. The use of plasma in the PEALD method allows for film formation at lower temperatures, which can be preferable in some cases.

[0083] 1A and 1B are cross-sectional views illustrating a configuration example of a transistor 100. FIG. 1 illustrates an example in which a layer 122 of a material that may have ferroelectricity and an insulating layer 124 are provided in this order above a conductive layer 103. Specifically, FIG. 1A is a cross-sectional view of the transistor 100 in the channel direction, and FIG. 1B is a cross-sectional view of the transistor 100 in the channel width direction. The transistor 100 is an OS transistor including a metal oxide (oxide semiconductor) in the semiconductor layer 130. The transistor 100 has a very small off-state current. The transistor 100 also has a wide subthreshold region in its gate-source voltage-drain current characteristics.

[0084] As shown in FIG. 1A, the transistor 100 includes a conductive layer 103 disposed so as to be embedded in an insulator, a ferroelectric layer 120 disposed on the conductive layer 103, a semiconductor layer 130 disposed on the ferroelectric layer 120, conductive layers 142a and 142b disposed in contact with the semiconductor layer 130 and spaced apart from each other, and a gate electrode 160.

[0085] The conductive layer 103 is disposed so as to be embedded in an insulator, and can be formed by a so-called damascene process. This configuration allows the ferroelectric layer 120 to be provided on a relatively flat surface. By forming the ferroelectric layer 120 on a highly flat surface, the stress applied to the material that can have ferroelectricity can be made uniform, and the crystalline structure of the material that can have ferroelectricity can be uniformly contained in the ferroelectric layer 120 as a crystalline structure that manifests ferroelectricity.

[0086] 1A, the conductive layer 103 is preferably formed to be longer than the gate electrode 160 in the cross section in the channel length direction. This is because such a configuration makes it easier for the transistor 100 to be affected by the spontaneous polarization generated in the ferroelectric layer 120.

[0087] Ferroelectric materials are insulators that exhibit polarization when an external electric field is applied, and the polarization remains even after the electric field is removed (in this specification, the polarization is assumed to remain in the same direction as the externally applied electric field). After forming a transistor, applying an electric field to the ferroelectric layer 120 on the back channel side to a degree that causes residual polarization can change the transistor characteristics (S value) due to the influence of the residual polarization of the ferroelectric layer 120. In the case of an n-channel OS transistor, the S value can be increased compared to the characteristics immediately after transistor formation by adjusting the direction of the residual polarization from the conductive layer 103 to the semiconductor layer (OS) 130. This is because the residual polarization in the ferroelectric layer 120 induces negative charges on the back channel side of the semiconductor layer (OS), reducing controllability by the electric field from the gate electrode.

[0088] 1, 0 V is applied to the gate electrode 160, the conductive layer 142 a, and the conductive layer 142 b, and a positive potential is applied to the conductive layer 103. At this time, a positive charge is induced in the conductive layer 103, and a negative charge is induced in the semiconductor layer (OS) 130. Next, when the potential of the conductive layer 103 is returned from the positive potential to 0 V, some of the dipoles in the ferroelectric layer become disordered and the polarization decreases, but the remaining dipoles remain aligned (residual polarization), and negative charges remain induced in the semiconductor layer (OS).

[0089] According to one embodiment of the present invention, a novel transistor can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable transistor having a large S value can be provided. Alternatively, according to one embodiment of the present invention, a transistor whose S value can be changed after fabrication of a semiconductor device can be provided.

[0090] Furthermore, one embodiment of the present invention makes it possible to selectively form a conductive layer and a ferroelectric layer on the back channel side of a transistor with or without the conductive layer, and thus makes it possible to provide a semiconductor device having, in a single circuit, a transistor whose S value can be changed after the semiconductor device is formed and a transistor with good characteristics.

[0091] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0092] (Embodiment 2) In this embodiment mode, a product-sum operation circuit including the transistors described in the above embodiment modes will be described.

[0093] <Configuration example of a multiply-accumulate circuit> FIG. 2 illustrates an example of a circuit (a product-sum circuit) that can be used for a product-sum operation. The product-sum circuit may be configured by arranging m (m is an integer of 2 or greater) circuits in a row direction and n (n is an integer of 2 or greater) circuits in a matrix as one cell. Hereinafter, for simplicity, the circuit will be described using a single-cell operation circuit as shown in FIG. 2. The circuit includes transistors Tr1, Tr2, M1, M2, and capacitors C1 and C2. The transistors M1 and M2 may be transistors that can have a large S value after fabrication, as described in Embodiment 1. Increasing the S values ​​of the transistors M1 and M2 can widen the voltage range for operating the product-sum circuit. Furthermore, by using OS transistors with low off-state current and small S values ​​as the transistors Tr1 and Tr2, a product-sum circuit with low power consumption and high-speed operation can be realized. The transistors Tr1 and Tr2 may have a single-gate structure or a dual-gate structure. In either structure, the transistors M1 and M2 can be manufactured in the same process.

[0094] The driver circuit for driving the circuit shown in Figure 2 may be fabricated on a Si substrate. Stacking the circuit with the cells can reduce the circuit's footprint. The driver circuit may also be formed using OS transistors. OS transistors have low leakage current, resulting in a circuit with low standby current and low power consumption. When using OS transistors, transistors M1 and M2 can be formed simultaneously with transistors Tr1 and Tr2, eliminating the need for additional processes and reducing costs.

[0095] <Example 1> Next, an example of the operation of the arithmetic circuit of FIG. 2 will be described.

[0096] The transistors M1 and M2 are transistors having a ferroelectric layer and a conductive layer on the back channel side. Here, the transistors M1 and M2 have gates G1 and G2, respectively. The conductive layers on the back channel side of the transistors M1 and M2 are designated as conductive layers BG1 and BG2, respectively.

[0097] <Writing into the ferroelectric layer> First, we will explain the case where the threshold voltages Vth of transistors Tr1, Tr2, M1, and M2 are positive after transistors Tr1, Tr2, M1, and M2 are fabricated. We also assume that the threshold voltages Vth of transistors Tr1, Tr2, M1, and M2 are the same. We also assume that the S values ​​of transistors Tr1, Tr2, M1, and M2 are initially set to S1.

[0098] Fig. 3 shows a timing chart (T1 to T5) of an example of the operation of the arithmetic circuit of Fig. 2. Also, Figs. 4 to 6 show the state at each timing.

[0099] In the unwritten state (before T1), the potentials of all wirings and terminals, including gate G1 and gate G2, are set to the ground potential GND. Also, assume that no spontaneous polarization occurs in the ferroelectric layers of transistors M1 and M2.

[0100] To increase the S value of transistors M1 and M2, a positive electric field greater than the coercive field can be applied from the conductive layers BG1 and BG2 on the back channel side toward the semiconductor layer. For example, during write (Figure 3: T1-T2 and Figure 4), a high-level potential Vhi (>Vth>0V) is applied to the conductive layers BG1 and BG2 and the wiring g, and a ground potential GND (~0V) is applied to the wiring x and wiring y. Applying such potentials generates polarization in the ferroelectric layers of transistors M1 and M2. Even when the potentials of the conductive layers BG1 and BG2 are returned to ground potential (T2), the polarization (residual polarization) remains. Due to the influence of the remanent polarization, the S value of transistors M1 and M2 changes to S2 (>S1). The ground potential can be applied to the conductive layers BG1 and BG2 except when writing to the ferroelectric layers.

[0101] The conductive layers BG1 and BG2 are electrically connected to each other, allowing the same potential to be applied to them. This reduces the number of wirings in the circuit and the area occupied by the circuit. The conductive layers BG1 and BG2 may also be individually controlled for potential. By controlling the potentials individually, an optimal potential can be applied to each transistor, enabling precise control over changes in the S value.

[0102] <Initial state> Next, we will explain the arithmetic processing in the transistors M1 and M2 after writing to the ferroelectric layers. The currents flowing through the wires x and y are Id1 and Id2, respectively. In the initial state (T3-T4 in FIG. 3, FIG. 5), a high-level potential Vhi is applied to the wire g, and a reference current value I x0flows, and a current value w×I, which is w times the reference current value, flows through the output wiring y. x0 The reference current value I x0 and current value w×I x0 is set as the amount of current that flows when the transistors M1 and M2 operate in the subthreshold region. Since the wiring g is at the high level potential Vhi, the transistors Tr1 and Tr2 are turned on, and over time, the gates G1 and G2 of the transistors M1 and M2 respectively flow with the reference current value I x0 and current value w×I x0 These potentials are equal to the potentials applied to the wiring x and wiring y, respectively. Here, these potentials are designated as Vg1 and Vg2.

[0103] After a certain time has elapsed (T4), the potential of the wire g is returned to the ground potential, which turns off the transistors Tr1 and Tr2, and maintains the potentials Vg1 and Vg2 of the gates G1 and G2 of the transistors M1 and M2, respectively.

[0104] <Calculation> Next (Fig. 3: T5~, Fig. 6), the potential of wire g remains at ground potential, and a current value x × I, which is x times the reference current value, is applied to input wire x. x0 Since the potential of the wiring g is the ground potential, the transistor Tr1 is in the off state and no current flows through the transistor Tr1. However, the potential of the gate G1 of the transistor M1 is increased by the capacitance coupling of the capacitor C1, resulting in a current value x × I x0 The amount of change in potential is denoted as Δ. In this case, if the capacitive coupling coefficient around the capacitor C1 is 1, the potential of the wiring x and the gate G1 of the transistor M1 becomes Vg1+Δ.

[0105] Similarly, if the capacitive coupling coefficient around the capacitor C2 is 1, the potential of the gate G2 of the transistor M2 also changes by Δ due to the capacitive coupling between the wiring x and the capacitor C2, becoming Vg2 + Δ. As a result, the output side wiring y has a capacitance of x × w × I x0This is x × w times the reference current value, and the result of multiplying x and w is output. Current value x × I x0 and current value x × w × I x0 is also set as the amount of current that flows when the transistor M1 and the transistor M2 operate in the subthreshold region.

[0106] Here, the current value flowing through the output wiring y is x × w × I x0 The current value can be detected by a current detector provided on the GND side of transistor M2. Furthermore, by providing this circuit in a matrix as one cell and using the column wiring y in common to detect the current, product-sum calculations become possible.

[0107] When the threshold voltage Vth is positive, a positive potential is applied to the wiring x and the wiring y, and when the conductive layer BG1 of the transistor M1 and the conductive layer BG2 of the transistor M2 are connected to GND, an electric field in the opposite direction to the writing is applied to the ferroelectric layers of the transistors M1 and M2. However, the potentials applied to the wiring x and the wiring y are potentials that cause the transistors M1 and M2 to operate in their respective subthreshold regions, and are small as electric fields. Furthermore, by driving the transistors at high speed, it is possible to complete the operation before the polarization (residual polarization) written in the ferroelectric layers is reversed or reduced.

[0108] <Example 2> Next, a case where the threshold voltages Vth of the transistors Tr1, Tr2, M1, and M2 are negative after the transistors Tr1, Tr2, M1, and M2 are fabricated will be described.

[0109] Fig. 7 shows a timing chart of an example of operation when the threshold voltage Vth is negative, and Figs. 8 to 10 show the state at each timing.

[0110] Even when the threshold voltage Vth is negative, the direction of the electric field applied to the ferroelectric layers of the transistors M1 and M2 is the same as when the threshold voltage Vth is positive. That is, for writing (T6 to T7 in FIG. 7, FIG. 8), a high-level potential Vhi (Vhi is a potential greater than 0 V) ​​is applied to the conductive layers BG1 and BG2, and a ground potential GND is applied to the wiring g, wiring x, and wiring y. The difference from when the threshold voltage Vth is positive is that even if the ground potential GND is applied to the wiring g, the gates of the transistors M1 and M2 are turned on, so it is not necessary to apply the high-level potential Vhi to the wiring g. Furthermore, at the timing (T7) when the potentials of the conductive layers BG1 and BG2 are returned to the ground potential, the potential of the wiring g is set to a low-level potential Vlo. Note that Vlo is a potential lower than the ground potential GND.

[0111] <Initial state> In the initial state (T8 to T9 in FIG. 7, FIG. 9), a ground potential GND (the ground potential GND is higher than Vth) is applied to the wiring g, and a reference current value I x0 flows, and a current value w×I, which is w times the reference current value, flows through the output wiring y. x0 The reference current value I x0 and current value w×I x0 is set as the amount of current that flows when the transistors M1 and M2 operate in the subthreshold region, but because Vth is negative, a potential lower than the ground potential GND is applied to the input side wiring x and the output side wiring y.

[0112] After a certain time has elapsed (T9), the potential of the wiring g is returned to the low-level potential Vlo, which turns off the transistors Tr1 and Tr2, and maintains the potentials Vg1 and Vg2 of the gates G1 and G2 of the transistors M1 and M2, respectively.

[0113] <Calculation> Next (T10 in Figure 7, Figure 10), the potential of the wire g remains at the low level potential Vlo, and a current value x × I, which is x times the reference current value, is applied to the input side wire x. x0Since the potential of the wiring g is the low level potential Vlo, the transistor Tr1 is in the off state and no current flows through the transistor Tr1. However, the potential of the gate G1 of the transistor M1 is increased by the capacitance coupling of the capacitor C1, resulting in a current value x×I x0 At this time, if the capacitive coupling coefficient around the capacitor C1 is 1, the potential of the wiring x and the gate G1 of the transistor M1 becomes Vg1+Δ.

[0114] Similarly, if the capacitive coupling coefficient around the capacitor C2 is 1, the potential of the gate G2 of the transistor M2 also changes by Δ due to the capacitive coupling between the wiring x and the capacitor C2, becoming Vg2 + Δ. As a result, the output side wiring y has a capacitance of x × w × I x0 This is x × w times the reference current value, and the result of multiplying x and w is output. Current value x × I x0 and current x×w×I x0 is also set as the amount of current that flows when the transistor M1 and the transistor M2 operate in the subthreshold region.

[0115] At this time, if the potential applied to the output side wiring y is changed, the calculation will not be performed correctly, so if the threshold voltage Vth is negative, the potential of the output side wiring must be fixed.

[0116] Writing to the ferroelectric layer only needs to be done once after the transistors are formed. Unless an electric field opposite to that used during writing is applied, the polarization remains intact, eliminating the need for a write operation each time a multiply-and-accumulate operation is performed. Furthermore, once writing to the ferroelectric layer is performed, the S values ​​of transistors M1 and M2 remain increased due to the influence of residual polarization. Therefore, during the calculation process, the conductive layers BG1 and BG2 can be set to a ground potential (GND), eliminating the need to apply or control potentials to the conductive layers BG1 and BG2, enabling low-power calculations. In other words, the periods between T2 and T3 and between T7 and T8 can be performed consecutively, but they do not have to be.

[0117] It is desirable to investigate in advance the characteristics of transistors M1 and M2 in the subthreshold region (the Id-Vg characteristics when the S value is S2). Because transistors M1 and M2 have characteristics in which the S value increases, the potential to be applied to the current to be passed through wiring x and wiring y can be finely (accurately) adjusted, enabling a product-sum operation with a wider range of driving voltages for wiring x and wiring y. Furthermore, even if the characteristics of transistors M1 and M2 in the subthreshold region are not clearly known, accurate operation is possible as long as the rise in potential of each wiring can be stopped by detecting the current value passed through wiring x and wiring y.

[0118] According to one embodiment of the present invention, a highly reliable transistor having a large S value can be provided. Alternatively, a semiconductor device using a subthreshold region for calculation can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device capable of performing product-sum operations with a wider range of operating voltages can be provided.

[0119] (Embodiment 3) In this embodiment, structural examples of the semiconductor device described in the above embodiment and structural examples of a transistor that can be applied to the semiconductor device will be described.

[0120] FIG. 11A is a cross-sectional view of the transistor 500 in the channel direction, and FIG. 11B is a cross-sectional view of the transistor 500 in the channel width direction. The transistor 500 shown in FIGS. 11A and 11B has a structure similar to that of the transistor 100 described in Embodiment 1. Although the transistor 500 is shown to have a structure including a layer 522 of a material that can exhibit ferroelectricity and a conductor 503, a transistor without the layer 522 of a material that can exhibit ferroelectricity or the conductor 503, or without both the layer 522 of a material that can exhibit ferroelectricity and the conductor 503, can also be fabricated at the same time. In this case, when the layer 522 of a material that can exhibit ferroelectricity is provided in the transistor, the layer 522 of the material that can exhibit ferroelectricity may be extended between the transistor 500 and the transistor 500 to share the layer, or the layer 522 of the material that can exhibit ferroelectricity may be provided separately.

[0121] The transistor 500 is disposed above an insulator 512 .

[0122] As shown in FIG. 11A , the transistor 500 includes an insulator 514 and an insulator 516 disposed on an insulator 512, a conductor 503 disposed so as to be embedded in the insulators 514 and 516, a ferroelectric layer 520 disposed on the insulator 516 and the conductor 503, an oxide 530 disposed on the ferroelectric layer 520, conductors 542a and 542b disposed apart from each other in the oxide 530, an insulator 580 disposed on the conductors 542a and 542b and having an opening formed therein overlapping the conductors 542a and 542b, an insulator 550 disposed on the bottom and side surfaces of the opening, and a conductor 560 disposed on the surface on which the insulator 550 is formed.

[0123] The conductor 503 is disposed so as to be embedded in the insulators 514 and 516, and can be formed by a so-called damascene process. With this configuration, the ferroelectric layer 520 can be provided on a relatively flat surface. By forming the ferroelectric layer 520 on a highly flat surface, the stress applied to the material that can have ferroelectricity can be made constant, and the crystalline structure of the material that can have ferroelectricity can be uniformly contained in the ferroelectric layer 520 as a crystalline structure that exhibits ferroelectricity.

[0124] Although the transistor 500 has a two-layer structure of oxides 530a and 530b in and around a channel formation region, one embodiment of the present invention is not limited to this structure. For example, the transistor may have a single layer of oxide 530b, a three-layer structure in which oxide 530c is provided over oxide 530b, or a stacked structure of four or more layers. Although the transistor 500 has a two-layer structure, one embodiment of the present invention is not limited to this structure. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. The transistor 500 illustrated in FIGS. 11A and 11B is merely an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration, driving method, and the like. In this specification, the oxide 530a and the oxide 530b may be collectively referred to as the oxide 530.

[0125] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source and drain electrodes, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangements of the conductors 560, 542a, and 542b are selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be positioned between the source and drain electrodes in a self-aligned manner. Therefore, the conductor 560 can be formed without providing an alignment margin, thereby reducing the area occupied by the transistor 500. This allows for miniaturization and high integration of semiconductor devices.

[0126] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. This reduces the parasitic capacitance formed between the conductor 560 and the conductor 542a and between the conductor 560 and the conductor 542b. This improves the switching speed of the transistor 500 and provides high frequency characteristics.

[0127] When the layer 522 of a material that can have ferroelectricity is not provided, the conductor 560 may function as a first gate (also referred to as a top gate) electrode. The conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 can increase the threshold voltage of the transistor 500 above 0 V and reduce the off-state current. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V compared to when a negative potential is not applied.

[0128] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. In this way, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and the channel formation region formed in the oxide 530 can be covered. In this specification and the like, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate electrode and the second gate electrode is called a surrounded channel (S-channel) structure.

[0129] Furthermore, when the layer 522 of the material that may have ferroelectricity is provided, the conductor 503 functions as an electrode that applies an electric field (electric field) to the layer 522 of the material that may have ferroelectricity and generates remanent polarization. In this case, the potential of the conductor 503 can be adjusted independently of the conductor 560, and a constant potential may be applied to the conductor 503 while the circuit is operating.

[0130] In addition, the conductor 503 has a conductor 503a formed in contact with the inner walls of the openings of the insulators 514 and 516, and a conductor 503b formed further inside. Note that although the transistor 500 has a structure in which the conductor 503a and the conductor 503b are stacked, one embodiment of the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0131] Here, the conductor 503a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, copper atoms, etc. (the impurities are less likely to permeate). Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate). In this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities or oxygen. Specifically, TiN X , TaN X It is preferable to use a metal nitride film such as the above.

[0132] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503b can be prevented from being oxidized and its conductivity from decreasing.

[0133] Furthermore, when the conductor 503 also functions as a wiring, it is preferable that the conductor 503b be made of a highly conductive material containing tungsten, copper, or aluminum as a main component. Although the conductor 503b is illustrated as a single layer, it may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above-mentioned conductive material.

[0134] The layer 522 of the material capable of exhibiting ferroelectricity can be formed using the material shown in the first embodiment. The material capable of exhibiting ferroelectricity is used under conditions that allow it to exhibit ferroelectricity. The conditions that allow it to exhibit ferroelectricity vary depending on the material used, and specifically, depend on the crystalline structure of the crystals contained in the film. For example, HfZrO is an example of a material capable of exhibiting ferroelectricity. X When using the above, the thickness of the layer of the material that can have ferroelectricity may be in the range of 2 nm to 30 nm, more preferably 5 nm to 15 nm, and ferroelectricity is exhibited by including an O phase in the crystal structure of the crystals contained in the film.

[0135] The ferroelectric layer 520 may be a stack of a layer 522 of a material that can have ferroelectricity and an insulator. FIG. 11 shows an example in which the layer 522 of a material that can have ferroelectricity is provided on the insulator 516 and the conductor 503, and an insulator 524, which is a first insulator, is provided on the layer 522 of the material that can have ferroelectricity. Alternatively, a second insulator may be provided on the insulator 516 and the conductor 503, and the layer 522 of a material that can have ferroelectricity may be provided on the second insulator. Alternatively, the insulator 524 may be provided on the side closer to the oxide 530 and the second insulator may be provided on the side closer to the conductor 503, and the second insulator, the layer 522 of a material that can have ferroelectricity, and the first insulator (insulator 524) may be provided in this order on the insulator 516 and the conductor 503.

[0136] When the conductor 503 is provided without providing the layer 522 of a material that may have ferroelectricity, the first insulator (insulator 524) or the second insulator, or the first insulator (insulator 524) and the second insulator, function as a second gate insulating film. Note that the second insulator can be made of a material that can be used for the first insulator (insulator 524).

[0137] Here, the insulator 524 in contact with the oxide 530 preferably contains more oxygen than the oxygen required for the stoichiometric composition. That is, an excess oxygen region is preferably formed in the insulator 524. By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies in the oxide 530 can be reduced and the reliability of the transistor 500 can be improved.

[0138] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating as an insulator having an excess oxygen region. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen converted to oxygen atoms is 1.0 × 10 in TDS (Thermal Desorption Spectroscopy) analysis. 18 atoms / cm 3 or more, preferably 1.0 × 10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / cm 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is one having the above properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0139] Alternatively, the oxide 530 may be brought into contact with the insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By performing such treatment, water or hydrogen in the oxide 530 can be removed. For example, in the oxide 530, V O A reaction occurs in which the bond of H is broken, in other words, "VO H→V O +H" reaction occurs, resulting in dehydrogenation. Some of the generated hydrogen may combine with oxygen to form HO and be removed from the oxide 530 or the insulator near the oxide 530. Some of the hydrogen may also be diffused or captured (also called gettered) in the conductor 542a and the conductor 542b.

[0140] The microwave treatment is preferably performed using, for example, an apparatus having a power source for generating high-density plasma or an apparatus having a power source for applying RF to the substrate side. For example, high-density oxygen radicals can be generated by using an oxygen-containing gas and high-density plasma, and the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator near the oxide 530 by applying RF to the substrate side. The microwave treatment is performed at a pressure of 133 Pa or higher, preferably 200 Pa or higher, and more preferably 400 Pa or higher. The gases introduced into the microwave treatment apparatus may be, for example, oxygen and argon, with an oxygen flow ratio (O2 / (O2+Ar)) of 50% or less, preferably 10% to 30%.

[0141] During the manufacturing process of the transistor 500, heat treatment is preferably performed with the surface of the oxide 530 exposed. The heat treatment may be performed, for example, at a temperature of 100° C. to 450° C., more preferably 350° C. to 400° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby eliminating oxygen vacancies (V O) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0142] By subjecting the oxide 530 to oxygen addition treatment, oxygen vacancies in the oxide 530 are repaired by the supplied oxygen. In other words, O Furthermore, the reaction of the hydrogen remaining in the oxide 530 with the supplied oxygen can be removed as H2O (dehydration). As a result, the hydrogen remaining in the oxide 530 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0143] The second insulator is preferably thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Furthermore, by combining a high-k insulator with silicon oxide or silicon oxynitride, a thermally stable second insulator with a laminated structure having a high dielectric constant can be obtained.

[0144] 11A and 11B, the ferroelectric layer 520 has a two-layer laminate structure, which includes a layer 522 made of a material that can have ferroelectricity and an insulator 524. However, the ferroelectric layer 520 may have a single layer, two layers, or a laminate structure of four or more layers. In this case, the ferroelectric layer 520 is not limited to a laminate structure made of the same material, and may have a laminate structure made of different materials.

[0145] In the transistor 500, a metal oxide functioning as an oxide semiconductor is preferably used for the oxide 530 including the channel formation region. The metal oxide functioning as an oxide semiconductor will be described in detail in Embodiment 4.

[0146] The metal oxide that functions as a channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0147] The oxide 530 has the oxide 530a below the oxide 530b, which can prevent impurities from diffusing from structures formed below the oxide 530a to the oxide 530b. Also, the oxide 530 has the oxide 530c on the oxide 530b, which can prevent impurities from diffusing from structures formed above the oxide 530c to the oxide 530b.

[0148] The oxide 530 preferably has a structure of multiple oxide layers with different atomic ratios of the metal atoms. Specifically, the atomic ratio of the element Ma among the constituent elements in the metal oxide used for the oxide 530a is preferably greater than the atomic ratio of the element Ma among the constituent elements in the metal oxide used for the oxide 530b. The atomic ratio of the element Ma to In in the metal oxide used for the oxide 530a is preferably greater than the atomic ratio of the element Ma to In in the metal oxide used for the oxide 530b. The atomic ratio of In to Ma in the metal oxide used for the oxide 530b is preferably greater than the atomic ratio of In to Ma in the metal oxide used for the oxide 530a. The oxide 530c can be the same metal oxide as that used for the oxide 530a or the oxide 530b.

[0149] Specifically, oxide 530a may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=1:3:4 or 1:1:0.5. Oxide 530b may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=4:2:3 or 1:1:1. Oxide 530c may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=1:3:4 and an atomic ratio of Ga to Zn of Ga:Zn=2:1 or Ga:Zn=2:5. Specific examples of the oxide 530c having a layered structure include layered structures in which the atomic ratios of In, Ga, and Zn are In:Ga:Zn=4:2:3 and In:Ga:Zn=1:3:4, layered structures in which the atomic ratios of Ga and Zn are Ga:Zn=2:1 and In:Ga:Zn=4:2:3, layered structures in which the atomic ratios of Ga and Zn are Ga:Zn=2:5 and In:Ga:Zn=4:2:3, and layered structures in which gallium oxide and In, Ga, and Zn are In:Ga:Zn=4:2:3.

[0150] Furthermore, for example, when the atomic ratio of In to element Ma in the metal oxide used for oxide 530a is smaller than the atomic ratio of In to element Ma in the metal oxide used for oxide 530b, an In-Ga-Zn oxide having a composition in which the atomic ratio of In to Ga to Zn is In:Ga:Zn=5:1:6 or thereabouts, In:Ga:Zn=5:1:3 or thereabouts, or In:Ga:Zn=10:1:3 or thereabouts, can be used as oxide 530b.

[0151] In addition to the compositions described above, oxide 530b may be made of a metal oxide having a composition of In:Zn=2:1, a composition of In:Zn=5:1, a composition of In:Zn=10:1, or a composition close to any one of these.

[0152] It is preferable to combine these oxides 530a, 530b, and 530c so that the atomic ratios satisfy the above relationship. For example, it is preferable that oxides 530a and 530c are metal oxides having a composition of In:Ga:Zn=1:3:4 or a composition close to that. It is also preferable that oxide 530b be a metal oxide having a composition of In:Ga:Zn=4:2:3 to 4.1 or a composition close to that, or a composition of In:Ga:Zn=1:1:2 or a composition close to that, or a composition of In:Ga:Zn=1:1:1.2 or a composition close to that. Note that the above compositions refer to the atomic ratios in the oxide formed on the substrate or in the sputtering target. Furthermore, increasing the In ratio in the composition of oxide 530b is preferable because it can increase the on-state current or field-effect mobility of the transistor.

[0153] The conduction band minimum energy of the oxide 530a and the oxide 530c is preferably higher than that of the oxide 530b. In other words, the electron affinity of the oxide 530a and the oxide 530c is preferably smaller than that of the oxide 530b.

[0154] Here, the energy level of the conduction band minimum changes gradually at the junction between the oxides 530a, 530b, and 530c. In other words, the energy level of the conduction band minimum at the junction between the oxides 530a, 530b, and 530c changes continuously or forms a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layers formed at the interface between the oxides 530a and 530b and at the interface between the oxides 530b and 530c.

[0155] Specifically, when the oxide 530a and the oxide 530b, and the oxide 530b and the oxide 530c have a common element (main component) other than oxygen, a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxide 530a and the oxide 530c may be made of an In-Ga-Zn oxide, a Ga-Zn oxide, or a gallium oxide.

[0156] In this case, the oxide 530b serves as the main carrier path. By configuring the oxide 530a and the oxide 530c as described above, the defect state density at the interface between the oxide 530a and the oxide 530b and at the interface between the oxide 530b and the oxide 530c can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-state current.

[0157] Conductors 542a and 542b, which function as a source electrode and a drain electrode, are provided on oxide 530b. Conductors 542a and 542b are preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing any of the above metal elements or an alloy combining any of the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel is preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Furthermore, metal nitride films such as tantalum nitride are preferred because they have barrier properties against hydrogen or oxygen.

[0158] 11A and 11B, the conductor 542a and the conductor 542b are shown as single-layer structures, but they may also have a stacked structure of two or more layers. For example, a tantalum nitride film and a tungsten film may be stacked. Alternatively, a titanium film and an aluminum film may be stacked. Alternatively, a two-layer structure in which an aluminum film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, or a two-layer structure in which a copper film is stacked on a tungsten film may be used.

[0159] Further, there are three-layer structures in which a titanium film or titanium nitride film is laminated on the titanium film or titanium nitride film, an aluminum film or copper film is laminated on the titanium film or titanium nitride film, and a titanium film or titanium nitride film is further formed thereon, a three-layer structure in which a molybdenum film or molybdenum nitride film is laminated on the molybdenum film or molybdenum nitride film, an aluminum film or copper film is laminated on the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further formed thereon, etc. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used.

[0160] Furthermore, when the conductors 542a and 542b are not oxides and a metal oxide is used for the oxide 530, contact between the conductors 542a and 542b and the oxide 530 may cause oxygen in the oxide 530 to diffuse into the conductors 542a and 542b, resulting in the oxidation of the conductors 542a and 542b. The oxidation of the conductors 542a and 542b is likely to result in a decrease in the conductivity of the conductors 542a and 542b. The diffusion of oxygen in the oxide 530 to the conductors 542a and 542b can be rephrased as the conductors 542a and 542b absorbing the oxygen in the oxide 530.

[0161] 11A, regions 543a and 543b may be formed as low-resistance regions at and near the interface of the oxide 530 with the conductor 542a (conductor 542b). In this case, the region 543a functions as one of the source region and the drain region, and the region 543b functions as the other of the source region and the drain region. A channel formation region is formed in the region sandwiched between the regions 543a and 543b.

[0162] By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, the oxygen concentration in the region 543a (region 543b) may be reduced. Also, a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and components of the oxide 530 may be formed in the region 543a (region 543b). In such a case, the carrier concentration in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.

[0163] The insulator 544 is provided to cover the conductors 542a and 542b and suppresses oxidation of the conductors 542a and 542b. In this case, the insulator 544 may be provided to cover the side surface of the oxide 530 and to be in contact with the insulator 524.

[0164] The insulator 544 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. Alternatively, the insulator 544 can be silicon nitride oxide, silicon nitride, or the like.

[0165] In particular, it is preferable to use, as the insulator 544, an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Hafnium aluminate is particularly preferable because it has higher heat resistance than a hafnium oxide film. Therefore, it is less likely to crystallize during heat treatment in a later step. Note that if the conductors 542a and 542b are made of an oxidation-resistant material or a material whose conductivity does not decrease significantly even when it absorbs oxygen, the insulator 544 is not an essential component. The insulator may be designed appropriately depending on the desired transistor characteristics.

[0166] The insulator 544 can prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing to the oxide 530b through the oxide 530c and the insulator 550. The insulator 580 can also prevent the conductor 542 from being oxidized by excess oxygen.

[0167] The insulator 550 functions as a first gate insulating film. Like the insulator 524, the insulator 550 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating.

[0168] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having vacancies can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0169] The insulator 550, which releases oxygen upon heating, can effectively supply oxygen to the channel formation region of the oxide 530b. Similar to the insulator 524, the concentration of impurities such as water or hydrogen in the insulator 550 is preferably reduced. The thickness of the insulator 550 is preferably 1 nm to 20 nm.

[0170] Furthermore, a metal oxide may be provided between the insulator 550 and the conductor 560 to efficiently supply excess oxygen contained in the insulator 550 to the oxide 530. The metal oxide preferably suppresses oxygen diffusion from the insulator 550 to the conductor 560. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. In other words, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 may be used.

[0171] The insulator 550 may have a layered structure. As transistors become smaller and more highly integrated, thinner gate insulating films can cause problems such as leakage current. Therefore, by using a layered structure of a high-k material and a thermally stable material for the insulator that functions as the gate insulating film, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Furthermore, a thermally stable layered structure with a high dielectric constant can be achieved.

[0172] The conductor 560 functioning as the gate electrode or first gate electrode is shown as having a two-layer structure in FIGS. 11A and 11B, but may have a single-layer structure or a stacked structure of three or more layers.

[0173] The conductor 560a is preferably made of a conductive material that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., NO, NO, and the like), and copper atoms. Alternatively, a conductive material that suppresses the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like) is preferably used. The conductor 560a has the function of suppressing the diffusion of oxygen, which can suppress the oxidation of the conductor 560b due to the oxygen contained in the insulator 550, thereby preventing a decrease in conductivity. Examples of conductive materials that suppress the diffusion of oxygen include tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Alternatively, the conductor 560a can be made of an oxide semiconductor that can be used for the oxide 530. In this case, the conductor 560b can be formed by sputtering to reduce the electrical resistance of the conductor 560a, thereby making it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0174] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Since the conductor 560b also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a layered structure, such as a layered structure of titanium or titanium nitride and the above conductive material.

[0175] The insulator 580 is provided over the conductor 542a and the conductor 542b with the insulator 544 interposed therebetween. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, or a resin. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Silicon oxide and silicon oxide having voids are particularly preferred because they allow for easy formation of excess oxygen regions in a later step.

[0176] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580 from which oxygen is released by heating, oxygen in the insulator 580 can be efficiently supplied to the oxide 530. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.

[0177] The opening of the insulator 580 is formed to overlap the region between the conductor 542a and the conductor 542b, so that the conductor 560 is formed to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.

[0178] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is also necessary to prevent the conductivity of the conductor 560 from decreasing. If the film thickness of the conductor 560 is increased to achieve this, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided so as to be embedded in the opening of the insulator 580. Therefore, even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 can be formed without collapsing during the process.

[0179] The insulator 574 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 550. By forming the insulator 574 by a sputtering method, excess oxygen regions can be provided in the insulator 550 and the insulator 580. This allows oxygen to be supplied from the excess oxygen regions into the oxide 530.

[0180] For example, the insulator 574 can be a metal oxide containing one or more of hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium.

[0181] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even when it is a thin film with a thickness of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can function as both an oxygen source and a barrier film against impurities such as hydrogen.

[0182] An insulator 581 functioning as an interlayer film is preferably provided over the insulator 574. Like the insulator 524, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen.

[0183] The conductor 540a and the conductor 540b are placed in openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544. The conductor 540a and the conductor 540b are provided opposite to each other with the conductor 560 interposed therebetween.

[0184] According to one embodiment of the present invention, a novel transistor can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable transistor having a large S value can be provided. Alternatively, according to one embodiment of the present invention, a transistor whose S value can be changed after fabrication of a semiconductor device can be provided.

[0185] Furthermore, one aspect of the present invention makes it possible to selectively fabricate a transistor with or without a conductive layer and / or a ferroelectric layer on the back channel side, thereby providing a semiconductor device having, in a single circuit, a transistor whose S value can be changed after the semiconductor device is formed and a transistor with good characteristics.

[0186] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0187] (Fourth embodiment) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0188] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0189] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 12A. Fig. 12A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0190] As shown in FIG. 12A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and polycrystal). "Crystalline" excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0191] The structure within the bold frame shown in Figure 12A is an intermediate state between "amorphous" and "crystal" and belongs to a new boundary region (new crystalline phase). In other words, this structure can be said to be completely different from the energetically unstable "amorphous" and "crystal."

[0192] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 12B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline" (the vertical axis represents intensity in arbitrary units (au)). The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 12B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 12B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 12B is 500 nm.

[0193] As shown in Figure 12B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 12B, the peak near 2θ = 31° is asymmetrical with respect to the angle at which the peak intensity is detected.

[0194] The crystalline structure of a film or substrate can be evaluated by the diffraction pattern (also called the nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Figure 12C. Figure 12C shows a diffraction pattern observed by NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 12C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed using a probe diameter of 1 nm.

[0195] As shown in FIG. 12C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0196] <<Structure of oxide semiconductor>> Note that oxide semiconductors may be classified differently from those shown in FIG. 12A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0197] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0198] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0199] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0200] In addition, in an In-M-Zn oxide (wherein the element Ma is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing the element Ma, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element Ma are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain the element Ma. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0201] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0202] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0203] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. The distortion may also have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0204] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0205] CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities or the formation of defects, the CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0206] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of the microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0207] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0208] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0209] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0210] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0211] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0212] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0213] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0214] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0215] Note that the CAC-OS does not include a stacked structure of two or more films with different compositions. Furthermore, the first and second regions do not refer to regions that are extracted from a layered crystal structure. In other words, if the first and second regions contain crystals, the crystals are different crystals.

[0216] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act complementarily, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0217] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0218] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0219] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0220] For the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 Less than 1×10, more preferably 11 cm -3 or less, more preferably 1 × 10 10 cm -3 Less than 1 x 10 -9 cm -3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0221] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0222] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0223] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0224] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0225] When an oxide semiconductor contains silicon and / or carbon, which are elements of Group 14, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon and / or carbon in the oxide semiconductor and the concentration of silicon and / or carbon near the interface with the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) are calculated to be 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0226] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0227] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0228] In particular, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, which may cause oxygen vacancies in the oxide semiconductor. When hydrogen enters an oxygen vacancy in the oxide 530, the oxygen vacancy and hydrogen bond to form V. O May form H. V O H functions as a donor and may generate electrons as carriers. In addition, some of the hydrogen may bond with oxygen that is bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily moved by stress such as heat or an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be deteriorated. In one embodiment of the present invention, V in the oxide 530 O It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic V. O To obtain an oxide semiconductor with a sufficiently reduced amount of H, it is important to remove impurities such as moisture and hydrogen from the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the oxide semiconductor to fill oxygen vacancies (sometimes referred to as oxygen addition treatment).O When an oxide semiconductor in which impurities such as H are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0229] A defect in which hydrogen is introduced into an oxygen vacancy can function as a donor in an oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, oxide semiconductors are sometimes evaluated using carrier concentration instead of donor concentration. Therefore, in this specification and the like, a carrier concentration assuming a state in which no electric field is applied may be used as a parameter of an oxide semiconductor instead of donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as "donor concentration."

[0230] Therefore, when an oxide semiconductor is used for the oxide 530, it is preferable that the amount of hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by secondary ion mass spectrometry (SIMS) is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 When an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0231] When an oxide semiconductor is used for the oxide 530, the oxide semiconductor has a wide band gap and is intrinsic (also referred to as I-type) or substantially intrinsic, and the carrier concentration of the oxide semiconductor in the channel formation region is 1×10 18 cm -3 Preferably, it is less than 1 x 10 17 cm -3More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the oxide semiconductor in the channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0232] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0233] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0234] (Embodiment 5) The semiconductor device according to one embodiment of the present invention can be used for a processor such as a CPU or a GPU, or a chip. By using the semiconductor device described in the above embodiment for a processor such as a CPU or a GPU, or a chip, the processor or chip can be miniaturized and power consumption can be further reduced. Specific examples of electronic devices including a processor such as a CPU or a GPU, or a chip according to one embodiment of the present invention are shown in Figures 13A to 13H.

[0235] <Electronic devices and systems> A chip such as a CPU or GPU according to one embodiment of the present invention can be mounted in various electronic devices. Examples of such electronic devices include electronic devices with relatively large screens, such as television devices, monitors for desktop or notebook information terminals, digital signage (electronic billboards), and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, electronic book readers, mobile phones, portable game machines, personal digital assistants, and audio playback devices. Furthermore, by providing an electronic device with a GPU or chip according to one embodiment of the present invention, it is possible to equip the electronic device with artificial intelligence.

[0236] The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0237] An electronic device according to one embodiment of the present invention may have a sensor (including a function for measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0238] An electronic device of one embodiment of the present invention can have various functions. For example, it can have a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading programs or data recorded on a recording medium, etc. Examples of electronic devices are shown in FIGS. 13A to 13H.

[0239] [Information terminal] 13A shows a mobile phone (smartphone), which is one type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102. As input interfaces, a touch panel is provided on the display unit 5102 and buttons are provided on the housing 5101.

[0240] By applying the chip of one embodiment of the present invention, the information terminal 5100 can execute applications using artificial intelligence. Examples of applications using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display portion 5102, an application that recognizes characters, figures, or the like input by a user to a touch panel provided in the display portion 5102 and displays the characters, figures, or the like on the display portion 5102, and an application that performs biometric authentication such as fingerprints or voiceprints.

[0241] 13B illustrates a notebook information terminal 5200. The notebook information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203.

[0242] The notebook information terminal 5200 can execute applications using artificial intelligence by applying a chip of one embodiment of the present invention, similar to the information terminal 5100 described above. Examples of applications using artificial intelligence include design support software, text correction software, and automatic menu generation software. Furthermore, new artificial intelligence can be developed by using the notebook information terminal 5200.

[0243] 13A and 13B, a smartphone and a notebook type information terminal are used as examples of electronic devices, but information terminals other than smartphones and notebook type information terminals can also be used. Examples of information terminals other than smartphones and notebook type information terminals include PDAs (Personal Digital Assistants), desktop type information terminals, and workstations.

[0244] [Game consoles] FIG. 13C illustrates a portable game console 5300, which is an example of a game console. The portable game console 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, operation keys 5306, and the like. The housing 5302 and the housing 5303 can be detached from the housing 5301. By attaching the connection unit 5305 of the housing 5301 to another housing (not shown), the video displayed on the display unit 5304 can be output to another video device (not shown). In this case, the housing 5302 and the housing 5303 can each function as an operation unit. This allows multiple players to play a game simultaneously. The chips described in the above embodiments can be incorporated into the substrates of the housings 5301, 5302, and 5303.

[0245] 13D shows an example of a game machine, a stationary game machine 5400. A controller 5402 is connected to the stationary game machine 5400 wirelessly or via a wire.

[0246] A game machine with low power consumption can be realized by applying a chip such as a CPU or a GPU according to one embodiment of the present invention to a game machine such as a portable game machine 5300 or a stationary game machine 5400. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0247] Furthermore, by applying a chip such as a CPU or a GPU according to one embodiment of the present invention to the portable game console 5300, the portable game console 5300 can have artificial intelligence.

[0248] Originally, the expression of the progress of a game, the behavior of creatures appearing in the game, and phenomena occurring in the game are determined by the program of the game, but by applying artificial intelligence to the portable game console 5300, it becomes possible to express things that are not limited to the game program. For example, it becomes possible to express things such as changes in the questions asked by the player, the progress of the game, the time, and the behavior of people appearing in the game.

[0249] Furthermore, when playing a game requiring multiple players on the portable game console 5300, the game players can be personified using artificial intelligence, so that the game can be played by one person by making the opponent an artificial intelligence game player.

[0250] 13C and 13D illustrate a portable game machine and a stationary game machine as examples of game machines, but game machines to which the chips such as a CPU and a GPU of one embodiment of the present invention are applied are not limited to these. Examples of game machines to which the chips such as a CPU and a GPU of one embodiment of the present invention are applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0251] [Mainframe Computer] A chip such as a CPU or GPU according to one embodiment of the present invention can be applied to a mainframe computer.

[0252] 13E is a diagram showing a supercomputer 5500, which is an example of a mainframe computer. FIG. 13F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.

[0253] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. The plurality of computers 5502 are stored in the rack 5501. The computer 5502 is provided with a plurality of boards 5504, and the GPU or chip described in the above embodiment can be mounted on the boards.

[0254] The supercomputer 5500 is a large-scale computer mainly used for scientific and technical calculations. Scientific and technical calculations require high-speed processing of enormous amounts of calculations, resulting in high power consumption and large amounts of heat generated by the chip. By applying a chip such as a CPU or GPU according to one embodiment of the present invention to the supercomputer 5500, a supercomputer with low power consumption can be realized. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the impact of heat generation on the circuit itself, peripheral circuits, and modules.

[0255] 13E and 13F illustrate a supercomputer as an example of a mainframe computer, but the mainframe computer to which the CPU, GPU, etc. chips of one embodiment of the present invention are applied is not limited to this. Examples of mainframe computers to which the CPU, GPU, etc. chips of one embodiment of the present invention are applied include computers (servers) that provide services and large general-purpose computers (mainframes).

[0256] [Moving object] A chip such as a CPU or GPU according to one embodiment of the present invention can be applied to automobiles, which are moving objects, and to the area around the driver's seat of an automobile.

[0257] Fig. 13G is a diagram showing the area around the windshield inside the interior of an automobile, which is an example of a moving body, showing display panel 5701, display panel 5702, and display panel 5703 attached to the dashboard, as well as display panel 5704 attached to a pillar.

[0258] The display panels 5701 to 5703 can provide various information by displaying a speedometer, tachometer, mileage, fuel gauge, gear status, air conditioning settings, etc. The display items and layout displayed on the display panels can be changed as appropriate to suit the user's preferences, allowing for improved design. The display panels 5701 to 5703 can also be used as lighting devices.

[0259] The display panel 5704 can complement the view (blind spot) blocked by the pillar by displaying an image from an imaging device (not shown) installed in the vehicle. That is, by displaying an image from an imaging device installed outside the vehicle, blind spots can be complemented and safety can be improved. Furthermore, by displaying an image that complements the invisible part, safety can be confirmed more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

[0260] A chip such as a CPU or a GPU according to one embodiment of the present invention can be used as a component of artificial intelligence, and therefore can be used, for example, in an automatic driving system for automobiles. Furthermore, the chip can be used in a system that provides road guidance, hazard prediction, etc. The display panels 5701 to 5704 may be configured to display information such as road guidance and hazard prediction.

[0261] Although an automobile is described above as an example of a moving body, the moving body is not limited to an automobile. For example, moving bodies can include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets), and the chip of one embodiment of the present invention can be applied to these moving bodies to provide a system using artificial intelligence.

[0262] [electric appliances] 13H shows an example of an electric appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0263] The electric refrigerator-freezer 5800 having artificial intelligence can be realized by applying the chip of one embodiment of the present invention to the electric refrigerator-freezer 5800. By using artificial intelligence, the electric refrigerator-freezer 5800 can have a function of automatically generating a menu based on ingredients stored in the electric refrigerator-freezer 5800 and their expiration dates, a function of automatically adjusting the temperature to match the ingredients stored in the electric refrigerator-freezer 5800, and the like.

[0264] Although electric refrigerator-freezers have been described as an example of electrical appliances, other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0265] The electronic devices, functions of the electronic devices, application examples of artificial intelligence, and effects thereof described in this embodiment can be appropriately combined with descriptions of other electronic devices.

[0266] At least part of the structures, methods, and the like described in this embodiment mode can be implemented in appropriate combination with other embodiment modes and examples described in this specification. [Example]

[0267] In this example, a simulation performed on the transistor 100 shown in FIG. 1 and the results thereof will be described.

[0268] In this simulation, we confirmed how the transistor characteristics (S value) change depending on whether or not there is remnant polarization (spontaneous polarization) in the ferroelectric layer on the back channel side of the transistor 100. Specifically, in the transistor of FIG. 1, a fixed charge equivalent to the remnant polarization was placed in the ferroelectric layer, and device simulation was performed. Note that parameters such as the film thickness and relative dielectric constant of each layer are omitted. The results of the device simulation are shown in FIGS. 14A to 14C. FIG. 14A shows the Id-Vg curve, and FIG. 14B shows the Id-Vg curve when Id is 1×10 -15 A to 1 x 10 -12 FIG. 14C is an enlarged view of the region up to A, and shows the S value calculated at each Id, with the horizontal axis representing the range of Id.

[0269] As shown in Figure 14B, by providing a fixed charge (corresponding to the presence of remanent polarization), the rise of Id in the subthreshold region is shifted to the negative side compared to when no fixed electric field is provided (corresponding to the absence of remanent polarization). Also, as shown in Figure 14C, it can be confirmed that the S value is larger. [Explanation of symbols]

[0270] 100: transistor, 103: conductive layer, 120: ferroelectric layer, 122: layer of material that may have ferroelectricity, 124: insulating layer, 130: semiconductor layer, 142a: conductive layer, 142b: conductive layer, 160: gate electrode, 500: transistor, 503: conductor, 503a: conductor, 503b: conductor, 512: insulator, 514: insulator, 516: insulator, 520: ferroelectric layer, 522: layer of material that may have ferroelectricity Layer of material, 524: insulator, 530: oxide, 530a: oxide, 530b: oxide, 530c: oxide, 540a: conductor, 540b: conductor, 542: conductor, 542a: conductor, 542b: conductor, 543a: region, 543b: region, 544: insulator, 550: insulator, 560: conductor, 560a: conductor, 560b: conductor, 574: insulator, 580: insulator, 581: insulator

Claims

1. a first transistor including: a first oxide semiconductor layer having a channel formation region; and a first conductive layer having a region overlapping with the first oxide semiconductor layer with a ferroelectric layer interposed therebetween; a second transistor including a second oxide semiconductor layer having a channel formation region and the ferroelectric layer, The semiconductor device wherein the second transistor does not have a conductive layer in contact with the ferroelectric layer in a region overlapping the second oxide semiconductor layer with the ferroelectric layer interposed therebetween.

2. In claim 1, The semiconductor device further comprises: a first conductive layer and a first oxide semiconductor layer; a first insulating layer and a second insulating layer; a second insulating layer and a second insulating layer;

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