Direct bonding method and structure

Abstract

Disclosed herein is a method for direct bonding. In some embodiments, the direct bonding method includes preparing a first bonding surface of a first element for direct bonding to a second bonding surface of a second element, and providing a protective layer having a thickness of less than 3 microns over the prepared first bonding surface of the first element after the preparing step.

Description

[Technical field]

[0001] [Incorporation by reference to any priority application] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 168,988, filed March 31, 2021, entitled "Direct Bonding Methods and Structures," which is hereby incorporated by reference in its entirety.

[0002] The field of the invention relates to Direct Bonding Methods and Structures. [Background technology]

[0003] Semiconductor elements, such as semiconductor wafers or integrated devices, can be stacked and directly bonded to each other without adhesives. For example, in some hybrid direct bond structures, non-conductive field regions of the elements can be directly bonded to each other, and corresponding conductive contact structures can also be directly bonded to each other. In some applications, it can be difficult to protect the contact pads before bonding. Thus, there remains a need for improved contact structures for direct bonding. Summary of the Invention [Means for solving the problem]

[0004] In one embodiment, a bonding method can include preparing a first bonding surface of a first element for direct bonding to a second bonding surface of a second element, and after the preparing step, providing a protective layer having a thickness of less than 3 microns over the prepared first bonding surface of the first element.

[0005] In some embodiments, preparing the first bonding surface comprises activating the first bonding surface. In some embodiments, activating the first bonding surface comprises plasma activating the first bonding surface. In some embodiments, plasma activating the first bonding surface comprises exposing the first bonding surface to a nitrogen-containing plasma. In some embodiments, the protective layer has a thickness less than 2 microns. In some embodiments, the protective layer has a thickness less than 0.25 microns. In some embodiments, the protective layer has a thickness in the range of 0.05 microns to 2 microns. In some embodiments, the protective layer has a thickness in the range of 0.1 microns to 0.25 microns. In some embodiments, the protective layer comprises an organic layer. In some embodiments, the protective layer comprises a hydrophobic coating and / or a hydrophilic coating. In some embodiments, the protective layer comprises a photoresist. In some embodiments, providing the protective layer comprises blanket depositing the protective layer over the first bonding surface. In some embodiments, the bonding method comprises removing the blanket deposited protective layer using a reactive ion etching (RIE) process. In some embodiments, the bonding method includes cleaning particles from the first element prior to the removing step. In some embodiments, the bonding method includes selectively providing a passivation layer over the plurality of contact pads prior to the providing protective layer step, the providing protective layer step including providing a protective layer over the passivation layer. In some embodiments, the providing protective layer step includes selectively providing a protective layer over the conductive contact pads of the first bonding surface. In some embodiments, the first bonding surface includes a plurality of contact pads, the contact pads protruding above a first non-conductive region of the first bonding surface, and the providing protective layer step includes providing a protective layer over at least the protruding contact pads. In some embodiments, the providing protective layer step includes blanket depositing the protective layer over the first bonding surface. In some embodiments, the bonding method includes planarizing the first element such that the plurality of contact pads are flush with or recessed below the first non-conductive region.In some embodiments, the first bonding surface includes a first plurality of conductive contact pads and a first non-conductive bonding region, the first plurality of conductive contact pads being recessed below the first non-conductive bonding region. In some embodiments, the first plurality of conductive contact pads are recessed below the first non-conductive bonding region by 10 nm or less. In some embodiments, the variation in recess depth of the first plurality of contact pads across the first element is less than 25%. In some embodiments, the variation in recess depth of the first plurality of contact pads across the first element is less than 10%. In some embodiments, the variation in recess depth of the first plurality of contact pads across the first element is less than 5%. In some embodiments, the bonding method includes removing the protective layer. In some embodiments, the first element comprises a wafer, and the method further includes singulating the wafer to form a plurality of singulated elements prior to removing the protective layer. In some embodiments, the bonding method includes directly bonding a first bonding surface of the first element to a second bonding surface of the second element without an intervening adhesive after removing the protective layer. In some embodiments, the first bonding surface includes a first plurality of conductive contact pads and a first non-conductive bonding area, and the second bonding surface includes a second plurality of conductive contact pads and a second non-conductive bonding area, and the directly bonding includes a hybrid direct bonding step including directly bonding the first and second plurality of conductive contact pads to each other without an adhesive and directly bonding the first and second non-conductive bonding areas to each other without an adhesive. In some embodiments, the first non-conductive bonding area includes a silicon-containing dielectric layer. In some embodiments, the bonding method includes activating the second bonding surface prior to the directly bonding step. In some embodiments, the steps of preparing the first bonding surface and providing the protective layer are performed at a first facility and the directly bonding is performed at a second facility that is located differently from the first facility. In some embodiments, the direct bonding step is performed more than 24 hours after the activating the first bonding layer step.

[0006] In another embodiment, a bonding method includes preparing a first bonding surface of a first element for direct bonding to a second bonding surface of a second element, selectively providing a passivation layer over a plurality of contact pads of the first bonding surface after the preparing step, and providing a protective layer over the passivation layer after the providing the passivation layer step.

[0007] In some embodiments, providing the protective layer comprises blanket depositing the protective layer over the first bonding surface. In some embodiments, the protective layer has a thickness less than 3 microns. In some embodiments, the protective layer has a thickness less than 2 microns. In some embodiments, the protective layer has a thickness less than 0.25 microns. In some embodiments, the protective layer has a thickness in the range of 0.05 microns to 2 microns. In some embodiments, the protective layer has a thickness in the range of 0.1 microns to 0.25 microns. In some embodiments, the protective layer comprises an organic layer. In some embodiments, the protective layer comprises a hydrophobic coating and / or a hydrophilic coating. In some embodiments, the method comprises removing the protective layer. In some embodiments, the first element comprises a wafer, and the method further comprises singulating the wafer to form a plurality of singulated elements prior to removing the protective layer. In some embodiments, the method comprises directly bonding the first bonding surface of the first element to the second bonding surface of the second element without an intervening adhesive after removing the protective layer. In some embodiments, the first plurality of conductive contact pads are recessed below the first non-conductive bonding region of the first bonding surface. In some embodiments, the first plurality of conductive contact pads are recessed below the first non-conductive bonding region by 10 nm or less. In some embodiments, the variation in recess depth of the first plurality of contact pads is less than 25%. In some embodiments, the variation in recess depth of the first plurality of contact pads is less than 10%, e.g., less than 5%.

[0008] In another embodiment, the bonding method can include preparing a first bonding surface of a first element for direct bonding to a second bonding surface of a second element, and after the preparing step, selectively providing a passivation layer over a plurality of contact pads of the first bonding surface.

[0009] In some embodiments, the first bonding surface further comprises a first non-conductive material, and the protective layer is not provided over the entirety of the first non-conductive material. In some embodiments, the protective layer has a thickness less than 3 microns. In some embodiments, the protective layer is less than 2 microns. In some embodiments, the protective layer is less than 0.25 microns. In some embodiments, the protective layer is in a range of 0.05 microns to 2 microns. In some embodiments, the protective layer is in a range of 0.1 microns to 0.25 microns. In some embodiments, the protective layer comprises an organic layer. In some embodiments, the protective layer comprises a hydrophobic coating and / or a hydrophilic coating. In some embodiments, the method can include providing a passivation layer comprising oxidizing a surface of the contact pad. In some embodiments, the method can include removing the protective layer. In some embodiments, the first element comprises a wafer, and the method can further include singulating the wafer to form a plurality of singulated elements prior to removing the protective layer. In some embodiments, the method can include, after removing the protective layer, directly bonding the first bonding surface of the first element to the second bonding surface of the second element without an intervening adhesive.

[0010] In another embodiment, a bonding method can include preparing a first bonding surface of a first element for direct bonding to a second bonding surface of a second element, the first bonding surface including a first non-conductive region and a first plurality of contact pads projecting above the first non-conductive region, and providing a protective layer over at least the first plurality of contact pads after the preparing step.

[0011] In some embodiments, providing a protective layer includes blanket depositing the protective layer over the first bonding surface. In some embodiments, the method can include planarizing the first element such that the first plurality of contact pads are recessed below the first non-conductive region. In some embodiments, the method can include removing the protective material.

[0012] In another embodiment, the bonding method can include preparing a first bonding surface of a first element for direct bonding to a second bonding surface of a second element, and after the preparing step, selectively providing a passivation layer over a plurality of contact pads of the first bonding surface.

[0013] In some embodiments, providing a passivation layer comprises oxidizing a surface of the contact pads. In some embodiments, the method may include singulating the first device with the passivation layer over the contact pads, the passivation layer being exposed at a top surface of the device during the singulation.

[0014] In some embodiments, the semiconductor device comprises a device region, a bonding layer over the device region, the bonding layer having a bonding surface prepared for direct hybrid bonding to a second device, and a protective layer over at least a portion of the prepared first bonding surface, the protective layer having a thickness less than 3 microns. In some embodiments, the protective layer comprises a photoresist. In some embodiments, the semiconductor device is in wafer form. In some embodiments, the protective layer has a thickness in the range of 0.05 microns to 2 microns. In some embodiments, the bonding layer comprises a plurality of conductive contact pads and a non-conductive bonding region. In some embodiments, the semiconductor device further comprises a passivation layer over the plurality of conductive contact pads between the plurality of contact pads and the protective layer. In some embodiments, the protective layer is selectively disposed over the plurality of conductive contact pads. In some embodiments, the plurality of conductive contact pads protrude above the bonding layer. In some embodiments, the plurality of conductive contact pads are recessed below an upper surface of the bonding layer. In some embodiments, the protective layer is blanket deposited over the bonding surface.

[0015] In some embodiments, a semiconductor device comprises a device region and a bonding layer over the device region, the bonding layer having a bonding surface prepared for direct hybrid bonding to a second device and including a plurality of conductive contact pads and a non-conductive bonding region, each of the plurality of conductive contact pads having a recessed depth such that the conductive contact pad is recessed below the bonding surface, the recessed depth of the plurality of contact pads varying by less than 25%. In some embodiments, the recessed depth of the plurality of conductive contact pads varying by less than 105%. In some embodiments, the recessed depth of the plurality of conductive contact pads varying by 0.5% to 10% or 0.1% to 5%.

[0016] In some embodiments, a semiconductor device comprises a device region, a bonding layer over the device region, the bonding layer having a bonding surface prepared for direct hybrid bonding, and a conductive layer exposed at a portion of the prepared bonding surface, the conductive layer having a dishing variation of less than 5 nm in the bonding surface of the device. In some embodiments, the dishing variation is less than 3 nm in the bonding surface of the device. In some embodiments, the dishing variation is less than 2 nm in the bonding surface of the device. In some embodiments, the dishing variation is less than 1 nm in the bonding surface of the device. In some embodiments, the dishing variation is between 0.5 nm and 5 nm in the bonding surface of the device. In some embodiments, the conductive layer comprises a plurality of conductive contact pads, each of the plurality of conductive contact pads having a dishing depth such that they are dished below the bonding surface. In some embodiments, the bonding layer comprises a non-conductive layer at least partially embedded with a conductive layer. In some embodiments, the non-conductive layer is polished.

[0017] These and other features, aspects, and advantages of the present disclosure will be described in connection with drawings of certain embodiments, which are intended to be illustrative of the present disclosure and not limiting. It will be understood that the accompanying drawings, which are incorporated in and constitute a part of this specification, are intended to illustrate the concepts disclosed herein and may not be to scale. [Brief description of the drawings]

[0018] [Figure 1a] 1A-1D are schematic diagrams illustrating a direct bonding process according to some embodiments. [Figure 1b] 1A-1D are schematic diagrams illustrating a direct bonding process according to some embodiments. [Diagram 2] FIG. 1 is a plot of maximum recession distance from the joining surface versus temperature for different thicknesses of thermally expandable metal contacts. [Diagram 3] 1A-1D illustrate an exemplary process for protecting a surface of a semiconductor device during processing in accordance with some embodiments. [Figure 4]1A-1D illustrate an exemplary process for protecting a surface of a semiconductor device during processing in accordance with some embodiments. [Diagram 5] 1A-1D illustrate an exemplary process for protecting a surface of a semiconductor device during processing in accordance with some embodiments. [Figure 6] 1A-1D illustrate an exemplary process for protecting a surface of a semiconductor device during processing in accordance with some embodiments. [Figure 7] 1A-1D illustrate an exemplary process for protecting a surface of a semiconductor device during processing in accordance with some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Various embodiments disclosed herein relate to a direct bond structure in which two elements can be directly bonded to each other without the use of adhesive. FIGS. 1a and 1b are schematic diagrams illustrating a process of forming a direct bond structure without the use of adhesive according to some embodiments. In FIGS. 1a and 1b, a direct bond structure 100 comprises two elements 102 and 104 that can be directly bonded to each other without the use of adhesive. Two or more semiconductor elements (e.g., integrated device dies, wafers, etc.) 102 and 104 can be stacked or bonded to each other to form the bond structure 100. The conductive contact pads 106a of the first element can be electrically connected to the corresponding conductive contact pads of the second element 104. Any suitable number of elements can be stacked in the bond structure 100. For example, a third element (not shown) can be stacked on top of the second element 104, a fourth element (not shown) can be stacked on top of the third element, and so on. Additionally or alternatively, one or more additional elements (not shown) may be stacked laterally adjacent to one another along the first element 102. In some embodiments, the laterally stacked additional elements may be smaller than the second element. In some embodiments, the laterally stacked additional elements may be twice as small as the second element.

[0020] In some embodiments, the elements 102 and 104 are directly bonded to each other without adhesive. In various embodiments, a non-conductive or dielectric material can serve as the first bonding layer 108a of the first element 102, which can be directly bonded without adhesive to a corresponding non-conductive or dielectric material field region that serves as the second bonding layer 108b of the second element 104. The non-conductive bonding layers 108a and 108b can be disposed on the front sides 114a and 114b of each of the device portions 110a and 110b, such as the semiconductor (e.g., silicon) portions of the elements 2, 3. Active devices and / or circuits can be patterned and / or otherwise disposed in or on the device portions 110a and 110b. Active devices and / or circuits may be disposed on or near the front sides 114a and 114b of the device portions 110a and 110b and / or on or near the opposing back sides 116a and 116b of the device portions 110a and 110b. The non-conductive material may be referred to as a non-conductive bonding region or bonding layer 108a of the first element 102. In some embodiments, the non-conductive bonding layer 108a of the first element 102 may be directly bonded to a corresponding non-conductive bonding layer 108b of the second element 104 using a dielectric-to-dielectric bonding technique. For example, the non-conductive bond or dielectric-to-dielectric bond may be formed without adhesives using direct bonding techniques as disclosed in at least U.S. Pat. Nos. 9,564,414, 9,391,143, and 10,434,749, the entire contents of each of which are incorporated herein by reference in their entirety for all purposes. It should be appreciated that in various embodiments, bonding layers 108a and / or 108b may comprise a non-conductive material, such as a dielectric material, such as silicon oxide, or an undoped semiconductor material, such as undoped silicon.

[0021] In various embodiments, a direct hybrid bond can be formed without the aid of an adhesive. For example, the dielectric bonding surfaces can be polished to a high smoothness. The bonding surfaces 112a and 112b can be cleaned and exposed to a plasma and / or an etchant to activate the bonding surfaces 112a and 112b. In some embodiments, the bonding surfaces 112a and 112b can be terminated with a chemical species after or during activation (e.g., during a plasma and / or etch process). Without being limited by theory, in some embodiments, an activation process can be performed to break the chemical bond of the bonding surfaces 112a and 112b, and a termination process can provide the bonding surfaces 112a and 112b with additional chemical species that improve the bonding energy during direct bonding. In some embodiments, activation and termination treatments are provided in the same step, e.g., with a plasma that activates and terminates the bonding surfaces 112a and 112b. In other embodiments, the bonding surfaces 112a and 112b can be terminated in a separate process to provide additional chemical species for direct bonding. In various embodiments, the termination chemical species can include nitrogen. Further, in some embodiments, the bonding surfaces 112a and 112b can be exposed to fluorine. For example, there may be one or more fluorine peaks near the layers and / or bonding interface 118. Thus, in the direct bond structure 100, the bonding interface 118 between the two non-conductive materials (e.g., bonding layers 108a and 108b) can include a very smooth interface with a higher nitrogen content and / or fluorine peak at the bonding interface 118. Additional examples of activation and / or termination treatments can be found throughout U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, the entire contents of each of which are incorporated herein by reference in their entirety for all purposes.

[0022] In various embodiments, the conductive contact pads 106a of the first element 102 can be directly bonded to the corresponding conductive contact pads 106b of the second element 104. For example, hybrid bonding techniques can be used to provide a conductor-to-conductor direct bond along a bonding interface 118 that includes a covalently directly bonded non-conductor-to-non-conductor (e.g., dielectric-to-dielectric) surface prepared as described above. In various embodiments, the conductor-to-conductor (e.g., contact pad 106a-contact pad 106b) direct bond and the hybrid dielectric-to-dielectric bond can be formed using at least the direct bonding techniques disclosed in U.S. Patent Nos. 9,716,033 and 9,852,988, the entire contents of each of which are incorporated herein by reference in their entirety for all purposes.

[0023] For example, non-conductive (e.g., dielectric) bonding surfaces 112a, 112b can be prepared and directly bonded to each other without an adhesive as described above. The conductive contact pads 106a and 106b (which may be surrounded by a non-conductive dielectric field region) can also be directly bonded to each other without an adhesive. In some embodiments, the respective contact pads 106a and 106b can be recessed below the outer (e.g., upper) surfaces 112a and 112b of the dielectric field or non-conductive bonding layers 108a and 108b by, for example, less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, in the range of 2 nm to 20 nm, or in the range of 4 nm to 10 nm. In various embodiments, prior to the direct bonding step, the recesses of the opposing elements can be sized such that the total gap between the opposing contact pads is less than 15 nm, or less than 10 nm. The non-conductive bonding layers 108a and 108b may be directly bonded to each other without adhesive at room temperature in some embodiments, after which the bonded structure 100 may be annealed. Upon annealing, the contact pads 106a and 106b may expand to contact each other and form a direct metal-metal bond. Advantageously, direct bond interconnect, or DBI®, a technology available from Xperi, Inc. of San Jose, Calif., may allow for high density pads (e.g., small or fine pitch for a regular array) connected throughout the direct bond interface 118. In some embodiments, the pitch of the bond pads 106a and 106b or conductive traces embedded in the bonding surface of one of the bonding elements may be less than 40 microns, or less than 10 microns, or even less than 2 microns. In some applications, it is desirable for the ratio of the pitch of the bond pads 106a and 106b to one of the bond pad dimensions (e.g., diameter) to be less than 5, or less than 3, and in some cases less than 2. In another application, the width of the conductive trace embedded in the bonding surface of one of the bonding elements may range from 0.3 microns to 20 microns, for example, from 0.3 microns to 3 microns.In various embodiments, the contact pads 106a and 106b and / or the traces may include copper, although other metals may also be suitable.

[0024] Thus, in a direct bonding process, the first element 102 can be directly bonded to the second element 104 without the aid of an adhesive. In some arrangements, the first element 102 can comprise a singulated element, such as a singulated integrated device die. In other arrangements, as shown in Figures 1a-1b, the first element 102 can comprise a carrier or substrate (e.g., a wafer) that includes a plurality (e.g., tens to hundreds or more) of device regions that, when singulated, form a plurality of integrated device dies. Similarly, the second element 104 can comprise a singulated element, such as a singulated integrated device die, as shown in Figures 1a-1b. In other arrangements, the second element 104 can comprise a carrier or substrate (e.g., a wafer). Thus, the embodiments disclosed herein can be applied to wafer-to-wafer, die-to-die, or die-to-wafer bonding processes.

[0025] As described herein, the first element 102 and the second element 104 can be directly bonded to each other without adhesive, which is different from a deposition process. In one application, the width of the first element 102 in the bonded structure can be similar to the width of the second element 104. In some other embodiments, the width of the first element 102 in the bonded structure is different from the width of the second element 104. Similarly, the width or area of ​​the larger element in the bonded structure can be at least 10% larger than the width or area of ​​the smaller element. Thus, the first element 102 and the second element 104 can include non-deposited elements. Furthermore, unlike deposited layers, the direct bond structure 100 can include defect areas along the bonded interface 118 where nanoscale voids (nanovoids) exist. The nanovoids can form due to activation (e.g., exposure to plasma) of the bonded surfaces 112a and 112b. As described above, the bonded interface 118 can include concentrations of material from the activation and / or final chemical treatment process. For example, in embodiments utilizing nitrogen plasma for activation, nitrogen peaks may form at the bond interface 118. In embodiments utilizing oxygen plasma for activation, oxygen peaks may form at the bond interface. In some embodiments, the bond interface 118 may include silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As described herein, the direct bonding step may include a covalent bond that is stronger than a van der Waals bond. The bonding layers 108a and 108b may include polished surfaces that are planarized to a high degree of smoothness.

[0026] In various embodiments, the metal-metal bond between the contact pads 106a and 106b can be bonded such that the copper grains grow into one another across the bond interface 118. In some embodiments, the copper can have grains oriented along the (111) crystal plane to improve diffusion of the copper across the bond interface 118. The bond interface 118 can extend substantially completely to at least a portion of the bonded contact pads 106a and 106b, such that there is substantially no gap between the non-conductive bonding layers 108a and 108b at or near the bonded contact pads 106a and 106b. In some embodiments, a barrier layer can be provided under the contact pads 106a and 106b (which can include, for example, copper). However, in other embodiments, there may be no barrier layer under the contact pads 106a and 106b, as described, for example, in U.S. Pat. No. 11,195,748, which is incorporated herein by reference in its entirety for all purposes.

[0027] Advantageously, the hybrid bonding techniques described herein allow for extremely fine pitches and / or small pad sizes between adjacent contact pads 106a and 106b. For example, in various embodiments, the pitch p (i.e., the edge-to-edge or center-to-center distance as shown in FIG. 1a) between adjacent pads 106a (or 106b) can be in the range of 0.5 microns to 50 microns, 0.75 microns to 25 microns, 1 micron to 25 microns, 1 micron to 10 microns, or 1 micron to 5 microns. Furthermore, the major lateral dimensions (e.g., pad diameter) can be similarly small, e.g., in the range of 0.25 microns to 30 microns, 0.25 microns to 5 microns, or 0.5 microns to 5 microns.

[0028] In various embodiments, the second element 104 can include a singulated device die and the first element 102 can include a wafer. In other embodiments, both the element 102 and the element 104 can include a singulated device die. In such embodiments, the second element 104 can be initially prepared in wafer form or on a larger substrate and singulated to form the singulated first element 104. However, the singulation process and / or other processing steps may generate debris that can contaminate the flat bonding surfaces and can leave voids and / or defects when bonding the two elements together. Thus, prior to singulation, a protective layer can be provided over the bonding surfaces prior to the activation and direct bonding steps to prevent debris from contaminating the bonding surfaces. The protective layer can include an organic or inorganic layer (e.g., photoresist) deposited (e.g., by spin coating, atomic layer deposition, vapor coating, etc.) over the bonding surfaces. Additional details of the protective layer can be found throughout U.S. Pat. No. 10,714,449, the entire contents of which are incorporated herein by reference in their entirety for all purposes. The wafer containing the first element can be singulated using any suitable method. A protective layer on the bonding surface can advantageously protect the bonding surface from debris. Prior to the direct bonding step, the protective layer can be removed from the bonding surface using a cleaning agent with a suitable solvent, such as, for example, an alkaline solution or other suitable cleaning agent recommended by the protective layer supplier. The protective layer cleaning agent can be selected so as not to substantially roughen the smooth bonding surface of the adhesive layer and not to significantly etch or contaminate the metal of the contact pads to increase recession of the pad metal after the cleaning operation. Excessive pad recession can form recesses that are too deep and may prevent pad-to-pad bonding (or reduce bond strength) under the appropriate annealing conditions (e.g., annealing temperature and time). The cleaning agent can be applied by a fan spray of liquid cleaning agent or other known methods. For example, the cleaned bonding surfaces can be ashed (e.g., using an oxygen plasma) and rinsed with deionized water (DIW). In some embodiments, the cleaned elements can be activated prior to the direct bonding step.

[0029] It may be important to protect the metal contact pads so that they do not recess too far below the non-conductive bond area. Excessive pad recession can be problematic with respect to the fabrication of hybrid bond devices. For example, increased pad recession can result in large gaps between opposing pads, which may lead to increased annealing temperatures to form electrical contact between the pads. The larger the recession, the higher the bonding temperature used to bring opposing conductive features into contact and form an electrical connection. Various embodiments disclosed herein can form reliable metal-metal direct bond interfaces at temperatures below about 200° C., preferably below about 180° C., and more preferably below about 150° C. In various embodiments, the metal recession before bonding can be less than 10 nm, e.g., in the range of 1 to 5 nm / μm for metal structures less than about 4 μm wide. For through silicon vias (TSVs), the metal recession before bonding can be 15 to 4100 nm, e.g., in the range of about 0.2 to 4 nm / μm deep depending on the TSV depth and bonding temperature. Typically, chemical mechanical polishing can result in pads with a recess of about 0.5 nm to about 100 nm. In some embodiments, after the CMP step, the pads 106a or 106b may be protruding. The height of the protruding pads 106a or 106b relative to the bonding surface 112a or 112b may range from about 0.5 nm to about 20 nm depending on the process specifications.

[0030] Thus, various embodiments disclosed herein can advantageously reduce the recess depth of structures to be hybrid direct bonded. Additionally, various embodiments can reduce intra-wafer and inter-wafer variations in recess. Providing reduced and / or uniform recess allows for the formation of highly reliable metal-to-metal direct bonds at relatively low annealing temperatures (e.g., below 275° C., preferably below 200° C., more preferably below about 180° C., more preferably below about 150° C.) for micron-scale and sub-micron features. Thermal budgets and / or manufacturing costs can also be reduced for the manufacture of direct hybrid bonded devices.

[0031] FIG. 2 illustrates a diagram showing annealing temperatures for copper pad recession for pads having different thicknesses. As shown, as the recession depth increases, higher annealing temperatures are utilized, thereby increasing the thermal budget of the direct bonding process. Furthermore, degradation of the copper pad increases the recession, thus increasing the annealing temperature for opposing copper pads to partially or completely contact one another and form a metallurgical bond. The metallurgical bond may be formed, for example, according to the methods, structures, and apparatus disclosed in U.S. Pat. No. 11,011,494, which is incorporated herein by reference in its entirety for all purposes.

[0032] In various embodiments disclosed herein, for example, a thin protective layer over the bonding surface can be utilized to protect the bonding surface and the semiconductor device during the singulation or dicing process. FIG. 3 illustrates a typical process using a thick protective coating or layer (e.g., greater than 3 microns thick). At block 320, a protective coating 312 is applied over a bonding surface 310 of a semiconductor device 302 having a non-conductive region 306 and a conductive contact region 308 on top of a semiconductor region 314 (e.g., device portion) secured on a dicing tape 304. The semiconductor region 314 can include a device portion having active circuitry patterned therein. The protective coating 312 can be applied, for example, by spin coating. In some embodiments, the protective coating 312 can include a polymer, such as, for example, a photoresist. In some embodiments, the material used for the protective coating 312 can include a solvent. The semiconductor device 302 is typically baked at 135° C. for about 180 seconds to remove any solvent in the protective coating 312 and harden the protective coating 312 (e.g., photoresist) to ensure good adhesion between the protective coating 312 and the underlying semiconductor device 302. The protective coating 312 may be deposited over the semiconductor device 302, which may be singulated in block 322 to form singulated devices 302a-302d having non-conductive regions 306a-306d and conductive contact regions 308a-308d. In block 324, the protective coating 312 may be removed.

[0033] The process depicted in FIG. 3 works reliably when using surfaces with relatively large topographical features in interconnect processes using ball grid arrays, controlled crush chip connections (C4), etc. (e.g., a typical C4 process may use solder balls with diameters of several microns to tens of microns). However, when used in direct bonding processes, the cleaning solutions used to remove the protective layer 312 may unacceptably increase dishing 309 of the copper pads used in direct bonding. For example, a relatively thick coating may require longer coating removal times (e.g., about 300 seconds to about 1200 seconds) and longer exposure to the cleaning medium, which may result in a greater degree of dishing 309. Non-uniform removal of the protective coating 312 across the substrate may also cause increased dishing non-uniformity across the semiconductor device 302. There may also be center-to-edge variations in the cleaned substrate, as well as large wafer-to-wafer variations. In some processes, e.g., direct bonding, it is important that the dishing of all pads within a die is substantially uniform. For example, various embodiments disclosed herein (e.g., the embodiments of FIGS. 4-7) can advantageously ensure that the die pad-to-pad dishing variation is less than 25%, less than 10%, less than 5%, less than 2%, or less than 1%, or less than about 0.5%. In various embodiments, the die pad-to-pad dishing variation can be in the range of 0.1% to 10%, in the range of 0.1% to 5%, or in the range of 0.5% to 5%. The dishing variation can be less than 5 nm, less than 3 nm, less than 2 nm, or less than 1 nm, e.g., in some embodiments, in the range of 0.5 nm to 5 nm. In some arrangements, the dishing variation can include an average difference between dish depths among multiple conductive contact features. In some arrangements, the dishing variation can include an average difference between dish depths among multiple conductive contact features. Residue management can also be difficult because a thick protective coating 312 can result in a relatively large amount of residue that is difficult to completely remove from the semiconductor devices 302a-302d. Additionally, the higher the baking temperature, the more difficult it may be to peel the protective layer 312 from the semiconductor devices 302a-302d.Furthermore, at high temperatures, the protective layer 312 may react with the metal bond pads 308a-308d, and such reactions may tend to roughen the metal bond pads 308a-308d and increase the recession of the metal bond pads 308a-308d.

[0034] In some embodiments, for conventional thick resist and high bake temperature approaches, the recession of the pads 308a-308d can range from about 60 nm to about 200 nm or more for a 2 micrometer thick metal pad, for example. After a solvent cleaning step to remove the protective layer 312, some of the pads 308a-308d located on different parts of the bonding surface 310 may be clean after, for example, 180 seconds, while pads on other parts of the bonding surface 310 may still be contaminated with the hard-baked protective layer 312. For example, an additional cleaning time of 180 seconds or more may be used to strip the protective layer from the surfaces of the pads 308a-308d or the bonding surface 310. Thus, some clean pads may be exposed to the action of the solvent for an even longer period of time. Depending on the dissolution or loss of pad material during the removal of the protective layer 312, large variations in recession may be formed within a given die and / or between dies located on different parts of the substrate 314, for example between a die located in the center and a die located near the edge of the substrate 314. The pad recession variation within any given die (i.e., the maximum difference between recession depths from the bonding surface 310 for any two pads) can be an amount greater than 10 nm, such as 15 nm or more. This large variation in recession 309 within a given die and across the substrate 314 can be problematic because it can require higher bonding temperatures to form a suitable metal-metal bond in the bonding substrate 100 of FIG. 1b for pads with deeper recesses, as shown in FIG.

[0035] Thus, in various embodiments, as shown in FIG. 4 at block 420, a thinner protective coating 412 can instead be applied over the bonding surface 310 of the semiconductor device 302, for example, by spin coating, atomic layer deposition, or vapor phase coating. The thin protective coating can have a thickness of less than 3 microns, less than 2 microns, less than 0.25 microns, or less than 0.1 microns. For example, in various embodiments, the thickness of the protective coating can range from 0.05 microns to 2 microns, or from 0.1 microns to 0.25 microns. The thin protective coating can include, for example, an organic layer in some embodiments. The thin protective layer can be baked at a temperature below 130° C., preferably below 110° C., and even below 70° C. For example, the protective layer can include a hydrophobic coating and / or a hydrophilic coating, or a combination of both. In some embodiments, the protective layer can include a photoresist. In the embodiment of FIG. 4, the protective layer can be blanket deposited over the entire semiconductor device, including over the contact pads 308 and over the non-conductive bonding regions 306. Advantageously, thinner protective layers may result in less variation in coating thickness than thicker layers.

[0036] In various embodiments, the bonding surfaces can be prepared for direct bonding before the protective layer 312 is applied. For example, the bonding surfaces can be planarized before the protective layer 312 is applied. In some embodiments, the bonding surfaces can be activated before the protective layer 312 is applied. Activating the first bonding surface can include plasma activating the first bonding surface. Plasma activating the first bonding surface can include exposing the first bonding surface to a nitrogen-containing plasma. In other embodiments, before the protective layer 312 is applied, the bonding surfaces of the semiconductor elements 302 to be singulated can be briefly exposed to an oxygen plasma (ashing) to form a very thin oxide (e.g., a few nanometers thick) on the surfaces of the pads 308.

[0037] The semiconductor device 302 may remain covered with the protective layer 312 for any suitable period of time. For example, in some embodiments, the semiconductor device 302 may be prepared for direct bonding, covered with the protective layer 312, and then stored and / or transported to a different location or facility. In some cases, the protected semiconductor device 302 may remain protected with the protective layer 312 for a period of more than 24 hours, or for a week or more, or for a month or more. As shown in block 422, prior to removing the protective layer 312, the semiconductor device may be singulated into a plurality of semiconductor devices having bonding surfaces 310a-310d, non-conductive regions 306a-306d, and conductive contact regions 308a-308d. In block 424, prior to direct bonding, the protective layer 312 may be removed in any suitable manner. For example, the protective layer 312 may be removed using any suitable cleaning process. In some embodiments, the first cleaning process may utilize a highly alkaline solution, such as dilute tetramethylammonium hydroxide, or other suitable solvents (e.g., polyglycol blends, or modified ketones, etc.) recommended by the protective layer supplier to strip the protective coating 412. The modified ketones may have minimal interaction with the dicing tape and / or metal of the contact pads 306a and 306b (unlike acetone, which may readily attack the dicing tape). In one embodiment, if the protective layer is a photoresist material, the applied photoresist protective layer may be exposed to UV light to degrade the resist layer, thereby reducing the cleaning time to strip the protective layer from the bonding surface of the semiconductor device. Advantageously, the protective layer 312 may be removed more quickly (e.g., in about 60 seconds or less) than a thick protective layer as shown in FIG. 3. The overstrip time may also be significantly shorter, e.g., less than 30 seconds, less than 20 seconds, or less than 15 seconds, whereas the overstrip time for a thick layer may often be greater than 1 minute, 2 minutes, or longer. In addition, there may be less debris remaining.

[0038] In some embodiments, a second cleaning process may be used in addition or instead. For example, the second cleaning process may be used to clean dicing particles and other debris from the die or diced sheet. In this example, the first cleaning step may strip the protective layer 312 from the bonding surface of the semiconductor device, and the second cleaning step may include a cleaning solution configured to remove unwanted organic material and unwanted particulates from the plurality of semiconductor devices and the dicing lanes of the dicing tape. In this embodiment, the first cleaning step may include a dry process, such as, for example, applying an oxygen plasma to strip a very thin organic protective layer from the surface of the singulated semiconductor device. In some embodiments, the second cleaning step may include a wet cleaning solution. In such a cleaning step, the ashed surface of the semiconductor device may be cleaned using a suitable solvent containing a suitable surfactant or particulate remover. Typically, the cleaning step is followed by a deionized (DI) water rinse and drying step.

[0039] Advantageously, a thin protective coating can utilize cleaning solutions that are more suitable for the materials used in the semiconductor device, as discussed above. The shorter duration of the removal process and overall cleaning time can advantageously reduce the degree of degradation of the copper pads due to the cleaning process compared to processes using thicker protective layers and longer cleaning processes. Thus, the embodiment of FIG. 4 can provide shallower recesses 309 and more uniform recess depths (i.e., less recess variation), which can improve the reliability of direct bonding in hybrid bond structures. In some embodiments, no two pads can have a recess depth difference of more than 5 nm, more than 3 nm, more than 1 nm, or more than 0.5 nm. The recess variation between pads of a die is less than 25%, less than 10%, less than 5%, less than 2%, or less than 1%, or less than about 0.5%. In various embodiments, the recess variation between pads can be in the range of 0.1% to 10%, in the range of 0.1% to 5%, or in the range of 0.5% to 5%. The dishing variation can be less than 5 nm, less than 3 nm, less than 2 nm, or less than 1 nm, for example, in some embodiments in the range of 0.5 nm to 5 nm. In some arrangements, the dishing variation can include an average difference between dishing depths among a plurality of conductive contact features. In some arrangements, the dishing variation can include an average difference between dishing depths among a plurality of conductive contact features.

[0040] 5 illustrates another exemplary process 500 in which a thin protective layer 512 is provided over a passivation layer 514 according to some embodiments. At step 520, the passivation layer 514 may be selectively provided over the contact pads 308. For example, wet chemical and / or plasma processes may be used to selectively oxidize the contact pads 308. In some embodiments, a few monolayers of a metal complexing agent, such as benzotriazole or a similar compound, may be selectively coated over the contact pads 308 using known methods.

[0041] At step 522, a thin protective layer 512 (e.g., a protective layer less than about 2 μm thick, preferably less than about 0.2 μm thick) may be provided over the pads 308 and the non-conductive bond regions 306 of the device. In the illustrated embodiment, the protective layer 512 is blanket deposited over the device. At step 524, the device 302 may be singulated, and at step 526, the protective layer 512 may be removed as described above. In some embodiments, the protective layer may be stripped in less than about 3 minutes. At step 528, the passivation layer 514 may be selectively removed from the contact pads 308 by wet etching, foaming gas, or other suitable means. Additional cleaning may be performed for particle control.

[0042] 6 illustrates another exemplary process 600 according to some embodiments in which the contact pads 308 protrude above the non-conductive bonding material 306 prior to application of the protective layer 612. As shown in block 620, the contact pads 308 may protrude above the bonding surface 310 of the non-conductive bonding material 306 (e.g., if the non-conductive bonding material 306 has been previously etched or as a result of a chemical mechanical polishing or CMP process). In block 622, a protective layer 612 (which may be the same as protective layer 412) may be provided over the protruding contact pads 308 and the non-conductive bonding material 306, and the devices 302 may be singulated. In block 624, the protective layer 612 may be removed. In some embodiments, the removal of the protective layer 612 in block 624 also causes some removal of the surface of the contact pads 308, reducing the protrusion of the contact pads 308 above the surface of the non-conductive bonding material 306. In block 626, the bonding surface may be planarized (e.g., by chemical mechanical polishing or CMP process) so that the contact pads 308 are recessed relative to the surface of the non-conductive bonding material 306. The recession of the pads may be controlled by managing the copper / oxygen interaction. In another embodiment, after stripping the protective layer 612, the bonding surface 310 and the pads 308 may be cleaned with a diluted pad cleaner to remove unwanted protrusions of the pads 308 and to create a known or desired recession in the pads 308. This cleaning may create a known recession without degrading the bonding surface 310 or the recessed pad bonding surface. For example, the cleaner may not result in significant roughening of the bonding surface 310 or the pads 308, and may not result in the formation of unwanted particles on the bonding surface that may directly affect the bonding between opposing substrates without the use of adhesive.

[0043] FIG. 7 illustrates an exemplary process 700 according to some embodiments in which a protective coating is selectively applied over the contact pads, rather than being deposited as a blanket coating. In block 720, a passivation layer 714 (which may be similar or the same as passivation layer 514) may be applied over the pads 308, and a protective layer 712 may be applied over the passivation layer 714. In some embodiments, the passivation layer 714 may be selectively applied without the protective layer 712 to protect the pads, thereby reducing the variation and increase in dishing due to removal of the protective layer 712. Thus, an organic blanket layer may not be applied over the entire surface of the semiconductor device. As a result, in some embodiments, a separate protective layer 712 may not be applied, as the passivation layer 714 may function as a protective layer to protect the pads during singulation. The passivation layer 714 may be applied to oxidize the pads, and may be more resistant to cleaning chemicals than copper. In block 722, the device 302 may be diced while maintaining a wet surface. After dicing, the elements 302 can be cleaned, for example, using water and a surfactant. The passivation layer on the pads can be removed using any suitable method. For example, the passivation layer can be removed using a dilute acid or base solution and / or by an oxidizing / etching agent to remove the hydrophobic coating areas without substantially attacking the copper pads.

[0044] In some embodiments, reactive ion etching (RIE) can be used to remove the thin protective coating.

[0045] In some embodiments, a saw can be used to singulate the device. In other embodiments, RIE can be used to singulate the semiconductor device into multiple singulated device dies. In such embodiments, the protective layer can be provided to a thickness of about 1 micron, for example, in the range of 1 micron to 3 microns. The RIE process can be used to singulate the device, and the protective layer can protect the pads during the RIE. However, the RIE process may reduce the thickness of the protective layer sufficiently that a subsequent cleaning process can be used to remove the remaining thin protective layer without causing excessively large recesses. In block 724, the protective layer 712, if present, can be removed, and in block 726, the passivation layer 714 can be removed to expose the faces of the conductive contact regions 308a-308d.

[0046] In some embodiments, conductive pads 308 having various dimensions may be formed in the dielectric layer 306, and the conductive pads 308 may have an exposed bonding surface. For example, different conductive features in a die may include pads having widths of 2 to 4 microns, 5 to 8 microns, or 10 to 15 microns. The conductive pads may be arranged in an array with a defined pitch. In some embodiments, the pitch of the small pads may be smaller than the pitch of the large pads. Advantageously, the methods described herein may result in the same or similar dimples formed across different pads of varying widths and pitches. For example, the dimple variation caused by protective layer coating, singulation, protective layer stripping, and other surface preparation steps may be less than about 3 nm across a given die, such as less than 2 nm or less than 1 nm across a die. In some embodiments, the dimple variation across a die may be in the range of 0.3 nm to 3 nm, in the range of 0.5 nm to 3 nm, or in the range of 1 nm to 3 nm. The shallow recess and small recess variation across the die allows the bonded structure (such as bonded structure 100) to be formed at a relatively lower temperature compared to dies with deeper recesses and / or larger recess variation for a given die. The lower temperature bonding operation can be used to directly bond dies with large differences in thermal expansion without an adhesive layer. For example, the thermal expansion of semiconductor element 104 can be different than the thermal expansion of semiconductor element 102. By way of example only, in some embodiments, the difference in thermal expansion of bonded semiconductor elements 102 and 104 may be at least 10%.

[0047] Unless the context clearly indicates otherwise, the words "comprises," "comprising," "including," "including," and the like throughout this specification and claims are to be construed in an inclusive sense, i.e., "including but not limited to," as opposed to a restrictive or inclusive sense. As used generally herein, the word "joined" refers to two or more elements that are either directly connected or connected through one or more intermediate elements. Similarly, as used generally herein, the word "connected" refers to two or more elements that are either directly connected or connected through one or more intermediate elements. In addition, the words "herein," "above," "below," and words of similar import, when used in this application, refer to this application as a whole and not to any particular portion of this application. Furthermore, as used herein, when a first element is described as being "on" or "over" a second element, the first element can be directly on or over the second element, such that the first and second elements are in direct contact, or the first element can be indirectly on or over the second element, such that there are one or more intervening elements between the first and second elements. Where the context permits, words using the singular or plural in the above detailed description can also include the plural or singular, respectively. The word "or" in connection with a list of two or more items covers all of the following interpretations for that word: any of the items in the list, all of the items in the list, and any and all combinations of the items in the list.

[0048] Additionally, conditional language used herein, such as, among others, "may," "could," "could," "may," "for example," "for example," and "such as," are generally intended to convey that certain embodiments include particular features, elements, and / or conditions, while other embodiments do not, unless specifically stated otherwise or understood otherwise within the context in which they are used. Thus, such conditional language is generally not intended to imply that a feature, element, and / or condition is in any way required for one or more embodiments.

[0049] Although certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in different other forms, and various omissions, substitutions, and modifications may be made to the forms of the methods and systems described herein without departing from the spirit of the present disclosure. For example, although blocks are presented in a given arrangement, alternative embodiments may perform similar functions using different components and / or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of the elements and operations of the various embodiments described above may be made to provide further embodiments. The claims and their equivalents are intended to cover such forms or modifications as fall within the scope and spirit of the present disclosure.

Claims

1. preparing a first bonding surface of a first element for direct bonding to a second bonding surface of a second element; after the preparing step, providing a protective layer having a thickness of less than 3 microns over at least a portion of the prepared first bonding surface of the first element; A bonding method comprising:

2. The method of claim 1 , wherein preparing the first faying surface comprises activating the first faying surface.

3. The bonding method according to claim 1 or 2, wherein the protective layer has a thickness of less than 2 microns.

4. The bonding method of claim 3 , wherein the thickness of the protective layer is in the range of 0.05 microns to 2 microns.

5. The method of claim 1 , wherein providing the protective layer comprises blanket depositing the protective layer over the first bonding surface.

6. prior to the step of providing the protective layer, selectively providing a passivation layer over the plurality of contact pads; providing the protective layer includes providing the protective layer over the passivation layer. The joining method according to claim 1 .

7. the first mating surface includes a plurality of contact pads projecting above a first non-conductive region of the first mating surface; providing the protective layer includes providing the protective layer over at least the protruding contact pads. The joining method according to claim 1 .

8. 2. The method of claim 1, wherein the first bonding surface includes a first plurality of conductive contact pads and a first non-conductive bonding area, the first plurality of conductive contact pads being recessed below the first non-conductive bonding area.

9. 9. The method of claim 8, wherein the variation in recess depth of the first plurality of contact pads across the first element is less than 25%.

10. 10. The method of claim 9, wherein the variation in recess depth of the first plurality of contact pads across the first element is less than 10%.

11. The bonding method of claim 1 further comprising the step of removing the protective layer.

12. the first element comprises a wafer; the method further comprising, prior to removing the protective layer, singulating the wafer to form a plurality of singulated devices. The bonding method according to claim 11.

13. 13. The bonding method according to claim 11 or 12, further comprising, after the step of removing the protective layer, a step of directly bonding the first bonding surface of the first element to the second bonding surface of the second element without the use of an adhesive.

14. the first bonding surface comprises a first plurality of conductive contact pads and a first non-conductive bonding region; the second bonding surface comprises a second plurality of conductive contact pads and a second non-conductive bonding area; the step of directly bonding includes a step of hybrid direct bonding including the steps of directly bonding the first and second plurality of conductive contact pads to one another without an adhesive and directly bonding the first and second non-conductive bonding regions to one another without an adhesive. The bonding method according to claim 13.

15. The method of claim 13 further comprising the step of activating the second bonding surface prior to the direct bonding step.

16. preparing a first bonding surface of a first element for direct bonding to a second bonding surface of a second element; after the preparing step, selectively applying a protective layer over a plurality of contact pads of the first bonding surface; A bonding method comprising:

17. The method of claim 16, wherein the protective layer has a thickness of less than 3 microns.

18. preparing a first bonding surface of a first element for direct bonding to a second bonding surface of a second element; after said preparing step, selectively providing a passivation layer over a plurality of contact pads of said first bonding surface; A bonding method comprising:

19. 20. The method of claim 18, wherein the step of providing a passivation layer comprises oxidizing a surface of the contact pad.

20. A device region; a bonding layer over the device area, the bonding layer having a first bonding surface prepared for direct hybrid bonding to a second element; a protective layer over at least a portion of the provided first bonding surface, the protective layer having a thickness of less than 3 microns; A semiconductor element comprising:

21. The semiconductor device of claim 20 , wherein the protective layer comprises a photoresist.

22. 21. The semiconductor device of claim 20, wherein the semiconductor device is in wafer form.

23. 21. The semiconductor device of claim 20, wherein the protective layer has a thickness in the range of 0.05 microns to 2 microns.

24. 21. The semiconductor device of claim 20, wherein the bonding layer comprises a plurality of conductive contact pads and non-conductive bonding regions.

25. 25. The semiconductor device of claim 24, further comprising a passivation layer spanning the plurality of conductive contact pads between the plurality of contact pads and the protection layer.

26. 25. The semiconductor device of claim 24, wherein the protective layer is selectively disposed over the plurality of conductive contact pads.

27. 25. The semiconductor device of claim 24, wherein the plurality of conductive contact pads protrude above the bonding layer.

28. 25. The semiconductor device of claim 24, wherein the plurality of conductive contact pads are recessed below a top surface of the bonding layer.

29. 21. The semiconductor device of claim 20, wherein the protective layer is blanket deposited over the bonding surface.

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