Direct bonding and peeling of carriers

Abstract

A bonding method is disclosed. The method can include directly bonding a first non-conductive bonding material of a semiconductor device to a second non-conductive bonding material of a carrier without an intervening adhesive. The first non-conductive bonding material is disposed on a device portion of the semiconductor device. The second non-conductive bonding material is disposed on a bulk portion of the carrier. A deposited dielectric layer is disposed between the device portion and the bulk portion. The method can include removing the carrier from the semiconductor device by transferring thermal energy to the dielectric layer to induce diffusion of gas from the dielectric layer.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 63 / 168,946, entitled “Direct Bonding and Debonding of Carriers,” filed March 31, 2021, the entire contents of each of which are hereby incorporated by reference herein.

[0002] The field of the invention relates to direct bonding of a semiconductor element to a carrier and removal of the carrier after direct bonding. [Background technology]

[0003] Semiconductor elements, such as semiconductor wafers, can be stacked and directly bonded to one another without adhesives. For example, in some direct bond structures, the non-conductive field regions of the elements can be directly bonded to one another. In some structures, the corresponding conductive contact structures can also be directly bonded to one another. Summary of the Invention [Problem to be solved by the invention]

[0004] In some applications, it can be difficult to form thinned dies and wafers and / or perform backside processing, therefore, there remains a need for improved methods and structures for direct bonding.

[0005] Specific implementations will now be described with reference to the following drawings, which are provided by way of example and not limitation. [Brief description of the drawings]

[0006] [Figure 1A] FIG. 2 is a schematic cross-sectional side view of two elements prior to bonding. [Figure 1B] FIG. 1B is a schematic cross-sectional side view of the two elements shown in FIG. 1A after bonding. [Figure 2A] 1A-1D are schematic cross-sectional views of various stages of a bonding method according to an embodiment. [Figure 2B] 1A-1D are schematic cross-sectional views of various stages of a bonding method according to an embodiment. [Figure 2C] 1A-1D are schematic cross-sectional views of various stages of a bonding method according to an embodiment. [Figure 2D] 1A-1D are schematic cross-sectional views of various stages of a bonding method according to an embodiment. [Figure 2E] 1A-1D are schematic cross-sectional views of various stages of a bonding method according to an embodiment. [Diagram 3] 1 is a flow chart illustrating a method for bonding and debonding a semiconductor device to a carrier. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] In various microelectronic devices, two or more elements 2, 3 can be directly bonded to each other without adhesive to form a bonded structure. The elements 2, 3 in FIG. 1A and FIG. 1B can comprise semiconductor elements in some embodiments. For example, in various embodiments, the first and second elements 2, 3 can comprise semiconductor wafers. In some embodiments, the first and second elements 2, 3 can comprise semiconductor device dies. In some embodiments, one of the first and second elements can comprise a semiconductor wafer and the other of the first and second elements can comprise a semiconductor device die. In various embodiments disclosed herein, the second element 3 can comprise a carrier that can be temporarily bonded directly to the first element 2 and subsequently removed (e.g., after thinning and / or other processing). For example, in some embodiments, the first element 2 can comprise a semiconductor element (e.g., a singulated integrated device die or a non-singulated wafer) having a device portion 5 and a first non-conductive bonding material 4a on the device portion 5. The device portion 5 can comprise a semiconductor material having active circuitry formed thereon. The second element 3 may comprise a substrate 6 and a second non-conductive bonding material 4b on the substrate 6. In some embodiments, the substrate 6 may comprise glass or a semiconductor (such as silicon).

[0008] In various embodiments, as shown in Figures 1A-1B, the non-conductive (e.g., semiconductive or inorganic dielectric) bonding material 4a of the first element 2 can be directly bonded to the corresponding non-conductive (e.g., semiconductive or inorganic dielectric) bonding material 4b of the second element 3 without an adhesive. In some embodiments (not shown), the conductive regions (e.g., metal pads or contact structures) of the first element 2 can be directly bonded to the corresponding conductive regions (e.g., metal pads or contact structures) of the second element 3 without an adhesive. In some embodiments, the non-conductive material 4a of the first element 2 can be directly bonded to the corresponding non-conductive material 4b of the second element 3 using adhesive-free bonding techniques using direct bonding techniques disclosed in at least U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, the contents of each of which are incorporated herein by reference in their entirety for all purposes. Additional examples of hybrid bonding can be found throughout U.S. Pat. No. 11,056,390, the contents of which are incorporated herein by reference in their entirety for all purposes. In other applications, in a bonding structure 1, the non-conductive material of the first element 2 can be directly bonded to the conductive material of the second element 3, so that the conductive material of the first element 2 is intimately bonded to the non-conductive material of the second element 3. Dielectric bonding surfaces or materials suitable for direct bonding include, but are not limited to, inorganic dielectrics such as silicon oxide, silicon nitride, or silicon oxynitride, or can include silicon carbide, silicon oxycarbonitride, low K dielectric materials, SICOH, silicon carbonitride, or diamond-like carbon, or materials with diamond surfaces. Such carbon-containing ceramic materials can be considered inorganic, despite the carbon content.

[0009] In various embodiments, a direct bond can be formed without the aid of an adhesive. For example, the semiconductor or dielectric bonding surfaces can be polished to a high degree of smoothness. The bonding surfaces can be cleaned and exposed to a plasma and / or an etchant to activate the bonding surfaces. In some embodiments, the bonding surfaces can be terminated with a chemical species after or during activation (e.g., during a plasma and / or etch process). Without being limited by theory, in some embodiments, an activation process can be performed to break chemical bonds at the bonding surfaces, and a termination process can provide additional chemical species at the bonding surfaces that improve the bond energy during direct bonding. In some embodiments, activation and termination treatments are provided in the same step, such as, for example, a plasma or wet etchant that activates and terminates the bonding surfaces. In other embodiments, the bonding surfaces can be terminated in a separate process to provide additional chemical species for direct bonding. In various embodiments, the termination chemical species can include nitrogen. For example, in some embodiments, the bonding surfaces can be exposed to a nitrogen-containing plasma. Additionally, in some embodiments, the bonding surfaces can be exposed to fluorine. For example, there may be one or more fluorine peaks near the layers and / or bonding interfaces, particularly the dielectric bonding interfaces. Thus, in a direct bond structure, the bond interface between two non-conductive materials can include a very smooth interface with a higher nitrogen content and / or fluorine peak at the bond interface. Additional examples of activation and / or termination treatments can be found throughout U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, the contents of each of which are incorporated herein by reference in their entirety for all purposes.

[0010] In various embodiments, the conductive contact pads of a first element can be directly bonded to corresponding conductive contact pads of a second element (e.g., in a configuration where both elements have contact pads). For example, direct hybrid bonding techniques can be used to provide conductor-to-conductor direct bonds along a bonding interface comprising a covalently directly bonded dielectric-to-dielectric surface prepared as described above. In various embodiments, conductor-to-conductor (e.g., contact pad-to-contact pad) direct bonds and dielectric-to-dielectric hybrid bonds can be formed using at least the direct bonding techniques disclosed in U.S. Patent Nos. 9,716,033 and 9,852,988, the contents of each of which are incorporated herein by reference in their entirety for all purposes. The bonding structures described herein may also lend themselves to direct metal bonding or other bonding techniques that do not involve bonding of non-conductive regions.

[0011] In some embodiments, inorganic dielectric bonding surfaces can be prepared and bonded directly to each other without an adhesive as described above. In a direct bond structure having contact pads, the conductive contact pads (which may be surrounded by non-conductive dielectric field regions) can also be bonded directly to each other without an adhesive. In some embodiments, each contact pad can be recessed below an outer surface (e.g., top surface) of the dielectric field region or non-conductive bonding region by, for example, less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, in the range of 2 nm to 20 nm or in the range of 4 nm to 10 nm. The coefficient of thermal expansion (CTE) of the dielectric can be, for example, in the range of 0.1 ppm / °C to 5 ppm / °C, and the CTE of the conductive material can be in the range of 6 ppm / °C to 40 ppm / °C or 8 ppm / °C to 30 ppm / °C. The difference between the CTE of the dielectric and the CTE of the conductive material inhibits lateral expansion of the conductive material during subsequent thermal processing operations, thereby facilitating the conductive pads to contact. The non-conductive bonding regions can in some embodiments be directly bonded together without adhesive at room temperature, and the bonded structure can then be annealed. Upon annealing, the contact pads can expand against the non-conductive bonding regions and contact each other to form a direct metal-metal bond. Advantageously, using hybrid bonding technologies such as Direct Bond Interconnect, or DBI®, available from Xperi, Inc., San Jose, Calif., allows for a high density of pads (e.g., small or fine pitch for a regular array) connected across the direct bond interface. In various embodiments, the contact pads can include copper, although other metals may also be suitable. In arrangements where the first and second elements 2, 3 do not have contact pads at the bonding surface, the non-conductive materials can be directly bonded at room temperature, and metal contact can be achieved without subsequent annealing.

[0012] Thus, in a direct bonding process, the first element can be directly bonded to the second element without the aid of an adhesive. In some arrangements, the first element can comprise a singulated element, such as a singulated integrated device die. In other arrangements, the first element can comprise a carrier or substrate (e.g., a wafer) comprising a plurality (e.g., tens to hundreds or more) of device regions that, when singulated, form a plurality of integrated device dies. Similarly, the second element can comprise a singulated element, such as a singulated integrated device die. In other arrangements, the second element can comprise a carrier or substrate (e.g., a wafer). In some embodiments, multiple dies with different CTEs can be bonded onto the same carrier. In some embodiments, the CTE of the substrate of the bonded dies can be similar to the CTE of the substrate of the carrier. In other embodiments, the CTE of the substrate of the bonded dies can be different from the CTE of the substrate of the carrier. The difference in CTE between the bonded dies or between the bonded die and the carrier may range from 1 ppm / °C to 70 ppm / °C, and may be less than 30 ppm / °C, such as less than 12 ppm / °C.

[0013] As described herein, the first and second elements can be directly bonded to each other without an adhesive, which is different from a deposition process. Thus, the first and second elements can include non-deposited elements. Furthermore, the direct bond structure, unlike a deposited layer, can include defect regions where nanovoids exist along the bond interface. The nanovoids can be formed due to activation (e.g., exposure to plasma) of the bonded surfaces. As described above, the bond interface can include concentrations of material from the activation and / or final chemical treatment process. For example, in embodiments utilizing nitrogen plasma for activation, a nitrogen peak can be formed at the bond interface. In embodiments utilizing oxygen plasma for activation, an oxygen peak or oxygen-rich layer can be formed at the bond interface. In some embodiments, the bond interface can include nitrogen-terminated inorganic non-conductive materials such as nitrogen-terminated silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride, and the level of nitrogen present at the bond interface represents the nitrogen termination for at least one of the elements prior to direct bonding. With the exception of nitrogen-containing dielectrics, the nitrogen content of the non-conductive material typically has a gradient that peaks at or near the surface. In some embodiments, nitrogen and nitrogen-related moieties may not be present at the bond interface. As described herein, the direct bond may include a covalent bond that is stronger than a van der Waals bond. The bonding layer may also include a polished surface that is planarized to a high degree of smoothness.

[0014] In various embodiments where the elements 2, 3 have directly bonded metallic contact pads, the metal-metal bond between the contact pads can be bonded such that the metal grains (e.g., copper grains) grow into each other across the bond interface. In some embodiments, the copper can have grains oriented perpendicularly along the (111) crystal plane to improve diffusion of the copper across the bond interface. However, in some embodiments, other crystal planes of the copper can be oriented perpendicularly to the contact pad surface. The non-conductive bond interface can extend substantially completely to at least a portion of the bonded contact pads, such that there is substantially no gap between the non-conductive bond regions at or near the bonded contact pads. In some embodiments, a barrier layer can be provided under the contact pads (which can include, for example, copper). However, in other embodiments, there may be no barrier layer under the contact pads, as described, for example, in U.S. Pat. No. 11,195,748, which is incorporated herein by reference in its entirety for all purposes.

[0015] In some applications, for example, in a multi-element device stack such as a memory device, it may be desirable to utilize a thinned semiconductor element. For example, a semiconductor element (such as a semiconductor element wafer) can be temporarily bonded to a carrier (e.g., a glass or silicon carrier wafer) through an adhesive, such as a thermally curable or UV-curable adhesive (e.g., an organic adhesive). The backside of the semiconductor element can be thinned, for example, by grinding and / or chemical mechanical polishing (CMP). Additionally, additional backside processing can be performed on the backside of the semiconductor element while it is attached to the carrier. For example, thin metallization or back-end interconnect (BEOL) layers can be deposited or otherwise provided on the thinned semiconductor element.

[0016] However, the use of adhesives for temporary bonding can be challenging in many ways. For example, when the device wafer is thinned, residual stresses from the BEOL thin films can cause a lateral increase in die size because the organic adhesives may not provide sufficient bond strength to suppress the lateral increase of the device wafer. Furthermore, the mechanical stability of the adhesive bond between the device wafer and the carrier wafer during the thinning process (e.g., grinding process) can be degraded or unreliable due to the forces applied during thinning. In some cases, the thinning process can cause the thickness of the device wafer to vary significantly, even exceeding the desired total thickness variation (TTV). For example, the temporary adhesive interposed between the device wafer and the carrier wafer can have non-uniformities, resulting in excessive thickness variation during thinning. Furthermore, the temporary adhesive bond may not have sufficient thermal and / or chemical stability when exposed to different processes. For example, the temporary adhesive can degrade when exposed to chemicals used in wafer cleaning, electrochemical deposition (ECD), and / or CMP. Alternatively or additionally, the adhesive may decompose during the deposition and / or etching process (chemical vapor deposition (CVD), plasma enhanced CVD, physical vapor deposition, etc.). In addition, when the carrier and adhesive are removed from the device wafer, the device wafer may contain residue from the adhesive, which may require additional cleaning steps. Thus, there remains a need for improved methods and structures for thinning semiconductor devices.

[0017] 2A-2E illustrate an exemplary bonding method according to various embodiments. Unless otherwise noted, components in FIGS. 2A-2E may be the same or substantially similar to like-numbered components in FIGS. 1A-1B. As shown in FIG. 2A, a first semiconductor element 2 may comprise a semiconductor device element in wafer form or as a singulated integrated device die. The semiconductor element 2 may comprise a device portion 5 having active circuitry and / or devices therein. In FIG. 2A, the semiconductor element 2 has a front side 15 and a back side 16 opposite the front side 15. The semiconductor element 2 and device portion 5 are shown in FIG. 2A prior to thinning, e.g., prior to grinding or polishing the back side 16 of the semiconductor element 2.

[0018] Additionally, a diffusion barrier layer 10 may be provided on the device portion 5. As described herein, the diffusion barrier layer 10 may have low gas permeability to reduce or prevent diffusion of gases into the device portion 5 and the active circuitry therein. The diffusion barrier layer 10 may be configured to reduce or inhibit diffusion of gases, such as hydrogen, into the device portion 5 and the active circuitry therein. In some embodiments, the diffusion barrier layer 10 may comprise an inorganic dielectric material with low gas permeability, such as silicon nitride. The diffusion barrier layer 10 may comprise a high density material having a density greater than 2.75 g / cc. In some embodiments, the diffusion barrier layer 10 may have a density in the range of 2.75 g / cc to 5 g / cc, 2.9 g / cc to 5 g / cc, 3 g / cc to 5 g / cc, 2.75 g / cc to 4 g / cc, 2.75 g / cc to 3.5 g / cc, or 3 g / cc to 3.5 g / cc. For example, the diffusion barrier layer 10 may have a density of about 3.17 g / cc. In some embodiments, the diffusion barrier layer 10 may have a density higher than the density of the device portion 5, the density of silicon, the density of silicon oxide, and / or the density of the first non-conductive bonding material 4a. For example, the barrier layer 10 may include a silicon-based layer deposited, for example, by chemical vapor deposition CVD (e.g., plasma-enhanced CVD (PECVD) or physical vapor deposition (PVD)). The first non-conductive bonding material 4a may be provided on the diffusion barrier layer 10. In various embodiments, the first non-conductive bonding material 4a may include a dielectric bonding layer, such as silicon oxide, silicon oxynitride, silicon nitride, silicon oxycarbonitride. In some embodiments, the first non-conductive bonding material 4a may include a semiconductor material. In some embodiments, the first non-conductive bonding material 4a may include a diffusion barrier layer 10 to itself act as a diffusion barrier against outgassing. The diffusion barrier layer 10 may be blanket deposited over the device portion 5 of the first semiconductor device 2, for example over the entire width of the device portion 5.

[0019] In FIG. 2A, the second element 3 can include a carrier 8. The carrier 8 can serve as a temporary support for the first semiconductor element 2 during various processing stages, such as thinning, backside metallization, and / or other processing. The carrier 8 can include a bulk carrier portion 6, which can include any suitable material, such as glass, low-doped silicon, etc. An inorganic light-to-heat (LTH) conversion layer 9 can be provided on the bulk portion 6. For example, in some embodiments, the LTH conversion layer 9 can be bulk deposited on the bulk portion 6, for example, through the entire width of the bulk carrier portion 6. As described herein, the LTH conversion layer 9 can be configured to convert light to thermal energy. In some embodiments, the LTH conversion layer 9 can include a metal. For example, the metal can include at least one of copper, aluminum, titanium, and titanium nitride. Other metals may also be suitable. In other embodiments, the LTH conversion layer 9 can include microcrystalline silicon (μc-Si).

[0020] As shown in Figure 2A, a dielectric layer 17 including a second non-conductive bonding material 4b can be provided on the LTH conversion layer 9. Figure 2A shows the dielectric layer 17 deposited on the LTH conversion layer 9 such that the LTH conversion layer 9 is disposed between the bulk portion 6 of the carrier 8 and the dielectric layer 17. In other embodiments, there may be no LTH conversion layer 9, as described herein. Rather, in such embodiments, the dielectric layer 17 can be provided on the bulk portion 6 (and / or over other build-up layers) without an intervening LTH conversion layer.

[0021] As shown in the embodiment of FIG. 2A, the carrier 8 can have a front surface 14 and a back surface 13 opposite the front surface 14. In the illustrated embodiment, a dielectric layer 17 (e.g., which can function as the second non-conductive bonding layer 4b in some embodiments) can at least partially define the front surface 14. For example, in some embodiments, the dielectric layer 17 can be bulk deposited on the LTH conversion layer 9, for example across the entire width of the LTH conversion layer 9. The dielectric layer 17 can include a porous dielectric material configured to allow gas release therefrom. Advantageously, the porosity and / or gas permeability of the dielectric layer 17 can be manipulated during the deposition process. For example, one or more impurity species can be introduced during the deposition process to increase the gas permeability of the dielectric layer 17 to achieve a desired gas permeability. In some embodiments, for example, the one or more impurity species can include at least one of carbon and nitrogen in the dielectric layer 17. For example, in some embodiments, the dielectric layer 17 can include silicon oxycarbonitride. As a result, various embodiments can advantageously use a deposition process to increase gas diffusion within the dielectric layer 17 as opposed to other methods such as post-deposition ion implantation. For example, the dielectric layer 17 can include a porous dielectric material having high gas permeability to, for example, hydrogen gas (H), argon, and / or water vapor. In some embodiments, to aid in the selection or derivation of the hydrogen release temperature, the deposition of the dielectric layer 17 can be designed to provide a desired level of hydrogen content in the dielectric layer 17. Also, to form a strong direct bond, the deposition of the dielectric material can be designed to have a high enough quality of dielectric material for direct bonding.

[0022] Turning to FIG. 2B, the front side 15 of the semiconductor device 2 and the front side 14 of the carrier 8 can be prepared for direct bonding as described herein. In some embodiments, the front side 15 and / or the front side 14 can have a surface roughness of less than 15 Å (rms), less than 10 Å (rms), or less than 5 Å (rms). The semiconductor device 2 and the carrier 8 can be bonded at room temperature. The prepared bonding surfaces can form a direct non-conductive bond along the bonding interface 7. Advantageously, the direct bonding interface 7 can provide a strong bond between the devices 2, 3 such that the bond between the semiconductor device 2 and the carrier 8 is strong enough to inhibit lateral growth of the device wafer. After the first device 2 is directly bonded to the carrier 8, the device portion 5 can be thinned to form a thin backside 16'. The thinned first device 2 of FIG. 2B can have any suitable thickness. Backside processing can be performed to process the backside 16' of the semiconductor device 2 to form one or more conductive features and prepare the backside for direct bonding or solder interconnection. For example, if TSVs (not shown) are included in element 2, a dielectric layer can be deposited on backside 16'. The TSVs can be exposed and the dielectric layer can be planarized to sub-nm roughness for direct bonding and processed using an appropriate material stack that covers the TSVs for solder interconnects. Backside features such as redistribution layers, etched features, and power distribution network can be fabricated on backside 16' before peeling element 3. The bonding surfaces (frontside 15 and / or frontside 14) have sub-nm roughness before bonding, and thickness variations during backside processing can be minimized since the bonding interface thickness is close to zero. The TTV in this case is primarily affected by the grinding process, not the temporary bonding process. For example, after thinning, the first element 2 can have a thickness of less than 100 microns, less than 50 microns, or less than 35 microns. For example, the thinned first element element 2 may have a thickness in the range of 5 microns to 50 microns, in the range of 25 microns to 250 microns, in the range of 30 microns to 250 microns, in the range of 35 microns to 250 microns, or in the range of 35 microns to 100 microns.

[0023] After processing the first semiconductor element 2, it can be directly bonded to other semiconductor device elements (not shown) before removing the carrier. In this case, the carrier 8 can constrain the lateral growth of the first semiconductor element 2 to allow for precise alignment of the first semiconductor element 2 with the mating device element. The carrier 8 can provide mechanical support to prevent or reduce potential damage to the thinned first semiconductor element 2 during preparation and bonding. This is particularly important for dies with thicknesses of less than 50 μm. This bonding process can lock precisely aligned features in place. Any suitable number of semiconductor elements can be stacked and directly bonded to each other while still supported by the carrier 8. The carrier 8 can then be removed. Removing the carrier 8 after the first semiconductor element 2 is aligned with the other device elements can prevent or reduce misalignment of already bonded devices.

[0024] Alternatively, the carrier 8 can be removed in a removal process after processing the first semiconductor element 2. For example, after thinning and / or backside metallization (or other processes), the carrier 8 can be removed to allow the semiconductor element 2 to undergo subsequent processes, such as bonding to other semiconductor device elements. Removing the carrier 8 at this point may allow the thinned element 2 to extend laterally freely. For relatively large dies with very fine bonding pitch applications, appropriate dimensional compensation can be applied to accurately align the element 2 to other semiconductor elements having various thicknesses. For example, the dimensional compensation techniques disclosed throughout U.S. Patent Application Publication No. 2021 / 0296282, filed March 19, 2021, which is incorporated herein by reference in its entirety for all purposes, can be used to improve alignment.

[0025] In FIG. 2C, light 11 can be irradiated onto the back surface 13 of the carrier 8. The light 11 can include a wavelength at which the bulk portion 6 of the carrier 8 is transparent. The light can pass through the bulk portion 6 and can interact with the LTH conversion layer 9. The LTH conversion layer 9 can have a high absorption coefficient for the wavelength of the light 11, such that the material of the layer 9 heats up when exposed to the light 11. In some embodiments, the LTH conversion layer 9 can be opaque or substantially opaque to the light 11 such that the light 11 does not pass through the layer 9 and impinge on the metal in the first semiconductor device 2. In various embodiments, the light 11 can include infrared (IR) radiation. For example, the light 11 can have a wavelength in the range of 800 nm to 1400 nm, in the range of 800 nm to 1200 nm, or in the range of 800 nm to 1100 nm, for example, about 1064 nm in one embodiment. Any suitable material having a high absorption coefficient at the wavelength of the light 11 can be used. For example, layer 9 can include silicon (e.g., microcrystalline silicon) or a metal (e.g., copper, aluminum, titanium, or titanium nitride) that has a high absorption coefficient for IR wavelengths. Layer 9 can also have good adhesion with dielectric layer 17 to ensure separation at bond interface 7 and not at the interface between dielectric layer 17 and LTH layer 9. In various embodiments, titanium or titanium nitride can be used. In various embodiments, a laser can be used to irradiate carrier 8 with light 11, for example, with multiple laser pulses.

[0026] Moving to FIG. 2D, the LTH layer 9 can absorb the light 11 incident on the carrier 8 and convert the light energy into thermal energy transferable to the dielectric layer 17. The thermal energy can heat the dielectric layer 17 and increase its temperature, which can cause degassing of trapped chemical species or gases. Gas bubbles 12 can form between the device portion 5 and the bulk portion 6. As described herein, the degassed bubbles 12 can include gases dissolved in the dielectric layer 17, such as hydrogen gas, argon gas, residual gas precursor elements from the dielectric material deposition process, and / or water vapor. The bubbles 12 can weaken the bond between the semiconductor element 2 and the carrier 8 and achieve removal of the carrier 8 from the semiconductor element 2. In this manner, as shown in FIG. 2D, a laser pulse of light 11 can cause localized absorption of light, which can be converted into heat and result in degassing through the bubbles 12. Gas bubbles 12 in dielectric layer 17 can form areas of weakness in, at, or near dielectric layer 17 that can cause carrier 8 (e.g., bulk portion 6) to delaminate and separate from first element 2. Diffusion barrier layer 10 can prevent or block gas bubbles 12 from diffusing into device region 5 and interacting with active circuitry.

[0027] In FIG. 2E, the laser can be scanned across the width of the carrier 8, e.g., across a wafer or die. Scanning the light 11 across the carrier 8 can create sufficient voids across the width (e.g., across the bonding interface 7) for the carrier 8 to peel from the first element 2. For example, as shown in FIG. 2E, in some embodiments, the carrier 8 (including the dielectric layer 17, the LTH conversion layer 9, and the bulk portion 6) is removed from the first semiconductor element 2, as peeling can occur along the bonding interface 7. In some embodiments, after removal, the front side 15 of the first element 2 can be processed to remove residues from the carrier 8 and / or prepare the first non-conductive bonding material 4a for subsequent direct bonding, e.g., to another semiconductor element (not shown). For example, the front side 15 can be etched and / or planarized (e.g., using a post-removal CMP process) after removal of the carrier. In some embodiments, after removal of the carrier 8, the first element 2 (which can be in wafer form) can be singulated into multiple device dies. In other embodiments, the first element 2 and carrier 8 may be singulated prior to removing the carrier 8.

[0028] After the first element 2 is separated from the carrier 8, the thinned and processed first element 2 can be directly bonded to other semiconductor elements to form a microelectronic device. In some embodiments, the first semiconductor element 2 can have an identifying characteristic indicative of the carrier removal process. For example, in some configurations, the non-conductive bonding material 4a of the first element 2 can include diffused gas. As mentioned above, the diffusion barrier layer 10 can prevent gas from diffusing into the device region 5 and adversely affecting the active circuitry, but the non-conductive bonding material 4a can still include residues or traces of the diffused gas. In some embodiments, the non-conductive bonding material 4a can include a higher content of a particular gas (diffusion gas) than the device region 5. In various embodiments, the diffusion gas can include at least one of hydrogen gas (H2), argon, and water vapor. However, in some embodiments, subsequent annealing (e.g., when bonding opposing contact pads) can result in further outgassing or out-diffusion of chemical species.

[0029] It should be appreciated that in various embodiments, the dielectric layer 17 may be provided elsewhere in the bonding structure 1. For example, while in the embodiment of Figures 2A-2E the dielectric layer 17 functions as the bonding layer 4b in the carrier 8, in other embodiments the dielectric layer 17 may be located below the bonding layer 4b. In still other embodiments the dielectric layer 17 may be located above the first semiconductor element 2, for example the dielectric layer may function as the first bonding material 4a or may comprise a dielectric layer between the first bonding material 4a and the diffusion barrier layer 10. Those skilled in the art will appreciate that other configurations may be suitable for positioning the dielectric layer 17 between the device portion 5 of the first semiconductor element 2 and the bulk portion 6 of the carrier 8.

[0030] As mentioned above, in the embodiment shown in Figures 2A to 2E, an LTH conversion layer 9 can be provided on the second device 3 to convert light to heat, thereby generating bubbles that remove the carrier 8 from the first device element 2. However, as described above in connection with Figure 2A, in other embodiments, there may be no intervening LTH conversion layer. Rather, as described above, a dielectric layer 17 can be provided on the bulk portion 6 (and / or on other build-up layers) without an intervening LTH conversion layer. In such an embodiment, the bonded structure 1 can be heated, for example, placed in an oven, to a temperature above room temperature by an amount sufficient to generate bubbles 12. The thermal energy transferred by the heating can form bubbles between the device portion 5 and the bulk portion 6. The bubbles 12 can weaken the bond between the semiconductor device 2 and the carrier 8, and can achieve removal of the carrier 8 from the semiconductor device 2.

[0031] FIG. 3 is a flow diagram illustrating a method for bonding and debonding a semiconductor device and a carrier. In step 22, the semiconductor device and carrier can be directly bonded to each other. In step 24, the semiconductor device can be processed. After thinning, backside processing can be performed to add features and prepare the backside for direct bonding or solder interconnect. For example, if TSVs are included in the semiconductor device 2, a dielectric layer can be deposited on the backside of the semiconductor device 2. The TSVs can be exposed and planarized to sub-nm roughness for direct bonding and prepared using an appropriate material stack for solder interconnect. Backside features such as redistribution layers, etched features, and power distribution circuitry can be fabricated on the backside before debonding the device 3. In step 26, at least the dielectric layer of the carrier can be heated to induce gas diffusion from the dielectric layer. For example, light can be incident on a light-to-heat (LTH) conversion layer through the transparent carrier of the carrier to generate thermal energy, which heats the dielectric layer and induces gas release and diffusion. In step 28, the semiconductor device can be removed from the carrier.

[0032] In one embodiment, a bonding method is disclosed that includes directly bonding a first non-conductive bonding material of a semiconductor device to a second non-conductive bonding material of a carrier without an adhesive, where the first non-conductive bonding material is disposed on a device portion of the semiconductor device and the second non-conductive bonding material is disposed on a bulk portion of the carrier, with a deposited dielectric layer disposed between the device portion and the bulk portion, and removing the carrier from the semiconductor device by transferring thermal energy to the dielectric layer to induce gas diffusion from the dielectric layer.

[0033] In some embodiments, the deposited dielectric layer comprises a porous dielectric material. In some embodiments, the second non-conductive bonding material of the carrier comprises a dielectric layer. In some embodiments, the transferring of thermal energy comprises heating the directly bonded carrier and semiconductor device. In some embodiments, the heating forms bubbles between the device portion and the bulk portion, which weaken the bond between the semiconductor device and the carrier to effect removal of the carrier from the semiconductor device. In some embodiments, an inorganic light-to-heat (LTH) conversion layer is disposed between the bulk portion of the carrier and the dielectric layer, the LTH conversion layer configured to convert light into thermal energy, and the transferring of thermal energy comprises irradiating the LTH conversion layer with light. In some embodiments, irradiating the LTH conversion layer heats the dielectric layer to form bubbles between the device portion and the bulk portion, which weaken the bond between the semiconductor device and the carrier to effect removal of the carrier from the semiconductor device. In some embodiments, the irradiating of the LTH conversion layer with light comprises irradiating the LTH conversion layer with infrared (IR) radiation. In some embodiments, illuminating the LTH conversion layer with light includes illuminating the LTH conversion layer with a laser. In some embodiments, illuminating the LTH conversion layer with a laser includes scanning a laser across a width of the carrier. In some embodiments, the carrier has a front surface and a back surface opposite the front surface, the second non-conductive bonding material at least partially defines the front surface, and illuminating the LTH conversion layer with light includes illuminating the back surface of the carrier with light. In some embodiments, the LTH conversion layer includes a metal. In some embodiments, the metal includes at least one of copper, aluminum, titanium, and titanium nitride. In some embodiments, the LTH conversion layer includes microcrystalline silicon (μc-Si). In some embodiments, the method can include depositing a dielectric layer on a bulk portion of the carrier. In some embodiments, the method can include depositing a light-to-thermal (LTH) conversion layer on a bulk portion of the carrier and depositing a dielectric layer on the LTH conversion layer. In some embodiments, depositing the dielectric layer comprises blanket depositing the dielectric layer over the LTH conversion layer, and depositing the LTH conversion layer includes blanket depositing the LTH conversion layer over the bulk portion.In some embodiments, the method may include providing one or more impurity species during the depositing step to increase gas permeability of the dielectric layer. In some embodiments, providing one or more impurity species includes providing at least one of carbon and nitrogen to the dielectric layer. In some embodiments, the dielectric layer includes silicon oxycarbonitride. In some embodiments, the method may include inducing diffusion of at least one of hydrogen gas (H2), argon, and water vapor from the dielectric layer. In some embodiments, the direct bonding is performed at room temperature. In some embodiments, the method may include activating at least one of the first and second non-conductive bonding materials prior to the direct bonding step. In some embodiments, the activating includes exposing at least one of the first and second non-conductive bonding materials to a nitrogen-containing plasma. In some embodiments, a diffusion barrier layer is disposed between the dielectric layer and circuitry in the device portion of the semiconductor device, the diffusion barrier layer having a lower gas permeability than the deposition layer. In some embodiments, the diffusion barrier layer includes silicon nitride. In some embodiments, the method can include thinning the backside of the semiconductor element after the direct bonding, i.e., the backside opposite the non-conductive bonding material. In some embodiments, the method can include directly bonding a second semiconductor element to the semiconductor element. In some embodiments, the removing step occurs after directly bonding the second semiconductor element to the semiconductor element. In some embodiments, the method can include singulating the semiconductor element into a plurality of singulated semiconductor elements after the removing step. In some embodiments, the method can include singulating the carrier and the semiconductor element into a plurality of bonded structures before the removing step.

[0034] In another embodiment, the carrier can include a bulk portion, a light-to-thermal (LTH) conversion layer on the bulk portion of the carrier, the light-to-thermal (LTH) conversion layer configured to convert light into thermal energy, and a dielectric layer on the LTH conversion layer, the dielectric layer including a deposition layer having sufficient permeability to allow gas diffusion out of the dielectric layer when heated.

[0035] In some embodiments, the dielectric layer comprises a porous inorganic dielectric material. In some embodiments, the LTH conversion layer is blanket deposited over the bulk portion and the dielectric layer is blanket deposited on the LTH conversion layer. In some embodiments, the bulk portion comprises at least one of glass and lightly doped silicon. In some embodiments, the LTH conversion layer comprises a metal. In some embodiments, the metal comprises at least one of copper, aluminum, titanium, and titanium nitride. In some embodiments, the LTH conversion layer comprises microcrystalline silicon (μc-Si). In some embodiments, the dielectric layer comprises silicon oxycarbonitride. In some embodiments, the dielectric layer comprises impurities added during its deposition. In some embodiments, the impurities comprise at least one of carbon and nitrogen. In some embodiments, the bonded structure can include a semiconductor device bonded directly to a carrier without an adhesive, with a non-conductive bonding material of the semiconductor device bonded directly to the dielectric layer. In some embodiments, a diffusion barrier layer can be disposed in or on the semiconductor device between the dielectric layer and the circuitry in the device portion of the semiconductor device, the diffusion barrier layer having a lower gas permeability than the deposited layer. In some embodiments, the diffusion barrier layer comprises silicon nitride. In some embodiments, the diffusion barrier layer is disposed between the non-conductive bonding material and the circuitry. In some embodiments, the non-conductive bonding material comprises a dielectric bonding layer.

[0036] In another embodiment, a semiconductor device can include a device portion including circuitry, a diffusion barrier layer blanket deposited over the device portion, the diffusion barrier layer having a sufficiently low permeability to prevent gas diffusion into the device portion, and a non-conductive bonding material over the diffusion barrier layer such that the diffusion barrier layer is between the non-conductive bonding material and the device portion, the non-conductive bonding material having a planarized bonding surface prepared for direct bonding to a second semiconductor device.

[0037] In some embodiments, the diffusion barrier layer comprises silicon nitride. In some embodiments, the non-conductive bonding material comprises a dielectric bonding layer. In some embodiments, the non-conductive bonding material comprises a gas diffused therein. In some embodiments, the diffusion gas comprises at least one of hydrogen gas (H2), argon, and water vapor. In some embodiments, the bonding structure can include a second semiconductor element bonded directly to the semiconductor element without an intervening adhesive.

[0038] In one embodiment, a bonding method is disclosed. The bonding method can include directly bonding a first non-conductive bonding material of a semiconductor device to a second non-conductive bonding material of a carrier without an intervening adhesive. The first non-conductive material is disposed on a device portion of the semiconductor device. The second non-conductive bonding material is disposed on a bulk portion of the carrier. A deposited dielectric layer is disposed between the device portion and the bulk portion. The bonding method can include removing the carrier from the semiconductor device by transferring thermal energy to the dielectric layer to induce gas diffusion from the dielectric layer.

[0039] In one embodiment, the deposited dielectric layer comprises a porous dielectric material.

[0040] In one embodiment, the second non-conductive bonding material of the carrier comprises a dielectric layer.

[0041] In one embodiment, transferring thermal energy includes heating the directly bonded carrier and semiconductor device, which can form bubbles between the device portion and the bulk portion, which can weaken the bond between the semiconductor device and the carrier and effect removal of the carrier from the semiconductor device.

[0042] In one embodiment, an inorganic light-to-thermal (LTH) conversion layer is disposed between the bulk portion of the carrier and the dielectric layer. The LTH conversion layer can be configured to convert light into thermal energy. The transferring of thermal energy can include irradiating the LTH conversion layer with light. The irradiating the LTH conversion layer can heat the dielectric layer to form bubbles between the device portion and the bulk portion. The bubbles can weaken the bond between the semiconductor device and the carrier to effect removal of the carrier from the semiconductor device. The irradiating the LTH conversion layer with light can include irradiating the LTH conversion layer with infrared (IR) radiation. The irradiating the LTH conversion layer with light can include irradiating the LTH conversion layer with a laser. The irradiating the LTH conversion layer with a laser can include scanning the laser across the width of the carrier. The carrier can have a front surface and a back surface opposite the front surface. A second non-conductive bonding material can at least partially define the front surface. The irradiating the LTH conversion layer with light can include irradiating the back surface of the carrier with light. The LTH conversion layer can include a metal, the metal including at least one of copper, aluminum, titanium, and titanium nitride. The LTH conversion layer can include microcrystalline silicon (μc-Si).

[0043] In one embodiment, the bonding method further comprises depositing a dielectric layer on the bulk portion of the carrier.

[0044] In one embodiment, the bonding method further includes depositing a light-to-thermal (LTH) conversion layer on the bulk portion of the carrier and depositing a dielectric layer on the LTH conversion layer. Depositing the dielectric layer can include blanket depositing the dielectric layer over the LTH conversion layer. Depositing the LTH conversion layer can include blanket depositing the LTH conversion layer over the bulk portion.

[0045] In one embodiment, the bonding method further comprises providing one or more impurity species during the depositing step to enhance gas permeability of the dielectric layer. Providing one or more impurity species may comprise providing at least one of carbon and nitrogen in the dielectric layer. The dielectric layer may comprise silicon oxycarbonitride.

[0046] In one embodiment, the bonding method further includes diffusing at least one of hydrogen gas (H2), argon, and water vapor from the dielectric layer.

[0047] In one embodiment, the direct bonding step is performed at room temperature.

[0048] In one embodiment, the bonding method further includes activating at least one of the first and second non-conductive bonding materials prior to the direct bonding step. The activating step can include exposing at least one of the first and second non-conductive bonding materials to a nitrogen-containing plasma.

[0049] In one embodiment, a diffusion barrier layer is disposed between the dielectric layer and the circuitry in the device portion of the semiconductor device. The diffusion barrier layer may have a lower gas permeability than the deposition layer. The diffusion barrier layer may include silicon nitride.

[0050] In one embodiment, the bonding method further comprises thinning the backside of the semiconductor element after the direct bonding step, i.e., the backside opposite the non-conductive bonding material. The bonding method may further comprise forming a conductive structure at or near the backside of the semiconductor element after the direct bonding step. The bonding method may further comprise directly bonding a second semiconductor element to the backside of the semiconductor element. The removing step is performed after directly bonding the second semiconductor element to the semiconductor element.

[0051] In one embodiment, the bonding method further includes singulating the semiconductor device after the removing step into a plurality of singulated semiconductor devices.

[0052] In one embodiment, the bonding method further comprises singulating the carrier and the semiconductor device into a plurality of bonded structures prior to the removing step.

[0053] In one aspect, a carrier is disclosed. The carrier can include a bulk portion, a light-to-thermal (LTH) conversion layer on the bulk portion of the carrier, and a dielectric layer on the LTH conversion layer. The LTH conversion layer is configured to convert light into thermal energy. The dielectric layer includes a stacking layer. The stacking layer has sufficient permeability to allow gas diffusion out of the dielectric layer when heated.

[0054] In one embodiment, the dielectric layer comprises a porous inorganic dielectric material.

[0055] In one embodiment, the LTH conversion layer is blanket deposited over the bulk portion and the dielectric layer is blanket deposited over the LTH conversion layer.

[0056] In one embodiment, the bulk portion includes at least one of glass and lightly doped silicon.

[0057] In one embodiment, the LTH conversion layer comprises a metal.

[0058] In one embodiment, the metal includes at least one of copper, aluminum, titanium, and titanium nitride.

[0059] In one embodiment, the LTH conversion layer comprises microcrystalline silicon (μc-Si).

[0060] In one embodiment, the dielectric layer comprises silicon oxycarbonitride.

[0061] In one embodiment, the dielectric layer includes impurities added during its deposition, the impurities including at least one of carbon and nitrogen.

[0062] In one embodiment, the bonding structure includes a semiconductor device bonded directly to the carrier without an intervening adhesive. The non-conductive bonding material of the semiconductor device is bonded directly to the dielectric layer. It may further include a diffusion barrier layer disposed within or on the semiconductor device between the dielectric layer and the circuitry in the device portion of the semiconductor device. The diffusion barrier layer may have a lower gas permeability than the deposition layer. The diffusion barrier layer may include silicon nitride. The diffusion barrier layer may be disposed between the non-conductive bonding material and the circuitry. The non-conductive bonding material includes a dielectric bonding layer.

[0063] In one aspect, a semiconductor device is disclosed. The semiconductor device can include a device portion including circuitry, a diffusion barrier layer blanket deposited over the device portion, and a non-conductive bonding material over the diffusion barrier layer such that the diffusion barrier layer is between the non-conductive bonding material and the device portion. The diffusion barrier layer is configured to reduce or prevent gas diffusion into the device portion. The non-conductive bonding material has a planarized bonding surface prepared for direct bonding to a second semiconductor device.

[0064] In one embodiment, the diffusion barrier layer includes a hydrogen barrier layer. The diffusion barrier layer can have a density in the range of 2.75 g / cc to 5 g / cc. The diffusion barrier layer can have a density greater than the density of the non-conductive bonding material. The diffusion barrier layer can have a density greater than the density of the device portion.

[0065] In one embodiment, the non-conductive bonding material comprises a dielectric bonding layer.

[0066] In one embodiment, the non-conductive bonding material includes a gas diffused therein. The diffused gas can include at least one of hydrogen gas (H2), argon, and water vapor.

[0067] In one embodiment, the bonding structure includes a second semiconductor element bonded directly to the semiconductor element without an intervening adhesive.

[0068] Unless the context clearly indicates otherwise, the words "comprises," "comprising," "including," "including," and the like throughout this specification and claims are to be construed in an inclusive sense, i.e., "including but not limited to," as opposed to a restrictive or inclusive sense. As used generally herein, the word "coupled" refers to two or more elements that are either directly connected or connected through one or more intermediate elements. Similarly, as used generally herein, the word "connected" refers to two or more elements that are either directly connected or connected through one or more intermediate elements. In addition, the words "herein," "above," "below," and words of similar import, when used in this application, refer to this application as a whole and not to any particular portion of this application. Furthermore, as used herein, when a first element is described as being "on" or "over" a second element, the first element can be directly on or over the second element such that the first and second elements are in direct contact, or the first element can be indirectly on or over the second element such that there are one or more intervening elements between the first and second elements. Where the context permits, words using the singular or plural in the above detailed description can also include the plural or singular, respectively. The word "or" in connection with a list of two or more items covers all of the following interpretations for that word: any of the items in the list, all of the items in the list, and any and all combinations of the items in the list.

[0069] Additionally, conditional language used herein, such as, among others, "may," "could," "could," "may," "for example," "for example," and "such as," are generally intended to convey that certain embodiments include particular features, elements, and / or conditions, while other embodiments do not, unless specifically stated otherwise or understood otherwise within the context in which they are used. Thus, such conditional language is generally not intended to imply that a feature, element, and / or condition is in any way required for one or more embodiments.

[0070] Although certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in different other forms, and various omissions, substitutions, and modifications may be made to the forms of the methods and systems described herein without departing from the spirit of the present disclosure. For example, although blocks are presented in a given arrangement, alternative embodiments may perform similar functions using different components and / or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of the elements and operations of the various embodiments described above may provide further embodiments. The claims and their equivalents are intended to cover such forms or modifications as fall within the scope and spirit of the present disclosure.

Claims

1. directly bonding a first non-conductive bonding material of a semiconductor device to a second non-conductive bonding material of a carrier without an adhesive along a bonding interface, the first non-conductive bonding material being disposed on a device portion of the semiconductor device, the second non-conductive bonding material being disposed on a bulk portion of the carrier, a deposited dielectric layer being disposed between the device portion and the bulk portion, and an inorganic light-to-thermal (LTH) conversion layer being disposed between the bulk portion of the carrier and the dielectric layer; separating the carrier from the semiconductor device by irradiating the LTH conversion layer, the LTH conversion layer configured to convert light into thermal energy to weaken a bond between the first non-conductive bonding material and the second non-conductive bonding material; A bonding method comprising:

2. The bonding method of claim 1 , wherein the deposited dielectric layer comprises a porous dielectric material.

3. The bonding method of claim 1 , wherein the second non-conductive bonding material of the carrier comprises the dielectric layer.

4. A bonding method as described in claim 1, inducing gas diffusion from the dielectric layer by converting light into thermal energy.

5. 5. The bonding method of claim 4, further comprising inducing gas diffusion from the dielectric layer to form bubbles between the device portion and the bulk portion, the bubbles weakening the bond between the first non-conductive bonding material and the second non-conductive bonding material to achieve the separation of the carrier from the semiconductor device.

6. The bonding method of claim 1 , wherein irradiating the LTH conversion layer with light comprises irradiating the LTH conversion layer with infrared (IR) radiation.

7. The bonding method of claim 1 , wherein the step of irradiating the LTH conversion layer with light includes the step of irradiating the LTH conversion layer with a laser.

8. The method of claim 7 , wherein irradiating the LTH conversion layer with the laser comprises scanning the laser across a width of the carrier.

9. the carrier has a front surface and a back surface opposite the front surface, the second non-conductive bonding material at least partially defining the front surface; illuminating the LTH conversion layer with light includes illuminating the back surface of the carrier with the light. The joining method according to claim 1 .

10. The bonding method of claim 1 , wherein the LTH conversion layer comprises a metal.

11. The bonding method of claim 10 , wherein the metal comprises at least one of copper, aluminum, titanium, and titanium nitride.

12. The bonding method of claim 1 , wherein the LTH conversion layer comprises microcrystalline silicon (μc-Si).

13. The bonding method of claim 1 further comprising depositing the dielectric layer over the bulk portion of the carrier.

14. The bonding method of claim 13 , wherein the LTH conversion layer is deposited on the bulk portion of the carrier, and the dielectric layer is deposited on the LTH conversion layer.

15. depositing the dielectric layer includes blanket depositing the dielectric layer over the LTH conversion layer; depositing the LTH conversion layer includes blanket depositing the LTH conversion layer over the bulk portion. The bonding method according to claim 14.

16. 14. The method of claim 13, further comprising providing one or more impurity species to enhance gas permeability of the dielectric layer during the depositing step.

17. 20. The method of claim 16, wherein providing the one or more impurity species comprises providing the dielectric layer with at least one of carbon and nitrogen.

18. The bonding method of claim 13 , wherein the dielectric layer comprises silicon oxycarbonitride.

19. The step of inducing gas diffusion from the dielectric layer includes inducing hydrogen gas (H 2 5. The method of claim 4, further comprising inducing diffusion of at least one of the following: oxygen, argon, and water vapor.

20. The method of claim 1 , wherein the direct bonding step is performed at room temperature.

21. The method of claim 1 further comprising the step of activating at least one of the first and second non-conductive bonding materials prior to the step of directly bonding.

22. 22. The method of claim 21, wherein activating comprises exposing at least one of the first and second non-conductive bonding materials to a nitrogen-containing plasma.

23. 2. The bonding method of claim 1, wherein a diffusion barrier layer having a lower permeability to the gas than the deposited layer is disposed between the dielectric layer and circuitry in the device portion of the semiconductor device.

24. The bonding method of claim 23 , wherein the diffusion barrier layer comprises silicon nitride.

25. 2. The bonding method of claim 1, further comprising the step of thinning a backside of the semiconductor element opposite the first non-conductive bonding material after the direct bonding step.

26. 26. The method of claim 25, further comprising forming a conductive structure at or near the backside of the semiconductor element after the direct bonding step.

27. 26. The method of claim 25, further comprising directly bonding a second semiconductor element to the backside of the semiconductor element.

28. 28. The method of claim 27, wherein the step of separating occurs after the step of directly bonding the second semiconductor element to the semiconductor element.

29. The bonding method of claim 1 , further comprising the step of singulating the semiconductor device into a plurality of singulated semiconductor devices after the separating step.

30. The bonding method of claim 1 , further comprising the step of singulating the carrier and the semiconductor device into a plurality of bonded structures prior to the separating step.

31. A carrier comprising: A bulk portion; a light-to-heat (LTH) conversion layer on the bulk portion of the carrier, the light-to-heat (LTH) conversion layer configured to convert light into thermal energy; a dielectric layer on the LTH conversion layer, the dielectric layer comprising a deposition layer having sufficient permeability to permit diffusion of gas out of the dielectric layer when heated; A carrier comprising:

32. The carrier of claim 31 , wherein the dielectric layer comprises a porous inorganic dielectric material.

33. 32. The carrier of claim 31, wherein the LTH conversion layer is blanket deposited over the bulk portion and the dielectric layer is blanket deposited over the LTH conversion layer.

34. 32. The carrier of claim 31, wherein the bulk portion comprises at least one of glass and lightly doped silicon.

35. 32. The carrier of claim 31 , wherein the LTH conversion layer comprises a metal.

36. 36. The carrier of claim 35, wherein the metal comprises at least one of copper, aluminum, titanium, and titanium nitride.

37. 32. The carrier of claim 31, wherein the LTH conversion layer comprises microcrystalline silicon (μc-Si).

38. 32. The carrier of claim 31 , wherein the dielectric layer comprises silicon oxycarbonitride.

39. 32. The carrier of claim 31, wherein the dielectric layer includes impurities added during deposition of the dielectric layer.

40. 40. The support of claim 39, wherein the impurities include at least one of carbon and nitrogen.

41. A joining structure, A semiconductor element directly bonded to the carrier according to claim 31 without the use of an adhesive; a non-conductive bonding material of the semiconductor element is bonded directly to the dielectric layer; Joint structure.

42. 42. The bond structure of claim 41, further comprising a diffusion barrier layer disposed in or on the semiconductor element between the dielectric layer and circuitry in a device portion of the semiconductor element, the diffusion barrier layer having a lower permeability to the gas than the deposition layer.

43. 43. The bond of claim 42, wherein the diffusion barrier layer comprises silicon nitride.

44. 43. The bonding structure of claim 42, wherein the diffusion barrier layer is disposed between the non-conductive bonding material and the circuitry.

45. 43. The bonded structure of claim 42, wherein the non-conductive bonding material comprises a dielectric bonding layer.

46. a device portion including a circuit; a diffusion barrier layer blanket deposited over the device portion, the diffusion barrier layer configured to reduce or prevent diffusion of gas into the device portion; a non-conductive bonding material across the diffusion barrier layer, the diffusion barrier layer being between the non-conductive bonding material and the device portion; the non-conductive bonding material having a planarized bonding surface prepared for direct bonding to a second semiconductor device; Semiconductor element.

47. 47. The semiconductor device of claim 46, wherein the diffusion barrier layer comprises a hydrogen barrier layer.

48. 48. The semiconductor device of claim 47, wherein the diffusion barrier layer has a density in the range of 2.75 g / cc to 5 g / cc.

49. 48. The semiconductor device of claim 47, wherein the diffusion barrier layer has a density greater than a density of the non-conductive bonding material.

50. 48. The semiconductor device of claim 47, wherein the diffusion barrier layer has a density greater than a density of the device portion.

51. 47. The semiconductor device of claim 46, wherein the non-conductive bonding material comprises a dielectric bonding layer.

52. 47. The semiconductor device of claim 46, wherein the non-conductive bonding material comprises a gas diffused within the non-conductive bonding material.

53. The diffused gas is hydrogen gas (H 2 53. The semiconductor device of claim 52, comprising at least one of the following: nitrogen, argon, and water vapor.

54. A second semiconductor element bonded directly to the semiconductor element of claim 46 without the use of an adhesive. A joint structure comprising:

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