Microelectronics package assembly and fabrication method

Abstract

A microelectronic package assembly and method of making the same are disclosed. The flange has a top surface and a first coating disposed on the top surface of the flange. The insulator has a bottom surface for mounting to the flange and a top surface opposite the bottom surface. A second coating is disposed on the bottom surface of the insulator and a third coating is disposed on the top surface of the insulator. The first coating, the second coating, and the third coating each have a thickness of 1 micron or less. At least one of the first coating, the second coating, and the third coating are applied by at least one of physical vapor deposition, atomic deposition, or chemical deposition.

Description

[Technical field]

[0001] Priority

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 185,768, filed May 7, 2021, which is incorporated herein by reference. Field

[0002] FIELD OF THE DISCLOSURE The present disclosure relates to microelectronics package assemblies and processing methods for making package assemblies for high heat dissipation applications such as high frequency radio frequency transistors. [Background technology]

[0002]

[0003] Radio frequency package assemblies with cavities to accommodate die attach materials are used for Si LDMOS (Laterally Diffused Metal Oxide) transistors, Doherty amplifiers, GaAs FETs, GaAs MMICs, GaN FETs, and GaN MMICs. These packages contain heat spreading or conducting devices that can transmit RF signals by leads. Such packages can be used to mount RF light emitting transistors and resistors for radio wave applications for telecommunications.

[0003]

[0004] Semiconductor dies, especially Gallium Nitride (GaN), have evolved with much higher power densities than previous transistor technologies. Higher power density generates more heat in a smaller area due to internal dissipation. The smaller dissipation area reduces the cross-sectional area of ​​the heat dissipation path, thereby increasing the junction temperature. Junction temperature is determined by power dissipation multiplied by thermal impedance.

[0004]

[0005] The performance of radio frequency integrated circuits can be dramatically affected by the packaging environment. The ever-changing and increasing demands for high speed digital and radio frequency applications require die attach packaging that considers RF performance in addition to mechanical concerns. The packaging must be able to withstand the maximum junction operating temperature for reliable operation.

[0005]

[0006] However, conventional package assemblies produced have relatively poor heat dissipation characteristics and limited RF signal strength and power output. Furthermore, conventional package assemblies include more processing steps and exhibit low yields due to processing limitations such as outgassing during plating steps that introduce organics, which can result in lower RF performance than required for some applications, e.g., 5G applications. Organics during processing adversely affect the sheer strength between components, e.g., between flanges and insulators.

[0006]

[0007] Although methods for fabricating package assemblies are available, a need exists for package assemblies and methods for fabricating same that improve shear strength, RF performance, and yield while providing high heat dissipation and high frequency. Summary of the Invention

[0007]

[0008] In one embodiment, the present disclosure relates to a microelectronic package assembly. The assembly includes a flange having a top surface, and a first coating disposed on the top surface of the flange. The assembly includes an insulator for partially enclosing a die, the insulator having a bottom surface for mounting to the flange and a top surface opposite the bottom surface, a second coating disposed on the bottom surface of the insulator, and a third coating disposed on the top surface of the insulator. The first coating, the second coating, and the third coating each have a thickness of 1 micron or less. At least one of the first coating, the second coating, and the third coating is applied by at least one of physical vapor deposition, atomic deposition, or chemical deposition. In one embodiment, the microelectronic package assembly is useful for (GaN) RF power transistors delivering greater than 5 W at frequencies between 2 and 10 GHz. The microelectronic package assembly herein is also useful for 5G wireless amplifiers operating at ultra-high frequencies, e.g., greater than 3 GHz.

[0008]

[0009] At least one of the first coating, the second coating, and the third coating can include titanium, copper, alloys thereof, sublayers thereof, or combinations thereof. Each of the first coating, the second coating, and the third coating can be free of nickel.

[0009]

[0010] The insulator may include sapphire, alumina (Al2O3), beryllia (BeO), aluminum nitride (AlN), zirconia toughened alumina (ZTA), silicon carbide (SiC), magnesium silicon carbide (Mg-SiC), silicon nitride (Si3N4), or combinations thereof. In some embodiments, the insulator is alumina (Al2O3) having a purity of 96% or greater. The insulator may include a plurality of through holes (or vias) through the thickness of the insulator. A braze layer to the top surface of the insulator can penetrate the through holes to bond the insulator to the flange.

[0010]

[0011] The flange may be a highly thermally conductive material having a thermal conductivity in the range of 140 to 2000 W / (mK) at room temperature and a coefficient of thermal expansion (CTE) in the range of 2.3 ppm / K to 17.5 ppm / K. The flange may include a diamond-based composite, Cu-CuMo-Cu (CPC), copper tungsten (CuW), Cu-Mo-Cu (CMC), Cu, or combinations thereof.

[0011]

[0012] The microelectronic package assembly may further include a first conductive alloy preform for bonding the insulator to the flange. The first conductive alloy preform contacts the first coating and the second coating. The microelectronic package assembly may further include one or more leads, at least one of the one or more leads having a width of 0.35 microns or less. The microelectronic package assembly may further include a second conductive alloy preform for bonding the one or more leads to the insulator, the second conductive alloy preform contacts the third coating and the one or more leads. At least one of the first and second conductive alloy preforms is a silver-copper (Ag-Cu) alloy or a gold-tin (Au-Sn) alloy.

[0012]

[0013] The one or more leads may include at least one of an alloy having a chemical composition of 30 wt% to 80 wt% nickel (Ni) and balance iron (Fe), a thermal conductivity in the range of 9.5 W / (mK) to 11.5 W / (mK), and a spacing distance between at least two of the one or more leads of 0.35 microns or less.

[0013]

[0014] The microelectronic package assembly may further include a cover forming a cavity with the insulator to partially surround the die. The cover may be alumina (Al2O3), aluminum nitride (AlN), liquid crystal polymer (LCP), or a combination thereof.

[0014]

[0015] In another embodiment, a method for making a microelectronic package assembly is disclosed. The method includes depositing a first coating having a thickness of 1 micron or less on opposing surfaces of a flange and an insulator, the flange being a highly thermally conductive material having a thermal conductivity in the range of 140-2000 W / (mK) at room temperature and a coefficient of thermal expansion (CTE) in the range of 2.3 ppm / K to 17.5 ppm / K. The method includes positioning a first conductive alloy preform between the flange and the coated surface of the insulator. The method includes depositing a second coating on at least a portion of a top surface of the insulator to a thickness of 1 micron or less to form an at least partially coated top surface. The method includes directly bonding one or more leads to the at least partially coated top surface using a second conductive alloy preform to enable the one or more leads to have a narrow width of 0.35 microns or less. The method includes bonding the first conductive preform to the insulator and flange and the second conductive preform to the insulator and leads at a temperature of 850° C. or greater. The step of depositing at least one of the first coating and the second coating includes physical vapor deposition, atomic deposition, or chemical deposition.

[0015]

[0016] The method includes that the first coating may include titanium, copper, an alloy thereof, a sublayer thereof, or a combination thereof, and the second coating includes titanium, copper, an alloy thereof, a sublayer thereof.

[0016]

[0017] The step of depositing at least one of the first coating and the second coating may include depositing two or more sublayers, where the first sublayer is titanium and the second sublayer is copper, and the first sublayer is between 15% and 35% of the total coating thickness and the second sublayer is between 65% and 85% of the total coating thickness.

[0017]

[0018] The method may further include attaching a cover to form the cavity of the die, the cover comprising a liquid crystal polymer, the cover being alumina (Al2O3), aluminum nitride (AlN), liquid crystal polymer (LCP), or a combination thereof.

[0018]

[0019] The method may further include forming a plurality of through holes through the thickness of the insulator prior to coating, and after depositing the second coating, the method includes brazing a layer to the top surface of the insulator so as to penetrate the through holes to bond the insulator to the flange.

[0019]

[0020] The method may further include wherein the step of depositing the second coating includes depositing over the entire top surface of the insulator, and further includes selectively laser ablating the second coating to form the circuitry.

[0020]

[0021] In another embodiment, the present disclosure relates to a microelectronic package assembly. The package assembly includes a flange, a first coating, an insulator, a second coating, and a conductive alloy preform. The flange has a top surface, the flange being a highly thermally conductive material having a thermal conductivity in the range of 140 to 2000 W / (mK) at room temperature and a coefficient of thermal expansion (CTE) in the range of 2.3 ppm / K to 17.5 ppm / K. The first coating is disposed on the top surface and has a thickness of 1 micron or less. The insulator is mounted partially surrounding the die, the insulator having a bottom surface. The second coating is disposed on the bottom surface of the insulator. The conductive alloy preform bonds the insulator to the flange. The conductive alloy preform contacts the first coating and the second coating.

[0021]

[0022] In another embodiment, a microelectronic package assembly includes a flange having an insulator mounted thereon. The insulator has a top surface. A first coating is disposed on the top surface of the insulator and has a thickness of 1 micron or less. The package assembly further includes one or more leads, at least one of the one or more leads having a width of 0.35 microns or less. A conductive alloy preform bonds the one or more leads to the insulator. The conductive alloy preform contacts the first coating and the one or more leads.

[0022]

[0023] In another embodiment, the present disclosure relates to a microelectronic package assembly. The package assembly includes a flange, a leadframe, and a cover. The flange includes an insulator and a die mounted thereon. The insulator may partially surround the die. The leadframe includes a plurality of leads surrounding the die on a surface of the insulator opposite the flange. The cover includes a liquid crystal polymer and forms a cavity for the die. The cover is adhered to the leadframe by a non-conductive adhesive.

[0023]

[0024] In yet another embodiment, a microelectronic package assembly includes a flange, a first coating, an insulator, a second coating, a first conductive alloy preform, a third coating, a lead frame, a second conductive alloy preform, and a cover. The flange has a top surface, and the flange is a highly thermally conductive material having a thermal conductivity in the range of 140 to 2000 W / (mK) at room temperature and a coefficient of thermal expansion (CTE) in the range of 2.3 ppm / K to 17.5 ppm / K. The first coating is disposed on the top surface of the flange and has a thickness of 1 micron or less. The insulator may be for mounting to partially surround the die. The insulator has a bottom surface and a top surface opposite the flange. The second coating is disposed on the bottom surface of the insulator and has a thickness of 1 micron or less. The first conductive alloy preform bonds the insulator to the flange. The conductive alloy preform contacts the first and second coatings. The third coating is disposed on a portion of the top surface of the insulator and has a thickness of 1 micron or less. The third coating may be the same as the second coating. The lead frame includes a plurality of leads configured to surround the die on the top surface of the insulator. A second conductive alloy preform bonds the lead frame to the insulator. The second conductive alloy preform contacts the third coating and the plurality of leads. The cover includes a liquid crystal polymer and forms a cavity for the die. The cover is adhered to the lead frame by a non-conductive adhesive.

[0024]

[0025] In one aspect, the present disclosure relates to a method for making a microelectronic package assembly, the method including depositing a coating having a thickness of 1 micron or less on opposing surfaces of a flange and an insulator, positioning a conductive alloy preform between the coated surfaces of the flange and the insulator, and bonding the conductive alloy preform to the flange and the insulator at a temperature of 850° C. or greater. The flange is a highly thermally conductive material with a thermal conductivity at room temperature in the range of 140-2000 W / (mK) and a coefficient of thermal expansion (CTE) in the range of 2.3 ppm / K to 17.5 ppm / K.

[0025]

[0026] In another aspect, a method for attaching leads to a microelectronic package assembly includes mounting an insulator to a flange, depositing a coating on a portion of a top surface of the insulator to a thickness of 1 micron or less, and bonding one or more leads directly to the coated top surface using a conductive alloy preform to enable the one or more leads to have a narrow width of 0.35 microns or less. The surface opposite the flange is the top surface of the insulator.

[0026]

[0027] In another aspect, the present disclosure relates to a method for covering a microelectronic package assembly, the method including the steps of attaching an insulator to a flange, forming a lead frame including a plurality of leads configured to surround a die on a surface of the insulator opposite the flange, and forming a cavity for the die by adhering a liquid crystal polymer cover to the lead frame with a non-conductive adhesive. The die may be attached to the flange or to the insulator.

[0027]

[0028] In yet another aspect, a method for making a microelectronic package assembly includes depositing a first coating having a thickness of 1 micron or less on opposing surfaces of a flange and an insulator. The flange is a highly thermally conductive material having a thermal conductivity in the range of 140-2000 W / (mK) at room temperature and a coefficient of thermal expansion (CTE) in the range of 2.3 ppm / K-17.5 ppm / K. The method includes positioning a first conductive alloy preform between the coated surfaces of the flange and the insulator. The method further includes depositing a second coating to a thickness of 1 micron or less on a portion of a top surface of the insulator to form a partially coated top surface, directly bonding one or more leads to the partially coated top surface using a second conductive alloy preform to enable the one or more leads to have a narrow width of 0.35 microns or less, and bonding the first conductive preform to the insulator and flange and the second conductive preform to the insulator and leads at a temperature of 850° C. or greater. The method may include attaching a cover comprising a liquid crystal polymer to form a cavity for the die. The cover is adhered to the lead frame by a non-conductive adhesive.

[0028]

[0029] In some embodiments, the flange is a highly thermally conductive material having a thermal conductivity in the range of 140-650 W / (mK) and a CTE in the range of 5.5 ppm / K to 17.5 ppm / K at room temperature. The flange may be a highly thermally conductive material having a thermal conductivity in the range of 140-400 W / (mK) and a CTE in the range of 5.5 ppm / K to 17.5 ppm / K at room temperature. The flange may be a highly thermally conductive material having a thermal conductivity in the range of 500-600 W / (mK) and a CTE in the range of 6.0 ppm / K to 10.5 ppm / K at room temperature.

[0029]

[0030] In some embodiments, the flange comprises a diamond-based composite, Cu-CuMo-Cu (CPC), copper-tungsten (CuW), Cu-Mo-Cu (CMC), Cu, or a combination thereof. The flange may comprise Cu-CuMo-Cu (CPC), copper-tungsten (CuW), Cu-Mo-Cu (CMC), Cu, or a combination thereof. The flange may comprise a copper-diamond composite or a silver-diamond composite.

[0030]

[0031] In some embodiments, at least one of the first and second coatings includes titanium, copper, alloys thereof, or combinations thereof. At least one of the first and second coatings may be applied by physical vapor deposition (PVD). The first and second coatings may be free of nickel.

[0031]

[0032] In some embodiments, at least one of the first and second conductive alloy preforms is a solder alloy. At least one of the first and second conductive alloy preforms may be a silver-copper (Ag-Cu) alloy or a gold-tin (Au-Sn) alloy.

[0032]

[0033] In some embodiments, the insulator comprises sapphire, alumina (Al2O3), beryllia (BeO), aluminum nitride (AlN), zirconia-toughened alumina (ZTA), silicon carbide (SiC), magnesium silicon carbide (Mg-SiC), silicon nitride (Si3N4), or a combination thereof. The insulator may comprise sapphire, alumina (Al2O3), aluminum nitride (AlN), or a combination thereof. The insulator may be alumina (Al2O3) having a purity of 96% or greater. The insulator may include a plurality of through holes penetrating a thickness of the insulator. The plurality of through holes may be configured in a pattern along a peripheral region of the insulator. The insulator may further include a nickel plate covering the coated bottom and top surfaces. The nickel plate may have a thickness of 1.0 to 3.5 microns.

[0033]

[0034] In some embodiments, the one or more leads include an alloy of iron, nickel, or a combination thereof. The one or more leads may include an alloy having a chemical composition of 30 wt% to 80 wt% nickel (Ni) and the balance iron (Fe). The one or more leads may have a thermal conductivity in the range of 9.5 W / (mK) to 11.5 W / (mK). At least two of the one or more leads may have a spacing distance of 0.35 microns or less.

[0034]

[0035] In some embodiments, the assembly further includes a cover for forming a cavity for the die. The cover may be alumina (Al2O3), aluminum nitride (AlN), liquid crystal polymer (LCP), or a combination thereof. The cover may include a non-conductive adhesive configured to provide a seal.

[0035]

[0036] In some embodiments, the assembly further includes a die, such as gallium nitride (GaN), gallium arsenide (GaAs), silicon (Si), or a combination thereof.

[0036]

[0037] In some aspects, the method includes depositing the coating comprises physical vapor deposition, atomic deposition, or chemical deposition. The depositing the coating may comprise physical vapor deposition. The depositing the coating may comprise deposition of two or more sublayers. The first sublayer may be titanium and the second sublayer may be copper. The first sublayer may be 15%-35% of the total coating thickness and the second sublayer may be 65%-85% of the total coating thickness. The method may further comprise attaching a die. The attaching the die may comprise welding the die with a gold-tin alloy.

[0037]

[0038] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings. [Brief description of the drawings]

[0038] [Figure 1]

[0039] 1 illustrates a perspective view of a microelectronic package assembly according to an embodiment herein. [Diagram 2]

[0040] 2 illustrates an exploded view of the microelectronic package assembly of FIG. 1; [Diagram 3]

[0041] 2 shows a cross-sectional view of the microelectronic package assembly taken along line "A" of FIG. 1. [Figure 4]

[0042] 2 illustrates a perspective view of the top of a flange of the microelectronic package assembly of FIG. 1. [Diagram 5]

[0043] 2 illustrates a cross-sectional view of a flange of the microelectronic package assembly of FIG. 1. [Figure 6]

[0044] 2 shows a perspective view of an insulator of the microelectronic package assembly of FIG. 1. [Figure 7]

[0045] FIG. 2 illustrates a bottom view of the insulator of the microelectronic packaging assembly of FIG. 1. [Figure 8]

[0046] 2 illustrates a cross-sectional view of an insulator of the microelectronic package assembly of FIG. 1. [Figure 9]

[0047] 1 illustrates a partial top view of another embodiment of an insulator showing through holes through the thickness of the insulator according to embodiments herein. [Figure 10]

[0048] 10 shows a perspective view of an insulator as in FIG. 9 including a through hole according to an embodiment herein. [Figure 11]

[0049] 1 illustrates a perspective view of a conductive alloy preform for bonding a flange to an insulator according to an embodiment herein. [Figure 12]

[0050] 1 illustrates a perspective view of a conductive alloy preform for attaching an insulator to a lead according to an embodiment herein. [Figure 13]

[0051] 1 illustrates a perspective view of a lead frame including multiple leads according to an embodiment herein. [Figure 14]

[0052] 1 illustrates a perspective view of a non-conductive adhesive for adhering an insulator to a cover according to an embodiment herein. [Figure 15]

[0053] 1 illustrates a perspective view of a cover of a microelectronic package assembly according to an embodiment herein. [Figure 16]

[0054] 1 illustrates a top view of a leadframe according to an embodiment herein. [Figure 17]

[0055] 1 illustrates a perspective view of another insulator including through holes according to embodiments herein. [Figure 18]

[0056] 18 illustrates a top view of the insulator of FIG. 17 according to an embodiment herein. [Figure 19]

[0057] 18 illustrates a perspective view of the insulator of FIG. 17 that has been further metallized and from which the metallization has been at least partially removed to form circuitry, according to embodiments herein. [Figure 20]

[0058] 1 illustrates a top perspective view of a KOVAR® ring frame according to an embodiment herein. [Figure 21]

[0059] 21 illustrates a bottom perspective view of the KOVAR® ring frame of FIG. 20 according to embodiments herein. [Figure 22]

[0060] 1 illustrates a perspective view of a microelectronic package assembly according to an embodiment herein. [Diagram 23]

[0061] 23 illustrates a bottom perspective view of an etch lid shown over a microelectronic package assembly as in FIG. 22 according to an embodiment herein. [Figure 24]

[0062] 1 illustrates a process flow chart according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0039] Introduction

[0063] According to various embodiments described herein, microelectronic package assemblies are manufactured to meet the demands of radio frequency (RF) performance, adhesion (high shear strength), and yield (no cracking due to mismatched thermal properties) especially for telecommunications applications. 5G wireless amplifiers operate at frequencies >3 GHz. For high power base stations located in rural areas, GaN RF power transistors need to deliver >5 W at frequencies between 2-10 GHz. RF performance using the package assemblies described meets these needs at frequencies up to 10 GHz with low losses. The methods herein provide significant improvements to reduce manufacturing time and reduce outgassing that adversely affects RF performance. By improving outgassing performance, the assemblies described herein also have fewer voids and improved adhesion, thereby extending the performance range at extreme temperatures such as up to 200°C.

[0040]

[0064] The inventors have now discovered that by using a thin film to coat the flange instead of repeated plating baths and sintering cycles, reliability can be improved and high dissipation materials can be used for the flange. Furthermore, by using a thin film to coat the insulator instead of repeated plating baths and sintering cycles, organic content within the insulator and at the interface between the insulator and other components is removed. Thin film coatings also allow the insulator to be selectively metallized for more precise control, narrowing the width of the leads and minimizing the spacing distance between the leads, further resulting in improved RF performance. The inventors have also discovered that improved RF performance can be achieved using laser removal (of metallization) to provide thin RF lines. Lead attachment is further enhanced using soft solders, as well as gold-tin alloy die attach. The package assembly can also be enhanced with a braze that penetrates the through holes to provide additional or alternative bonding means. The package assemblies disclosed herein are also compatible with thermoplastic covers, particularly liquid crystal polymer covers for gross leak-safe packaging. The package assembly disclosed herein is also compatible with KOVAR® ring frames and etch lids to provide a ceramic cover for hermetically sealed fine leak-safe packaging. KOVAR® is an iron-nickel-cobalt alloy.

[0041] term

[0065] In the following description, specific terminology is used for the sake of clarity, but these terms are intended to refer only to the particular structures of the embodiments selected for illustration in the drawings, and are not intended to define or limit the scope of the present disclosure. In the drawings and the following description that follows, it should be understood that like numerical designations refer to components of similar function.

[0042]

[0066] The singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise.

[0043]

[0067] As used in this specification and the claims, the term "comprising" can include "consisting of" and "consisting essentially of" embodiments. As used herein, the terms "comprise(s)", "include(s)", "having", "has", "can", "containing" and variations thereof are intended to be open-ended transitional phrases, terms, or words that require the presence of the recited ingredients / components / steps and permit the presence of other ingredients / components / steps. However, such descriptions should also be construed as describing the composition, article, or method as "consisting of" and "consisting essentially of" the recited ingredients / components / steps, which permits only the recited ingredients / components / steps to be present along with impurities that may result therefrom, and excludes other ingredients / components / steps.

[0044]

[0068] Numerical values ​​in the specification and claims of this application should be understood to include numerical values ​​that are the same when reduced to the same number of significant figures, and numerical values ​​that differ from the stated value by less than experimental error of conventional measuring techniques of the type described in this application to determine the value.

[0045]

[0069] All ranges disclosed herein are inclusive of the recited endpoints and are independently combinable (e.g., the range "from 2.3 ppm / K to 17.5 ppm / K" includes the endpoints, 2.3 ppm / K or 17.5 ppm / K, and all intermediate values).

[0046]

[0070] Method steps described herein refer to temperatures, and unless specified, this refers to the temperature reached by the material being referred to, not the temperature at which the heat source (e.g., furnace, oven) is set. The term "room temperature" refers to the range of 20°C to 25°C (68°F to 77°F).

[0047] Microelectronics Package Assembly

[0071] The present disclosure relates to a microelectronic package assembly having the aforementioned advantages and a method for making the same. An example of a microelectronic package assembly is shown in Figures 1 and 2. The package assembly 100 comprises a flange 120, an insulator 150, and a conductive alloy preform 130 disposed between the flange 120 and the insulator 150. The insulator 150 further comprises a top surface 152 at least partially coated with a coating 155. Depending on the application, the insulator 150 can partially surround a semiconductor die and / or can be used to mount the die. It should be understood that multiple dies can be utilized without affecting the scope of the invention. Figure 2 shows a die 195 centrally positioned on a portion of the insulator top surface 152 coated with the coating 155. Other configurations for surrounding and / or mounting the die are contemplated, including alternatively positioning the die 195 on a flange. Additionally, package assembly 100 includes a conductive alloy preform 130 (shown in FIG. 11), and a lead frame 170 having a plurality of leads 172, a non-conductive adhesive 180, and a cover 190, as shown in FIGS. 1-2.

[0048]

[0072] FIG. 3 shows a cross-sectional view of the package assembly 100 taken along line "A" in FIG. 1. The flange 120 includes a coating 125. The coating 125 on the top surface of the flange is also referred to herein as a first coating. The conductive alloy preform 130 is in contact with the coating 125. The insulator 150 includes a coating 145 and a coating 155. The coating 145 on the bottom surface of the insulator is also referred to herein as a second coating. The coating 155 on the top surface of the insulator is referred to herein as a third coating. In some cases, the coatings 125 and 145 on the opposing surfaces of the flange and the insulator may each be referred to as a first coating, in which case the coating 155 on the top surface of the insulator is referred to as a second coating. In addition to the conductive alloy preform 130 being in contact with the coating 125, the conductive alloy preform 130 is also in contact with the coating 145. Coating 155 is selectively applied to only partially coat the top surface of insulator 150 where the leads, interconnects, and / or die will be attached. Alternatively, coating 155 can be applied to the entire top surface of the insulator and selectively removed by a laser where the leads, interconnects, and / or die will be positioned. Leads and / or interconnects 172 are in contact with coating 155. Non-conductive adhesive 180 is in contact with leads 172 as shown and in contact with insulator 150 away from line "A" where coating 155 is not present because coating 155 was selectively applied. Cover 190 is in contact with non-conductive adhesive 180 and defines cavity 185 in which die 195 resides. Die 195 may be attached to package assembly 100.

[0049]

[0073] The flange 120 may have through holes 115 for mounting packaging in microelectronic applications, as shown in the perspective view of FIG. 4. It should be understood that the through holes 115 are not particularly limiting and that slots or grooves may be formed in the flange. The holes, slots, or grooves may be used to attach the flange to a substrate or heat sink base. In one embodiment, the holes, slots, or grooves are formed by etching, milling, grinding, stamping, or other suitable methods. As seen in FIG. 5, which is a cross-sectional view of the flange 120 of FIG. 4, the top surface 122 of the flange 120 may have a coating 125, preferably a thin coating t C The flange 120 may have another coating (not shown) applied to its bottom, opposite surface 122. The thickness of the flange t F is defined between the top surface 122 and the bottom surface 118 .

[0050]

[0074] The insulator 150 is shown in Figures 6-8. Figure 8 shows a cross section taken along line "A" in Figure 6. In one embodiment, the entire bottom surface 148 of the insulator 150 is coated with a coating 145, preferably a thin coating t C is placed on the insulator 150. The faces 146 connecting the bottom face 148 to the top face 152 of the insulator 150 are free of any coating. The insulator 150 is partially metallized. In one embodiment, a coating 155 is selectively applied to portions of the top face 152 of the insulator 150. The portions having the coating 155 are intended for later attachment of leads, interconnects, and / or die.

[0051]

[0075] Insulation thickness t Iis defined between the top surface 152 and the bottom surface 148. In some embodiments, the insulator may include a plurality of through holes 154 through the thickness, as shown in a partial plan view of the insulator 250 as in FIG. 9. The through holes (also called vias) may be arranged in a pattern along the peripheral region 255 of the insulator 250. Depending on the application and die, the through holes 154 may be drilled in the insulator to enhance the RF signal. The through holes 154 may have a diameter ranging from 0.01 mm to 0.7 mm, e.g., 0.10 mm to 0.7 mm, 0.10 mm to 0.25 mm, or 0.15 mm to 0.2 mm. In a preferred embodiment, the through holes are 0.15 mm ±10% in diameter. Coatings applied to any surface of the insulator do not adversely affect the performance of the through holes.

[0052]

[0076] FIG. 10 shows a perspective view of the ceramic insulator 250 shown partially in FIG. 9. The insulator 250 has an opening 205. The opening 205 is a central void space, and therefore the insulator may also be referred to as a ceramic ring. The insulator 250 includes a number of through holes 154 that penetrate the thickness of the insulator. The through holes may also be referred to as vias. In FIG. 10, the vias 154 are represented by crosshairs due to their small size, but are circular through holes with a diameter. In the illustrated embodiment of FIG. 10, the diameter of the through holes 154 is 0.15 mm. The insulator 250 may be, for example, Al2O3, and may include 50 to 300 vias, depending on the design of the structure to allow the RF waves to travel. In the illustrated example, there are 146 through holes, and in the center of the insulator 250 is an opening 205 or void measuring 11.7 mm by 13.5 mm. The through holes or vias may be utilized to enhance coupling. In a subsequent brazing step, the braze metal penetrates the through holes to improve the bond between the insulator and the preform and / or flange to which the insulator 250 is joined.

[0053]

[0077] Additional components of the package assembly 100 are shown separately in Figures 11-15. Figure 11 shows a perspective view of a conductive alloy preform 130 for bonding the flange to the insulator. The preform 130 may be Ni plated to enhance bonding to the flange and / or the insulator. The lead frame 130 is also referred to herein as a first conductive alloy preform. Figure 12 shows a perspective view of another conductive alloy preform 160 for attaching the insulator to the leads. The preform 160 is also referred to herein as a second conductive alloy preform. Figure 13 shows a perspective view of a lead frame 170 including a plurality of leads 172. Figure 14 shows a perspective view of a non-conductive adhesive 180 for bonding the insulator to the cover. Figure 15 shows a perspective view of a cover 190 for covering, protecting and encapsulating the microelectronic package assembly. The cover may be an LCP as shown. Alternatively, a ceramic cover may be used (as shown in Figure 23).

[0054]

[0078] FIG. 16 illustrates a plan view of another lead frame 270 according to an embodiment herein. The lead frame can be cut from an alloy sheet, for example a nickel-iron alloy sheet, approximately 2 mils thick. The sheet is etched away to create void areas 205. This design allows the RF lines and ground to be spaced apart for optimal performance. In the example shown in FIG. 16, the RF lines are 0.012″ (0.31 mm) wide, w RF The gland has a width of 0.020'' (0.51 mm), w ground has.

[0055]

[0079] Other package assembly configurations are contemplated and the examples herein should not be considered limiting. For example, alternative configurations of microelectronic package assemblies are shown in Figures 17-23.

[0056]

[0080] FIG. 17 shows a perspective view of another ceramic insulator 350. Insulator 350 includes coating 345 on the bottom insulator surface and coating 355 on the top insulator surface (similar to that described above for insulator coatings 145 and 155). The insulator includes through holes or vias 354. The insulator may have an opening 305 (to accommodate subsequent die placement). In an alternative embodiment, the insulator may have one or more openings to accommodate shims and / or risers to provide a pedestal above the plane of the top surface of the insulator. The shims and / or risers may be CuW, or other suitable materials such as Cu-CuMo-Cu, Cu-Mo-Cu, Cu, or combinations thereof. The die may be positioned within the opening or on the pedestal.

[0057]

[0081] The through holes 354 may be infiltrated with braze as previously described to enhance the bond between the bottom surface of the insulator and the mating components (eg, flanges and / or preforms).

[0058]

[0082] Figure 18 shows a top view of the insulator of Figure 17 with coatings 345 and 355 (e.g., as described above for coatings 145 and 155) deposited on the top surface of the insulator. Such coatings may include one or more deposited layers of titanium and / or copper, and may further include deposited layers of gold and / or nickel. The top layer of metallization 452 is gold, so the top surface of insulator 450 is completely coated with gold prior to laser ablation of the metallization layers for circuitization.

[0059]

[0083] Figure 19 shows a perspective view of the insulator of Figures 17 and 18 after further processing. The metallization of Figure 18, which includes gold, is at least partially removed to form a circuit including the RF leads shown in Figure 19. The RF ceramic leads are very fine in dimensions (narrow width RF), and therefore suitable for high temperature thermal applications. In this example, the via holes are formed by laser and then the insulator, which may be Al2O3, is metallized. Thus, both the top and bottom surfaces of the insulator are metallized as well as the inner walls of the vias, which are infiltrated with the braze material, thereby enhancing bonding with other components.

[0060]

[0084] To provide a fine leak-safe hermetically sealed package assembly, a KOVAR® ring frame 480 as illustrated in FIG. 20 (top view) can be utilized with a package assembly according to an embodiment herein. FIG. 21 shows a bottom perspective view of the KOVAR® ring frame 480 of FIG. 20. The ring frame 480 can be sealed using an Au-Sn seam seal around the sides and / or for sealing with the lid 490. FIG. 22 shows a perspective view of a microelectronic package assembly 400 having a flange 420, insulator 450, ring 480, and lid 490 as described herein. A bottom perspective etch lid 490 as illustrated in FIG. 23 can be used with the microelectronic package assembly 400 as in FIG. 22. The KOVAR® ring frame 480 and etch lid 490 are Ni / Au plated. In some cases, multiple layers are formed, such as Ni / Au / Ni / Au, to reduce the effects of oxidation. In other cases, palladium plating is used in conjunction with or instead of Ni / Au plating. The package assembly may be provided to the customer without the die, such that the placement of the die in the insulator opening 305 is performed separately (as in FIG. 19).

[0061] material

[0085] Important properties to consider in material selection for components of a packaging assembly include, for example, thermal conductivity, coefficient of thermal expansion (CTE), heat dissipation, and dielectric properties, as well as mechanical properties, among others. Matching of CTE between components is particularly important for mechanical integrity, for example to minimize or eliminate the possibility of flange and / or ceramic cracking.

[0062]

[0086] The flange is a heat spreading material that efficiently dissipates heat. The flange is constructed to maintain the temperature of the die below a maximum operating temperature, which may be 200°C or less for some RF applications. A suitable heat spreading material for the flange may be non-magnetic or non-ferrous. The flange 120 is a highly thermally conductive material having a thermal conductivity in the range of 140-2000 W / (mK), e.g., 140-600 W / (mK) or 175-550 W / (mK) at room temperature, and a coefficient of thermal expansion (CTE) in the range of 2.3 ppm / K to 17.5 ppm / K, e.g., 2.3 ppm / K to 14.4 ppm / K or 4.6 ppm / K to 14.4 ppm / K. In a preferred embodiment, the flange material may have a thermal conductivity in the range of 140-650 W / (mK) at room temperature and a CTE in the range of 5.5 ppm / K to 17.5 ppm / K. Examples of suitable flange materials include diamond-based composites, Cu-CuMo-Cu (CPC), copper tungsten (CuW), Cu-Mo-Cu (CMC), Cu, or combinations thereof.

[0063]

[0087] In certain embodiments, the flange is a highly thermally conductive material having a thermal conductivity in the range of 140-400 W / (mK) at room temperature and a CTE in the range of 5.5 ppm / K to 17.5 ppm / K. Examples of suitable flange materials include Cu-CuMo-Cu (CPC), copper tungsten (CuW), Cu-Mo-Cu (CMC), Cu, or combinations thereof. These examples may include laminates as the flange material.

[0064]

[0088] In another aspect, the flange high thermal conductivity material has a thermal conductivity in the range of 500-600 W / (mK) at room temperature and a CTE in the range of 6.0 ppm / K-10.5 ppm / K. Examples of suitable flange materials include copper diamond composites such as DC60 or DC70, or silver diamond composites such as AD90. Diamond composites are available from A.L.M.T. Corporation or the Sumitomo Electric Group. In one embodiment, it is desirable for the flange to be made of a material having a substantially similar CTE to the insulator material.

[0065]

[0089] The flange thickness defined between the flange top surface 122 and the flange base surface 118 is a thickness t F Flange thickness t F is in the range of 0.5 mm to 5.0 mm, for example 1.0 mm to 3.0 mm, or 1.5 mm to 2.5 mm.

[0066]

[0090] Specifically, the inventors have found that thin film coatings, as described below, are more suitable for diamond composite flange materials. The methods described herein are particularly suited to diamond composites and overcome the drawbacks of repeated plating baths and sintering cycles. Thus, in one embodiment, thin films of coatings 125, 145 and / or 155 are useful to provide a number of advantages to the package assemblies disclosed herein.

[0067]

[0091] Referring back to FIG. 3, the coatings include coatings 125, 145 and 155 (a first coating 125 on the top surface of flange 120, a second coating 145 on the bottom surface of insulator 150, and a third coating 155 on the top surface of insulator 150), which may each comprise a thin film of titanium, copper, or a combination thereof. Preferably, the thin coatings are applied in a manner that results in a controlled, substantially uniform thickness. The coating thickness t of coatings 125, 145 and 155 is C For example, the thickness t C The lower limit of the thickness t may be 0.1 μm to 1.0 μm, for example, 0.4 μm to 1.0 μm, 0.5 μm to 1.0 μm, 0.6 μm to 1.0 μm, or 0.7 μm to 0.9 μm. C The thickness t may be greater than 0.1 μm, for example, greater than 0.2 μm, greater than 0.3 μm, greater than 0.4 μm, greater than 0.5 μm, greater than 0.6 μm, greater than 0.7 μm, or greater than 0.8 μm. The thin coating needs a sufficient amount of material for adhesion to the conductive alloy preform, and if the thickness is too thin, the adhesive strength may decrease. Cmay be less than 1.0 μm, e.g., less than 0.9 μm, less than 0.8 μm, less than 0.7 μm, or less than 0.6 μm. The methods described herein provide sufficient material for thin coatings, as coatings that are too thick can lead to reduced production times and inefficient processes. Thus, in preferred embodiments, the thickness t C In one embodiment, the thickness t C The insulator coatings 345 and 355 shown in FIG. 17 for the insulator 350 (see also the embodiment shown in FIG. 22), as well as the flange coating 325 (not shown), also have a thickness t C has.

[0068]

[0092] In some embodiments, any of the coatings 125, 145, and 155 (and even 325, 345, and 355) described herein can each include two or more sublayers, where the total thickness of the sublayers is also 1 micron or less, e.g., the total thickness of the sublayers is less than or equal to a thickness t CFor example, a first sublayer of titanium having a thickness of 0.05 μm to 0.35 μm, or any 0.05 μm increment therebetween, is applied, and a second sublayer of copper is applied over the first sublayer. The copper sublayer has a thickness of 0.45 μm to 0.75 μm, or any 0.05 μm increment therebetween. The combined thickness of the first and second sublayers is 1 micron or less. In a preferred embodiment, the first sublayer of titanium is 0.12 μm to 0.28 μm, and the second sublayer of copper is 0.52 μm to 0.68 μm. In one embodiment, the first sublayer of titanium is about 0.2 μm ± 10% and the second sublayer of copper is about 0.6 μm ± 10%. Any or all of the coatings 125, 145 and 155 (as well as 325, 345 and 355) can be applied by physical vapor deposition (PVD), atomic deposition, chemical deposition, or other suitable sputtering techniques. In certain aspects, the first, second and third coatings for the flange and insulator (e.g., 125, 145, 155 or 325, 345, 355, respectively) are deposited by PVD. In one embodiment, the coatings 125, 145 and 155 are nickel-free. In another embodiment, the coatings 325, 345 and 355 are nickel-free.

[0069]

[0093] Optionally, coatings 125, 145 and 155 may further include nickel plating thereon. The thickness of the nickel plating on coatings 125, 145 and 155 may be between 1.0 microns and 5.0 microns, e.g., between 1.0 μm and 4.0 μm, between 1.0 μm and 3.5 μm, or between 1.5 μm and 3.0 μm. On the lower limit, the nickel plating thickness may be greater than 1.0 μm, e.g., greater than 1.5 μm. On the upper limit, the nickel plating thickness may be less than 5.0 μm, e.g., less than 4.5 μm, less than 4.0 μm, or less than 3.5 μm. In a preferred embodiment, the nickel plating thickness is comprised in an amount of between about 1.5 μm and about 3.0 μm.

[0070]

[0094] A conductive alloy preform 130 for bonding the insulator 150 to the flange 120 contacts the coatings 125 and 145. In one embodiment, the preform 130 is nickel plated. The Ni plating on the preform enhances the bond strength of the leads by reducing oxidation. The thickness of the nickel plating on the conductive alloy preform 130 is as described above. A conductive alloy preform 160 for bonding a lead frame 170 including a plurality of leads 172 to the insulator 150 contacts the coating 155. At least one of the conductive alloy preforms 130 and 160 is a solder alloy. In some embodiments, at least one of the conductive alloy preforms 130 and 160 is a silver-copper (Ag-Cu) alloy or a gold-tin (Au-Sn) alloy. In some embodiments, the preform 130 is an iron / nickel alloy, such as Alloy 42, and the lead frame 170 is a silver / copper alloy, such as Ag72Cu28.

[0071]

[0095] In some embodiments, at least one of the first and second conductive alloy preforms (130, 160) is an alloy having a chemical composition of 50-90% silver and 10-50% copper, such as 60-80% silver and 20-40% copper, or 70-80% silver and 20-30% copper. The first and second conductive alloy preforms (130, 160) may have a thickness in the range of 0.01-0.10 millimeters, such as 0.1-5 mm. The thickness of the conductive alloy preform may be 0.01 mm to 0.10 mm, such as 0.01 mm to 0.08 mm, 0.01 mm to 0.05 mm, 0.01 mm to 0.04 mm, or 0.015 mm to 0.035 mm. For the lower limit, the thickness of the conductive alloy preform may be greater than 0.01 mm, such as greater than 0.015 mm, or greater than 0.02 mm. As an upper limit, the thickness of the conductive alloy preform may be less than 0.10 mm, such as less than 0.08 mm, less than 0.06 mm, or less than 0.04 mm. In a preferred embodiment, the thickness of the conductive alloy preform is included in an amount of about 0.025 mm ±10%.

[0072]

[0096] The insulator provides a dielectric material that is non-conductive. In certain aspects, the insulator material has a thermal conductivity in the range of 1-200 W / (mK) and a CTE in the range of 4.5 ppm / K-11.5 ppm / K at room temperature. Examples of suitable insulator materials include sapphire, alumina (Al2O3), beryllia (BeO), aluminum nitride (AlN), zirconia toughened alumina (ZTA), silicon carbide (SiC), magnesium silicon carbide (Mg-SiC), silicon nitride (Si3N4), ceramic, or combinations thereof. In some embodiments, the insulator comprises sapphire, alumina, aluminum nitride, or combinations thereof. In a preferred embodiment, the insulator is alumina having a purity of 96% or greater.

[0073]

[0097] The insulator thickness defined between the insulator top surface 152 and the insulator bottom surface 148 is a thickness t I The thickness of the insulator t I is in the range of 0.05 mm to 1 mm, for example, 0.1 mm to 0.5 mm.

[0074]

[0098] The insulator having the coating 155 on its top surface 152 may further have a plating thereon, such as a gold-tin (Au-Sn) alloy. This plating is particularly suitable for attachment of a die 195, as shown in Figures 2 and 3. The die 195 is not particularly limited by the embodiments described herein, and in some embodiments, the die 195 may be GaN, GaAs, Si, or other suitable semiconductor material. The microelectronic assembly packages herein may not include the die itself, and the die may be positioned later by a consumer.

[0075]

[0099] FIG. 12 shows a lead frame 170 having a number of leads 172. The lead frame can be etched to size. The number of leads 172 comprises an alloy of iron, nickel, or a combination thereof. A suitable alloy is iron / nickel, such as alloy 42 and / or alloy 52. ​​The number of leads 172 may comprise a nickel-iron alloy having 30-80 wt.% nickel, for example 35-80 wt.% nickel, with trace amounts of less than 1 wt.% copper, manganese, chromium, aluminum, silicon, and / or molybdenum, and the balance iron. In a preferred embodiment, the number of leads comprises an alloy having a chemical composition of 39-43% nickel (Ni), 0-2% manganese (Mn), and the balance iron (Fe).

[0076]

[0100] The multiple leads may have a thermal conductivity in the range of 9.5 W / (mK) to 11.5 W / (mK), e.g., 9.5 W / (mK) to 11 W / (mK), or 10 W / (mK) to 10.5 W / (mK). The multiple leads may have a CTE in the range of 5.0 ppm / K to 9.0 ppm / K, 5.5 ppm / K to 9.0 ppm / K, or 6.0 ppm / K to 9.0 ppm / K.

[0077]

[0101] The one or more leads 172 have a width w of 0.35 microns or less, e.g., 0.30 microns or less or 0.25 microns or less. L In some embodiments, at least two of the one or more leads can have a spacing distance d of 0.35 microns or less, e.g., 0.30 microns or less or 0.25 microns or less. L Lead width w L and the spacing distance d L is shown in FIG.

[0078]

[0102] The cover 190 as in FIG. 15 or the etch lid or cover 490 as in FIG. 22 and FIG. 23 can comprise alumina (Al2O3), aluminum nitride (AlN), liquid crystal polymer (LCP), or combinations thereof. The LCP cover is a thermoplastic moldable polymer with glass bead reinforcement to withstand high heat while maintaining the properties of the polymer. The LCP may comprise 15%-50% particulates, such as glass fibers, glass beads, and / or inorganic fillers, 0-2% other additives, and the balance aromatic liquid crystal polymer. Other additives can include carbon black, less than 2%, such as less than 1.5%, or less than 1.0%. The LCP cover performs well at the operating temperatures of the microelectronic package assembly without microcracks / failures as exhibited by some ceramic covers. In a preferred embodiment, the cover is an LCP. LCPs are available, such as Laperos® E471i from Polyplastics Co., Ltd. In one embodiment, the LCP comprises 63% or more aromatic liquid crystal polymer, 35% glass fiber / inorganic fillers, less than 1% carbon black, and less than 1% others. In some embodiments, the cover 190 (and / or 490) comprises an iron-nickel-cobalt alloy etch configured to provide a hermetic seal that is fine leak-safe. Suitable iron-nickel-cobalt alloy etchants include KOVAR®. In other embodiments, the cover comprises a non-conductive adhesive, such as an epoxy, configured to provide a gross leak-safe seal. The cover 190 has a CTE in the range of 3 ppm / K to 10 ppm / K, and a cover thickness range in the range of 0.2 mm to 10 mm, such as 0.5 mm to 5 mm, or 1 mm to 3 mm.

[0079] method

[0103] In addition to material selection considerations, other processing considerations are important to provide microelectronic package assemblies with high frequency RF performance and good adhesion. Specifically, the methods of forming coatings disclosed herein advantageously remove organics. As previously mentioned, introduced organics undesirably lead to the formation of features such as voids. Such features adversely affect RF performance, adhesion, and shear strength.

[0080]

[0104] Specifically, the aforementioned coatings 125, 145 and 155 are advantageously applied by deposition, such as physical vapor deposition, atomic deposition, or chemical deposition. Physical vapor deposition (PVD) is a widely used technique for the production of thin films and surface coatings and may refer to a variety of vacuum deposition methods. Sputtering and / or evaporation generates vapor in the form of atoms, molecules or ions of the coating material delivered from a target. These atoms are then transported and deposited on the substrate surface, either the flange or the insulator, resulting in a thin coating. In one embodiment, PVD is used to form a thin coating on the flange and / or the insulator.

[0081]

[0105] Deposition such as PVD replaces conventional nickel plating and sintering cycles to provide a coating on the surfaces of the flanges and insulators. In conventional nickel plating and sintering cycles, outgassing and organics such as nickel that traps hydrogen during plating are trapped on the surfaces of the flanges and insulators, forming voids during subsequent sintering. The PVD process is performed in a vacuum and no organics are introduced. As such, the resulting processed package assembly with the PVD thin film coating on the flanges and insulators is substantially free of organics that result in trapped gases and the formation of voids. Thus, harmful trapped organics that burn during conventional sintering cycles that typically result in voids are not present with PVD, and the package assemblies disclosed herein are substantially free of voids at the interfaces between the surfaces of the flanges and insulators and / or coatings, e.g., coatings 125, 145, 155, that interface with the respective surfaces of the flanges and / or insulators.

[0082]

[0106] Methods for making microelectronic package assemblies herein include coatings applied by PVD up to a thickness of 1 micron or less, such as coatings 125, 145, 155, which have been previously described. The coatings, such as coatings 125, 145, 155, provide adhesion that results in improved shear strength when tested at 1,000 g to 5,000 g compared to coatings provided by repeated cycles of conventional plating / sintering.

[0083]

[0107] Various methods for making a microelectronic package assembly are disclosed herein.

[0084]

[0108] A method for making a microelectronic package assembly includes depositing a coating on a flange, the flange being a highly thermally conductive material having a thermal conductivity in the range of 140 to 2000 W / (mK) and a coefficient of thermal expansion (CTE) in the range of 2.3 ppm / K to 17.5 ppm / K at room temperature. The flange may be Cu-CuMo-Cu (CPC), copper tungsten (CuW), Cu-Mo-Cu (CMC), Cu, or combinations thereof. In some embodiments, the flange is CPC.

[0085]

[0109] A flange, such as flange 120 (and similarly for 420) described herein, includes a top surface 122 as shown in FIG. 5. The method includes depositing a coating on the top surface of the flange such that the coating has a thickness of 1 micron or less. Coating the flange may include one or more sublayers, i.e. a first sublayer, e.g. titanium, and a second sublayer, e.g. copper. Deposition of the coating on the flange may include the described deposition techniques, such as PVD. In some embodiments, the method includes depositing a coating (i.e., first coating 125 or 325) on the flange top surface having a first sublayer of titanium, e.g., 15%-35% of the total flange (top) coating thickness, and a second sublayer of copper on top of the first sublayer of titanium, e.g., 65%-85% of the total flange (top) coating thickness. In one embodiment, the step of depositing the first coating includes depositing two (or more) sublayers: a first sublayer of titanium that is 15%-35% of the total coating thickness, and a second sublayer of copper that is 65%-85% of the total coating thickness. For example, a coating (e.g., first coating 125 or 325) may include a first sublayer of titanium that is 25%±10% of the flange coating thickness, and a second sublayer of copper on the first sublayer, where the copper sublayer is 75%±10% of the flange coating thickness.

[0086]

[0110] The method includes depositing a coating on an insulator surface opposite the coated flange top surface 122 (e.g., bottom surface 148 of insulator 150 shown in FIG. 8, and similarly for the bottom surface of insulator 350). The insulator can include sapphire, alumina (Al2O3), beryllia (BeO), aluminum nitride (AlN), zirconia toughened alumina (ZTA), silicon carbide (SiC), magnesium silicon carbide (Mg-SiC), silicon nitride (Si3N4), or combinations thereof. In some embodiments, the insulator is Al2O3 or AlN.

[0087]

[0111] An insulator, such as insulator 150 (and further 250, 350 or 450) described herein, has a bottom surface. The method includes depositing a coating on the bottom surface 148 of the insulator over its entirety such that the coating has a thickness of 1 micron or less. The deposition of the coating 145 (or 345) on the insulator bottom surface can include one or more sublayers, in other words (as in the case of the flanges described above), a first sublayer, e.g., titanium, and a second sublayer, e.g., copper. The deposition of the coating on the insulator bottom surface can include the described deposition techniques, such as PVD. In some embodiments, the method includes depositing a coating (i.e., second coating 145 or 345) on the insulator bottom surface 148 having a first sublayer of titanium, e.g., 15%-35% of the total insulator (bottom) coating thickness, and a second sublayer of copper on top of the first sublayer of titanium, e.g., 65%-85% of the total insulator (bottom) coating thickness. In some embodiments, the method includes coating the insulator bottom surface with a first sublayer of titanium, which can be 25%±10% of the insulator coating thickness, and a second sublayer of copper over the first sublayer, the copper sublayer being 75%±10% of the insulator bottom surface coating thickness.

[0088]

[0112] The coating / insulator interface is of particular importance for the deposition of the coating by the described deposition techniques. Previously, techniques such as repeated plating bath and sintering cycles, and / or metallization with pastes such as pastes containing molybdenum manganese, introduced organics and binders that resulted in residuals on the insulator after heating. The trapped organic content introduced oxide contaminants and / or voids that adversely affected adhesion properties and therefore RF performance.

[0089]

[0113] The method also includes depositing a coating (i.e., third coating 155 or 355) on the insulator top surface 152 having a first sublayer of titanium, e.g., 15%-35% of the total insulator (top) coating thickness, and a second sublayer of copper over the first sublayer of titanium, e.g., 65%-85% of the total insulator (top) coating thickness. In some embodiments, the method includes depositing a coating on the insulator top surface having a first sublayer of titanium, which may be 25%±10% of the insulator top coating thickness, and a second sublayer of copper over the first sublayer, the copper sublayer being 75%±10% of the insulator top coating thickness. In some implementations, the insulator 150 is coated (e.g., by deposition techniques described herein) to completely coat the bottom and top surfaces of the insulator, and therefore the insulator coatings may be collectively referred to as second coatings (as opposed to second and third coatings).

[0090]

[0114] Optionally, the coated layer can be ablated with a laser to form circuitry directly on the insulator, thus advantageously eliminating the need for a printed circuit board (PCB). The method can further include the insulator having plating thereon (over coating 155 or 355), such as a gold-tin (Au-Sn) alloy. The method can include laser ablation to selectively remove the coating and / or gold-tin plating in areas as needed to expose the top surface of insulator 150 (or 250, 350 or 450).

[0091]

[0115] The method includes positioning a conductive alloy preform, such as the conductive alloy preform 130 described herein, for bonding the insulator to the flange. The positioning includes contacting the conductive alloy preform with the flange coating (top surface of the flange) and the insulator coating (bottom surface of the insulator). Bonding the conductive alloy preform to the flange and insulator can be performed in a furnace at a temperature of 850° C. or higher, such as 875° C. or higher or 900° C. or higher.

[0092]

[0116] The method may include cutting the conductive alloy preform to a desired size and pattern. The thickness of the preform may be 0.01-0.05 mm, for example, 0.025 mm ± 10%. The conductive alloy preform may be a nickel-iron alloy (e.g., 42 alloy) or a silver-copper (Ag-Cu) alloy as described herein. The conductive alloy preform, also referred to herein as a braze, may be in sheet form that is cut to fit the configuration of the flanges and / or insulators. In some embodiments, the preform is a lead frame made from 42 alloy, a material available in sheet form, which is cut to form the lead frame. In some embodiments, the preform 130 is nickel plated to enhance bonding.

[0093]

[0117] The aforementioned method eliminates the need for lengthy repeated plating bath and sintering cycles as these are replaced by a single deposition coating method for the surfaces of each component. Also, importantly, the assemblies formed by this method are advantageously free of organics, trapped gases and / or voids, thereby exhibiting superior adhesion properties and RF performance. This method allows the conductive alloy preforms to be brazed to flanges and insulators without techniques that introduce outgassing and organics that are harmful to semiconductors.

[0094]

[0118] A method for attaching leads to a microelectronic package assembly is described. The method includes attaching an insulator to a flange, such as flange 120 described herein. The insulator, such as insulator 150 described herein, includes a top surface. The method includes depositing a coating to a thickness of 1 micron or less on a portion of the top surface of the insulator. The deposition of the coating on the top surface is selective to precisely coat only the portion of the top surface of the insulator that will later contact the leads, interconnects, or die. Selectively coating may include masking portions of the top surface of the insulator where coating is not desired. The sides of the insulator are also masked, for example, surface 146 as in FIG. 8. The deposition of the coating on the portion of the top surface of the insulator may include one or more of the sublayers described above, in other words, a first sublayer, such as titanium, and a second sublayer, such as copper. The deposition of the coating on the portion of the top surface of the insulator includes the deposition techniques described above, such as PVD.

[0095]

[0119] The method includes directly bonding one or more leads, such as lead 172 described herein, to the coated top surface of the insulator. Due to the deposited coating, at least one of the one or more leads can have a width of 0.35 microns or less. This method importantly allows the width of the leads to be narrowed, thereby improving the R-value. The directly bonding step includes positioning a conductive alloy preform, such as conductive alloy preform 160 described herein, for adhering the one or more leads to the insulator. The positioning includes contacting the conductive alloy preform with the coated top surface of the insulator and the one or more leads. The method may include cutting the conductive alloy preform to a desired size and pattern. The preform can have a thickness of 0.01-0.05 mm, for example 0.025 mm ± 10%. The conductive alloy preform may be a silver-copper (Ag-Cu) alloy as described herein.

[0096]

[0120] The aforementioned method allows for the application of complex circuit patterns to the insulator. This is because coating the top surface of the insulator with the described single deposition method allows for tighter tolerances on the coating pattern than previous techniques such as repeated plating bath and sintering cycles. The deposited coating can be applied to the exact width desired. Previous techniques required the user to consider shrinkage during sintering in repeated plating bath and sintering cycles. Previous techniques also introduced excessive amounts of conductive alloy preform, resulting in undesired dendritic growth that could short between leads. The deposition of the coating herein selectively and minimally metallizes the desired areas with a patterned coating of the top surface of the insulator. The absence of a sintering step allows the metallized portion of the top surface of the insulator of the present invention to maintain its integrity because no shrinkage occurs that affects the pattern accuracy. Additionally, the coating of the top surface of the insulator described herein is of a thickness of 1 micron or less. Previous techniques simply did not allow for leads with widths of 0.35 microns or less because of the larger coating thickness required. Narrower leads are not possible with conventional techniques such as repeated plating bath and sintering cycles or paste application. Packages made according to the methods herein accommodate narrower leads while achieving high yields.

[0097]

[0121] The methods herein may include alternatives to selectively coating and / or masking portions of the top surface of the insulator as described above. Specifically, a deposition coating, for example by PVD, may be applied to the entire top surface of the insulator. These coatings may further include gold and / or nickel and / or palladium plating thereon. Laser ablation is then utilized to selectively remove the coating for circuit formation. Laser ablation of the deposited coating allows for very tight tolerances to form thin RF lines required for high performance applications, for example, telecommunications 5G technology.

[0098]

[0122] A method is described for covering a microelectronic package assembly. The method includes attaching an insulator (such as the insulator 150 described herein) to a flange (such as the flange 120 described herein). A die, such as the die 195 described herein, may be attached to the flange or the insulator, and the insulator may partially surround the die. Attaching the die to the insulator (or to the flange in an alternative configuration) may include bonding or otherwise attaching the die, such as GaN. For example, attaching the die may include welding with an Au-Sn alloy. As described below, attaching the die may occur after bonding the first and second conductive preforms with a brazing process or after attaching a cover. In some embodiments, the second conductive preform and / or the lead frame may be a silver-copper alloy, such as Ag72Cu28 (Ag72wt% and Cu28wt%).

[0099]

[0123] The method includes forming a lead frame including a plurality of leads configured to surround the die on a surface of the insulator opposite the flange. The leads, such as lead 172 described herein, may include a nickel-iron alloy having 30-80 wt.% nickel, e.g., 35-80 wt.% nickel, with trace amounts of less than 1 wt.% copper, manganese, chromium, aluminum, silicon, and / or molybdenum, and the balance iron. Advantageously, the leads can have a narrow width of 0.35 microns or less.

[0100]

[0124] The method includes forming a cavity for the die by adhering a liquid crystal polymer cover to a lead frame by a non-conductive adhesive. The aforementioned method advantageously enables the use of LCP to cover a microelectronic package assembly. The inclusion of glass particulates, e.g., fibers or beads, increases the melting temperature in the LCP, allowing the LCP cover to be used at higher temperatures than polymers without such additives. Thus, the LCP cover replaces ceramic covers, thereby providing advantages over ceramic covers that may experience microcracks and even failure due to heat and thermal expansion. Furthermore, the LCP cover exhibits superior compatibility for bonding with non-conductive adhesives, such as epoxies, resulting in a stronger bond. The flexibility of the LCP cover contributes to the success of the analysis of failure analysis. Unlike ceramic covers, the LCP cover is removable or detachable without damaging the semiconductor chip, e.g., die, in the package assembly, thus enabling accurate failure analysis.

[0101]

[0125] Instead of the LCP cover mentioned above, the method may include a KOVAR® ring enclosure and a ceramic etch lid for fine leak-safe hermetic sealing of the assembly. The KOVAR® ring may be formed from KOVAR® sheet. The KOVAR® ring may be Ni / Au plated, or Ni / Au / Ni / Au plated, or palladium plated.

[0102]

[0126] The method may also include a shim or riser within the assembly, for example, a shim may be positioned within the opening of the insulator ring. Deposition of a coating onto the shim, which may be CuW, may include a PVD coating, such as those described above. The shim may be further plated with Ni / Au, or Ni / Au / Ni / Au, or palladium. The shim may be utilized to provide a seat upon which the die may be positioned within the assembly.

[0103]

[0127] Another method for making a microelectronic package assembly is described. The method includes depositing a first coating having a thickness of 1 micron or less on opposing surfaces of a flange and an insulator, such as the insulator 150 described. The flange, such as the flange 120 described, is a highly thermally conductive material having a thermal conductivity in the range of 140-2000 W / (mK) at room temperature and a coefficient of thermal expansion (CTE) in the range of 2.3 ppm / K to 17.5 ppm / K. Deposition of the coating on the flange and the insulator may include the deposition techniques described, such as PVD. Each coating on the top surface of the flange (e.g., coating 125) and the bottom surface of the insulator (e.g., coating 145) may include one or more sublayers, i.e., a first sublayer, e.g., titanium, and a second sublayer, e.g., copper. In some embodiments, the method includes depositing a coating on the flange top surface and / or the insulator bottom surface having a first sublayer of titanium, which may be 15%-35% of the flange coating thickness, and depositing a second sublayer of copper on the first sublayer, the copper sublayer being 65%-85% of the flange coating thickness. The method includes positioning a first conductive alloy preform between the flange and the coated surface of the insulator for adhering the flange to the insulator. The first conductive alloy preform, such as the preform 130 described, is for adhering the insulator to the flange. The first conductive alloy preform contacts the coated flange top surface and the coated insulator bottom surface. The method may include cutting the first conductive alloy preform to a desired size and pattern. The thickness of the preform may be 0.01-0.05 mm, such as 0.025 mm ±10%.

[0104]

[0128] The method includes depositing another coating on a portion of the top surface of the insulator to a thickness of 1 micron or less to form a partially coated top surface (e.g., coating 155). As described above for depositing the coating on the flange top surface and the insulator bottom surface, depositing the coating on the portion of the top surface of the insulator can include the described deposition techniques, such as PVD. Depositing the coating on the portion of the top surface of the insulator can include one or more sublayers, similar to those described above.

[0105]

[0129] The method includes bonding one or more leads directly to the partially coated top surface using a second conductive alloy preform to allow the one or more leads to have a narrow width of 0.35 microns or less. The leads, such as lead 172 described, may be part of the lead frame or may surround the die on the coated surface of the insulator opposite the flange. The lead 172 may include a nickel-iron alloy having 30-80 wt.% nickel, for example 35-80 wt.% nickel, with trace amounts of less than 1 wt.% copper, manganese, chromium, aluminum, silicon, and / or molybdenum, and the balance being iron. In a preferred embodiment, the lead includes a nickel-iron alloy etched to size, the alloy being 42 alloy and / or 52 alloy. A second conductive alloy preform, such as preform 160 described, is for bonding the lead frame to the insulator. The second conductive alloy preform contacts the coated insulator top surface and the plurality of leads. The method may include cutting the second conductive alloy preform to a desired size and pattern. The thickness of the preform may be 0.01-0.05 mm, for example 0.025 mm ±10%.

[0106]

[0130] The method includes bonding a first conductive preform to the insulator and flange, and a second conductive preform to the insulator and lead at a temperature of 850° C. or higher. The bonding may include a brazing process, in which the assembly is heated in a furnace to bond the surfaces in contact with the conductive alloy preforms. The brazing process simultaneously bonds the insulator to the lead and the insulator to the flange. The brazing process may be performed in a belt furnace for manufacturing efficiency, or in a box furnace. Additionally, the brazing process may penetrate through holes, or vias, a number of which may be formed by a laser through the thickness of the insulator. The braze enhances the bond between the insulator and other components in the assembly.

[0107]

[0131] The method includes attaching a cover including a liquid crystal polymer to form a cavity for the die. Alternatively, the cover may include a KOVAR® ring and a ceramic etch lid cover as described. A cover such as cover 190 (or 490) as described herein is adhered to the lead frame by a non-conductive adhesive such as non-conductive adhesive 180 as described cut to size, or by a Au80Sn20 frame of a KOVAR® ring, e.g., 80 wt% gold and 20 wt% tin. Au80Sn20 can also be used as a preform for attaching a shim to a flange. Attachment of the cover with a non-conductive adhesive can be done at temperatures below 180° C., so does not affect other package assembly components. The method may further include mounting the die to an insulator (or to a flange in an alternative configuration). In particular, GaN die is difficult to attach with conventional packaging methods that rely on nickel plating / sintering techniques. GaN does not bond to nickel. In one embodiment, the method includes welding GaN to a top surface of an insulator that is coated with an Ag—Sn alloy.

[0108]

[0132] 24 shows a flow chart according to method 2400, an exemplary method of making a microelectronic package assembly. Deposition 2410 of a coating is performed on at least one surface of the flange and at least one surface of the insulator. The flange may be CPC or other suitable material described herein, and the insulator may be alumina or other suitable material described herein. The coating may be deposited by PVD to metallize the top surface of the flange and the bottom surface of the insulator. The coating may be titanium and / or copper as described herein.

[0109]

[0133] To form a flange / insulator subassembly, a first conductive alloy preform, for example a lead frame of 42 alloy, is positioned 2420 between the flange and the coated surface of the insulator. A further coating is deposited 2430 on the top surface of the insulator, optionally or alternatively over the entire top surface of the insulator. Optionally, a laser ablation of the metallization 2440 forms the desired circuitry. A bonding of one or more leads to the coated insulator 2450 is performed using a second conductive preform. Optionally, the insulator includes laser formed through holes, and the brazing of the insulator includes penetrating the through holes to bond the insulator to the flange. A bonding of the first and second conductive preforms to the insulator / flange assembly 2560 is performed at a temperature of 850° C. or greater, for example 850° C., 875° C., or 900° C. A cover is attached 2570 to form a microelectronic package assembly. The cover may be an LCP or KOVAR® ring and ceramic etch lid cover as described above. The method optionally includes the steps of positioning the die in an assembly and hermetically sealing the assembly.

[0110]

[0134] The aforementioned method advantageously provides an assembly that exhibits high RF performance and excellent adhesion properties while allowing for complex circuitry, and an LCP cover, or alternatively a cover including a KOVAR® ring and ceramic lid, to complete the microelectronic package assembly. The aforementioned method also provides a package assembly suitable for mounting GaN dies, thus improving performance by 2x to 6x compared to Si dies. The method also provides higher performance with less packaging volume and / or weight, as it is suitable for increasingly smaller packaging architecture sizes. Microelectronics Package Assembly Configuration

[0135] In one embodiment, a microelectronic package assembly includes a flange having a top surface, the flange being a highly thermally conductive material having a thermal conductivity in the range of 140-2000 W / (mK) at room temperature and a coefficient of thermal expansion (CTE) in the range of 2.3 ppm / K to 17.5 ppm / K; a first coating disposed on the top surface having a thickness of 1 micron or less; an insulator for mounting partially surrounding a die, the insulator having a bottom surface, a second coating disposed on the bottom surface of the insulator; and a conductive alloy preform for bonding the insulator to the flange, the conductive alloy preform contacting the first and second coatings. This configuration provides a flange / insulator assembly useful for microelectronic package assembly. Without being limited thereto, this configuration may include, for example, a CPC flange assembled with an alumina insulator having a first PVD coating (less than 1 micron) of titanium and copper deposited (on the top surface) and a similar second PVD coating (less than 1 micron) of titanium and copper deposited (on the bottom surface). A nickel-plated 42 alloy (first) preform is positioned between the top surface of the flange and the bottom surface of the insulator. The flange / insulator assembly is bonded at a temperature of 850°C or greater.

[0111]

[0136] In another aspect, a microelectronic package assembly comprising a flange having an insulator mounted thereon, the insulator having a top surface, a first coating disposed on the top surface of the insulator having a thickness of 1 micron or less; one or more leads, at least one of the one or more leads having a width of 0.35 microns or less; and a conductive alloy preform for bonding the one or more leads to the insulator, the conductive alloy preform contacting the first coating and the one or more leads. This configuration provides a flange / insulator / lead assembly useful for microelectronic package assemblies. Without being limited thereto, this configuration includes, for example in combination with the above configuration, a (third) PVD coating (less than 1 micron) of titanium and copper deposited on the top surface of the insulator. Another (second) preform is positioned above the insulator surface to include a silver-copper frame and / or preform for the multiple leads. Advantageously, the distance between the leads is minimized for higher RF performance. As will be appreciated, the above configuration can be provided as is for subsequent die mounting.

[0112]

[0137] In another aspect, a microelectronic package assembly includes a flange having an insulator and a die mounted thereon, the insulator partially surrounding the die; a lead frame including a plurality of leads surrounding the die on a surface of the insulator opposite the flange; and a cover including a liquid crystal polymer to form a cavity for the die, the cover being attached to the lead frame by a non-conductive adhesive. This configuration provides a die mounted and covered microelectronic package assembly. Alternatively, the assembly and cover may be provided for subsequent die mounting. As is adaptable to customer needs, the cover may be hermetically sealed for fine leak safety. Alternatively, gross leak safe covers and sealing may be utilized.

[0113]

[0138] In yet another aspect, a microelectronic package assembly includes a flange having a top surface, the flange being a highly thermally conductive material having a thermal conductivity in the range of 140 to 2000 W / (mK) at room temperature and a coefficient of thermal expansion (CTE) in the range of 2.3 ppm / K to 17.5 ppm / K; a first coating disposed on the top surface of the flange having a thickness of 1 micron or less; an insulator for partially surrounding and mounting a die, the insulator having a bottom surface and a top surface opposite the flange, a second coating disposed on the bottom surface of the insulator having a thickness of 1 micron or less; a first conductive alloy preform for bonding the insulator to the flange, the first and second coatings being disposed on the bottom surface of the insulator. a first conductive alloy preform contacting the die, a third coating disposed on a portion of a top surface of the insulator having a thickness of 1 micron or less, the third coating being the same as the second coating; a lead frame including a plurality of leads configured to surround the die on the top surface of the insulator; a second conductive alloy preform for adhering the lead frame to the insulator, the second conductive alloy preform contacting the third coating and the plurality of leads; and a cover including a liquid crystal polymer for forming a cavity for the die, the cover being adhered to the lead frame by a non-conductive adhesive.

[0114]

[0139] In a preferred embodiment, a microelectronic package assembly includes a flange having a top surface; a first coating disposed on the top surface of the flange; an insulator for partially enclosing a die, the insulator having a bottom surface for mounting on the flange and a top surface opposite the bottom surface, a second coating disposed on the bottom surface of the insulator, and a third coating disposed on the top surface of the insulator, the first coating, the second coating, and the third coating each having a thickness of 1 micron or less, and at least one of the first coating, the second coating, and the third coating being applied by at least one of physical vapor deposition, atomic deposition, or chemical deposition. This configuration provides a complete assembly useful for microelectronic package assembly for subsequent die mounting. Without being limited thereto, this configuration can include a CPC flange assembled with an alumina insulator having a first PVD coating (less than 1 micron) of titanium and copper deposited (on the top surface) and a similar second PVD coating (less than 1 micron) of titanium and copper deposited (on the bottom surface). A nickel-plated 42 alloy (first) preform is positioned between the top surface of the flange and the bottom surface of the insulator. The flange / insulator assembly is bonded at a temperature of 850° C. or higher. This configuration includes a (third) PVD coating (less than 1 micron) of titanium and copper deposited on the top surface of the insulator. The third coating is deposited over the entire top surface of the insulator, after which the third coating is selectively removed using a laser. Another (second) preform is positioned over the insulator surface to include a silver-copper frame and / or preform for multiple leads. Advantageously, the distance between the leads is minimized for higher RF performance. The insulator may be a ceramic ring with an opening to accommodate an optional CuW shim with a (fourth) PVD coating (less than 1 micron) of titanium and copper deposited on the top surface of the shim. A KOVAR® ring is positioned over the top surface of the insulator ceramic ring with the third coating.The assembly is nickel plated and sealed using a gold-tin (Au80Sn20) frame on a KOVAR® ring and a gold-tin (Au80Sn20) preform Au80Sn20 on a CuW shim. A Ni / Au plated ceramic etch lid covers the assembly. Laser ablation is further used to remove excess (plating and / or coating) before optionally mounting a die therein and hermetically sealing it.

[0115]

[0140] Any of the above configurations may include that the flange is a highly thermally conductive material having a thermal conductivity in the range of 140-650 W / (mK) and a CTE in the range of 5.5 ppm / K-17.5 ppm / K at room temperature. In some embodiments, the flange is a highly thermally conductive material having a thermal conductivity in the range of 140-400 W / (mK) and a CTE in the range of 5.5 ppm / K-17.5 ppm / K at room temperature, or a highly thermally conductive material having a thermal conductivity in the range of 500-600 W / (mK) and a CTE in the range of 6.0 ppm / K-10.5 ppm / K at room temperature. Suitable flange materials include diamond-based composites, Cu-CuMo-Cu (CPC), copper tungsten (CuW), Cu-Mo-Cu (CMC), Cu, or combinations thereof. As in some of the above examples, the flange is Cu-Cu-Mo-Cu (CPC). In other examples, the flange comprises a copper diamond composite or a silver diamond composite.

[0116]

[0141] Any of the above configurations may include at least one of the first and second coatings comprising titanium, copper, alloys thereof, or combinations thereof. At least one of the first and second coatings is applied by physical vapor deposition (PVD). The first and second deposition coatings are free of nickel.

[0117]

[0142] Any of the above configurations may include at least one of the first and second conductive alloy preforms being a solder alloy. At least one of the first and second conductive alloy preforms being a silver-copper (Ag-Cu) alloy or a gold-tin (Au-Sn) alloy.

[0118]

[0143] Any of the above configurations may include the insulator comprising sapphire, alumina (Al2O3), beryllia (BeO), aluminum nitride (AlN), zirconia-toughened alumina (ZTA), silicon carbide (SiC), magnesium silicon carbide (Mg-SiC), silicon nitride (Si3N4), or combinations thereof. As in some of the above examples, the insulator is alumina (Al2O3) having a purity of 96% or greater.

[0119]

[0144] Any of the above configurations may include the insulator including a plurality of through holes extending through a thickness of the insulator, the plurality of through holes may be arranged in a pattern along a peripheral region of the insulator.

[0120]

[0145] Optionally, the insulator as in any of the above configurations further comprises a nickel plate on the coated bottom and top surfaces, the nickel plate having a thickness of 1.0 to 3.5 microns.

[0121]

[0146] The one or more leads as in any of the above configurations include an alloy of iron, nickel, or a combination thereof. In some examples above, the one or more leads include an alloy having a chemical composition of 30 wt% to 80 wt% nickel (Ni) and the balance iron (Fe). The one or more leads can have a thermal conductivity in the range of 9.5 W / (mK) to 11.5 W / (mK). Any of the above configurations can include at least two of the one or more leads having a spacing distance of 0.35 microns or less.

[0122]

[0147] Any of the above configurations may include a cover to form the cavity of the die. The cover may be alumina (Al2O3), aluminum nitride (AlN), liquid crystal polymer (LCP), or a combination thereof. The cover may include a non-conductive adhesive configured to provide a seal. For hermetic sealing, the cover is ceramic, such as alumina (Al2O3) or aluminum nitride (AlN), and is sealed using a gold-tin frame and a KOVAR® ring.

[0123]

[0148] Any of the above configurations may include a die mounted therein or may be configured to subsequently mount a die. The die may include gallium nitride (GaN), gallium arsenide (GaAs), silicon (Si), or a combination thereof. EXAMPLES

[0124]

[0149] Dimensional testing was performed on the microelectronic package assemblies fabricated according to method 2400 above, and the results are summarized in Table 1.

[0125] [Table 1]

[0150] All components passed the pre-assembly check, dimensional testing, as shown in Table 1. The testing included the use of Scanning Electron Microscopy with Energy Dispersive X-ray Spectroscopy (SEM / EDX) and X-ray Fluorescence (XRF) to check plating thickness.

[0126]

[0151] Functional testing of the package assemblies was performed. Functional testing included leakage testing in the cross leakage test range, lead peel testing for shear testing from 1,000g to 5,000g, electrical conductivity testing using an ohmmeter to test for shorts or discontinuous connections, and solderability testing by immersion in a solder pot to check for wettability.

[0127] [Table 2]

[0152] As shown in Table 2, the package assembly passed all functional tests.

[0128] Embodiment

[0153] The following embodiments are contemplated: All combinations of features and embodiments are contemplated.

[0129]

[0154] Embodiment 1: A microelectronic package assembly comprising: a flange having a top surface; a first coating disposed on the top surface of the flange; an insulator for partially enclosing a die, the insulator having a bottom surface for mounting on the flange and a top surface opposite the bottom surface, a second coating disposed on the bottom surface of the insulator, and a third coating disposed on the top surface of the insulator, wherein the first coating, the second coating, and the third coating each have a thickness of 1 micron or less, and at least one of the first coating, the second coating, and the third coating is applied by at least one of physical vapor deposition, atomic deposition, or chemical deposition.

[0130]

[0155] Embodiment 2: The assembly of any preceding or subsequent embodiment, wherein at least one of the first coating, the second coating, and the third coating comprises titanium, copper, an alloy thereof, a sublayer thereof, or a combination thereof.

[0131]

[0156] Embodiment 3: The assembly of any preceding or subsequent embodiment, wherein each of the first coating, the second coating, and the third coating is nickel-free.

[0132]

[0157] Embodiment 4: The assembly of any preceding or subsequent embodiment, wherein the insulator comprises sapphire, alumina (Al2O3), beryllia (BeO), aluminum nitride (AlN), zirconia toughened alumina (ZTA), silicon carbide (SiC), magnesium silicon carbide (Mg-SiC), silicon nitride (Si3N4), or a combination thereof.

[0133]

[0158] Embodiment 5: The assembly of any preceding or subsequent embodiment, wherein the insulator is alumina (Al2O3) having a purity of 96% or greater.

[0134]

[0159] Embodiment 6: The assembly of any preceding or subsequent embodiment, wherein the insulator includes a plurality of through holes through a thickness of the insulator and a braze layer to a top surface of the insulator penetrates the through holes to bond the insulator to the flange.

[0135]

[0160] Embodiment 7: The assembly of any preceding or subsequent embodiment, wherein the flange is a highly thermally conductive material having a thermal conductivity in the range of 140 to 2000 W / (mK) and a coefficient of thermal expansion (CTE) in the range of 2.3 ppm / K to 17.5 ppm / K at room temperature.

[0136]

[0161] Embodiment 8: The assembly of any preceding or subsequent embodiment, wherein the flange comprises a diamond-based composite, Cu-CuMo-Cu (CPC), copper tungsten (CuW), Cu-Mo-Cu (CMC), Cu, or a combination thereof.

[0137]

[0162] Embodiment 9: The assembly of any preceding or subsequent embodiment, further comprising a first conductive alloy preform for adhering the insulator to the flange, the first conductive alloy preform contacting the first coating and the second coating.

[0138]

[0163] Embodiment 10: The assembly of any preceding or subsequent embodiment, further comprising one or more leads, at least one of the one or more leads having a width of 0.35 microns or less, and a second conductive alloy preform for adhering the one or more leads to the insulator, the second conductive alloy preform in contact with the third coating and the one or more leads.

[0139]

[0164] Embodiment 11: The assembly of any preceding or subsequent embodiment, wherein at least one of the first and second conductive alloy preforms is a silver-copper (Ag-Cu) alloy or a gold-tin (Au-Sn) alloy.

[0140]

[0165] Embodiment 12: The assembly of any preceding or subsequent embodiment, wherein the one or more leads comprise an alloy having a chemical composition of 30-80 wt% nickel (Ni) and balance iron (Fe), a thermal conductivity in the range of 9.5 W / (mK) to 11.5 W / (mK), and at least one of a spacing distance between at least two of the one or more leads of 0.35 microns or less.

[0141]

[0166] Embodiment 13: The assembly of any preceding or subsequent embodiment, further comprising a cover forming a cavity with an insulator for partially enclosing the die.

[0142]

[0167] Embodiment 14: The assembly of any preceding or subsequent embodiment, wherein the cover is alumina (Al2O3), aluminum nitride (AlN), liquid crystal polymer (LCP), or a combination thereof.

[0143]

[0168] Embodiment 15: A method for making a microelectronic package assembly comprising the steps of depositing a first coating having a thickness of 1 micron or less on opposing surfaces of a flange and an insulator, the flange being a highly thermally conductive material having a thermal conductivity in the range of 140 to 2000 W / (mK) and a coefficient of thermal expansion (CTE) in the range of 2.3 ppm / K to 17.5 ppm / K at room temperature; positioning a first conductive alloy preform between the flange and the coated surfaces of the insulator; depositing a second coating to a thickness of 1 micron or less on at least a portion of a top surface of the insulator. forming an at least partially coated top surface using a second conductive alloy preform; directly bonding one or more leads to the at least partially coated top surface using a second conductive alloy preform to enable the one or more leads to have a narrow width of 0.35 microns or less; adhering the first conductive preform to the insulator and flange and the second conductive preform to the insulator and leads at a temperature of 850° C. or greater, wherein depositing at least one of the first coating and the second coating comprises physical vapor deposition, atomic deposition, or chemical deposition.

[0144]

[0169] Embodiment 16: The method of any preceding or subsequent embodiment, wherein the first coating comprises titanium, copper, an alloy thereof, a sublayer thereof, or a combination thereof, and the second coating comprises titanium, copper, an alloy thereof, a sublayer thereof.

[0145]

[0170] Embodiment 17: The method of any preceding or subsequent embodiment, wherein the step of depositing at least one of the first coating and the second coating includes depositing two or more sublayers, wherein the first sublayer is titanium and the second sublayer is copper, and wherein the first sublayer is between 15% and 35% of the total coating thickness and the second sublayer is between 65% and 85% of the total coating thickness.

[0146]

[0171] Embodiment 18: The method of any preceding or subsequent embodiment, further comprising attaching a cover to form a cavity for the die, wherein the cover comprises a liquid crystal polymer, wherein the cover is alumina (Al2O3), aluminum nitride (AlN), liquid crystal polymer (LCP), or a combination thereof.

[0147]

[0172] Embodiment 19: The method of any preceding or subsequent embodiment, further comprising forming a plurality of through holes through the thickness of the insulator prior to coating, and after depositing the second coating, comprising brazing a layer to the top surface of the insulator so as to penetrate the through holes, bonding the insulator to the flange.

[0148]

[0173] Embodiment 20: The method of any preceding or subsequent embodiment, wherein the step of depositing the second coating includes depositing over the entire top surface of the insulator, and further includes selectively laser ablating the second coating to form the circuitry.

[0149]

[0174] Embodiment 21: A microelectronic package assembly comprising: a flange having a top surface, the flange being a highly thermally conductive material having a thermal conductivity in the range of 140 to 2000 W / (mK) at room temperature and a coefficient of thermal expansion (CTE) in the range of 2.3 ppm / K to 17.5 ppm / K; a first coating disposed on the top surface having a thickness of 1 micron or less; an insulator for partially surrounding and mounting a die, the insulator having a bottom surface, a second coating disposed on the bottom surface of the insulator; and a conductive alloy preform for adhering the insulator to the flange, the conductive alloy preform in contact with the first and second coatings.

[0150]

[0175] Embodiment 22: A microelectronic package assembly comprising: a flange having an insulator mounted thereon, the insulator having a top surface, a first coating disposed on the top surface of the insulator having a thickness of 1 micron or less; one or more leads, at least one of the one or more leads having a width of 0.35 microns or less; and a conductive alloy preform for adhering the one or more leads to the insulator, the microelectronic package assembly comprising the first coating and the conductive alloy preform in contact with the one or more leads.

[0151]

[0176] Embodiment 23: A microelectronic package assembly comprising: a flange having an insulator and a die mounted thereon, the insulator partially surrounding the die; a leadframe including a plurality of leads surrounding the die on a surface of the insulator opposite the flange; and a cover including a liquid crystal polymer to form a cavity for the die, the cover being adhered to the leadframe by a non-conductive adhesive.

[0152]

[0177] Embodiment 24: A microelectronic package assembly, comprising: a flange having a top surface, the flange being a highly thermally conductive material having a thermal conductivity in the range of 140 to 2000 W / (mK) at room temperature and a coefficient of thermal expansion (CTE) in the range of 2.3 ppm / K to 17.5 ppm / K; a first coating disposed on the top surface of the flange having a thickness of 1 micron or less; an insulator for partially surrounding and mounting a die, the insulator having a bottom surface and a top surface opposite the flange, a second coating disposed on the bottom surface of the insulator having a thickness of 1 micron or less; a first conductive alloy preform for adhering the insulator to the flange, the first and second coatings being disposed on the bottom surface of the insulator. a first conductive alloy preform contacting a die, a third coating disposed on a portion of a top surface of the insulator having a thickness of 1 micron or less, the third coating being the same as the second coating; a lead frame including a plurality of leads configured to surround a die on the top surface of the insulator; a second conductive alloy preform for adhering the lead frame to the insulator, the second conductive alloy preform contacting the third coating and the plurality of leads; and a cover including a liquid crystal polymer for forming a cavity for the die, the cover being adhered to the lead frame by a non-conductive adhesive.

[0153]

[0178] Embodiment 25: A method for making a microelectronic package assembly, comprising the steps of depositing a coating having a thickness of 1 micron or less on opposing surfaces of a flange and an insulator, wherein the flange is a highly thermally conductive material having a thermal conductivity in the range of 140 to 2000 W / (mK) and a coefficient of thermal expansion (CTE) in the range of 2.3 ppm / K to 17.5 ppm / K at room temperature; positioning a conductive alloy preform between the coated surfaces of the flange and the insulator; and adhering the conductive alloy preform to the flange and the insulator at a temperature of 850° C. or greater.

[0154]

[0179] Embodiment 26: A method for attaching leads to a microelectronic package assembly, comprising the steps of: attaching an insulator to a flange, the surface opposite the flange being a top surface of the insulator; depositing a coating on a portion of the top surface of the insulator to a thickness of 1 micron or less; and directly bonding one or more leads to the coated top surface using a conductive alloy preform to enable the one or more leads to have a narrow width of 0.35 microns or less.

[0155]

[0180] Embodiment 27: A method for covering a microelectronic package assembly, comprising the steps of: attaching an insulator to a flange, wherein a die is attached to the flange or to the insulator; forming a lead frame including a plurality of leads configured to surround the die on a surface of the insulator opposite the flange; and forming a cavity for the die by adhering a liquid crystal polymer cover to the lead frame with a non-conductive adhesive.

[0156]

[0181] Embodiment 28: A method for making a microelectronic package assembly comprising the steps of depositing a first coating having a thickness of 1 micron or less on opposing surfaces of a flange and an insulator, the flange being a highly thermally conductive material having a thermal conductivity in the range of 140 to 2000 W / (mK) at room temperature and a coefficient of thermal expansion (CTE) in the range of 2.3 ppm / K to 17.5 ppm / K; positioning a first conductive alloy preform between the flange and the coated surfaces of the insulator; depositing a second coating to a thickness of 1 micron or less on a portion of a top surface of the insulator to partially coat the second coating. forming a coated top surface; directly bonding one or more leads to the at least partially coated top surface using a second conductive alloy preform to enable the one or more leads to have a narrow width of 0.35 microns or less; bonding the first conductive preform to the insulator and flange and the second conductive preform to the insulator and leads at a temperature of 850° C. or greater; and attaching a cover comprising a liquid crystal polymer to form a die cavity, the cover being bonded to the lead frame by a non-conductive adhesive.

[0157]

[0182] Embodiment 29: The assembly of any preceding or subsequent embodiment, wherein the flange is a highly thermally conductive material having a thermal conductivity in the range of 140 to 650 W / (mK) and a CTE in the range of 5.5 ppm / K to 17.5 ppm / K at room temperature.

[0158]

[0183] Embodiment 30: The assembly of any preceding or subsequent embodiment, wherein the flange is a highly thermally conductive material having a thermal conductivity in the range of 140 to 400 W / (mK) and a CTE in the range of 5.5 ppm / K to 17.5 ppm / K at room temperature.

[0159]

[0184] Embodiment 31: The assembly of any preceding or subsequent embodiment, wherein the flange is a highly thermally conductive material having a thermal conductivity in the range of 500 to 600 W / (mK) at room temperature and a CTE in the range of 6.0 ppm / K to 10.5 ppm / K.

[0160]

[0185] Embodiment 32: The assembly of any preceding or subsequent embodiment, wherein the flange comprises a diamond-based composite, Cu-CuMo-Cu (CPC), copper tungsten (CuW), Cu-Mo-Cu (CMC), Cu, or a combination thereof.

[0161]

[0186] Embodiment 33: The assembly of any preceding or subsequent embodiment, wherein the flange comprises Cu-CuMo-Cu (CPC), copper tungsten (CuW), Cu-Mo-Cu (CMC), Cu, or a combination thereof.

[0162]

[0187] Embodiment 34: The assembly of any preceding or subsequent embodiment, wherein the flange comprises a copper diamond composite or a silver diamond composite.

[0163]

[0188] Embodiment 35: The assembly of any preceding or subsequent embodiment, wherein at least one of the first and second coatings comprises titanium, copper, an alloy thereof, or a combination thereof.

[0164]

[0189] Embodiment 36: The assembly of any preceding or subsequent embodiment, wherein at least one of the first and second coatings is applied by physical vapor deposition (PVD).

[0165]

[0190] Embodiment 37: The assembly of any preceding or subsequent embodiment, wherein the first and second coatings do not include nickel.

[0166]

[0191] Embodiment 38: The assembly of any preceding or subsequent embodiment, wherein at least one of the first and second conductive alloy preforms is a solder alloy.

[0167]

[0192] Embodiment 39: The assembly of any preceding or subsequent embodiment, wherein at least one of the first and second conductive alloy preforms is a silver-copper (Ag-Cu) alloy or a gold-tin (Au-Sn) alloy.

[0168]

[0193] Embodiment 40: The assembly of any preceding or subsequent embodiment, wherein the insulator comprises sapphire, alumina (Al2O3), beryllia (BeO), aluminum nitride (AlN), zirconia toughened alumina (ZTA), silicon carbide (SiC), magnesium silicon carbide (Mg-SiC), silicon nitride (Si3N4), or a combination thereof.

[0169]

[0194] Embodiment 41: The assembly of any preceding or subsequent embodiment, wherein the insulator comprises sapphire, alumina (Al2O3), aluminum nitride (AlN), or a combination thereof.

[0170]

[0195] Embodiment 42: The assembly of any preceding or subsequent embodiment, wherein the insulator is alumina (Al2O3) having a purity of 96% or greater.

[0171]

[0196] Embodiment 43: The assembly of any preceding or subsequent embodiment, wherein the insulator includes a plurality of through holes extending through a thickness of the insulator.

[0172]

[0197] Embodiment 44: The assembly of any preceding or subsequent embodiment, wherein a plurality of through holes are configured in a pattern along a peripheral region of the insulator.

[0173]

[0198] Embodiment 45: The assembly of any preceding or subsequent embodiment, wherein the insulator further comprises a nickel plate on the coated bottom and top surfaces, the nickel plate having a thickness of 1.0 to 3.5 microns.

[0174]

[0199] Embodiment 46: The assembly of any preceding or subsequent embodiment, wherein the one or more leads comprise an alloy of iron, nickel, or a combination thereof.

[0175]

[0200] Embodiment 47: The assembly of any preceding or subsequent embodiment, wherein the one or more leads comprise an alloy having a chemical composition of 30-80 wt% nickel (Ni) and the balance iron (Fe).

[0176]

[0201] Embodiment 48: The assembly of any preceding or subsequent embodiment, wherein one or more leads have a thermal conductivity in the range of 9.5 W / (mK) to 11.5 W / (mK).

[0177]

[0202] Embodiment 49: The assembly of any preceding or subsequent embodiment, wherein at least two of the one or more leads have a spacing distance of 0.35 microns or less.

[0178]

[0203] Embodiment 50: The assembly of any preceding or subsequent embodiment, further comprising a cover to form a cavity in the die.

[0179]

[0204] Embodiment 51: The assembly of any preceding or subsequent embodiment, wherein the cover is alumina (Al2O3), aluminum nitride (AlN), liquid crystal polymer (LCP), or a combination thereof.

[0180]

[0205] Embodiment 52: The assembly of any preceding or subsequent embodiment, wherein the cover includes a non-conductive adhesive configured to provide a seal.

[0181]

[0206] Embodiment 53: The assembly of any preceding or subsequent embodiment, wherein the die comprises gallium nitride (GaN), gallium arsenide (GaAs), silicon (Si), or a combination thereof.

[0182]

[0207] Embodiment 54: The method of any preceding or subsequent embodiment, wherein the step of depositing the coating comprises physical vapor deposition, atomic deposition, or chemical deposition.

[0183]

[0208] Embodiment 55: The method of any preceding or subsequent embodiment, wherein the step of depositing the coating comprises physical vapor deposition.

[0184]

[0209] Embodiment 56: The method of any preceding or subsequent embodiment, wherein the step of depositing the coating comprises depositing two or more sublayers.

[0185]

[0210] Embodiment 57: The method of any preceding or subsequent embodiment, wherein the first sublayer is titanium and the second sublayer is copper.

[0186]

[0211] Embodiment 58: The method of any preceding or subsequent embodiment, wherein the first sublayer is 25%±10% of the total coating thickness and the second sublayer is 75%±10% of the total coating thickness.

[0187]

[0212] Embodiment 59: The method of any preceding or subsequent embodiment, wherein the attaching step includes welding the die with a gold and tin alloy.

[0188]

[0213] Although the present invention has been described in detail, modifications within the spirit and scope of the present invention will be readily apparent to those skilled in the art. In consideration of the above discussion, the relevant knowledge in the art, and the references discussed above in connection with the background art and the detailed description, all of these disclosures are incorporated herein by reference. In addition, it should be understood that the aspects of the present invention and various embodiments and various features described below and / or in the appended claims can be combined or interchanged in whole or in part. In the above description of various embodiments, an embodiment that refers to another embodiment can be appropriately combined with other embodiments as understood by those skilled in the art. Furthermore, those skilled in the art will understand that the above description is merely illustrative and is not intended to be limiting.

Claims

1. 1. A microelectronic package assembly comprising: a flange having an upper surface, the flange being a highly thermally conductive material having a thermal conductivity in the range of 140 to 2000 W / (mK) and a coefficient of thermal expansion (CTE) in the range of 2.3 ppm / K to 17.5 ppm / K at room temperature; a first coating disposed on the upper surface of the flange; an insulator for partially enclosing the die, the insulator having a bottom surface for mounting on said flange and a top surface opposite said bottom surface; a second coating disposed on the bottom surface of the insulator, and a third coating disposed on the top surface of the insulator. wherein the first coating, the second coating, and the third coating each have a thickness of 1 micron or less, and at least one of the first coating, the second coating, and the third coating is applied by at least one of physical vapor deposition, atomic deposition, or chemical deposition.

2. 10. The microelectronic package assembly of claim 1, wherein at least one of the first coating, the second coating, and the third coating comprises titanium, copper, an alloy thereof, a sublayer thereof, or a combination thereof.

3. The microelectronic package assembly of claim 1, wherein each of the first coating, the second coating, and the third coating is nickel-free.

4. The insulator is made of sapphire, alumina (Al ２ O ３ ), Beryllia (BeO), Aluminum Nitride (AlN), Zirconia Toughened Alumina (ZTA), Silicon Carbide (SiC), Magnesium Silicon Carbide (Mg-SiC), Silicon Nitride (Si ３ N ４ 10. The microelectronic package assembly of claim 1, comprising:

5. The insulator is made of alumina (Al ２ O ３ 5. The microelectronic package assembly of claim 4, wherein

6. 2. The microelectronic package assembly of claim 1, wherein the insulator includes a plurality of through holes extending through a thickness of the insulator, and a braze layer on the top surface of the insulator penetrates the through holes to bond the insulator to the flange.

7. The microelectronic package assembly of claim 1, wherein the flange comprises a diamond-based composite, Cu-CuMo-Cu (CPC), copper tungsten (CuW), Cu-Mo-Cu (CMC), Cu, or a combination thereof.

8. 10. The microelectronic package assembly of claim 1, further comprising a first conductive alloy preform for bonding said insulator to said flange, said first conductive alloy preform contacting said first coating and said second coating.

9. The microelectronic package assembly of claim 8, further comprising: one or more leads, at least one of the one or more leads having a width of 0.35 microns or less; and a second conductive alloy preform for adhering the one or more leads to the insulator, the second conductive alloy preform contacting the third coating and the one or more leads.

10. 10. The microelectronic package assembly of claim 9, wherein at least one of the first and second conductive alloy preforms is a silver-copper (Ag-Cu) alloy or a gold-tin (Au-Sn) alloy.

11. the one or more leads An alloy having a chemical composition of 30-80 wt. % nickel (Ni) and the balance iron (Fe); A thermal conductivity in the range of 9.5 W / (mK) to 11.5 W / (mK), and a spacing distance between at least two of said one or more leads of 0.35 microns or less; The microelectronic package assembly of claim 9 , comprising at least one of:

12. The microelectronic package assembly of claim 1 further comprising a cover forming a cavity with said insulator for partially enclosing said die.

13. The microelectronic package assembly of claim 12, wherein the cover is alumina (Al 2 O 3 ), aluminum nitride (AlN), liquid crystal polymer (LCP), or a combination thereof.

14. 1. A method for making a microelectronic package assembly, the method comprising: depositing a first coating having a thickness of 1 micron or less on opposing surfaces of the flange and the insulator, the flange being a highly thermally conductive material having a thermal conductivity in the range of 140 to 2000 W / (mK) at room temperature and a coefficient of thermal expansion (CTE) in the range of 2.3 ppm / K to 17.5 ppm / K; depositing a second coating on at least a portion of an upper surface of the insulator to a thickness of 1 micron or less to form an at least partially coated upper surface; wherein depositing at least one of the first coating and the second coating comprises physical vapor deposition, atomic deposition, or chemical deposition.

15. The method of claim 14 , wherein the first coating comprises titanium, copper, an alloy thereof, a sublayer thereof, or a combination thereof, and the second coating comprises titanium, copper, an alloy thereof, a sublayer thereof, or a combination thereof.

16. The method of claim 14, wherein the step of depositing at least one of the first coating and the second coating includes depositing two or more sublayers, a first sublayer being titanium and a second sublayer being copper, the first sublayer being 15% to 35% of a total coating thickness and the second sublayer being 65% to 85% of a total coating thickness.

17. The method further includes attaching a cover to form a cavity for the die, the cover comprising a liquid crystal polymer, and the cover being made of alumina (Al ２ O ３ ), aluminum nitride (AlN), liquid crystal polymer (LCP), or a combination thereof.

18. 15. The method of claim 14, further comprising forming a plurality of through holes through a thickness of the insulator prior to coating, and comprising, after depositing a second coating, brazing a layer on the top surface of the insulator so as to penetrate the through holes to bond the insulator to the flange.

19. 15. The method of claim 14, wherein depositing a second coating comprises depositing over the entire top surface of the insulator, and further comprising selectively laser ablating the second coating to form circuitry.

20. The method of claim 14, further comprising the steps of: positioning a first conductive alloy preform between the flange and the coated surface of the insulator; directly bonding one or more leads to the at least partially coated top surface using a second conductive alloy preform to enable one or more leads to have a narrow width of 0.35 microns or less; and adhering the first conductive preform to the insulator and the flange, and the second conductive preform to the insulator and the leads, at a temperature of 850°C or greater.

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