Hybrid Library Latch Array

Abstract

A static random access memory (SRAM) includes fast SRAM bit cells and fast multiplexer circuits formed in a first row of fast cells in a hybrid standard cell architecture. Slower SRAM bit cells and slower multiplexer circuits are formed in a second row of slower cells. The slower multiplexer circuits provide column outputs to the faster SRAM bit cells and the faster multiplexer circuits provide column outputs to the slower SRAM bit cells. Thus, one SRAM column has fast bit cells and a slower multiplexer stage while an adjacent SRAM column has slower bit cells and a faster multiplexer stage, thereby providing an improved performance balance when reading the SRAM.

Description

[Technical field]

[0001] This application relates to SRAMs and SRAM bit cells. SRAMs traditionally use 6T or 8T bit cells. Because SRAMs typically contain a large number of bit cells, ensuring the efficiency of SRAM bit cell area utilization is important to reduce the cost of SRAMs in terms of silicon area utilized. Summary of the Invention [Means for solving the problem]

[0002] Disclosure of embodiments of the present invention Thus, in one embodiment, a static random access memory (SRAM) includes a first plurality of bit cells and a first plurality of multiplexer circuits. The SRAM further includes a second plurality of bit cells and a second plurality of multiplexer circuits. The first plurality of bit cells are coupled to a first multiplexer circuit of the second plurality of multiplexer circuits, and the second plurality of bit cells are coupled to a second multiplexer circuit of the first plurality of multiplexer circuits. The first plurality of bit cells and the first plurality of multiplexer circuits have a first performance level, and the second plurality of bit cells and the second plurality of multiplexer circuits have a second performance level that is lower than the first performance level.

[0003] In another embodiment, a method for operating a static random access memory (SRAM) includes providing first bitcell outputs from a first plurality of bitcells to a first multiplexer, the first plurality of bitcells having a first performance level and the first multiplexer having a second performance level lower than the first performance level. The first multiplexer provides one of the first bitcell outputs as a first multiplexer output signal from the first multiplexer. The method further includes providing a second bitcell output from a second plurality of bitcells having the second performance level to a second multiplexer having the first performance level. The second multiplexer provides one of the second bitcell outputs as a second multiplexer output signal.

[0004] A static random access memory (SRAM) includes a first plurality of SRAM bit cells and a first multiplexer circuit formed from standard cells in a first row of cells having a first performance level. A second plurality of SRAM bit cells and a second multiplexer circuit are formed in a second row of cells having a second performance level lower than the first performance level. The second multiplexer circuit receives first outputs of each of the first plurality of bit cells and selects one of the respective first outputs as a second multiplexer output signal. The first multiplexer circuit receives second outputs of each of the second plurality of SRAM bit cells and selects one of the respective second outputs as a first multiplexer output signal.

[0005] The present invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings. [Brief description of the drawings]

[0006] [Figure 1] FIG. 2 illustrates an embodiment of a latch bit cell, according to one embodiment. [Diagram 2] FIG. 2 illustrates an exemplary layout of a latch bit cell. [Diagram 3] FIG. 13 illustrates how different threshold voltages can be used in the read and write portions of a latch bit cell. [Figure 4] FIG. 2 shows a column of 32 latch bit cells. [Diagram 5] FIG. 2 is a high-level block diagram of two columns, each having 64 rows of latch bit cells. [Figure 6] FIG. 2 illustrates one embodiment of a write masked latch bit cell. [Figure 7] FIG. 13 illustrates a layout of a write masked latch bit cell. [Figure 8] FIG. 13 illustrates another embodiment of a write masked latch bit cell. [Figure 9] FIG. 1 illustrates one embodiment of a pulse generator for generating a WRZERO or WRONEX pulse. [Figure 10] FIG. 9 illustrates a layout of the write masked latch bit cell of FIG. 8. [Figure 11] 2 illustrates one embodiment of a column formed by the latch bit cells of FIG. 1. [Figure 12A] FIG. 1 illustrates a conventional standard cell architecture having two fins per transistor finger. [Figure 12B] FIG. 1 illustrates a hybrid standard cell architecture with alternating two fins per transistor finger and one fin per transistor finger. [Figure 12C] FIG. 1 is a high-level block diagram of a finfet with one fin per transistor finger and two fins per transistor finger. [Figure 13] FIG. 1 illustrates an embodiment of a latch bit cell array utilizing a hybrid standard cell library. [Figure 14] FIG. 14 illustrates an embodiment of a latch bit cell array that utilizes a hybrid standard cell library that provides more balanced performance than the embodiment of FIG. [Figure 15] FIG. 2 is a high-level block diagram of one embodiment of a latch bit cell array. [Figure 16] FIG. 2 is a high-level block diagram of one embodiment of a latch bit cell array using masked write bit cells. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] The use of the same symbols in different drawings indicates similar or identical items.

[0008] Eight transistor (8T) static random access memory (SRAM) arrays have not scaled well in terms of area at newer technology nodes. However, circuits built with standard cell design rules continue to scale relatively well at newer technology nodes. Building SRAM arrays with standard cell design rules allows for the use of smaller areas even when more transistors are present. FIG. 1 shows an SRAM bitcell implemented as a latch bitcell 100 with separate read and write ports. Note that the latch bitcell 100 uses 12 transistors per bit compared to 8 transistors in an 8T SRAM bitcell, but still uses less area for a given fabrication technology due to the use of standard cell design rules. A significant difference between latch type bitcells and classical 6T / 8T SRAM bitcells is that latch bitcells disable feedback during writes. In contrast, in a 6T / 8T bitcell, the pass gates must resist pull-ups to perform a write. A latch bitcell has no such contention during writes.

[0009] The approach of FIG. 1 implemented using standard cell design rules means that there is no overhead required for using custom SRAM macros, thereby reducing area. For example, the use of standard cell layout rules allows for the abutment of 0 connected poly pitch (CPP) (horizontal distance between transistors) to standard cell logic. More traditional approaches to SRAM have border and edge cells required for lithography purposes. Because standard cell design rules scale well, implementing the latch bit cell 100 and SRAM cells based on standard cell design rules allows SRAM designs to scale in area in the same way as future standard architectures.

[0010] The latch bitcell shown in FIG. 1 amortizes the local inverters that are typically present in latches across many more cells. The latch bitcell shown in FIG. 1 eliminates the local inverters that would traditionally be used on the inputs to the latch, including the write bit line (WBL), the write word line (WWL), the active low write word line (WWLX), the read word line (RWL), and the active low read word line (RWLX). In more traditional latch arrays, CMOS combinational stages are used between the latches. The latch bitcell 100 uses tri-state outputs to the RBL 101. The use of tri-state drivers by the latch bitcell allows the outputs (read bit lines) of several cells, e.g., 16 cells, to be combined together using tri-state output drivers to avoid any additional combinational stages (such as NOR / NANDing) of the output data.

[0011] FIG. 2 shows a stick layout of latch bit cell 100 showing seven transistors in the horizontal direction. Boxes indicate the source / drain connections of the transistors. The gate regions of the transistors are shown as vertical lines with the same labels as the transistors in FIG. 1. The long vertical line 201 indicates the shared gate connections, for example with transistors PFBO and NFBO and transistors PINV and NINV. Where there is white space in the boxes, there are nodes that are not named in FIG. 1, but the source / drain connections and gate connections that are not identified can be easily seen in FIG. 1. The layout includes dummy cell (DUM) transistors. Dummies are transistors that are formed but not connected. The use of dummy transistors provides an efficient way to provide isolation between other transistors. The use of dummy transistors also provides an advantage in the ability to change the type of transistor used with respect to threshold voltage (Vt). In an embodiment, the write portion of the latch (transistors PPG, NPG, PINV, NINV, NFB1, NFB0, PFB0, PFB1) does not require high performance, but the read portion of the latch (transistors PRP1, PRP0, NRP0, NRP1) does require high performance. Note that the first letter of the transistor name refers to the type of transistor (N or P) and the remaining letters refer to its function (PG is pass gate, INV is inverter, FB is feedback, RP is read port).

[0012] Referring to FIG. 3, this allows the read portion 301 of the latch bitcell 100, including transistors PRP0, PRP1, NRP0, and NRP1, to be implemented using lower Vt transistors (such as ultra-low Vt (ulvt)), thereby providing the required high performance, while the write portion 303 of the latch bitcell 100 to the left of the dummy transistors in FIG. 3 is implemented with higher threshold voltage transistors (such as low Vt (lvt) transistors). The higher Vt transistors provide lower performance, but also less leakage, and the lower Vt transistors are utilized only when required for performance. This layout option thus allows different threshold voltages to be utilized for the read and write ports, which have different performance requirements, thereby allowing leakage current to be reduced compared to having to use lower Vt devices for all devices to meet performance requirements for only a portion of the bitcell. The transistors in the read and write ports share diffusion between neighboring cells, reducing the xtor (transistor) load by half, if possible, over a non-optimized design.

[0013] Referring again to FIG. 1, the operation of the latch bit cell 100 will be described. Data to be written to the cell on the write bit line WBL 102 (also referred to herein as write data (WD)) is provided to a pass gate 103 formed from transistors NPG and PPG. The gates or transistors are coupled to the write word line (WWL) and write word line X (WWLX), respectively, where "X" represents the signal active low. When WWL and WWLX are asserted, the data on WBL is passed as data "D" to an inverter 104 formed by transistors PINV and NINV. Transistors NFB1 and PFB1 are turned off when WWL and WWLX are asserted. The gates of NFB0 and PFB0 in the feedback portion of the bit latch cell 100 receive the output D_X (the inverse value of "D") from the inverter. The gates of PRP1 and NRP1 in the read portion 106 of the latch also receive D_X. When WWL and WWLX are deasserted, pass gate 103 is cut off and transistors NFB1 and PFB1 are turned on, which allows D_X to turn on either transistor NFB0 or ​​PFB0 to provide "D" as a feedback signal. Transistors NFB1, NFB0, PFB0, and PFB1 act as a keeper circuit 108, which, together with an inverter formed by transistors PINV and NINV, ensures that the data on node D is maintained when WWL and WWLX are deasserted. In this way, the value of D is maintained in the write portion of latch bit cell 100 and is available when the latch is read. In latch bit cell 100, PMOS transistors PINV, PFB1, and PRP1 are coupled at their sources to a power supply voltage (VDD). NMOS transistors NINV, NFB1, and NRP1 are coupled at their sources to a second power supply voltage (ground).

[0014] To read a latch bit cell, the read word line (RWL) and RWLX are asserted, turning on NRP0 and PRP0, respectively. Note that "X" denotes an active low signal. The assertion of RWL and RWLX allows the value of D_X to determine the value of the output signal read bit line (RBL) 101, also referred to herein as read data (RD). When RWL and RWLX are deasserted, RBL is set to high impedance, allowing other SRAM cells to drive RBL if they are selected to be read.

[0015] Figure 4 shows an embodiment where a group of 32 latch bit cells are formed into two groups of latch bit cells (bits <31:16> and bits <15:0>). Each group of latch bit cells feeds a bit to a multiplexer 401, which selects a bit from either bits <31:16> or bits <15:0> and provides the selected bit on rdData 403. In the embodiment of Figure 4, a three-state driver on the read side of the latch bit cells allows 16 bits (only one active at a time) to drive the same RBL that is fed to multiplexer 401. Therefore, only one RWL / RWLX is on at a time in each group [31:16] and [15:0] to ensure that multiple latch bit cells do not drive RBL at the same time, which can cause a high current situation. It is also important to ensure that any of the RWL / RWLX signals are active and any of the bitcells drive either a high or low logic level on RBL. Any RWL / RWLX pair that is deasserted will result in a floating node on RBL, which can cause high current draw in downstream CMOS gates that receive signals halfway between VDD and VSS.

[0016] FIG. 5 shows a block diagram of an embodiment having 64 rows and 2 columns of bit cells, with multiplexer 501 selecting one bit from the 64 rows and 2 columns. Although not shown in FIG. 5 for ease of illustration, the embodiment shown in FIG. 5 also requires a write column multiplexer function. One way to achieve this is to provide a WWL / WWLX pair to the even physical columns and another WWL / WWLX pair to the odd physical columns. In this way, every other cell can be written. Another way to achieve the write multiplexer function is to use a write mask, as described further herein.

[0017] During a write operation, when the word line for a particular word line is asserted, all the bits in the word line can change state. It is advantageous to write only to selected cells of a word line rather than changing the state of all the bits in the word line, which helps make the write operation more efficient. Thus, in another embodiment shown in FIG. 6, the latch bit cell 600 includes a write mask. The write mask utilizes a write one x (WRONEX) signal (where "X" represents the signal is active low) and a write zero (WRZERO) signal. The write mask circuit is formed of transistors PWD 601 and NWD 603, where WD represents write data. When WRONEX is asserted (active low), the write data (WD) node is pulled high through transistor PWD, and when WRZERO is asserted, the WD node is pulled low through transistor NWD. The write mask allows the write word line for a row of cells to be asserted without changing the state of all the cells. For example, only one byte or a few bits on the word line can be changed by asserting the word line and using a write mask to ensure that only the cells of interest are written. In addition to transistors PWD and NWD used to determine the value of WD, write masked latch bit cell 600 includes transistors NFB2 and PFB2 used in keeper circuit 605. These transistors are used to ensure that the feedback function of the keeper circuit continues to operate so that the latch bit cell maintains its state even when WWL and WWLX are asserted. If WWLX is asserted, NFB1 is off, and if WWL is asserted, PFB1 is off. Transistors NFB2 and PFB2 ensure that if the bit has a write mask that effectively prevents the latch bit cell from being written, the keeper circuit continues to drive "D" with the correct value from the node between NFB0 and PFB0 when WWL and WWLX are asserted. Note that WD floats when WRONEX and WRZERO are deasserted.By incorporating the PWD and NWD transistors into the bitcell itself, the capacitance on the intermediate node WD is kept low enough to avoid cell stability issues when WWL / WWLX are asserted. The keeper stack (KSTK) nodes PKSTK 602 and NKSTK 604 are labeled in FIG.

[0018] Figure 7 is a stick diagram of the layout of the write masked latch bit cell 600 shown in Figure 6. Note that the solution of Figure 6 increases the size of the cell by four transistors and includes an extra dummy cell compared to the layout shown in Figure 2. Thus, the write masked latch bit cell 600 (Figure 6) represents an increase of 3 CPP to 10 CPP compared to the layout of Figure 2 (7 CPP) for the latch bit cell 100 shown in Figure 1.

[0019] FIG. 8 illustrates a more efficient embodiment of a write masked latch bit cell 800 compared to the write masked latch bit cell 600 of FIG. 6. Note that extra transistors NFB2 and PFB2 coupled to the keeper stack nodes in the write masked latch bit cell 600 replace NFB1 and PFB1 in the write masked latch bit cell 800. The write masked latch bit cell 800 does not disable the keeper circuit 805 by turning off NFB1 and PFB1 when WWL and WWLX are asserted (see FIG. 1 and FIG. 6); instead, the write masked latch bit cell 800 simply disables the keeper in response to WRONEX or WRZERO being asserted. This ensures that the latch bit cell 800 retains state when the latch bit cell 800 is masked. Note that WWL and WWLX are coupled only to the pass gate transistors PPG and NPG in the write masked latch bit cell 800. When WRONEX is asserted (goes active low), transistor NFB2 is turned off, and when WRZERO is asserted, transistor PFB2 is turned off. Assuming that WWLX and WWL are asserted, when WRONEX is asserted, node WD is high and node D is high, and when WRZERO is asserted (goes active low), node WD is low and node D is low. When the respective mask lines (WRONEX and WRZERO) are deasserted, both NFB2 and PFB2 are turned on, and the keeper circuit maintains the value of node D according to the value of D_X provided by the inverter formed by transistors PINV and NINV. D_X either turns on transistor NFB0 to maintain a low value for node D, or turns on PFB0 to maintain a high value for node D. The write mask circuit is formed by transistors PWD801 and NWD803, which is similar to the embodiment shown in FIG. 6.The read side of the write masked latch bit cell 800, formed by transistors PRP1, PRP0, NRP0, NRP1, is identical to the previous latch bit cell embodiments 100 and 600 shown in Figures 1 and 6, respectively.

[0020] Whenever either WRONEX or WRZERO is asserted, the keeper circuits of all bit cells in the column tied to WRONEX and WRZERO are disabled. This is because asserting WRONEX turns off NFB2, preventing D_X from being pulled to VSS via NFB0 and NFB2, and asserting WRZERO turns off PFB2, preventing D_X from being pulled to BDD via PFB0 and PBF2. Thus, node D floats in response to the assertion of WRONEX or WRZERO. If the assertion of WRONEX or WRZERO is long enough, cells along the column can change state because at least some of the keeper circuits are turned off due to NFB1 or PFB1 being disabled by the assertion of WRONEX or WRZERO. Therefore, WRONEX and WRZERO should be asserted as a pulse write. These signals should then be asserted as self-timed pulses several inverter delays long, for example 50 ps. The pulses can be generated using, for example, nine inverters. The number of inverters depends on the technology used. FIG. 9 shows an embodiment of a pulse circuit 901 for WRZERO and a pulse circuit 903 for WRONEX. Note that an odd number of inverters are used in each of the pulse circuits shown in FIG. 9. In FIG. 9, the inputs to the logic gates (write 0 and write 1) are assumed to be active high. Many other pulse generator circuits that provide suitable pulse widths for WRONEX and WRZERO are known to those skilled in the art. The pulse should be long enough to write one cell, but short enough so that other cells along the column do not lose state due to node D floating during the pulse, so the area penalty for the additional write mask capability is relatively small compared to the write masked latch bit cell shown in FIG. 6.

[0021] Figure 10 shows an example layout of the circuit of Figure 8. Note that only one dummy transistor is required for latch bit cell 800. The layout of latch bit cell 800 shown in Figure 10 has only one extra CPP relative to the baseline latch bit cell 100 shown in Figure 2.

[0022] FIG. 11 shows a latch array column of the latch shown in FIG. 1, formed in a single standard cell row. Note that the term "single standard cell row" refers to a physical row of an integrated circuit, not a logical row of an SRAM. In a standard design using a non-hybrid standard cell library convention, all devices typically have the same number of fins. In a traditional standard cell architecture, all rows of devices have the same height. In the finfet world, this also generally means that the number of fins per finger is the same. FIG. 12A shows a traditional standard cell architecture for PFETs and NFETs with two fins per finger. Each standard cell is uniform in the row and has a P and an N transistor.

[0023] The hybrid standard cell architecture utilizes alternating rows of high performance standard cells and high density (but lower performance) standard cells. For example, this means that in one embodiment, the high performance cells have two fins per transistor finger and the lower performance cells have one fin per transistor finger. As shown in FIG. 12B, it results in alternating rows of taller and shorter cells and shorter rows. The advantage of the hybrid standard cell architecture is smaller area and reduced power, but the shorter cell height results in reduced performance compared to the larger two-fin cells. FIG. 12C shows an exemplary one fin per transistor finger device 1201 and two fins per transistor finger device 1203.

[0024] FIG. 13 illustrates that moving from a traditional standard cell library to a hybrid standard cell library approach to constructing a standard cell latch array can result in performance imbalance between adjacent bits. For example, the bit cells in column 1301 are formed from “fast” standard cells, e.g., with two fins per finger. The logical SRAM column 1301 is in a physical fast row of a hybrid row architecture in the illustrated embodiment. The bit cells in column 1303 are “slow” cells, e.g., with one fin per finger. Thus, reading Rddata[1] 1302 from any of the bit cells in column 1301 is faster than reading Rddata[0] 1304 from column 1302. Thus, adjacent bits are read at different times (one fast, the other slow), which is undesirable.

[0025] To provide a more balanced performance between the fast and slow cells, the embodiment shown in FIG. 14 uses a group of bit cells from one column, e.g., bit cells in column 1401 (fast physical row) or 1403 (slow physical row), but uses multiplexer circuits from the other row. For example, slow multiplexer 1407 selects one bit from 32 fast bit cells, which are fast bit cell 1404 (only one of bits <15:0> is shown) and fast bit cell 1406 (only one of bits <31:16> is shown). Fast multiplexer 1415 selects one bit from 32 slow bit cells, which are slow bit cell 1409 (only one of bits <15:0> is shown) and slow bit cell 1411 (only one of bits <31:16> is shown). Similarly, fast bitcells 1421 and 1423 use slow multiplexer 1425, and slow bitcells 1427 and 1429 use fast multiplexer 1431. The read data (Rddata[1]) provided by fast multiplexer 1435 has a fast multiplexer (2 fins) but a slow bitcell (1 fin), and the read data (Rddata[0]) has a slow multiplexer (1 fin) but a fast bitcell (2 fins). Thus, one logical SRAM column has fast bitcells and a slow multiplexer stage, while the adjacent SRAM logical column has slow bitcells and a fast multiplexer stage. This provides an improved performance balance compared to arrays where every other bit has significantly different timing, i.e., fast and slow.

[0026] Figure 15 shows a higher level block diagram of an array of bit cells. While Figure 14 shows the latch bit cells of Figure 1 utilized as the bit cells in columns 1401 and 1403, in other embodiments, other bit cells can be used. Figure 16 shows an embodiment in which the masked write latch bit cell 600 of Figure 6 or the masked write latch bit cell 800 of Figure 8 are utilized. Figure 16 shows that the mask signals WRONEX and WRZERO are distributed to the bit cells.

[0027] Thus, a hybrid cell standard cell architecture is described having alternating rows of high performance and high density standard cells, where the bit cells and multiplexing stages alternate to provide a more balanced read timing. The description of the invention described herein is exemplary and is not intended to limit the scope of the invention as described in the appended claims. Variations and modifications of the embodiments disclosed herein may be made based on the description described herein without departing from the scope of the invention as described in the appended claims.

Claims

1. A static random access memory (SRAM), comprising: a first plurality of bit cells and a first plurality of multiplexer circuits; a second plurality of bit cells and a second plurality of multiplexer circuits; the first plurality of bit cells are coupled to a first multiplexer circuit of the second plurality of multiplexer circuits; the second plurality of bit cells are coupled to a second multiplexer circuit of the first plurality of multiplexer circuits; the first plurality of bit cells and the first plurality of multiplexer circuits have a first performance level, and the second plurality of bit cells and the second plurality of multiplexer circuits have a second performance level that is lower than the first performance level. Static Random Access Memory (SRAM).

2. the SRAM includes alternating rows of first cells having the first performance level and second cells having the second performance level; The SRAM of claim 1.

3. a third plurality of bit cells having the first performance level; a fourth plurality of bit cells having the second performance level; the third plurality of bit cells are coupled to a third multiplexer circuit of the second plurality of multiplexer circuits; the fourth plurality of bit cells being coupled to a fourth multiplexer circuit of the first plurality of multiplexer circuits; The SRAM of claim 1.

4. the first multiplexer circuit and the third multiplexer circuit are coupled to a fifth multiplexer circuit of the second plurality of multiplexer circuits; the second multiplexer circuit and the fourth multiplexer circuit are coupled to a sixth multiplexer circuit of the first plurality of multiplexer circuits. The SRAM of claim 3.

5. the first performance level is determined, at least in part, according to a first number of fins per transistor finger and the second performance level is determined, at least in part, according to a second number of fins per transistor finger, the first number of fins being greater than the second number of fins; The SRAM of claim 1.

6. the first number of fins is two and the second number of fins is one; The SRAM of claim 5.

7. the first plurality of bit cells forming at least a portion of a first column of the SRAM, and the second plurality of bit cells forming at least another portion of a second column of the SRAM. The SRAM of claim 1.

8. the first column and the second column are adjacent in the SRAM; The SRAM of claim 7.

9. each of the first plurality of bit cells and the second plurality of bit cells is a latch bit cell; The SRAM of claim 7.

10. each of the first plurality of bit cells and the second plurality of bit cells is a write masked bit cell; The SRAM of claim 7.

11. 1. A method for operating a static random access memory (SRAM), comprising: providing first bitcell outputs from a first plurality of bitcells having a first performance level to a first multiplexer having a second performance level, the second performance level being lower than the first performance level; providing one of the first bitcell outputs as a first multiplexer output signal from the first multiplexer; providing second bitcell outputs from a second plurality of bitcells having the second performance level to a second multiplexer having the first performance level; providing one of the second bitcell outputs as a second multiplexer output signal. method.

12. providing third bitcell outputs from a third plurality of bitcells having the first performance level to a third multiplexer having the second performance level, the third multiplexer providing a third multiplexer output signal; providing fourth bitcell outputs from a fourth plurality of bitcells having the second performance level to a fourth multiplexer having the first performance level, the fourth multiplexer providing a fourth multiplexer output signal.

12. The method of claim 11.

13. providing the first multiplexer output signal and the third multiplexer output signal to a fifth multiplexer circuit having the second performance level, the fifth multiplexer circuit providing a fifth multiplexer output signal; providing the second multiplexer output signal and the fourth multiplexer output signal to a sixth multiplexer circuit having the first performance level, the sixth multiplexer circuit providing a sixth multiplexer output signal.

13. The method of claim 12.

14. The method of claim 13, further comprising: providing the fifth multiplexer output signal as a read data bit from a first SRAM column; and providing the sixth multiplexer output signal as another read data bit from a second SRAM column adjacent to the first SRAM column.

14. The method of claim 13.

15. the first performance level is determined, at least in part, according to a first number of fins per transistor finger and the second performance level is determined, at least in part, according to a second number of fins per transistor finger, the first number of fins being greater than the second number of fins.

12. The method of claim 11.

16. the first number of fins is two and the second number of fins is one; 16. The method of claim 15.

17. providing the first bitcell output from a first write masked bitcell and the second bitcell output from a second write masked bitcell.

12. The method of claim 11.

18. A static random access memory (SRAM), comprising: a first plurality of SRAM bit cells and a first multiplexer circuit formed in a first row of cells having a first performance level; a second plurality of SRAM bit cells and a second multiplexer circuit formed in a second row of cells having a second performance level lower than the first performance level; the second multiplexer circuit is coupled to receive the first output of each of the first plurality of SRAM bit cells and selects one of the first outputs as a second multiplexer output signal; the first multiplexer circuit is coupled to receive the second outputs of each of the second plurality of SRAM bit cells and selects one of the second outputs as a first multiplexer output signal; Static Random Access Memory (SRAM).

19. the first plurality of SRAM bit cells and the second plurality of SRAM bit cells are in adjacent SRAM columns. The SRAM of claim 18.

20. a third plurality of bit cells in the first row having the first performance level; a fourth plurality of bit cells in the second row having the second performance level; the third plurality of bit cells are coupled to a third multiplexer circuit in the second row, and the fourth plurality of bit cells are coupled to a fourth multiplexer circuit in the first row. The SRAM of claim 18.

Images