Through trench isolation for die

Abstract

The device includes a die (100) having a protective overcoat (128) and a substrate (104), the substrate (104) including a first region (108) and a second region (112) that are spaced apart. The device also includes an isolation dielectric (124) between the protective overcoat (128) and the die (100). A pre-metal dielectric (PMD) barrier (120) is between the isolation dielectric (124) and the substrate (104), the PMD barrier (120) having a first region (136) that contacts the first region of the substrate (108) and a second region that contacts the second region of the substrate (112), the first region (136) and the second region of the PMD barrier (120) being spaced apart. A through trench (132) filled with a polymer dielectric (134) extends between the first region (108) and the second region (112) of the substrate (104) and between the first region (120) and the second region (140) of the PMD (120) and abuts the isolation dielectric (124).

Description

[Technical field]

[0001] The present description relates to a die. In particular, the present description relates to a die with through trenches for isolation between regions of the die. [Background technology]

[0002] In electronics, a wafer (also called a slice) is a thin slice of semiconductor, such as crystalline silicon (c-Si), used for the fabrication of integrated circuits (ICs). The wafer serves as the substrate for the microelectronic devices integrated in and on the wafer. The wafer may undergo many microfabrication processes, such as doping, ion implantation, etching, thin film deposition of various materials, and photolithographic patterning. Finally, the individual dies containing the microcircuits are separated by wafer dicing and packaged as integrated circuits.

[0003] Parylene is an organic polymer that contains hydrogen (H) and carbon (C) atoms. Parylene is hydrophobic and resistant to many chemicals. Coatings of parylene are often applied to electronic circuits and other devices as electrical insulation, a moisture barrier, or protection against corrosion and chemical attack. Parylene coatings are applied by chemical vapor deposition in an atmosphere of the monomer paraxylylene. Summary of the Invention

[0004] A first example relates to a device including a die with a protective overcoat and a substrate, the substrate having a first region and a second region spaced apart. The device also includes an isolation dielectric between the protective overcoat and the die. A premetal dielectric (PMD) barrier is between the isolation dielectric and the substrate, the PMD barrier having a first region that contacts the first region of the substrate and a second region that contacts the second region of the substrate, the first and second regions of the PMD barrier being spaced apart. A through trench filled with a polymer dielectric extends between the first and second regions of the substrate and between the first and second regions of the PMD barrier and contacts the isolation dielectric.

[0005] A second example relates to a method of forming a device. The method includes depositing a patterned coat of resist on a wafer. A metallization stack is on a first surface of the wafer, the metallization stack including a pre-metal dielectric (PMD) barrier and an isolation dielectric. The method also includes etching through trenches in the wafer such that the through trenches protrude into the isolation dielectric of the metallization stack and removing the resist coat. The method further includes depositing a polymer dielectric on a second surface of the wafer to fill the through trenches, and singulating dies from the wafer such that the dies include the through trenches. [Brief description of the drawings]

[0006] [Figure 1] 1 illustrates a cross-sectional view of an area of ​​a first example die usable for an integrated circuit (IC) package.

[0007] [Diagram 2] 1 illustrates a cross-sectional view of an area of ​​a second example die usable for an IC package.

[0008] [Diagram 3] 1 illustrates a cross-sectional view of an area of ​​a third example die usable for an IC package.

[0009] [Figure 4] 1 illustrates a cross-sectional view of an area of ​​a fourth example die usable for an IC package.

[0010] [Diagram 5] 13 illustrates a cross-sectional view of an area of ​​a fifth example die usable for an IC package.

[0011] [Figure 6] 1 illustrates a cross-sectional view of an area of ​​a sixth example die usable for an IC package.

[0012] [Figure 7] 1 shows a plan view of a third example die usable for an IC package.

[0013] [Figure 8] 1 shows three examples of trench architectures at tri-points on an IC package die.

[0014] [Figure 9] 1 illustrates an IC package including a die mounted within a first exemplary IC package formed from a plastic molding material.

[0015] [Figure 10] 1 illustrates an IC package including a die mounted within a second exemplary IC package formed from a plastic molding material.

[0016] [Figure 11] 1 shows an IC package that includes a die mounted on a printed circuit board (PCB).

[0017] [Figure 12] 1 shows a first step in the processing method of a wafer for die singulation.

[0018] [Figure 13] 4 illustrates a second stage of the method for processing the wafer for die singulation.

[0019] [Figure 14] 4 illustrates a third stage of the method for processing the wafer for die singulation.

[0020] [Figure 15] 4 illustrates a fourth stage of the method for processing the wafer for die singulation.

[0021] [Figure 16] 4 illustrates a fifth stage of the method for processing the wafer for die singulation.

[0022] [Figure 17] 13 illustrates a sixth step in the method of processing a wafer for die singulation.

[0023] [Figure 18] 13 illustrates a seventh stage of the method for processing the wafer for die singulation.

[0024] [Figure 19] 13 illustrates an eighth stage of the method for processing a wafer for die singulation.

[0025] [Figure 20] 1 shows a flow chart of an example method for forming an IC package. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] The present description relates to a die for an integrated circuit (IC) package (or, more generally, a device). The die is singulated from a wafer. The die has a metallization stack located on a surface of the die. The metallization stack includes a protective overcoat (PO). The substrate includes a first region and a second region. The first region and the second region have circuitry embedded therein. Also, in some examples, the circuitry embedded in the first region has a first voltage rating and the circuitry in the second region has a second voltage rating different from the first voltage rating. An isolation dielectric of the metallization stack is disposed between the protective overcoat and the die, and a pre-metal dielectric (PMD) barrier of the metallization stack is disposed between the isolation dielectric and the die. The PMD barrier has a first region in contact with the first region of the substrate and a second region in contact with the second region of the substrate. The PMD barrier and the first and second regions of the substrate are spaced apart. The PMD barrier is made of a material such as silicon nitride (SiN), and the isolation dielectric is silicon dioxide (SiO 2 ) and other materials.

[0027] A through trench filled with a polymer dielectric extends between the first and second regions of the substrate and between the first and second regions of the PMD barrier and is in contact with the isolation dielectric. The through trench filled with the polymer dielectric electrically isolates the first region of the die and the second region of the die to avoid undesired electromagnetic interference (EMI). In some examples, the through trench protrudes into the isolation dielectric. Also, in some examples, the through trench has a rounded corner on an end proximate to the isolation dielectric. The polymer dielectric is formed of a material such as parylene. The polymer dielectric filling the through trench has a coefficient of thermal expansion greater than the PMD barrier. Also, the isolation dielectric has a lower modulus of elasticity than the PMD barrier.

[0028] To singulate the die, the wafer is cut into individual die for device creation. In some instances, the individual die instances are ready for use in a product, such as in a wafer-scale package with solder. In other instances, bump bonds are added between the die and the product base to bond the die to the product base. In some instances, there is a thermal cycle involved to attach the die to the wafer-scale package or product base. For example, in the case of solder connections, the die is attached to the product base using a reflow process, where the product base and die are placed together and heated to above the melting temperature of the solder (e.g., about 250° C.). In some instances, this attachment process has a short time at peak temperature (e.g., about 5 seconds or less) and a fast cooling rate (e.g., about 1 second for 5 degrees Celsius or more).

[0029] In some examples, after singulation, multiple instances of the die are placed into a package with a protective plastic layer. In this example, the die is then mounted onto the interconnect (e.g., a lead frame). In some examples, additional wire connections (wire bonds) are used to electrically couple the die to the interconnect. In other examples, the attachment between the die and the interconnect is an electrical connection (bump or solder bond). In examples where wire bonds are used, the die attachment is an insulating layer (an epoxy-like compound, possibly with a ceramic filler), a conductive material such as silver (Ag) filled with epoxy, etc. In response to mounting the die onto the interconnect (and in some examples, attaching the wires), the die and interconnect are encased in a molding (e.g., plastic) to form an IC package.

[0030] In some examples, these IC package formation operations (or some subset thereof) include a thermal anneal between about 100° C. and about 200° C. The first thermal anneal is used to attach the die to an interconnect (e.g., a lead frame), and in some examples, the IC package is soldered to a product substrate using the reflow process described above to mount the formed IC package.

[0031] As mentioned above, the isolation dielectric has a lower modulus of elasticity than the PMD barrier and also has a larger coefficient of thermal expansion. The modulus of elasticity of the isolation dielectric also has a temperature coefficient such that at high temperatures, such as during annealing and reflow of the IC package, it is less stiff than at ambient temperatures (e.g., 0°C to 32°C). Thus, the force applied by the polymer dielectric filling the through trench due to thermal expansion slightly deforms the isolation dielectric. This deformation causes the polymer dielectric to partially compress the isolation dielectric, reducing the force transmission to the PO. Thus, the force on the PO due to the thermal expansion of the polymer dielectric filling the through trench is reduced. This reduction in force reduces the likelihood of cracking components of the metallization stack during solder reflow or other times the die is heated.

[0032] FIG. 1 illustrates a cross-sectional view of a region of a die 100 usable for an integrated circuit (IC) package (device). The die 100 is singulated from a wafer. The die 100 includes a substrate 104. The substrate 104, in some examples, is formed of a semiconductor material such as silicon (Si). The substrate 104 includes a first region 108 and a second region 112. A metallization stack 116 overlies the substrate 104. The metallization stack 116 includes a pre-metal dielectric (PMD) barrier 120, an isolation dielectric 124, and a protective overcoat (PO) 128. In some examples, a silicon dioxide (SiO ) layer is disposed between the PMD barrier 120 and the substrate. 2 ). In some examples, the metallization is based on an aluminum metal layer with tungsten (W) via layers and contacts to Si. In other examples, the metallization is copper with vias of the same material. The contacts can be tungsten, copper, ruthenium, or other conductive layers. The metallization layers can have diffusion barrier or adhesion layers such as Ti, TiN, Ta, TaN, TiAl, or TiAlN.

[0033] The PMD barrier 120 contacts the substrate 104, the isolation dielectric 124 overlies the PMD barrier 120, and the PO 128 overlies the isolation dielectric 124. In such a situation, the PO 128 protects the metallization stack 116 from exposure to the environment, except for the exposed metal pads, which are not shown. The isolation dielectric 124 comprises a PMB barrier. In some examples, the PMD barrier 120 is a silicon dioxide (SiO ), such as phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG). 2 Underlying this portion (the PMD layer) of the isolation dielectric 124 is a PMD barrier 120, which in some examples is made of silicon nitride (SiN), silicon oxynitride (SiON), and other silicon dioxide (SiO 2 In another example, the isolation dielectric 124 may include a material such as a silicon nitride (SiN), a fluorine doped silicon oxide (SiO 2, or silsesquioxane [RSiO 3 / 2 ] n It is made of low K dielectrics such as

[0034] The first region 108 and the second region 112 include circuit components (e.g., transistors, resistors, capacitors, etc.) formed with standard processing techniques. The first region 108 and the second region 112 are separated by a through trench 132. The through trench 132 provides dielectric isolation between the first region 108 and the second region 112 of the substrate 104. In this manner, the first region 108 and the second region 112 may have different power domains. As an example, the first region 108 has a high supply voltage (e.g., 80V or higher) and some of the components integrated with the first region 108 are rated for the high supply voltage. Conversely, in this example, the second region 112 has a low supply voltage (e.g., 10V or lower) and the components integrated with the second region 112 of the substrate 104 are rated for the low supply voltage. The inclusion of the through trench 132 prevents unwanted EMI leakage and / or shorts between the two power domains.

[0035] The through trench 132 is filled with a polymer dielectric 134, such as a parylene containing some of the functional groups of parylene, such as parylene-F, parylene-HT or parylene-AF4, parylene-VT4, parylene-N, or parylene-C. The polymer dielectric 134 filling the through trench 132 has a greater coefficient of thermal expansion than the PMD barrier 120. In other words, the polymer dielectric 134 filling the through trench 132 has a first coefficient of thermal expansion and the PMD barrier 120 has a second coefficient of thermal expansion, the first coefficient of thermal expansion being greater than the second coefficient of thermal expansion.

[0036] Also, in some examples, the isolation dielectric 124 has a lower elastic modulus than the PMD barrier 120, which is formed of a material such as silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbon oxynitride (SiCON). In other words, the isolation dielectric 124 has a first elastic modulus, and the PMD barrier 120 has a second elastic modulus that is greater than the first elastic modulus. The elastic modulus of a material (e.g., the isolation dielectric 124 and the PMD barrier 120) characterizes the material's ability to resist elastic (e.g., non-permanent) deformation when a stress is applied to the material. In examples where the die 100 is heated, the different materials forming the die 100 will tend to expand based on their respective thermal expansion coefficients. In some examples, these materials are constrained by the surrounding materials and therefore also experience forces that the die 100 materials exert on the surrounding materials. In instances where the polymer dielectric 134 in the trench 132 has a larger coefficient of thermal expansion than the substrate 104, the polymer dielectric 134 will expand more than the substrate 104 and therefore exert a stress away from the trench 132. If there is a stiff layer (high modulus of elasticity) near the trench 132, the stress in this layer will be greater than its neighbors.

[0037] The PMD barrier 120 includes a first region 136 and a second region 140. The first region 136 of the PMD barrier 120 contacts the first region 108 of the substrate 104, and the second region 140 contacts the second region 112 of the substrate 104. In addition, the first region 136 and the second region 140 of the PMD barrier 120 are spaced apart. More specifically, a region of the PMD barrier 120 has been etched away.

[0038] A first end 144 of the through trench 132 is proximate to the isolation dielectric 124. The first end 144 extends in a first direction. The first end 144 includes a first corner 148 and a second corner 152. The first corner 148 and the second corner 152 are rounded corners having a radius of curvature of about 0.01 micrometers (μm) to about 0.2 μm. Unless otherwise stated, in this description, "about" before a value means + / - 10 percent of the stated value. The through trench 132 is formed such that the polymer dielectric 134 filling the through trench 132 protrudes beyond the PMD barrier 120 into a region of the isolation dielectric 124.

[0039] The through trench 132 also includes a second end 156 opposite the first end 144. The second end 156 is distal to the isolation dielectric 124. The second end 156 includes a first region 166 and a second region 170 that extend perpendicular to the first direction. The first region 166 of the second end 156 of the through trench 132 also underlies the first region 108 of the substrate 104. Similarly, the second region 170 of the second end 156 of the through trench 132 underlies the second region 112 of the substrate 104. The second end 156 of the through trench 132 further includes a third region 174 between the first region 166 and the second region 170. The third region 174 of the second end 156 faces a portion of the first end 144 that protrudes beyond the PMD barrier 120 into the isolation dielectric 124. In some examples, the third region 174 of the second end 156 includes a notch 178 (eg, a void) from the polymer dielectric 134 that flows through the through trench 132 .

[0040] During the manufacture of an IC package, the die 100 must endure many thermal cycles depending on the packaging process. A rough overview of example packaging processes includes wafer-scale encapsulation, bump to interconnect (e.g., lead frame) processes using gold (Au) solder bumps, wire bond packages in plastic with solder attachment to a printed circuit board (PCB), and plastic packages with solder attachment to a PCB. In examples where solder attachment is used, the die 100 is heated above about 250° C., which is the solder reflow temperature for common lead-free solders. In some examples, this solder reflow temperature is the maximum temperature reached during the packaging process. Heating the die 100 causes components of the die 100 to expand. However, as described, the polymer dielectric 134 that fills the through trench 132 has a larger coefficient of thermal expansion than the PMD barrier 120. In conventional approaches, the PMD barrier 120 extends over the through trench 132 (e.g., no portion is etched away). Thus, in this conventional approach, the thermal expansion of the polymer dielectric 134 causes the PMD barrier 120 to exert a force in the direction indicated by arrow 182. In some instances, this force may be large enough to cause a crack to form, which may propagate through the other layers or some subset thereof. The greater stiffness of the PMD barrier 120 compared to the surrounding material concentrates the force, making it more susceptible to failure due to cracking. This force (in the conventional approach) is transferred to the isolation dielectric 124 and again to the PO 128, resulting in cracking of the PO 128 in some instances.

[0041] In contrast to conventional approaches, because the portion of the PMD barrier 120 overlapping the first end 144 of the through trench 132 has been etched away, the thermal expansion of the polymer dielectric 134 filling the through trench 132 in the direction indicated by the arrow 182 does not exert a force on the PMD barrier 120. Also, as described above, the isolation dielectric 124 has a lower elastic modulus than the PMD barrier 120. Thus, the force applied in the direction of the arrow 182 by the polymer dielectric 134 filling the through trench 132 due to thermal expansion slightly deforms the isolation dielectric 124. This deformation causes the polymer dielectric 134 to partially compress the isolation dielectric 124, reducing the transmission of the force to the PO 128. In other words, because the isolation dielectric 124 is partially compressed by the thermal expansion of the polymer dielectric 134, the force applied by such thermal expansion of the polymer dielectric 134 is partially absorbed by the isolation dielectric 124, and this absorbed force is not transmitted to the PO 128. Thus, the force on the PO 128 in the direction of arrow 182 due to the thermal expansion of the polymer dielectric 134 filling the through trench 132 is reduced. This reduction in force reduces the likelihood of cracking components of the metallization stack 116 (including the PO 128) during solder reflow or any other time the die 100 is heated.

[0042] Figure 2 shows a cross-sectional view of a region of a die 200 that can be used for IC packaging. The die 200 has been singulated from a wafer and can be used to package the die 100 of Figure 1. Therefore, for simplicity, the same reference numbers are used in Figures 1 and 2, and some features will not be reintroduced.

[0043] In the example shown in FIG. 2, the through trench 132 is covered with a silicon dioxide (SiO 2 The substrate 202 is filled with a polymer dielectric 204 (e.g., Parylene) coated with a layer of silicon dioxide (SiO 2 Plasma-enhanced chemical vapor deposition (PECVD) of H 2 O, O 2 , O3 , Plasma O 2 , N 2 SiO by pulsed deposition of Si containing organics such as TEOS using an oxidizer such as O 2 Atomic layer deposition of SiO using TEOS+Ozone 2 or PECVD, ALD, or CVD of silicon nitride (SiN) before filling the remainder of the through trench 132 with a polymer dielectric 204; or Al 2 O 3 The coating 208 is formed by CVD, ALD, or PECVD. With a few exceptions, the coating 208 is tapered from the second end 156 to the first end 144. That is, the thickness of the coating 208 is thickest at the second end 156 of the through trench 132 and thinnest at the first end 144 of the through trench 132 such that the polymer dielectric 204 has a dovetail shape within the through trench 132. The polymer dielectric 204 improves the dielectric properties of the trench 132 and increases its strength by increasing the thickness of the dielectric overlying the trench 132. Another technique for producing such trench shapes is to use a substrate etching process in which the diameter of the hole at the beginning of the hole 132 is narrower than the center or bottom of the hole. In some cases, the hole is only wider at the bottom 144 near the PMD barrier 120.

[0044] The polymer dielectric 204 may also be pre-treated with silicon dioxide (SiO ) prior to filling the remaining portion of the through-trench 132 with the polymer dielectric 204. 2 ) or silicon nitride (SiN). The void 212 is an unfilled area of ​​the through trench 132 that is surrounded by the polymer dielectric 204.

[0045] To attach the die 200 to the interconnects, the die 200 is heated during a die attach bake. Heating the die 200 causes the components of the die 200 to expand. The polymer dielectric 204 has a greater coefficient of thermal expansion than the PMD barrier 120. Because of the presence of the voids 212, the polymer dielectric 204 expands in the direction indicated by the arrows 220 and 224 to fill the voids 212. Also, a force is generated in the direction indicated by the arrow 182. Because the portion of the PMD barrier 120 overlying the first end 144 of the through trench 132 has been etched away, the thermal expansion of the polymer dielectric 204 filling the through trench 132 in the direction indicated by the arrow 182 reduces the force (in the same direction) on the PMD barrier 120.

[0046] Also, the polymer dielectric 204 filling the through trench 132 causes the force applied in the direction of the arrow 182 due to thermal expansion to slightly deform the isolation dielectric 124. This deformation causes the polymer dielectric 204 to partially compress the isolation dielectric 124, reducing the force transmission to the PO 128. Also, the expansion of the polymer dielectric 204 in the direction indicated by the arrow 182 is reduced compared to the example shown in FIG. 1 due to the presence of the voids 212 (which are compressed during the thermal expansion of the polymer dielectric 204). Thus, the force in the direction of the arrow 182 on the PO 128 due to the thermal expansion of the polymer dielectric 204 filling the through trench 132 is reduced. This reduction in force reduces the likelihood of cracking components of the metallization stack 116 (including the PO 128) during solder reflow or another time the die 200 is heated.

[0047] Figure 3 shows a cross-sectional view of a region of a die 300 that can be used for IC packaging. The die 300 has been singulated from a wafer and can be used to package the die 100 of Figure 1. Therefore, for simplicity, the same reference numbers are used to indicate the same structures in Figures 1 and 3, and some features will not be reintroduced.

[0048] 3, the through trench 132 is filled with a polymer dielectric 302 (e.g., parylene). A first contact 304 overlaps and abuts the first corner 148 of the first end 144 of the through trench 132. A second contact 308 overlaps and abuts the second corner 152 of the through trench 132.

[0049] The first contact 304 and the second contact 308 have a first region 312 and a second region 316. The first region 312 of the first contact 304 and the second contact 308 has a rectangular parallelepiped shape. The second region 316 of the first contact 304 and the second contact 308 also has a rectangular parallelepiped shape. In the illustrated example, the second region 316 has a larger volume than the first region 312. Also, the first region 312 of the first contact 304 is proximate to the first corner 148, and the first region 312 of the second contact 308 is proximate to the second corner 152. The second region 316 overlaps the first region 312 of the first contact 304 and the second contact 308. The second region 316 of the first contact 304 is distal to the first corner 148 and the second region 316 of the second contact 308 is distal to the second corner 152 .

[0050] The first region 312 and / or the second region 316 of the first contact 304 and the second contact 308 are formed of a metal, such as tungsten (W), aluminum (Al), copper (Cu), or some combination thereof. The first contact 304 and the second contact 308 are formed of a material that is harder than the material forming the PMD barrier 120 (e.g., silicon nitride) or the isolation dielectric 124 (e.g., silicon dioxide). Thus, the first contact 304 and the second contact 308 strengthen the first corner 148 and the second corner 152 of the through trench 132, respectively. Thus, the first contact 304 and the second contact 308 resist movement due to the application of a force in the direction of the arrow 182 due to the thermal expansion of the polymer dielectric 404 (e.g., parylene) filling the through trench 132. Thus, resistance to movement in the direction of arrow 182 by first contact 304 and second contact 308 further reduces the likelihood of cracking components of metallization stack 116 (including PO 128) during solder reflow or at any other time when die 300 is heated.

[0051] Figure 4 shows a cross-sectional view of a region of a die 400 that can be used for IC packaging. The die 400 has been singulated from a wafer and can be used to implement the die 100 of Figure 1. Thus, for simplicity, the same reference numbers are used to indicate the same structures in Figures 1 and 4, and some features will not be reintroduced.

[0052] In the example shown in FIG. 4, the through trench 132 is filled with a polymer dielectric 404 (e.g., parylene). K dummy metal patches 408 are implanted into the isolation dielectric 124 (e.g., silicon dioxide), where K is an integer greater than or equal to 1. Each of the dummy metal patches 408 are spaced apart from one another. The additional dummy metal patches 408 are offset (in and / or out of the illustrated view) from the dummy metal patches 408 shown in FIG. 4.

[0053] The dummy metal patch 408 is positioned to extend the length of the through trench 132. The dummy metal patch 408 adds stiffness to the isolation dielectric 124 (e.g., silicon dioxide). Thus, by including the dummy metal patch 408, the isolation dielectric 124 resists the transmission of force to the PO 128 in response to the application of force in the direction of the arrow 182 due to the thermal expansion of the polymer dielectric 404 (e.g., Parylene). Thus, the resistance to force transmission in the direction of the arrow 182 by including the dummy metal patch 408 in the isolation dielectric 124 reduces the likelihood of cracking components of the metallization stack 116 (including the PO 128) during solder reflow or other times when the die 400 is heated.

[0054] Figure 5 shows a cross-sectional view of a region of a die 450 that can be used for IC packaging. The die 450 has been singulated from a wafer and can be used to implement the die 100 of Figure 1. Thus, for simplicity, the same reference numbers are used to indicate the same structures in Figures 1 and 5, and some features will not be reintroduced.

[0055] In the example shown in FIG. 5, the through trench 132 is filled with a polymer dielectric 454 (e.g., parylene). Also, R stepped dummy metal patches 458 are disposed within the isolation dielectric 124 (e.g., silicon dioxide), where R is an integer equal to or greater than 1. Each of the stepped dummy metal patches 458 are spaced apart from each other. Each of the stepped dummy metal patches 458 includes two or more layers of dummy metal patches having different lengths. In the illustrated example, each of the stepped dummy metal patches 458 includes a first dummy metal patch 462, a second dummy metal patch 466, and a third dummy metal patch 470, although in other examples, there are more or less dummy metal patches in each of the stepped dummy metal patches 458. The first dummy metal patch 462 is adjacent to the PMD barrier 120, and the third dummy metal patch 470 is adjacent to the PO 128. In some examples, the first dummy metal patch 462 is rather wider than the trench so that the edge of the trench does not overlap the metal layer even if due to an inherent misalignment between the trench and the metal layer. The second dummy metal patch 466 is disposed between the first dummy metal patch 462 and the third dummy metal patch 470. The stepped dummy metal patch 458 is disposed to extend the length of the through trench 132. The stepped dummy metal patch 458 is connected to a via 472.

[0056] The first dummy metal patch 462 is the shortest, the third dummy metal patch 470 is the longest, and the second dummy metal patch 466 has a length between the first dummy metal patch 462 and the third dummy metal patch 470. Thus, the dummy metal patches of the layered dummy metal patch 458 have different lengths. Thus, the third dummy metal patch 470 of the two different stepped dummy metal patches 458 is closer than the first dummy metal patch 462 of the same two stepped dummy metal patches 458. In other words, the gap between the third dummy metal patch 470 of the two different stepped dummy metal patches 458 is narrower than the gap between the first dummy metal patch 462 of the same two stepped dummy metal patches 458. The stepped dummy metal patch 458 adds rigidity to the isolation dielectric 124 (e.g., silicon dioxide) because the dielectric strength of the isolation dielectric 124 (e.g., silicon dioxide) is greater than the dielectric strength of the polymer dielectric 454 (e.g., parylene). The vias 472 also add further strength by connecting the different steps of the stepped dummy metal patch 458 together.

[0057] The die 450 also includes an array of shallow trench isolation features 476 that extend over the first ends 144 of the trenches 132. In other words, the array of shallow trench isolation features 476 extends over the trenches 132. In some examples, the shallow trench isolation features 476 are present only near the center of the trenches 132. In other examples, the shallow trench isolation features 476 extend to provide a certain overlap of the trenches 132 (filled with the polymer dielectric 454) and the isolation dielectric 124. The array of shallow trench isolation features 476 is below the PMD barrier 120 but is connected to the PMD barrier 120. The array of shallow trench isolation features 476 is formed of a silicon dioxide (SiO 2) and in some examples, the array of shallow trench isolation features 476 also includes silicon nitride (SiN) or silicon oxynitride (SiON). The array of shallow trench isolation features 476 creates a complex surface topography at the interface of the polymer dielectric 454 and the isolation dielectric 124 to improve adhesion between the polymer dielectric 454 and the isolation dielectric 124 near the first end 144. The improved adhesion allows the polymer dielectric 454 to expand with heating and relax with increased heating without delaminating. Additionally, as the polymer dielectric 454 cools, it is under tension and the roughened surface provided by the array of shallow trench isolation features 476 increases the surface area to keep the polymer dielectric 454 adhered to the isolation dielectric 124 near the first end 144 under increased tensile loads. In various examples, the array of shallow trench isolation features 476 has random dimensions (particularly perpendicular to the trench width) and random spacing. In some examples, the shallow trench isolation features 476 within the region of the trench 132 are smaller than the shallow trench isolation features 476 outside the trench 132, indicating that the shallow trench isolation features 476 are partially etched. In some such examples, the shallow trench isolation features 476 are longer in a first direction (e.g., height) measured along the contour of the trench 132 from the PMD barrier 120 toward the second region 170 of the trench 132 than in a second direction (e.g., width) perpendicular to the first direction. Also, in some examples, the array of shallow trench isolation features 476 is selected to increase surface area by reducing the dimensions of the individual shallow trenches in the array of shallow trench isolation features 476.

[0058] By including the array of stepped dummy metal patches 458 and shallow trenches, the isolation dielectric 124 resists the transmission of force to the PO 128 in response to an applied force in the direction of arrow 182 due to thermal expansion of a polymer dielectric 454 (e.g., Parylene), or the like. Thus, the resistance to force transmission in the direction of arrow 182 by including the array of stepped dummy metal patches 458 and shallow trench isolation features 476 in the isolation dielectric 124 further reduces the likelihood of cracking components of the metallization stack 116 (including the PO 128) during solder reflow or other times when the die 450 is heated.

[0059] Figure 6 shows a cross-sectional view of a region of a die 500 that can be used for IC packaging. The die 500 has been singulated from a wafer and can be used to package the die 100 of Figure 1. Thus, for simplicity, the same reference numbers are used to indicate the same structures in Figures 1 and 6, and some features will not be reintroduced.

[0060] In the example shown in FIG. 6, the through trench 132 is filled with a polymer dielectric 504 (e.g., parylene) or the like. Also, R deep trenches 508 are disposed within the through trench 132, where R is an integer equal to or greater than 1. The deep trenches 508 are disposed at the edges and / or center of the through trench 132. In the example shown, there are three deep trenches 508, disposed on both edges and on the center of the through trench 132. In contrast to the array of shallow trench isolation features 476 of FIG. 4, the deep trenches 508 are deeper than the array of shallow trench isolation features 476. In various examples, the depth of the deep trenches 508 ranges from about 5 μm to about 40 μm. In some examples, the depth of the deep trenches 508 is less than the thickness of the first region 108 and the second region 112 of the substrate. For example, in one example, the depth of the deep trenches 508 is about 20% of the thickness of the first region 108 and the second region 112 of the substrate. In this example, the PMD barrier 120 includes a portion that extends over each deep trench 508. In some such examples, the PMD barrier 120 includes a third region 516 that borders the deep trenches 508 and is centrally located in the through trench 132. In this situation, the polymer dielectric 504 fills the gap between each deep trench 508 and improves the electrical isolation and strength of the isolation dielectric 124.

[0061] Also, in some instances, a metal layer 520 overlies the PO 128. The metal layer 520 improves the stiffness of the PO 128. Thus, adding the metal layer 520 increases the stress that the PO 128 can be subjected to before it cracks during solder reflow or another time that the die 500 is heated.

[0062] 7 shows a plan view of a layout for a die 600 for an IC package. The die 600 includes a first region 604, a second region 608, and a third region 612. In some examples, the third region 612 has a high supply voltage and the components integrated in the third region 612 are rated for the high supply voltage. Conversely, in this example, the second region 608 has a low supply voltage (e.g., 10V or less) and the components in the second region 608 are rated for the low supply voltage. Also, in this example, the components in the first region 604 are rated for a third supply voltage (e.g., an intermediate voltage) between the low and high supply voltages. A trench 616 electrically isolates the first region 604, the second region 608, and the third region 612 from each other. Trench 616 has a cross-section corresponding to the cross-section of die 100 of Figure 1, die 200 of Figure 2, die 300 of Figure 3, die 400 of Figure 4, die 450 of Figure 5, or die 500 of Figure 6. Trench 616 is therefore filled with a polymer dielectric (e.g., parylene).

[0063] In this example, a first coupling capacitor 620 electrically couples the second region 608 to the third region 612. In this manner, the components in the second region 608 and the third region 612 communicate. Also in this example, a second coupling capacitor 624 couples the first region 604 to an external region (not shown) to enable communication between the die 600 and the external components. The first coupling capacitor 620 and the second coupling capacitor 624 have low parasitic capacitance (e.g., about 100 femtofarads or less). This type of capacitor can be used to transfer power as well as data. For power transfer, the dimensions of the capacitor can be large, such as 200 fF or more.

[0064] At some point in the layout of the die 600, the first region 604, the second region 608, and the third region 612 come close to form a tri-point, such as a particular tri-point 630. In other words, at the tri-point 630 (at a given point on the die 600), the first region 604, the second region 608, and the third region 612 are separated by a trench 616. There are multiple architectures for the trench 616 at such a junction.

[0065] Although the die 600 provides isolation with a single trench 616, in other instances it is possible to provide multiple trenches to increase isolation failure and reduce capacitive coupling between regions. For example, it is possible to have two rows of trenches and a region between the trenches (e.g., third region 612) connected to a ground connection with controlled parasitic capacitance and resistance to reduce noise coupling. In instances where both greater isolation and capacitive coupling are required, providing multiple trenches requires additional area and also uses additional perimeter to achieve the same capacitance because the dielectric thickness increases, reducing capacitance density.

[0066] 8 shows a first architecture 650, a second architecture 660, and a third architecture 670 for the trench 616 of FIG. 7 where three regions come together, such as the tri-point 630 of FIG. 7. The first architecture 650 is referred to as a curved connection. The second architecture 660 is referred to as a Y-shaped connection, and the third architecture 670 is referred to as a T-shaped connection. Each of the first architecture 650 (curved connection), second architecture 660 (Y-shaped connection), and third architecture 670 (T-shaped connection) creates additional stresses compared to simpler structures that are more susceptible to mechanical failure due to cracks.

[0067] The second architecture 660 (Y-shaped connection) has the lowest stress and the lowest probability of mechanical failure compared to the first architecture 650 (curved connection) and the third architecture 670 (T-shaped connection) for a given width of the trench 616 in FIG. 7. The second architecture 660 (Y-shaped connection) has the lowest stress and the lowest probability of mechanical failure because the second architecture 660 has smoother corners than the first architecture 650 and the third architecture 670, reducing mechanical stress. As an example, the second architecture 660 (Y-shaped connection) has 120 degree corners and the third architecture 670 (T-shaped connection) has 90 degree corners. The second architecture 660 is further strengthened by adding rounded corners (e.g., circular segments) with additional processing to widen the opening at the junction. In yet another example, a dummy metal patch (e.g., dummy metal patch 408 in FIG. 4 or stepped dummy metal patch 458 in FIG. 5) is added to further increase strength at the illustrated joint. Additionally or alternatively, additional polymer dielectric (e.g., parylene) is added to the edges of the trench and corners of the connection.

[0068] FIG. 9 illustrates an IC package 700 including a die 704 mounted within an IC package 708 formed from a plastic molding material. The die 704 is packaged with the die 200 of FIG. 2, the die 300 of FIG. 3, the die 400 of FIG. 4, the die 450 of FIG. 5, and / or the die 500 of FIG. 6. The IC package 708 is a wirebond package including a plurality of wirebonds 712. The wirebonds 712 electrically connect the die 704, such as voltage domains within the die 704, to pads 720 of an interconnect 724 (also referred to as a leadframe). The wirebonds 712 are coupled to the die 704 with corresponding solder balls 728 formed on conductive pads 732 formed on a first surface of the die 704.

[0069] A second surface of the die 704 opposite the first surface of the die 704 is mounted on a pad 740 (e.g., a center pad) of the interconnect 724. More specifically, a die attach material 744 (e.g., solder paste) is sandwiched between the pad 740 of the interconnect 724 and the second surface of the die 704.

[0070] The die 704 includes a first trench 760 and a second trench 764 that separate regions of the die 704. In some examples, the first trench 760 and the second trench 764 can be used to implement the through trench 132 of Figures 1-6. These regions of the die 704 that are separated by the first trench 760 and / or the second trench 764 can be used to implement different voltage levels, as described herein.

[0071] Figure 10 shows an IC package 750 including a die 754 mounted within an IC package 758 formed of a plastic molding material. The die 754 may be packaged with the die 200 of Figure 2, the die 300 of Figure 3, the die 400 of Figure 4, and / or the die 500 of Figure 6. The IC package 758 is a solder interconnect package including a plurality of solder balls 762 coupled to a surface of the die 754. The solder balls 762 are coupled to metal contacts 766 (formed, for example, of aluminum or copper) and pads 770 of interconnects 774 mounted on the surface of the die 754.

[0072] Die 754 includes a first trench 760 and a second trench 764 that separate regions of die 754. In some examples, first trench 760 and second trench 764 can be used to implement through trench 132 of Figures 1-5. These regions of die 754 that are separated by first trench 760 and / or second trench 764 can be used to implement different voltage levels, as described herein.

[0073] FIG. 11 illustrates an IC package 800 including a die 804 mounted on a printed circuit board (PCB) 808. In some such examples, the die 804 is encased in a molding material (not shown) and mounted on the PCB 808 prior to singulation. The die 804 is packaged with the die 200 of FIG. 2, the die 300 of FIG. 3, the die 400 of FIG. 4, the die 450 of FIG. 5, and / or the die 500 of FIG. 6. The die 804 is coupled to pads 810 of the PCB 808 via a plurality of solder balls 812 coupled to a first surface of the die 804. The solder balls 812 are coupled to metal contacts 816 (e.g., formed of aluminum) mounted on the first surface of the die 804 and to the pads 810 of the PCB 808. The pads 810 are coupled to vias in the PCB 808. In some examples, the IC package 800 includes an additional polymer layer (not shown) between the die 804 and the PCB 808 to enhance mechanical properties and improve the voltage rating between different bump areas. This polymer layer is sometimes referred to as an underfill coating.

[0074] Die 804 includes a first trench 830 and a second trench 834 that separate regions of die 804. In some examples, first trench 830 and second trench 834 can be used to implement through trench 132 of Figures 1-6. These regions of die 804 that separate first trench 830 and / or second trench 834 can be used to implement different voltage levels, as described herein.

[0075] Figures 9-11 show different approaches for mounting a die, such as die 100 of Figure 1, die 200 of Figure 2, die 300 of Figure 3, die 400 of Figure 4, die 50 of Figure 5, and / or die 500 of Figure 6, into a package to form an IC package. As shown in Figures 9-11, the die shown throughout this description are process independent.

[0076] Figures 12-19 show stages in a method of processing a wafer for singulation of a die, such as die 100 of Figure 1, die 200 of Figure 2, die 300 of Figure 3, die 400 of Figure 4, die 50 of Figure 5, and / or die 500 of Figure 6, to be mounted in a package to form an IC package, such as IC package 700 of Figure 9, IC package 750 of Figure 8, or IC package 800 of Figure 11. The method of Figures 12-19 shows how the wafer is processed to add through trenches for isolation trenches.

[0077] In a first stage of the method, as shown in FIG. 12, at 900, a wafer 1000 is provided. The wafer 1000 includes a substrate 1004 having circuit components (e.g., embedded transistors, resistors, and / or capacitors) therein. A metallization stack 1008 is disposed on a first surface 1010 of the substrate 1004. The metallization stack 1008 is a multi-layered semiconductor layer including a dielectric material, such as silicon nitride (SiN), and silicon dioxide (SiO 2 The metallization stack 1008 includes a PMD barrier 1012 formed of an isolating dielectric 1014, such as a PMD barrier 1012 formed of an insulating ...

[0078] In a second stage of the method, as shown in FIG. 13, at 910, the wafer 1000 is flipped over and an adhesive tape 1020 is applied to the wafer 1000 for further processing. In a third stage of the method, as shown in FIG. 14, at 920, the substrate 1004 is ground and polished to a thickness of about 80 to about 1020 micrometers (μm). In a fourth stage of the method, as shown in FIG. 15, at 930, a coating of resist 1024 is patterned on the wafer 1000. The coating of resist 1024 includes gaps 1028 that facilitate the formation of through trenches. More specifically, in a fifth stage of the method, as shown in FIG. 16, at 940, a first through trench 1032 and a second through trench 1036 are etched into the substrate 1004 and the resist 1024 is removed. The first through trench 1032 and the second through trench 1036 are etched sufficiently to expose the metallization stack 1008. More specifically, the PMD barrier 1012 of the metallization stack 1008 is etched such that the first through trench 1032 and the second through trench 1036 protrude into the isolation dielectric 1014, and a relatively small portion of the isolation dielectric is also etched. As a result of etching the substrate 1004, the substrate 1004 is separated into regions, namely, a first region 1040, a second region 1044, and a third region 1046. As described above in connection with FIG. 2, after trench formation and prior to polymer filling, a SiO 2 It is possible to deposit an additional dielectric such as SiON or SiN, or AlOx.

[0079] In a sixth step of the method, as shown in Figure 17, a polymer dielectric 1048, such as parylene, is applied to the wafer 1000 at 950. The polymer dielectric 1048 fills the first through trench 1032 and the second through trench 1036 and forms a layer overlying a second surface 1052 of the substrate 1004, the second surface 1052 facing the first surface 1010. Also, at 950, additional processing actions are included in some examples. For example, in some examples, voids (e.g., voids 212 of Figure 2) are formed in the first through trench 1032 and the second through trench 1036.

[0080] In a seventh step of the method, as shown in Figure 18, at 960, the second region 1044 of the substrate 1004 is cut at locations 1056 to singulate the first die 1060 and the second die 1064. In various examples, the wafer 1000 is cut at locations 1056 with a saw, laser, ion beam, or plasma cutter. The first die 1060 and / or the second die 1064 can be used to implement the die 100 of Figure 1, the die 200 of Figure 2, the die 300 of Figure 3, the die 400 of Figure 4, the die 450 of Figure 5, or the die 500 of Figure 6. In some examples, the first region 1040 of the first die 1060 and the third region 1046 of the second die 1064 have embedded components rated for different voltage levels than the second region 1044 (which is divided between the first die 1060 and the second die 1064).

[0081] In an eighth step of the method, as shown in FIG. 19, the first die 1060 is flipped over and mounted on the interconnects 1068 (e.g., a lead frame) at 970. Wire bonds 1072 also couple the pads of the interconnects 1068 to the conductive pads 1016 of the first die 1060 at 970. The first die 1060 and the interconnects 1068 are also placed in a molding 1076 made of plastic to form an IC package 1080 at 970. To mount the first die 1060 on the interconnects 1068 and attach the wire bonds 1072, the first die 1060 is heated for solder reflow. However, because the PMD barrier 1012 has been etched, the forces caused by the thermal expansion of the polymer dielectric 1048 are not transferred through the PMD barrier 1012 to the protective overcoat 1015. Thus, the likelihood of cracking the protective overcoat 1015 during such solder reflow is reduced.

[0082] 20 shows a flow chart of an example method 1100 for forming an IC package. At 1110, a patterned coating of resist is deposited on a wafer (e.g., wafer 1000 of FIGS. 12-18). A metallization stack (e.g., metallization stack 116 of FIG. 1) is located on a first surface of the wafer. The metallization stack includes a PMD barrier (e.g., PMD barrier 120 of FIG. 1) and an isolation dielectric (e.g., isolation dielectric 124 of FIG. 1).

[0083] At 1115, through trenches are etched into the wafer such that the through trenches (e.g., through trench 132 in FIG. 1) protrude into the isolation dielectric of the metallization stack, and the resist coating is removed. At 1120, a polymer dielectric (e.g., parylene) is deposited on a second surface of the wafer to fill the through trenches. At 1125, dies are singulated from the wafer such that the dies include through trenches. At 1130, certain of the singulated dies are mounted on interconnects (e.g., interconnect 1068 in FIG. 19). At 1135, the dies and interconnects are placed into a molding (e.g., molding 1076 in FIG. 19).

[0084] Modifications in the described embodiments are possible, and other embodiments are possible, within the scope of the claims.

Claims

1. A device comprising: a substrate having a first surface and a second surface opposite the first surface, the substrate including a through-trench extending between the first and second surfaces and filled with a first dielectric material, a first region, and a second region, the first and second regions being separated by the through-trench and the first dielectric material, the first dielectric material extending over the first surface to cover the first surface; a barrier layer covering the second surface of the substrate, the barrier layer including a first region over the first region of the substrate and a second region over the second region of the substrate, the first and second regions of the barrier layer being separated by the through-trench and the first dielectric material; a second dielectric material on and in contact with the barrier layer and the through-trench, the first dielectric material extending partially into the second dielectric material; a metallization structure surrounded by the second dielectric material; a third dielectric material overlapping the second dielectric material; and the device further comprising a third dielectric material overlapping the second dielectric material.

2. The device of claim 1, wherein: an end of the through-trench proximate the second dielectric material includes a curved corner.

3. The device of claim 2, wherein: the first dielectric material has a first coefficient of thermal expansion; the barrier layer includes a material having a second coefficient of thermal expansion that is also less than the first coefficient of thermal expansion.

4. The device of claim 2, wherein: the barrier layer includes silicon nitride and the first dielectric material includes parylene.

5. The device of claim 2, further comprising: a metal patch within the second dielectric material.

6. The device of claim 2, further comprising: a metal layer extending over the third dielectric material.

7. The device of claim 2, wherein: an end of the through-trench is a first end, and the through-trench includes a notch at a second end of the through-trench distal from the first end.

8. The device of claim 2, further comprising: voids within the first dielectric material.

9. The device of claim 8, wherein: A device in which the surface of the through-trench is covered with a silicon dioxide coating, the first dielectric material includes parylene, and the void is within the parylene.

10. The device according to claim 2, further comprising a plurality of layers of metal patches of different lengths above the through-trench within the second dielectric material.

11. The device according to claim 1, a first contact on a first corner of an end of the through-trench adjacent to the second dielectric material, a second contact on a second corner of the end of the through-trench adjacent to the second dielectric material, and further comprising.

12. The device according to claim 11, wherein the first contact and the second contact include at least one of tungsten, aluminum, and copper.

13. The device according to claim 1, further comprising a trench within the first dielectric material within the through-trench.

14. The device according to claim 1, wherein the substrate further includes a third region spaced apart from the first region and the second region, and the through-trench crosses a location on the substrate where the first region, the second region, and the third region are separated by the through-trench.

15. The device according to claim 14, wherein the trench at the location is one of a curved connection and a Y-shaped connection.

16. The device according to claim 1, wherein the third dielectric material is a protective overcoat.

17. The device according to claim 1, wherein the barrier layer and the third dielectric material are made of the same dielectric material.

18. The device according to claim 1, further comprising a trench or a depression adjacent to an interface between the through-trench and the second dielectric material.

19. The device according to claim 1, wherein the barrier layer is in contact with the second surface of the substrate on the second surface of the substrate.

20. The device according to claim 1, wherein the first region includes a first circuit element, the second region includes a second circuit element, and the first and second circuit elements are in different power domains.

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