Chip module and method for forming a chip module - Patents.com

Abstract

Disclosed is a chip module (40a, 40b, 62) including an integrated circuit (IC) chip (34, 64), a first flexible substrate layer (18) having a plurality of holes (28), a second adhesive substrate layer (16) having a plurality of holes (26), and a third substrate layer (14) made of a conductive material, the second substrate layer being sandwiched between and fixedly engaged with the first substrate layer and the third substrate layer, the holes in the first substrate layer and the holes in the second substrate layer being aligned with one another to form a plurality of cavities (12, 66) that each accommodate at least a portion of the IC chip.

Description

[Technical field]

[0001] FIELD OF THEINVENTION The present invention relates to chip modules, such as integrated circuit (IC) chip modules, chip module card inlays comprising such chip modules, methods of forming such chip modules, and methods of forming such chip module card inlays. [Background technology]

[0002] 2. Background of the Invention Chip module card inlays are frequently used for the manufacture of smart cards, such as credit cards, identification cards, and the like. Such cards are frequently used and may warp or bend when carried or used by a user. Such warping and bending of the card may adversely affect the structural integrity and proper functioning of the card. Furthermore, conventional chip modules in the smart card industry do not provide a flat and uniform top surface, which adversely affects the manufacturing process of chip module card inlays and smart cards. In particular, chip modules are conventionally formed with a two-height stepped structure or a non-flat top housing, such as in the chip-on-board method. Summary of the Invention [Problem to be solved by the invention]

[0003] It is therefore an object of the present invention to provide a chip module, a chip module card inlay, a method of forming a chip module, and a method of forming a chip module card inlay which alleviates the above-mentioned disadvantages or at least provides a useful alternative for the industry and the general public. [Means for solving the problem]

[0004] Summary of the Invention According to a first aspect of the present invention, there is provided a chip module comprising an integrated circuit (IC) chip, a first substrate layer at least partially made of a flexible material and having a first hole, a second substrate layer at least partially made of an adhesive material and having a second hole, and a third substrate layer at least partially made of a conductive material, the second substrate layer being sandwiched between the first substrate layer and the third substrate layer and positionally fixedly engaged with the first substrate layer and the third substrate layer, the first hole of the first substrate layer and the second hole of the second substrate layer being aligned with each other to form a first cavity, and at least a first portion of the IC chip being accommodated in the first cavity.

[0005] According to a second aspect of the present invention, there is provided a chip module card inlay including at least one chip module, the chip module including an integrated circuit (IC) chip, a first substrate layer at least partially made of a flexible material with a first hole, a second substrate layer at least partially made of an adhesive material with a second hole, and a third substrate layer at least partially made of a conductive material, the second substrate layer being sandwiched between the first substrate layer and the third substrate layer and positionally fixedly engaged with the first substrate layer and the third substrate layer, the first hole of the first substrate layer and the second hole of the second substrate layer being aligned with each other to form a first cavity, and at least a first portion of the IC chip being accommodated in the first cavity.

[0006] According to a third aspect of the present invention, there is provided a method of forming a chip module, the method comprising: providing a first substrate layer at least partially made of a flexible material with a plurality of first holes; providing a second substrate layer at least partially made of an adhesive material with a plurality of second holes; providing a third substrate layer at least partially made of a conductive material; aligning the first holes of the first substrate layer with the second holes of the first substrate layer to form a plurality of first cavities; sandwiching the second substrate layer between the first substrate layer and the third substrate layer; positionally fixingly engaging the first substrate layer, the second substrate layer and the third substrate layer to form a first laminate structure; positionally fixingly engaging at least a first portion of an integrated circuit (IC) chip in one of the first cavities of the first laminate structure; and cutting at least one chip module from the first laminate structure positionally engaged with the IC chip.

[0007] According to a fourth aspect of the present invention, there is provided a method of forming a chip module card inlay, comprising forming at least one chip module, the method comprising the steps of: providing a first substrate layer at least partially of a flexible material with a plurality of first holes; providing a second substrate layer at least partially of an adhesive material with a plurality of second holes; providing a third substrate layer at least partially of a conductive material; and adhering the first holes of the first substrate layer to the second substrate layer to form a plurality of first cavities. a first cavity of the first laminate structure; a second substrate layer being aligned with a hole in the first cavity of the first laminate structure; a third substrate layer being sandwiched between the first substrate layer and the third substrate layer; a first substrate layer being fixedly engaged with the second substrate layer and the third substrate layer to form a first laminate structure; a first portion of an integrated circuit (IC) chip being fixedly engaged in one of the first cavities of the first laminate structure; and a cutting out of the first laminate structure at least one chip module fixedly engaged with the IC chip.

[0008] Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which: [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a perspective view showing a chip housing carrier formed from five substrate layers suitable for forming chip modules and chip module card inlays according to one embodiment of the present invention. [Diagram 2] FIG. 2 is an exploded perspective view of one chip housing carrier shown in FIG. 1. [Diagram 3] 2 is a plan view of five substrate layers forming one chip housing carrier shown in FIG. 1. [Figure 4] FIG. 1 is a front view showing a flip integrated circuit (IC) chip. [Diagram 5] 5A-5C show steps for forming a chip module from one chip housing carrier shown in FIG. 1 and the flip IC chip shown in FIG. 4. [Figure 6] 6A-6C show steps for forming a chip module card inlay from the chip module formed in FIG. 5. [Figure 7] 6 is another diagram showing the step of forming a chip module card inlay from the chip module formed in FIG. 5. [Figure 8] 6 is yet another diagram illustrating a step of forming a chip module card inlay from the chip module formed in FIG. 5. [Figure 9] 6 is yet another diagram illustrating a step of forming a chip module card inlay from the chip module formed in FIG. 5. [Figure 10] FIG. 1 is a cross-sectional view of a chip module card inlay according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Description of the embodiments FIG. 1 shows a strip of chip housing carrier 10 formed from five substrate layers for forming chip modules and chip module card inlays according to one embodiment of the present invention. Chip housing carrier 10 is elongated and may be wound in the form of a reel, and thus unwound for the subsequent step of forming chip modules and chip module card inlays. A plurality of cavities 12 are formed along chip housing carrier 10. Cavities 12 may have a square, rectangular or circular cross-sectional shape. As shown in FIG. 1 by way of example, cavities 12 are arranged in three rows, but it should be understood that chip housing carrier 10 may be formed with other numbers of rows of cavities 12.

[0011] Figure 2 is an exploded perspective view of one chip housing carrier 10 shown in Figure 1. In this embodiment, the chip housing carrier 10 is made up of five substrate layers 14, 16, 18, 20, and 22 stacked on top of one another. It should be understood that in accordance with the present invention, the chip housing carrier 10 may be formed from a different number of substrate layers, or may be formed from just substrate layers 14, 16, and 18.

[0012] The five substrate layers 14, 16, 18, 20, and 22 are shown individually in FIG. 3. Substrate layer 14 is made of copper (or another conductive material). Substrate layer 14 has three rows of slits 24 formed along its length. Substrate layer 16 is provided on top of substrate layer 14, with three rows of holes 26 along its length. Substrate layer 16 is made of an adhesive material. Substrate layer 18 is provided on top of substrate layer 16, with three rows of holes 28 along its length. Substrate layer 18 is flexible and made of a flexible material such as one or more of polyimide (PI), polyethylene terephthalate (PET), and glass-reinforced epoxy laminate materials (such as "FR-4," a composite material made of woven glass fibers with an epoxy resin binder that is flame retardant).

[0013] On top of substrate layer 18 is substrate layer 20, which has three rows of holes 30 along its length. Substrate layer 20 is made of an adhesive material. On top of substrate layer 20 is substrate layer 22, which has three rows of holes 32. Substrate layer 22 is made of one or more conductive materials, such as copper and nickel, or is electroplated with one or more conductive materials.

[0014] The holes 26, 28, 30, 32 in each of the substrate layers 16, 18, 20, 22 have the same size and shape and are arranged such that when the substrate layers 16, 18, 20, 22 are properly assembled and stacked on top of each other, the holes 26, 28, 30, 32 in each of the substrate layers 16, 18, 20, 22 are aligned with each other to collectively form a plurality of cavities 12 extending through the substrate layer 16 and into the substrate layer 22. The substrate layer 16 is positioned below and in contact with the substrate layer 14 such that each slit 24 is positioned below each cavity 12 formed by the row of aligned holes 26, 28, 30, 32.

[0015] FIG. 4 shows an integrated circuit (IC) chip 34. The IC chip 34 may be a contactless chip or another type of chip. In electronics manufacturing, integrated circuit (IC) packaging is the final stage of semiconductor device fabrication, where a block of semiconductor material is encapsulated in a supporting case (also known as a "package") that resists physical damage and corrosion. A common plastic used to form the package is cresol-novolac epoxy (also called "epoxy-cresol-novolac"). The IC chip 34 is shown with two conductive legs 36 extending from the package 38 of the IC chip 34.

[0016] Referring to Figure 5, Figure 5 shows a chip housing carrier 10 with a number of cavities 12 formed by the alignment of holes 26, 28, 30, 32 in respective substrate layers 16, 18, 20, 22 with substrate layer 14 forming the bottom. Substrate layers 14, 16, 18, 20, 22 are stacked in positionally fixed engagement with one another to form a laminated structure, chip housing carrier 10. An IC chip 34 is positioned in one of the cavities 12 such that IC chip 34 is fully contained within cavity 12 with legs 36 contacting substrate layer 14 such that electrical and physical connections are established between legs 36 (and thus IC chip 34) and substrate layer 14. The depth of cavity 12 formed by the alignment of holes 26, 28, 30, 32 in substrate layers 16, 18, 20, 22 is greater than or equal to the overall height h of IC chip 34, with a portion of IC chip 34 accommodated within the cavity formed by holes 26, 28 and another portion of IC chip 34 accommodated within the cavity formed by holes 30, 32.

[0017] Once the IC chip 34 is received within the cavity 12 (and the legs 36 of the IC chip 34 are physically and electrically connected to the base layer 14), an adhesive (glue) fills any space within the cavity 12 that is not occupied by the IC chip 34, thereby enhancing the positionally fixed engagement of the IC chip 34 within the cavity 12 and within the chip housing carrier 10.

[0018] When the IC chip 34 is fixedly engaged and housed in the cavity 12 of the chip housing carrier 10, a plurality of chip modules 40a, 40b can be cut out from the chip housing carrier 10 by, for example, die cutting. Each of the chip modules 40b, 40c includes an IC chip 34 fixedly housed and engaged in the substrate layer 14, 16, 18, 20, 22, where the substrate layer 14 is fixedly engaged with the legs 36 of the IC chip 34. The shapes of the chip modules 40b, 40c are different from each other, where the chip module 40b is generally rectangular prism-shaped, and the chip module 40c is generally elliptical prism-shaped. Generally speaking, the chip modules 40a, 40b according to the present invention are both in the shape of a prism, a cylinder or an elliptical cylinder with a relatively short thickness / height, and more specifically, in the shape of a right square cylinder, a right circular cylinder or a right elliptical cylinder. The two opposing major surfaces of chip module 40a (only one of which, major surface 41a, is shown in FIG. 5) are flat, identically shaped, and parallel to each other. Similarly, the two opposing major surfaces of chip module 40b (only one of which, major surface 41a, is shown in FIG. 5) are flat, identically shaped, and parallel to each other. Thus, chip modules 40a, 40b are not formed with a two-level stepped structure or with a non-flat upper housing, as is the case with conventional chip modules.

[0019] 6-9 show steps of forming a chip module card inlay using chip module 40a as an example.

[0020] As shown in FIG. 6, the chip module 40a is positioned in a hole 42 in a substrate layer 44, which may be made of a plastic material such as polycarbonate (PC), polyvinyl chloride (PVC) or glycol modified polyethylene terephthalate (PETG). For a conventional two-height stepped structure chip module, at least two such substrate layers (also called "compensation layers") are required to meet the requirements of the different shapes of the two heights. On the other hand, the chip module according to the present invention may be in the shape of a rectangular cylinder, a circular cylinder or an elliptical cylinder, more specifically a right rectangular cylinder, a right circular cylinder or a right elliptical cylinder, so that only one compensation layer is required. This facilitates the manufacture of the chip module card inlay (described below) and the subsequent manufacture of the smart card.

[0021] 7, a conductive wire 46 (e.g., made of copper) is embedded in a main surface 48 of the substrate layer 44. The wire 46 may be bent several times and embedded in the main surface 48 of the substrate layer 44, for example to form an antenna. The two free ends of the wire 46 are bonded to the chip module 40a, for example by thermal bonding.

[0022] The substrate layer 44 is sandwiched between two protective substrate layers 50, 52. The two substrate layers 50, 52 may be made of PC, PVC or PETG. The substrate layers 44, 50, 52 thus stacked on top of one another are then laminated to positionally engage the substrate layers 44, 50, 52 to form a laminated structure, the chip module card inlay 54.

[0023] 10 shows a cross-sectional view of a chip module card inlay 60 with a chip module 62. The chip module 62 has an IC chip 64 housed in a cavity 66 formed by the alignment of holes 26, 28 in the respective substrate layers 16, 18. The legs 36 of the IC chip 64 are physically and electrically connected to the substrate layer 14 above the substrate layer 16. Thus, the substrate layer 16 is sandwiched between and fixedly engaged with the substrate layers 14, 18.

[0024] The chip module 62 is housed within a hole 68 in an inner substrate layer 70 and is electrically connected (e.g., by bonding) to an antenna formed from a conductive wire 72 (which may be made of copper). The inner substrate layer 70 is sandwiched between two outer substrate layers 74, 76. The substrate layers 70, 74, 76 are stacked and thus positionally fixedly engaged with one another to form the laminated structure chip module card inlay 60. The depth of the cavity 66 formed by the alignment of the holes 26, 28 in the substrate layers 16, 18 is equal to or greater than the overall height of the IC chip 64.

[0025] It will be understood that the foregoing is merely an illustration and description of ways in which the invention may be practiced, and that modifications and / or variations may be made without departing from the spirit and scope of the invention.

[0026] It is also to be understood that certain features of the invention that are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention that are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable subcombination.

Claims

1. A chip module, comprising: an integrated circuit (IC) chip; a first substrate layer at least partially made of a flexible material and having a first hole; a second substrate layer having a second hole and at least partially made of an adhesive material; a third substrate layer at least partially made of a conductive material; Including, the second substrate layer is sandwiched between the first substrate layer and the third substrate layer and fixedly engaged to the first substrate layer and the third substrate layer; the first hole in the first substrate layer and the second hole in the second substrate layer are aligned with one another to form a first cavity; and At least a first portion of the IC chip is housed in the first cavity. Chip module.

2. 2. The chip module of claim 1, wherein said third substrate layer is comprised at least in part of copper.

3. 2. The chip module of claim 1, wherein the third base layer includes at least one slit that engages a leg of the IC chip to electrically connect the IC chip to the third base layer.

4. 2. The chip module of claim 1, wherein said first hole and said second hole are substantially the same size and shape.

5. 2. The chip module of claim 1, wherein the first substrate layer is made of polyimide (PI), polyethylene terephthalate (PET) and / or glass reinforced epoxy laminate material.

6. 2. The chip module of claim 1, further comprising: a fourth substrate layer having a third hole and a fifth substrate layer having a fourth hole, the fourth substrate layer being at least partially made of an adhesive material.

7. 7. The chip module of claim 6, wherein the third hole and the fourth hole are aligned with each other to form a second cavity, in which at least a second portion of the IC chip is housed.

8. 8. The chip module of claim 7, wherein said third hole and said fourth hole are substantially the same size and shape.

9. 7. The chip module of claim 6, wherein said fifth substrate layer is made of or is electroplated with a conductive material.

10. 2. The chip module of claim 1, wherein the chip module is in the shape of a rectangular prism, a circular cylinder, or an elliptical cylinder.

11. A chip module card inlay comprising at least one chip module according to any one of claims 1 to 10.

12. The chip module card inlay of claim 11 , wherein the chip module is received in a fifth hole in the sixth substrate layer.

13. 13. The chip module card inlay of claim 12, wherein the sixth substrate layer is sandwiched between and fixedly engaged with the seventh substrate layer and the eighth substrate layer.

14. The chip module card inlay of claim 11 , wherein the chip module is electrically connected to at least one conductive wire.

15. 1. A method of forming a chip module, comprising: Providing a first substrate layer at least partially made of a flexible material, the first substrate layer having a plurality of first holes; Providing a second substrate layer having a plurality of second holes formed at least partially from an adhesive material; Providing a third substrate layer at least partially made of a conductive material; aligning the first holes of the first substrate layer with the second holes of the second substrate layer to form a plurality of first cavities; sandwiching the second substrate layer between the first substrate layer and the third substrate layer; fixedly engaging the first substrate layer, the second substrate layer, and the third substrate layer to form a first laminate structure; fixedly engaging at least a first portion of an integrated circuit (IC) chip within one of the first cavities of the first laminate structure; Slicing at least one chip module from the first laminate structure fixedly engaged with the IC chip; A method comprising:

16. The method of claim 15 , wherein the third substrate layer is comprised at least in part of copper.

17. The method of claim 15, further comprising engaging legs of the IC chip with at least one slit in the third substrate layer to electrically connect the IC chip to the third substrate layer.

18. The method of claim 15 , wherein the first hole and the second hole are substantially the same size and shape.

19. 16. The method of claim 15, further comprising filling at least a portion of a space between the first portion of the IC chip and the first cavity with an adhesive material.

20. The method of claim 15, wherein the first substrate layer is comprised of polyimide (PI), polyethylene terephthalate (PET) and / or glass reinforced epoxy laminate material.

21. 16. The method of claim 15, further comprising providing a fourth substrate layer having a plurality of third holes and a fifth substrate layer having a plurality of fourth holes, the fourth substrate layer being at least partially comprised of an adhesive material.

22. 21. The method of claim 20, further comprising: aligning the third hole of the fourth substrate layer with the fourth hole of the fifth substrate layer to form a plurality of second cavities; and positioning at least a second portion of the IC chip within one of the second cavities.

23. The method of claim 22 , wherein the third hole and the fourth hole are substantially the same size and shape.

24. 22. The method of claim 21, wherein the fifth substrate layer is comprised of or is electroplated with a conductive material.

25. The method of claim 21 , further comprising fixedly engaging the fourth substrate layer and the fifth substrate layer to the first laminate structure to form a second laminate structure.

26. A method of forming a chip module card inlay, comprising forming at least one chip module by the method of any one of claims 15 to 24.

27. 27. The method of claim 26, further comprising positioning the chip module in a fifth hole in a sixth substrate layer.

28. 28. The method of claim 27, comprising sandwiching the sixth substrate layer between a seventh substrate layer and an eighth substrate layer, and fixedly engaging the sixth substrate layer, the seventh substrate layer, and the eighth substrate layer to one another.

29. 27. The method of claim 26, further comprising electrically connecting the chip module to at least one conductive wire.

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