Thin-film semiconductor switching devices

Abstract

A novel semiconductor device is taught. The novel device includes a thin film transistor (TFT) having an n-type semiconductor layer forming a channel between a source and a drain. The TFT further includes a source-channel interface member adjacent at least a source contact of the device, which provides depletion layer control of the operation of the TFT.

Description

[Technical field]

[0001] Priority This application claims the benefit of convention priority to U.S. Provisional Patent Application No. 63 / 221,292, filed July 13, 2021, which is incorporated by reference in its entirety into this specification.

[0002] The present invention relates to semiconductor devices, and more particularly to thin film semiconductor switching devices such as transistors.

[0003] 2. Background of the Invention Thin film semiconductor switching devices, such as thin film transistors (TFTs), are widely used in a variety of applications.

[0004] TFTs are perhaps the most common example of a thin-film semiconductor switching device, they are three-terminal field-effect devices with a "source", a "drain" and a "gate". The gate is a control terminal used to enable or block the flow of current from the source to the drain depending on a voltage applied to it.

[0005] The electrical behavior of a TFT is determined by the dominant charge carrier in the active material, which is usually a semiconductor. The dominant charge carrier transports most of the charge or current through the semiconductor. Typically, the dominant charge carrier accumulates at the interface between the gate insulator and the semiconductor material, forming a "channel" through which charge can move through the semiconductor material. The TFT is said to be in the "on" state when the channel has sufficient conductivity from source to drain, allowing current to flow through the channel from source to drain.

[0006] There is an increasing interest in producing smaller TFTs for a variety of reasons. However, conventional TFTs do not scale well to smaller dimensions, such as TFTs with semiconductor lengths below about 1000 nm, in particular TFTs with channel lengths below 200 nm. Below these dimensions, TFTs are difficult to control, and known TFTs, when produced at small dimensions, have threshold voltages (the gate voltage point at which a channel is formed such that the TFT is in the "on" state and conducts current) that occur below 0V, resulting in the TFT being normally "on". These low (often negative) threshold voltages can reduce the output resistance and overall transistor performance of conventional TFTs produced at small dimensions, and such TFTs often require a negative voltage to be applied to their gates to achieve the "off" state and reduce leakage current.

[0007] It would be desirable to have thin film semiconductor devices that can be fabricated with semiconductor or channel lengths of less than 1000 nm and have inherent enhancement threshold voltages that are normally "off" and more easily controlled. Ideally, such devices would also be fabricable as back-end of line ("BEOL") processes.

[0008] Summary of the Invention It is an object of the present invention to provide a novel thin film semiconductor switching device that avoids or mitigates at least one of the disadvantages of the prior art.

[0009] According to a first aspect of the present invention, there is provided a thin film transistor comprising: a substrate; an insulating layer formed on the substrate; a source formed on the insulating layer; a drain formed on the insulating layer and spaced apart from the source; an n-type semiconductor material formed on the insulating layer and extending between the source and the gate; a source-channel interface member electrically connecting at least the source to the semiconductor material; a gate dielectric layer formed above the semiconductor layer; and a gate formed above the dielectric layer such that when a positive voltage is applied, current can flow from the source through the source-channel interface member and a channel formed in the semiconductor material to the drain.

[0010] Preferably, the n-type semiconductor material is a metal oxide. More preferably, the n-type semiconductor material is selected from the group including zinc oxide, tin oxide, indium gallium zinc oxide, gallium oxide, germanium oxide, or a combination thereof.

[0011] Also preferably, the source-channel interface material is an oxide formed by catalytic growth of the source. Also preferably, the source-channel interface material is formed by atomic layer deposition. Also preferably, when the source-channel interface material is an oxide formed by catalytic growth, oxygen preferably migrates to the source-channel interface to form the source-channel interface material.

[0012] According to another aspect of the present invention, there is provided a vertical thin film transistor comprising: a substantially flat substrate; an insulating layer formed on the substrate; a source formed on the insulating layer; a second insulating layer formed on the source and forming a vertical well having an inner surface; a source-channel interface member formed on the inner surface of the vertical well and on the source; an n-type semiconductor material formed on the source-channel interface member such that the source is electrically connected to the n-type semiconductor material by the source-channel interface member; a gate dielectric layer formed above the n-type semiconductor layer; a gate formed above the dielectric layer; and a drain formed on the insulating layer in electrical contact with the n-type semiconductor material, wherein when a positive voltage is applied to the gate, a current can flow from the source through the source-channel interface member and the channel formed in the semiconductor material to the drain.

[0013] According to another aspect of the present invention, there is provided a vertical thin film transistor comprising: a substantially planar substrate; an insulating layer formed on the substrate; a drain formed on the insulating layer; a second insulating layer formed on the drain and forming a vertical well having an inner surface extending upwardly from the drain; an n-type semiconductor material formed on the inner surface of the well and on the drain; a gate dielectric layer formed above the semiconductor layer; a gate formed above the dielectric layer; a source; and a source-channel interface member formed on the second insulating layer and electrically connecting the source to the n-type semiconductor material, wherein when a positive voltage is applied to the gate, current can flow from the source through the source-channel interface member and the channel formed in the semiconductor material to the drain.

[0014] According to yet another aspect of the present invention, there is provided a vertical thin film transistor comprising: a substantially planar substrate; an insulating layer formed on the substrate; a drain formed on the insulating layer; a second insulating layer formed on the drain and forming a vertical well having an inner surface extending upwardly from the drain; an n-type semiconductor material formed on the inner surface of the well and on the drain; a gate dielectric layer formed above the semiconductor layer; a gate formed above the dielectric layer; a source; and a source-channel interface member formed on the second insulating layer and electrically connecting the source to the n-type semiconductor material, wherein when a positive voltage is applied to the gate, a current can flow from the source through the source-channel interface member and the channel formed in the semiconductor material to the drain.

[0015] Other features and advantages of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: It should be understood that the detailed description and the specific examples contained therein, while indicating preferred embodiments at the time of filing, are given by way of example only, since the spirit and scope of the present invention is defined solely by the claims, and various changes and modifications therein will be apparent to those skilled in the art.

[0016] For a better understanding of the various embodiments of the invention described herein, reference is made to the accompanying drawings, which are not drawn to scale and are intended to improve clarity of understanding of the specification, but are not intended to limit the scope of the invention described herein. [Brief description of the drawings]

[0017] [Figure 1a] FIG. 1 is a cross-sectional view showing a TFT of the prior art. [Figure 1b] FIG. 1 is a cross-sectional view showing a TFT of the prior art. [Figure 1c] FIG. 1 is a cross-sectional view showing a TFT of the prior art. [Figure 1d] FIG. 1 is a cross-sectional view showing a TFT of the prior art. [Figure 1e] Cross-sectional view showing a conventional TFT. [Figure 2a] Cross-sectional view showing a TFT according to an embodiment of the present invention, cut along line A-A of FIG. 2b. [Figure 2b] Top view showing the TFT of FIG. 2a. [Figure 2c] Cross-sectional view showing a TFT according to another embodiment of the present invention. [Figure 2d] Cross-sectional view showing a TFT according to another embodiment of the present invention. [Figure 3a] Schematic symbol of the TFT of FIG. 2a. [Figure 3b] Cross-sectional view showing a part of the TFT of FIG. 2a operating in the forward active state. [Figure 3c] Cross-sectional view showing a part of the TFT of FIG. 2a operating in the off state. [Figure 3d] Cross-sectional view showing a part of the TFT of FIG. 2a operating in the zero voltage state. [Figure 4a] Schematic symbol of the TFT of FIG. 2c. [Figure 4b] Cross-sectional view showing a part of the TFT of FIG. 2c operating in the forward active state. [Figure 4c] Cross-sectional view showing a part of the TFT of FIG. 2c operating in the off state. [Figure 4d] Cross-sectional view showing a part of the TFT of FIG. 2c operating in the zero voltage state. [Figure 5a] Schematic symbol of the TFT of FIG. 2d. [Figure 5b] Cross-sectional view showing a part of the TFT of FIG. 2d operating in the forward active state. [Figure 5c] Cross-sectional view showing a part of the TFT of FIG. 2d operating in the off state. [Figure 5d] Cross-sectional view showing a part of the TFT of FIG. 2d operating in the zero voltage state. [Figure 6] Flowchart showing a method for manufacturing a TFT according to an embodiment of the present invention. [Figure 7a]7A to 7C are cross-sectional views showing a stage in the fabrication of a TFT by the method of FIG. [Figure 7b] 7A to 7C are cross-sectional views showing a stage in the fabrication of a TFT by the method of FIG. [Figure 7c] 7A to 7C are cross-sectional views showing a stage in the fabrication of a TFT by the method of FIG. [Figure 7d] 7A to 7C are cross-sectional views showing a stage in the fabrication of a TFT by the method of FIG. [Figure 7e] 7A to 7C are cross-sectional views showing a stage in the fabrication of a TFT by the method of FIG. [Figure 7f] 7A to 7C are cross-sectional views showing a stage in the fabrication of a TFT by the method of FIG. [Figure 7g] 7A to 7C are cross-sectional views showing a stage in the fabrication of a TFT by the method of FIG. [Figure 7h] 7b is a top view of the fabrication stage of the TFT of FIG. 7a. [Figure 7i] 7b is a top view of the TFT fabrication stage of FIG. 7b. [Figure 7j] 7c is a top view of the TFT fabrication stage of FIG. [Figure 7k] FIG. 7D is a top view of the TFT fabrication stage of FIG. [Figure 7l] FIG. 7e is a top view of the TFT fabrication stage of FIG. [Figure 7m] FIG. 7f is a top view of the TFT fabrication stage. [Figure 7n] FIG. 7g is a top view of the TFT fabrication stage. [Figure 8a] 1 is a cross-sectional view of a TFT during fabrication according to one embodiment of the present invention. [Figure 8b] 4 is a cross-sectional view showing a TFT under construction according to another embodiment of the present invention. [Figure 8c] FIG. 8b is a top view of the TFT of FIG. 8a. [Figure 8d] FIG. 8b is a top view of the TFT. [Figure 9a] FIG. 2 is a cross-sectional view showing a vertical TFT according to another embodiment of the present invention. [Figure 9b] FIG. 2 is a cross-sectional view illustrating another vertical TFT according to an embodiment of the present invention. [Figure 9c]FIG. 2 is a cross-sectional view illustrating another vertical TFT according to an embodiment of the present invention. [Figure 9d] FIG. 9c is a cross-sectional view of a vertical TFT fabricated in a similar but asymmetric embodiment to that of FIG. 9b. [Figure 10a] 4 is a flow chart illustrating a method for fabricating a TFT according to another embodiment of the present invention. [Figure 10b] 4 is a flow chart illustrating a method for fabricating a TFT according to another embodiment of the present invention. [Figure 11a] 10a and 10b are cross-sectional views showing a stage in manufacturing a TFT by the method of FIG. [Figure 11b] 10a and 10b are cross-sectional views showing a stage in manufacturing a TFT by the method of FIG. [Figure 11c] 10a and 10b are cross-sectional views showing a stage in manufacturing a TFT by the method of FIG. [Figure 11d] 10a and 10b are cross-sectional views showing a stage in manufacturing a TFT by the method of FIG. [Figure 11e] 10a and 10b are cross-sectional views showing a stage in manufacturing a TFT by the method of FIG. [Figure 11f] 10a and 10b are cross-sectional views showing a stage in manufacturing a TFT by the method of FIG. [Figure 11g] 10a and 10b are cross-sectional views showing a stage in manufacturing a TFT by the method of FIG. [Figure 11h] 10a and 10b are cross-sectional views showing a stage in manufacturing a TFT by the method of FIG. [Figure 11i] 10a and 10b are cross-sectional views showing a stage in manufacturing a TFT by the method of FIG. [Figure 11j] 10a and 10b are cross-sectional views showing a stage in manufacturing a TFT by the method of FIG. [Figure 11k] 10a and 10b are cross-sectional views showing a stage in manufacturing a TFT by the method of FIG. [Figure 11l] FIG. 11b is a top view of the TFT of FIG. [Figure 11m]FIG. 11b is a top view of the TFT. [Figure 11n] FIG. 11c is a top view of the TFT. [Figure 11o] FIG. 11d is a top view of the TFT. [Figure 11p] FIG. 11e is a top view of the TFT. [Figure 11q] FIG. 11f is a top view of the TFT. [Figure 11r] FIG. 11g is a top view of the TFT. [Figure 11s] FIG. 11h is a top view of the TFT. [Figure 11t] FIG. 11i is a top view of the TFT. [Figure 11u] FIG. 11j is a top view of the TFT. [Figure 11v] FIG. 11k is a top view of the TFT. [Figure 12a] 4 is a flow chart illustrating a method of making a TFT according to another embodiment of the present invention. [Figure 12b] 4 is a flow chart illustrating a method of making a TFT according to another embodiment of the present invention. [Figure 13a] FIG. 12c is a cross-sectional view showing a TFT during fabrication according to the method of FIGS. 12a and 12b. [Figure 13b] FIG. 12c is a cross-sectional view showing a TFT during fabrication according to the method of FIGS. 12a and 12b. [Figure 13c] FIG. 12c is a cross-sectional view showing a TFT during fabrication according to the method of FIGS. 12a and 12b. [Figure 13d] FIG. 12c is a cross-sectional view showing a TFT during fabrication according to the method of FIGS. 12a and 12b. [Figure 13e] FIG. 12c is a cross-sectional view showing a TFT during fabrication according to the method of FIGS. 12a and 12b. [Figure 13f] FIG. 12c is a cross-sectional view showing a TFT during fabrication according to the method of FIGS. 12a and 12b. [Figure 13g] FIG. 12c is a cross-sectional view showing a TFT during fabrication according to the method of FIGS. 12a and 12b. [Figure 13h] FIG. 12c is a cross-sectional view showing a TFT during fabrication according to the method of FIGS. 12a and 12b. [Figure 13i] FIG. 12c is a cross-sectional view showing a TFT during fabrication according to the method of FIGS. 12a and 12b. [Figure 13j] FIG. 12c is a cross-sectional view showing a TFT during fabrication according to the method of FIGS. 12a and 12b. [Figure 13k] FIG. 12c is a cross-sectional view showing a TFT during fabrication according to the method of FIGS. 12a and 12b. [Figure 13l] FIG. 13b is a top view of the TFT of FIG. [Figure 13m] FIG. 13b is a top view of the TFT. [Figure 13n] FIG. 13c is a top view of the TFT. [Figure 13o] FIG. 13d is a top view of the TFT. [Figure 13p] FIG. 13e is a top view of the TFT. [Figure 13q] FIG. 13f is a top view of the TFT. [Figure 13r] FIG. 13g is a top view of the TFT. [Figure 13s] FIG. 13h is a top view of the TFT. [Figure 13t] FIG. 13i is a top view of the TFT. [Figure 13u] FIG. 13j is a top view of the TFT. [Figure 13v] FIG. 13k is a top view of the TFT.

[0018] Further aspects and features of the exemplary embodiments described herein will become apparent from the following description taken in conjunction with the accompanying drawings.

[0019] Detailed Description of the Invention In the following description, like components and like elements are designated by like reference numerals. Moreover, as will be appreciated by those skilled in the art, most semiconductor devices are manufactured in a series of steps, i.e., substantially planar layers of materials are formed, and portions of these layers are subsequently removed, processed, and / or replaced with subsequent layers to obtain the desired semiconductor device. Thus, as used herein, the terms "horizontal" and "vertical" are used with respect to the planes of these layers, with the horizontal direction referring to a direction generally parallel to the planes of the layers, and the vertical direction referring to a direction generally perpendicular to the planes of the layers. Similarly, terms such as "up," "down," "on," and "under" are also used with respect to these planar layers.

[0020] Furthermore, while the fabrication of layers and / or features of the semiconductor devices described herein may be referred to herein as "forming" those layers and / or features, as will be apparent to those of skill in the art, "forming" is intended to include all semiconductor fabrication techniques that may be suitable and applicable for the fabrication herein, including, but not limited to, deposition (such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, etc.), sputtering, PECVD (plasma enhanced chemical vapor deposition), implantation and annealing, oxidation, etc.

[0021] Before describing embodiments of the present invention, an example of a prior art TFT will be described with reference to Figures 1a-1e for ease of understanding.

[0022] 1a shows a first example of a prior art TFT, generally designated 100a. The TFT 100a has a substrate 120 with an insulating layer 118 formed thereon. The TFT 100a further includes a gate 102, a source 106, and a drain 110.

[0023] The gate 102 includes a gate electrode 104 and a gate contact 103, the source 106 includes a source electrode 107 and a source contact 108, and the drain 110 includes a drain electrode 111 and a drain contact 112. As will be apparent to one skilled in the art, the source electrode 107 and the source contact 108 may be comprised of the same or different materials. In particular, the material of the source contact 108 may be selected to provide a desired work function, while the material of the source electrode 107 may also be selected to simplify connection of the source electrode 107 to other devices, etc. The gate electrode 104 and the gate contact 103, the drain electrode 111 and the drain contact 112 may likewise be formed of the same or different materials, respectively, as desired.

[0024] The TFT 100a also includes a dielectric layer 114 and a semiconductor layer 116. The TFT 100a may optionally include a gate tuning layer 122, as will be appreciated by those skilled in the art.

[0025] The operation of the TFT 100a relies on the use of a semiconductor layer 116 as an active material capable of forming a channel. When the semiconductor layer 116 is in an active state, a channel is formed between the source contact 108 and the drain contact 112, allowing current to flow therebetween. In the illustrated embodiment, an n-type semiconductor is shown.

[0026] In an n-type semiconductor-based TFT (or “n-type TFT”), such as TFT 100a, a voltage (i.e., V g ) is the threshold voltage (i.e., V th ), the TFT is in its active ("on" state. In a TFT containing an n-type semiconductor, a positive gate voltage above the threshold voltage causes negatively charged electrons to be injected from the source into the n-type semiconductor. When a voltage (i.e., V dWhen a voltage is applied, the injected electrons move from the source to the drain through a channel formed in the semiconductor, causing a current, i.e., a source-drain current (I ds ) or drain current (I d ) occurs.

[0027] 1b, which shows a detailed view of a relevant portion of TFT 100a, illustrates accumulation layer 130. Accumulation layer 130 is illustrated by a gradient indicating a varying electron concentration along a channel through semiconductor layer 116, where a higher electron concentration (indicated by a darker color in accumulation layer 130) is present closer to source contact 107 than to drain contact 111.

[0028] When a low drain voltage (relative to the gate voltage) is applied, the charge carrier concentration in the channel tends to be uniform across the channel and the TFT 100a is considered to be “ohmic.” When a high drain voltage is applied, the channel “pinches off” and the highly insulating region adjacent to the drain contact 111 begins to form a depletion layer 135, which exhibits a reduced charge carrier density, as shown in FIG. 1c.

[0029] A conventional TFT typically has two channels for current flow: the first channel is formed via an ohmic connection between the source contact 107 and the drain contact 111, and the second channel is formed by an accumulation layer at the interface between the gate dielectric layer 114 and the semiconducting layer 116.

[0030] TFT 100a has a limited "off" state due to current flow through this channel due to the channel available under gate contact 103. Thus, conventional TFTs do not always "pinch off" well and can then have substantial leakage problems where some current continues to flow even though it is intended to be "off."

[0031] Conventional TFTs may also experience output resistance problems if the source contact 107 and drain contact 111 are too close to each other. For example, as discussed above, significant levels of leakage occur when the source contact 107 and drain contact 111 are spaced less than about 1000 nm apart, and especially less than 200 nm apart. Thus, conventional TFTs are typically in an "on" state even under zero bias. In many cases, a negative gate voltage must be applied to conventional TFTs to create a depletion layer or region in order to limit the flow of current between the source contact 107 and drain contact 111 and effectively "turn off" the TFT.

[0032] FIG. 1d shows a source-gated TFT 100d. TFT 100d is similar to TFT 100a, except that the source 106′ of TFT 100d is made of a Schottky metal and the source 106 and drain 110 of TFT 100a are ohmic contacts. Also, in some cases, TFT 100d may differ from TFT 100a in terms of fabrication method, semiconductor material, or both. TFT 100d may take advantage of the asymmetry of the source 106′ and drain 110 to enhance electrical conductivity between the source 106′ and drain 110.

[0033] 1e shows another type of source-gated TFT 100e. TFT 100e is similar to TFT 100a, except that both the source 106' and drain 110' of TFT 100e are made of Schottky metal. Unlike TFT 100d, TFT 100e takes advantage of the symmetry of the source contact 106' and the drain contact 110'.

[0034] However, both TFT 100d and TFT 100e face similar challenges as those discussed above with respect to TFT 100a, especially when fabricated at smaller dimensions.

[0035] 2a shows a cross-sectional view of a TFT 200a taken along line 2A-2A in FIG. 2b according to one embodiment of the present invention. As shown, the TFT 200a includes a gate 202, a source 206, and a drain 210. The gate 202 includes a gate electrode 204 and a gate contact 203, the source 206 includes a source electrode 208 and a source contact 207, and the drain 210 includes a drain electrode 212 and a drain contact 211. As in the case of the conventional TFT 100a described above, the electrodes and contacts of each of these features can each be formed from the same material, or the materials can be selected separately as desired. For example, the source contact 207 can be formed from a material selected for its desired work function, while the source electrode 208 can be selected from a material better suited for connection to other components of a circuit, such as a metallization layer.

[0036] The TFT 200a also includes a dielectric layer 214 and a semiconducting layer 216. The TFT 200a may have an optional gate tuning layer 222. These layers, and the TFT 200a as a whole, are formed on an insulating layer 218 that is formed above a substrate 220. In many circumstances, the substrate 220 is assumed to be a silicon wafer, as is commonly used in semiconductor manufacturing, although the invention is not so limited and the substrate 220 may in fact be a wide variety of materials, including, but not limited to, glass, ceramic, metal, flexible polymer or other plastics, and the like.

[0037] In the illustrated embodiment, the semiconductor layer 216 is an n-type semiconductor layer. The n-type semiconductor layer 216 is preferably a semiconductor material selected such that it can be formed at a temperature less than 300° C. Examples of suitable materials for the semiconductor layer 216 include, but are not limited to, zinc oxide, tin oxide, indium gallium zinc oxide, gallium oxide, germanium oxide, and the like.

[0038] Unlike prior art TFTs, TFT 200a further includes a source-channel interface 250, which in this embodiment is a layer of p-type semiconductor material that extends from source contact 207 to drain contact 211 below semiconductor layer 216. Source-channel interface 250 electrically connects source contact 207 to semiconductor layer 216, and is otherwise electrically isolated from semiconductor layer 216. Additionally, in this example, source-channel interface 250 electrically connects semiconductor layer 216 to drain contact 211.

[0039] The gate contact 203 can include any elemental material or material compound that is electrically conductive. Examples of materials that can be used for the gate contact 203 include titanium, titanium nitride, chromium, hafnium, tantalum nitride, or any other elemental or bimetallic element or compound. The gate electrode 204 can be formed from the same material as the gate contact 203 or from another material that provides the desired properties for connecting the gate electrode 204 to other components.

[0040] The source 206 and drain 210 can include any elemental material or material compound that has electrical conductivity. In particular, the source contact 207 and drain contact 211 can be metal or degenerate (heavily doped) semiconductor. Examples of suitable materials that can be used in the source contact 207 and / or drain contact 211 include nickel, tungsten, molybdenum, aluminum, gold, copper, cobalt, ruthenium, titanium nitride, tantalum nitride, silicon, and / or any III-V compound semiconductor with high electrical conductivity. In some cases, the drain contact 211 is made of the same material as the source contact 207. In other cases, the drain contact 211 is made of a material with a higher electrical conductivity that can reduce the barrier to electron transport than the material used in the source contact 207.

[0041] The source-channel interface material 250 is provided to store complementary excess negative charge and serves to deplete the channel in at least a region of the semiconductor layer 216 adjacent the source contact 207. In this manner, the source-channel interface material 250 acts as an electron transport barrier such that substantially no current flows through the semiconductor layer 216 when the TFT 200a is in the "off" state.

[0042] The operation of the source-channel interface member 250 can be achieved in a variety of configurations including p-type semiconductors, piezoelectric induced dipoles, controllable tunnel barriers, combinations of these, or other mechanisms for modulating the injection current by an externally applied electric field.

[0043] For example, when implemented as a p-type semiconductor, the source-channel interface material 250 may be formed from elemental germanium or by using a p-type dopant in the relevant portion of the semiconductor layer 216. In other cases, the source-channel interface material 250 may be comprised of an oxide or sulfide, or other elements corresponding to Group VI(A) of the periodic table, or chalcogens, such as oxygen, sulfur, selenium, tellurium, or polonium.

[0044] The source-channel interface material 250 may also be formed by catalytic growth of the material that forms the source contact 207. In this case, oxygen may preferentially migrate to the source-channel interface, thereby creating the source-channel interface material. In other cases, the source-channel interface material 250 may be formed by depositing a p-type dopant, such as a p-type metal oxide or other semiconductor, by a deposition technique, such as atomic layer deposition, sputtering physical vapor deposition, or chemical vapor deposition.

[0045] In an embodiment of TFT 200a, source-channel interface member 250 is formed as a continuous member extending from source contact 207 to drain contact 211. Although source-channel interface member 250 need only be disposed adjacent source contact 207 for electrical connection between source contact 207 and semiconductor layer 216, it may also be formed as a layer extending between source contact 207 and drain contact 211, as a layer adjacent only source contact 207, or as a layer adjacent each of source contact 207 and drain contact 211, depending on the manufacturing process used to fabricate TFT 200a.

[0046] To prevent charge depletion during the "on" state of TFT 200a, it may be desirable to form semiconductor layer 216 with compositional control such that semiconductor layer 216 is highly n-type near source contact 207 and drain contact 211. In other embodiments, semiconductor layer 216 is formed to be highly n-type near source contact 207, drain contact 211, and gate contact 203 to allow tuning of the threshold voltage of TFT 200a. Thus, the properties of TFT 200a can be controlled based on the location and degree of n-type doping in semiconductor layer 216.

[0047] 2a, a dielectric layer 214 separates the gate contact 203 from the semiconductor layer 216. The dielectric layer 214 blocks electron flow to the gate contact 203 and allows electrons to form a channel between the source contact 207 and the drain contact 211, which has a high electron concentration. The dielectric layer 214 may be made of a material such as hafnium oxide (HfO2), zirconium dioxide (ZrO2), silicon dioxide (SiO2), silicon nitride (Si3N4), or any other suitable material as would occur to one skilled in the art.

[0048] The TFT 200a may also include an optional gate tuning layer 222. The gate tuning layer 222 may be a layer of metal atoms used to tune the effective barrier height and / or work function of the gate contact 203, as desired, as would be apparent to one of ordinary skill in the art.

[0049] In TFT 200a, each of the gate electrode 204, source electrode 208, and drain electrode 212 are typically formed from a highly conductive metal, such as copper or aluminum, which is used to electrically connect the corresponding electrode to appropriate elements in the remainder of the integrated circuit in which TFT 200a is formed.

[0050] The TFT 200a also includes an insulating layer 218 formed on the substrate 220. The substrate 220 serves as a foundation for building components and devices such as transistors and integrated circuits, and the insulating layer 218 is the substrate 220 dielectrically isolated from the source contact 207 and the drain contact 211. Examples of the insulating layer 218 include materials such as silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), and examples of the substrate 220 include silicon, glass, plastic materials and / or flexible polymers, printed circuit boards, and the like. In some circumstances, such as the case shown in FIG. 2a, the source-channel interface member 250 extends between the source contact 207 and the drain contact 211, but depending on the material of the substrate 220, it may also function as the insulating layer 218, in which case the insulating layer 218 would be formed prior to forming the source contact 207 and the drain contact 211.

[0051] As discussed above, TFT 200a has improved operating characteristics compared to prior art TFTs, and is intended to operate at particularly high threshold voltages, particularly when fabricated with channel length dimensions of 1000 nm or less.

[0052] As discussed above, the source-channel interface 250 is used to create a reservoir of complementary excess negative charge and functions to deplete the channel at least in the region of the semiconductor layer 216 adjacent the source contact 207. In a TFT fabricated according to an embodiment of the invention, such as TFT 200a, the distance from the gate contact 203 through the gate dielectric layer 214, the semiconductor layer 216, and the source-channel interface 250 to the source contact 207 is selected such that the electric field induced by a voltage applied to the gate contact 203 reduces the blocking potential of the complementary excess negative charge reservoir introduced by the source-channel interface 250, causing the TFT, i.e., TFT 200a, to be in the "on" state. In the absence of such applied gate voltage, the blocking potential causes the TFT to be in the "off" state.

[0053] The TFT 200a can be fabricated with its various elements formed within a range of thicknesses. As will be apparent to those skilled in the art, the primary limiting factor is the need for the gate contact 203 to be sufficiently electrically close to the source contact 207 so that a threshold voltage applied to the gate 202 is used to effectively reduce the barrier to electron flow into the semiconductor layer 216 induced by the source-channel interface member 250. The inability to induce a sufficient electric field reduces the ability to turn on the TFT 200a. This is very similar to a well-known criterion for MOSFETs and the like, typically referred to as the Ada(η) coefficient.

[0054] In a first example of TFT 200a, the semiconductor layer 216 is formed to a thickness of about 20 nm (dielectric constant of about 8), the source-channel interface member 250 is formed to a thickness of about 2 nm (dielectric constant of about 10), and the dielectric layer 214 is formed to a thickness of about 10 nm (dielectric constant of about 24).

[0055] In another example of TFT 200a, semiconductor layer 216 is formed to a thickness of about 5 nm (dielectric constant of 17), source-channel interface member 250 is formed to a thickness of about 0.5 nm (dielectric constant of about 10), and dielectric layer 214 is formed to a thickness of about 5 nm (dielectric constant of about 24).

[0056] The actual selection of the respective vertical thicknesses of the semiconductor layer 216, the dielectric layer 214, and the source-channel interface member 250 will depend in part on the properties of the materials selected and the fabrication techniques used, although certain such selections are now well within the ability of those of ordinary skill in the art in light of the disclosure herein.

[0057] 2c shows a cross-sectional view of a TFT 200c according to another embodiment of the invention. In the TFT 200c, the source-channel interface material 250 is not a continuous layer extending between the source contact 207 and the drain contact 211, but instead is formed only at the source contact 207 and the drain contact 211, respectively. In the TFT 200c, the source-channel interface material 250 can be formed by catalytic growth of the metal that forms the source contact 207 and the drain contact 211. In some cases, the source-channel interface material 250 is comprised of an oxide or sulfide or other element corresponding to group VI(A) of the periodic table, or a chalcogen.

[0058] 2d shows a cross-sectional view of another TFT 200d according to another embodiment of the invention. In the TFT 200d, the source-channel interface material 250 is formed only at the source contact 207 and can be formed by catalytic growth of the metal forming the source contact 207. In this case, the material forming the drain contact 211 can be selected to be "noble", i.e., not readily interact with oxidizing agents. The source-channel interface material 250 can be formed from oxides or sulfides, or other elements corresponding to group VI(A) of the periodic table, or chalcogens.

[0059] The presence or absence of the source-channel interface material 250 on the drain contact 211 changes the electrical characteristics of the TFT 200c. In the TFT 200c, the absence of the source-channel interface material 250 on the drain contact 211 increases the threshold voltage of the TFT 200c by about 0.1 V to 2 V compared to the TFTs 200a and 200b. If the source-channel interface material 250 is formed by catalytic growth of an oxide or sulfide, it can be readily formed on the drain contact 211 in addition to forming the source-channel interface material 250 on the source contact 207, and additional processing to remove the source-channel interface material 250 from the drain contact 211 is not required unless a reduction in the threshold voltage is desired.

[0060] Reference is now made to Figures 3a-3d, which illustrate a TFT 300 according to one embodiment of the present invention and its performance under various operating conditions. In the set of Figures 3, 4 and 5 below, the substrate and insulating layers have been omitted from the figures for ease of understanding.

[0061] In various embodiments illustrated herein, a structure functionally similar to a bipolar junction transistor (BJT) is introduced by the source-channel interface member 250 adjacent to the source contact 207. The TFT embodiments disclosed herein effectively combine a field effect transistor (FET) architecture with a structure similar to the emitter of a BJT at the source contact.

[0062] BJT-like structures similar to these have a collector and base coupled either by a direct ionic short or a collection of recombination centers, and electrons are injected from an emitter-like structure into the source contact 207. A schematic diagram of a TFT 300 having a source-channel interface member 350 at each of the source contact 307 and drain contact 311 is shown generally in Figure 3a.

[0063] Figure 3b shows the TFT 300 in a forward active state (here VDS >0V GS >.V Threshold 3c shows a cross-sectional view of an example TFT 300 when the TFT 300 is in an off state (here V DS >0V GS <V Threshold 3b when the TFT 300a is in a 0V state (here V DS >0V GS <V Threshold 3, a cross-sectional view of an example TFT 300 is shown when in a 3D display.

[0064] TFT 300 is similar to TFT 200a of FIG. 2a, with source contact 307, source electrode 306, drain contact 311, drain electrode 310, gate electrode 302, gate contact 303, dielectric layer 314, source-channel interface member 350 and n-type semiconductor layer 316 being similar to the respective elements described above with respect to TFT 200a of FIG. 2a.

[0065] In the embodiment of TFT 300, similar to TFT 200a, a source-channel interface member 350 extends between the source contact 307 and the drain contact 311, thereby forming a structure similar to a gate limited junction field effect transistor (JFET) or accumulation MOSFET with a BJT equivalent at the source contact 307 and the drain contact 311.

[0066] 3b shows the operation of the TFT 300 in its forward active state (or "on" state). The forward active state is when the drain voltage (V DS ) is greater than 0V, and the gate voltage (V GS ) is the threshold voltage (V Threshold ) In the forward active state, an electron accumulation layer 330 forms beneath the gate contact 303, below the dielectric layer 314. In that operating state, the accumulation layer 330 allows electrons to flow from the source contact 307 to the drain contact 311.

[0067] FIG. 3c shows the TFT 300 in the “off” state mode. The TFT 300 is driven by a gate voltage (V GS ) is the threshold voltage (V Threshold ) the operation is turned off. In the illustrated embodiment, the drain voltage (V DS A depletion region 335 is formed in the semiconductor layer 316 below the gate contact 303 such that electron flow between the source contact 307 and the drain contact 311 is greatly reduced or substantially eliminated even when V 1 is greater than 0 V.

[0068] FIG. 3d shows the TFT 300 in a “0V” state, with no voltage applied to the TFT 300. GS ) is at or near 0V, the depletion region 335 becomes more pronounced and proximate to both the source contact 307 and the drain contact 311, which greatly reduces or substantially eliminates the electron flow between the source contact 307 and the drain contact 311. This places the TFT 300 in an enhanced off state and reduces or substantially eliminates the parasitic channel in the TFT 300.

[0069] 4a-4d, which illustrate a TFT 400 according to one embodiment of the present invention and its performance under various operating conditions. TFT 400 is similar to TFT 200c of FIG. 2c, with source contact 407, drain contact 411, gate contact 403, dielectric layer 414, source-channel interface material 450 and n-type semiconductor layer 416 being similar to the respective elements described above with respect to TFT 200c of FIG. 2c.

[0070] Figure 4a is a schematic model of a TFT 400. In this embodiment of the TFT 400, a source-channel interface member 450 is formed on each of the source contact 407 and drain contact 411, but does not extend between the two. This effectively forms a JFET-like device with a structure similar to a BJT at the source contact 407 and drain contact 411, similar to Figure 3a.

[0071] Figure 4b shows the forward active state (here, V DS >0V GS >V Threshold ) is shown. Similar to TFT 300 in its forward active state, an electron storage layer 430 is formed below gate contact 403 below dielectric layer 414. In its operating state, storage layer 430 allows electrons to flow from source contact 406 to drain contact 410.

[0072] Figure 4c shows the “off” state (here, V DS >0V GS <V Threshold ), where a depletion region 435 blocks electron flow between source contact 407 and drain contact 411.

[0073] FIG. 4d shows the TFT 400 in a 0V state. Similar to TFT 300, the gate voltage (V GS ) is at or near 0V, the depletion region 435 becomes more pronounced and approaches both the source contact 407 and the drain contact 411, which greatly reduces or substantially eliminates the electron flow between the source contact 407 and the drain contact 411. This places the TFT 400 in an enhanced off state and reduces or substantially eliminates the parasitic channel of the TFT 400.

[0074] The difference in the gradient and configuration (e.g., thickness) of the accumulation layer and depletion region between TFT 300 and TFT 400 arises from the presence or absence of source-channel interface material in the devices, with the higher concentration and more highly dispersed presence of the source-channel interface material providing better depletion control of the n-type semiconductor channel.

[0075] 5a-5e, which illustrate a TFT 500 according to one embodiment of the present invention and its performance under various operating conditions. TFT 500 is similar to TFT 200d of FIG. 2d, with source electrode 507, source contact 506, drain electrode 511, drain contact 510, gate electrode 503, gate contact 502, dielectric layer 514, source-channel interface material 550 and n-type semiconductor layer 516 being similar to source electrode 208, source contact 207, drain electrode 212, drain contact 211, gate electrode 204, gate contact 203, dielectric layer 214, source-channel interface material 250 and semiconductor layer 216 of FIG. 2d.

[0076] 5a is a schematic model of a TFT 500 in which a source-channel interface member 550 is adjacent only to a source contact 506, effectively forming a JFET with a BJT at the source contact 506.

[0077] Figure 5b shows the TFT 500 in a forward active state, Figure 5c shows the TFT 500 in an "off" state, and Figure 5d shows the TFT 500 in a 0V state.

[0078] The characteristics of the accumulation layer 530 and depletion regions 535, 540 of TFT 500 are similar to those of TFT 300 of FIG. 3a and TFT 400 of FIG. 4a, where depletion region 540 is an asymmetric version of depletion region 435 of FIG. 4d in the 0V state.

[0079] Reference is now made to Figure 6, which is a flow chart illustrating a method 600 for manufacturing a TFT in accordance with one embodiment of the present invention. Method 600 of Figure 6 will be discussed with reference to Figures 7a-7n, which show examples of various steps associated with the method, for TFT 700, and with reference to Figures 8a-8d, for TFT 800a and TFT 800b.

[0080] The terms "forming" or "forming" as used herein are intended to encompass any suitable manner for producing the structures described herein, which may include processes such as atomic layer deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, sputtering, ion implantation, oxidation, electrochemical deposition, molecular beam epitaxy, etc. Selection of a particular suitable process is well within the discretion of one of ordinary skill in the art.

[0081] Method 600 begins at step 605, where source contact 707 and drain contact 711 are formed on top of an insulating layer 718, which is itself then formed on top of a substrate 720, as shown in Figure 7a. Figure 7a shows a cross-sectional view of TFT 700 taken along line BB in Figure 7h, which shows the corresponding top view.

[0082] As mentioned above, the insulating layer 718 may be formed from materials such as silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), etc. The substrate 720 may be any suitable substrate that may be suitable to serve as a foundation for building components and devices such as transistors and integrated circuits, image sensors and displays, examples of which include, but are not limited to, silicon, flexible polymers and other plastics, ceramic materials, optical glasses, metals, etc.

[0083] In some cases, the source contact 707 and the drain contact 711 are formed by deposition via a lithography process. However, as will be apparent to one of ordinary skill in the art, the method of forming the source contact 707 and the drain contact 711 is not particularly limited and may be formed by a variety of other processes apparent to one of ordinary skill in the art.

[0084] If the source contact 707 and the drain contact 711 are formed from the same material, then both the source contact 707 and the drain contact 711 can be formed simultaneously in the same step in step 605. If the source contact 707 and the drain contact 711 are made of different materials, then the source contact 707 and the drain contact 711 can be formed in separate steps.

[0085] In step 610, a source-channel interface member 750 is formed. In the example shown in Figure 7b, which is a cross-sectional view taken along line CC of Figure 7i, the source-channel interface member 750 is formed on top of the source contact 707 and the drain contact 711 and extends across the area of ​​the insulating layer 718 therebetween. The source-channel interface member 750 may be a p-type semiconductor formed by any suitable technique, including deposition techniques such as, but not limited to, atomic layer deposition, sputtering, or chemical vapor deposition.

[0086] However, source-channel interface material 750 can be formed in other ways, and reference is now made to Figure 8a, which illustrates a cross-sectional view taken along line DD of TFT 800 of Figure 8c, similar to that of Figure 7b, according to another embodiment of the invention. In TFT 800, source-channel interface material 850 has been formed by controlled oxidation of metal structures underlying both source contact 807 and drain contact 811. As shown, this results in source-channel interface material 850 being formed on source contact 807, and source-channel interface material 850 being formed on drain contact 811.

[0087] Figure 8b shows a cross-sectional view of a TFT 800b according to another embodiment of the invention taken along line EE of Figure 8d. In TFT 800b, drain contact 811 is formed from a material that is noble (i.e., does not oxidize), and source-channel interface material 850 is formed by controlled oxidation of the metal structure just below source contact 807. As shown, this results in source-channel interface material 850 only above source contact 807.

[0088] 7a-7n and method 600, in step 615, an n-type semiconductor layer 716 is formed. Figure 7c shows a cross-sectional view taken along line FF of Figure 7j after semiconductor layer 716 has been formed across TFT 700, including on top of source-channel interface member 750.

[0089] In step 620, a dielectric layer 714 is formed. As shown in Figure 7d, a cross-sectional view taken along line GG of Figure 7k, the dielectric layer 714 is formed over the entire device, including on top of the semiconductor layer 716. The dielectric layer 714 is preferably formed from a material having a high dielectric constant, although other materials such as SiO2 or Si3N4 can be used.

[0090] In step 625, a gate contact 703 is formed. The gate contact 703 is formed on the dielectric layer 714, as shown in Figure 7e, a cross-sectional view taken along line HH in Figure 7l. In some cases, an optional gate tuning layer 722 may be formed between the dielectric layer 714 and the gate contact 703. In this case, the gate tuning layer 722 is formed first, and then the gate contact 703 is formed on top of the gate tuning layer 722, as shown in Figure 7e.

[0091] In step 630, the dielectric layer 714 and the underlying unwanted portions of the semiconductor layer 716 and source-channel interface layer 750 are removed. Figure 7f, a cross-sectional view taken along line II of the TFT 700 in Figure 7m, shows that the gate contact 703 can be used as a mask to remove portions of the dielectric layer 714 and the underlying semiconductor layer 716 and source-channel interface layer 750.

[0092] In step 635, gate electrode 704, source electrode 708 and drain electrode 712 are formed, as shown in FIG. 7g, a cross-sectional view taken along line JJ of FIG. 7n.

[0093] In some circumstances, it may be desirable to fabricate TFTs according to embodiments of the present invention in a vertical configuration. Thus, Figures 9a, 9b and 9c show embodiments of TFTs formed vertically in this manner. As will be appreciated by those skilled in the art, vertically formed TFTs allow for increased "packing density" (i.e., an increased number of devices in a given horizontal area), which may be important for some applications, such as display screens or image sensors. Furthermore, because TFTs according to the present invention can be fabricated on a variety of substrates, TFTs according to the present invention can be "stacked" on top of one another, thereby increasing device density, which may be highly desirable for many different applications. For example, the present invention allows for the formation of layers of vertical TFTs and any associated interconnects or other components, and then a layer of insulating material, such as silicon dioxide, can be formed on top of these layers, which can then be used as a substrate and insulating layer for another set of TFTs formed on top of it. It is envisioned that by forming multiple layers of TFTs in this manner, circuit density can be significantly increased compared to the prior art.

[0094] 9a shows a TFT 900a including a gate 902, a source 906 and a drain 910. The gate 902 includes a gate contact 903 and a gate electrode 904, the source 906 includes a source contact 907 and a source electrode 908, and the drain 910 includes a drain contact 911 and a drain electrode 912. The TFT 900a also includes a dielectric layer 914 around the gate 902 of the TFT 900a, and further includes a first insulating layer 918 and a second insulating layer 925 formed above a substrate 920. The TFT 900a further includes an n-type semiconductor layer 916 and a source-channel interface member 950. If desired, the TFT 900a can also include a gate tuning layer 922 as shown.

[0095] In the TFT 900a, a source 906 including a source contact 907 and a source electrode 908 is at the bottom (with respect to the orientation of the figure) of the TFT 900a formed on top of a first insulating layer 918. A second insulating layer 925 is formed over the portion of the source contact 907 leaving the portion of the source contact 907 exposed in the center of the TFT 900a. A drain contact 911 and a drain electrode 912 formed thereon are formed on either side of the exposed portion of the source contact 907. The source contact 907 is insulated from the drain contact 911 by the second insulating layer 925.

[0096] In TFT 900a, a source-channel interface material 950 is formed on the exposed portions of the source contacts 907 described above, on the inner surface of the second insulating layer 925, and on the drain contacts 911. The gate contact 903 is surrounded by an (optional) gate tuning layer 922, which is itself surrounded by a dielectric layer 914. A semiconductor layer 916 is formed between the dielectric layer 914 and the source-channel interface material 950.

[0097] FIG. 9b shows another embodiment of the invention, a TFT 900b, similar to TFT 900a but with the extent and location of source-channel interface member 950 altered.

[0098] In particular, in TFT 900b, source-channel interface material 950 is formed as a layer over the entire top surface of source contact 907. As shown in Figure 9b, unlike the embodiment of Figure 9a, source-channel interface material 950 is not present on the inner surface of second insulating layer 925 and drain contact 911 of TFT 900b. Instead, semiconductor layer 916 is formed between dielectric layer 914, the inner surface of second insulating layer 925, and drain contact 911.

[0099] Figure 9c shows a cross-sectional view of a TFT 900c according to another embodiment of the invention. Like the TFT 990a of Figure 9a and the TFT 900b of Figure 9b, the TFT 900c is an implementation of a vertical TFT according to one embodiment of the invention.

[0100] However, TFT 900c differs from TFTs 900a and 900b described above in that its bottom contact is a drain contact 911. In contrast, the top contact of TFT 900c is a source contact 907. As shown in FIG. 9c, a source-channel interface material 950 is formed around the source contact 907. The source-channel interface material 950 is separated from the drain contact 911 by the presence of a second insulating layer 925 and from the dielectric layer 914 by a semiconducting layer 916.

[0101] Although the embodiments of Figures 9a, 9b and 9c show "symmetric" implementations of vertical TFTs according to aspects of the invention, those skilled in the art will readily appreciate that such symmetry is not required. For example, Figure 9d shows an asymmetric implementation of TFT 900d, in which the right side (with respect to the orientation of the figure) of TFT 900b has been omitted. Various other asymmetric and / or reduced area implementations of vertical TFTs according to aspects of the invention will now be apparent to those skilled in the art.

[0102] As will be apparent to those skilled in the art, TFT 900a, TFT 900b, TFT 900c, and TFT 900d function similarly to other embodiments of the invention disclosed herein. As mentioned above, TFT 900a, TFT 900b, TFT 900c, and TFT 900d can be formed as vertical cylinders, parallelepipeds, hexagonal prisms, etc., and these various possible shapes allow the "footprint" of TFT 900a, TFT 900b, TFT 900c, and TFT 900d to be selected to optimize the density with which TFT 900a, TFT 900b, TFT 900c, and TFT 900d can be formed in a device. This provides several advantages, especially in applications such as DRAM memories where increasing memory cell density is an important goal.

[0103] Additionally, as noted above, the TFTs 900a, 900b, and 900c can be "stacked" to increase circuit element density. In particular, an array of TFTs 900a, 900b, or 900c can be formed on a substrate and / or insulator that covers an underlying layer of circuit elements (including TFTs 900a, 900b, and 900c), which are then covered by a substrate and / or insulator with another array of TFTs 900a, 900b, and 900c formed on top of the substrate, thereby forming a true 3D integrated circuit.

[0104] Reference is now made to Figures 10a and 10b, which are a flow chart of a method 1000 for manufacturing a vertical TFT 1200, similar to the TFT 900a described above. The method 1000 of Figures 10a and 10b will now be described with reference to Figures 11a to 11v, which show the various steps involved in the method.

[0105] The method 1000 begins at step 1005, where a source electrode 908 and a source contact 907 are formed on a first insulating layer 918, which itself is then formed on a substrate 920, as shown in FIG. 11a. FIG. 11a is a cross-sectional view of FIG. 11l taken along line KK. The source contact 907 may be made of copper, tungsten, or any other material that would occur to one skilled in the art that can be used to fabricate a vertical transistor. In particular, the material of the source contact 907 is selected based on the work function and surface oxidation characteristics of the material to provide the desired effect of injection of electrons into the accumulation layer during operation of the TFT 1200, as will become apparent to one skilled in the art below. It is also contemplated that the source electrode 908 and the source contact 907 may be the same element, if desired.

[0106] In step 1010, a second insulating layer 925 is formed over the source contact 907, as shown in Figure 11b, which is a cross-sectional view taken along line LL in Figure 11m. As can be seen, the second insulating layer 925 is formed over the entire top surface of the source contact 907. The second insulating layer 925 may be formed using any suitable technique as would occur to one of ordinary skill in the art, including spin-coating a polymer, chemical vapor deposition of a dielectric, etc.

[0107] In step 1015, a drain contact 911 is formed as shown in Figure 11c, which is a cross-sectional view taken along line MM in Figure 11n. As shown, the drain contact 911 is formed over the entire top surface of the second insulating layer 925.

[0108] In step 1020, unwanted material of the drain contact 911 is removed. The unwanted material may be removed in any suitable manner as would occur to one of ordinary skill in the art, such as by patterning and etching. The result of step 1020 is shown in FIG. 11d, a cross-sectional view taken along line NN in FIG. 11o. It will be apparent to one of ordinary skill in the art that the unwanted material of the drain contact 911 may be removed as desired, which may allow the drain contact 911 to be formed in a geometric shape, such as a hexagon, allowing for increased packaging density of the TFT 1200.

[0109] In step 1025, the unwanted portions of the second insulating layer 925 are removed down to the source contact 907, as shown in Figure 11e, a cross-sectional view taken along line OO in Figure 11p. In some embodiments, the unwanted portions of the second insulating layer 925 are removed by an etching process selected to stop on the underlying source contact 907, although any other suitable method of removing the unwanted portions of the second insulating layer 925 as would occur to one of ordinary skill in the art may also be used.

[0110] In step 1030, a source-channel interface member 950 is formed over the result of step 1025. As shown in Figure 11f, a cross-sectional view taken along line PP in Figure 11q, the source-channel interface member 950 is now formed over the entire top surface of the TFT 1200, including over the drain contact 911 and over the exposed portions of the source contact 907. The source-channel interface member 950 can be formed in a variety of ways, and in one embodiment is deposited using atomic layer deposition techniques.

[0111] In step 1035, an n-type semiconductor layer 916 is formed over the source-channel interface member 950, as shown in Figure 11g, which is a cross-sectional view taken along line QQ of Figure 11r. The semiconductor layer 916 can be formed in a variety of ways, and in one embodiment is deposited using atomic layer deposition techniques.

[0112] In step 1040, a dielectric layer 914 is formed, as shown in Figure 11h, which is a cross-sectional view taken along line RR in Figure 11s. The dielectric layer 914 is formed on the semiconductor layer 916. The choice of material for the dielectric layer 914 is not particularly limited, and the dielectric layer 914 may be any suitable material having a high dielectric constant as would occur to one skilled in the art.

[0113] In step 1045, an (optional) gate tuning layer 922 can be formed over the dielectric layer 914, and a gate contact 903 is formed over the gate tuning layer 922. The gate tuning layer 922 and the gate contact 903 can be formed in a variety of ways, including atomic layer deposition techniques, as will be appreciated by those skilled in the art. If the gate tuning layer 922 is not provided, the gate contact 903 is formed directly on the dielectric layer 914. The result of step 1045 is shown in Figure 11i, which is a cross-sectional view taken along line SS of Figure 11t.

[0114] In step 1050, unwanted material is removed from the various layers formed to expose underlying layers or features, as shown in FIG. 11j, which is a cross-sectional view taken along line TT in FIG. 11u. As shown, the drain contact 911, the source-channel interface member 950, the semiconductor layer 916, the dielectric layer 914, the gate tuning layer 922, and the gate contact 903 are appropriately exposed. The method of removing unwanted material from the various layers is not particularly limited and can be accomplished in a variety of ways, including mechanical polishing, wet chemical etching, dry chemical etching, atomic layer etching, etc., as will be apparent to one skilled in the art.

[0115] In step 1055, the drain electrode 912 and the gate electrode 904 are formed. In the embodiment shown in FIG. 11k, which is a cross-sectional view taken along line UU in FIG. 11v, the drain electrode 912 and the gate electrode 904 can be deposited and patterned using a masking approach. However, the method used to form the drain electrode 912 and the gate electrode 904 is not particularly limited, and various suitable methods will be apparent to one of ordinary skill in the art.

[0116] 12a and 12b show a flow chart of a method 1100 of the present invention for manufacturing or fabricating another embodiment of a TFT 1300 similar to TFT 900b described above. Method 1100 will now be described with reference to Figures 13a-13v.

[0117] Method 1100 begins with a substrate 920 on which an insulating layer 918 is formed. In step 1105, a source electrode 908 and a source contact 907 are formed on the insulating layer 918, as shown in FIG. 13a, which is a cross-sectional view taken along line BL-BL in FIG. 13l. As will be apparent to one skilled in the art, the source electrode 908 and the source contact 907 may be the same part if they are formed from the same material. Step 1105 is similar to step 1005 in FIG. 10, and FIGS. 13a and 13l are similar to FIGS. 11a and 11l, respectively.

[0118] In step 1110, a p-type semiconductor material 950 is formed on the source contact 907. As shown in FIG. 13b, which is a cross-sectional view taken along line BM-BM of FIG. 13m, the source-channel interface material 950 is formed as a layer over the entire top surface of the source contact 907. The source-channel interface material 950 can be formed in a variety of ways, and in some embodiments is deposited using atomic layer deposition techniques, although the method of forming the source-channel interface material 950 is not particularly limited, and may be formed, for example, by catalyzing the metal surface of the source contact 907 to form a suitable metal oxide, or by other suitable methods as would be apparent to one of ordinary skill in the art.

[0119] In step 1115, a second insulating layer 925 is formed on the source-channel interface member 950, as shown in Figure 13c, which is a cross-sectional view taken along line BN-BN of Figure 13n. In some embodiments, the second insulating layer 925 is deposited using spin-coating of a polymer, although the method of forming the second insulating layer 925 is not particularly limited and the second insulating layer 925 can be deposited using, for example, chemical vapor deposition ("CVD") of a dielectric, or any other suitable method as would be apparent to one of ordinary skill in the art.

[0120] In step 1120, a drain contact 911 is formed. As shown in Fig. 13d, a cross-sectional view taken along line BO-BO in Fig. 13o, the drain contact 911 is formed on the entire upper surface of the second insulating layer 925. Again, the method of forming the drain contact 911 is not particularly limited, and a suitable method will be apparent to one skilled in the art.

[0121] In step 1125, the unwanted material is removed from the drain contact 911, as shown in Figure 13e, which is a cross-sectional view taken along line BP-BP in Figure 13p. The method of removing the unwanted material from the drain contact 911 is not particularly limited. Furthermore, if desired, the unwanted material can be removed, such as by etching, so that the drain contact 911 can be formed in a predetermined pattern, such as the illustrated hexagonal pattern or stripe pattern (not shown), to increase the packing density of the resulting TFT.

[0122] In step 1130, unwanted material is removed from the second insulating layer 925, as shown in Figure 13f, which is a cross-sectional view taken along line BQ-BQ of Figure 13q. As shown, the second insulating layer 925 has been removed down to the source-channel interface member 950.

[0123] Steps 1135-1155 of method 1100 are similar to steps 1035-1055 of method 1000 described above. In step 1135, shown in Figure 13g, which is a cross-sectional view taken along line BR-BR of Figure 13r, an n-type semiconductor layer 916 is formed above source-channel interface member 950. N-type semiconductor layer 205 can be formed in a variety of ways, including atomic layer deposition techniques, as will be appreciated by those skilled in the art.

[0124] In step 1140, a dielectric layer 914 is formed over the semiconductor layer 916. This is shown in Figure 13h, a cross-sectional view taken along line BS-BS of Figure 13s. Again, the dielectric layer 914 can be formed in a variety of suitable manners as will be apparent to those skilled in the art.

[0125] In step 1145, a gate contact 903 is formed above the dielectric layer 914, as shown in Figure 13i, which is a cross-sectional view taken along line BT-BT of Figure 13t. As shown, if desired, an optional gate tuning layer 922 can be formed on the dielectric layer 914 before the gate contact 903 is formed. The gate tuning layer 922 and the gate contact 903 can be formed by any suitable process as would occur to one skilled in the art, for example, by atomic layer deposition techniques.

[0126] In step 1150, the TFT 1300 is processed to remove unwanted material and expose underlying layers and features, as shown in Figure 13j, a cross-sectional view taken along line BU-BU of Figure 13u. The material removed to expose the layers and features of Figure 13j can be removed in any suitable manner, for example, by mechanical polishing of the TFT 1300. In the illustrated embodiment, the underlying layers are exposed and a hexagonal pattern is formed.

[0127] In step 1155, drain electrode 912 and gate electrode 904 are formed. If desired, drain electrode 912 and gate electrode 904 can be patterned in a hexagonal pattern, stripe pattern, or other pattern by a masking process, as shown in Figure 13k, a cross-sectional view taken along line BV-BV of Figure 13v.

[0128] As should be apparent by now, the present invention includes various embodiments of novel semiconductor devices. In particular, the present invention discloses TFTs that have improved performance even when fabricated with channel dimensions less than 200 nm.

[0129] Another contemplated advantage of semiconductor devices according to embodiments of the present invention is that they can be fabricated in back-end ("BEOL") processing.

[0130] As known to those skilled in the art, semiconductor fabrication processes are often distinguished between front-end ("FEOL") and back-end processes. Traditionally, the transistors, capacitors, resistors, and inductors of an integrated circuit are first formed on a wafer by FEOL processes. Once these devices are fabricated on a wafer, they are then processed by BEOL processes, in which metallization layers and bonding sites are formed.

[0131] Traditionally, once FEOL processing has been completed on a wafer (or other substrate), it has generally not been possible to add additional devices to the wafer during BEOL processing because exposure of the wafer to the temperatures required to fabricate conventional semiconductor devices would destroy the semiconductor structures and devices already formed on the wafer by the FEOL processes.

[0132] Recently, there have been attempts to fabricate TFTs as BEOL processes using indium gallium zinc oxide ("IGZO") as the semiconductor or channel material. While some success has been achieved with such devices, they tend not to perform as well as desired, generally having low threshold voltages, high leakage levels or poor "off" characteristics. Furthermore, the processes used to fabricate IGZO devices have proven difficult to control, and the resulting devices are fragile and can be difficult to survive other BEOL processes such as annealing.

[0133] In contrast, TFTs according to embodiments of the present invention can be fabricated by techniques and processes that are known to not damage previously fabricated FEOL devices or structures, to work well at semiconductor or channel lengths of less than 200 nm, and to not be damaged by other BEOL processes.

[0134] As detailed above, TFTs according to embodiments of the present invention employ six basic fabrication processes, namely source formation, drain formation, gate formation, semiconductor formation, dielectric or insulator formation, and source-channel interface member formation, each of which can typically be accomplished in multiple possible ways. Selection of one or more appropriate alternatives to each of the fabrication processes for use in the fabrication of BEOL TFTs or TFTs fabricated by FEOL or alternative processes is within the ordinary skill of one of ordinary skill in the art.

[0135] As an example, in determining how to fabricate a TFT according to the present invention, if it is desired not to exceed a temperature of 300° C. during the fabrication process, the source, drain and gate formations are accomplished by sputtering and patterning, the semiconductor layer formation is accomplished by atomic layer deposition, the dielectric or insulator formation is accomplished by atomic layer deposition, and the source-channel interface members are accomplished by oxidation of the source contact (if the material is an oxidizable metal) or by sputtering a degenerately doped monoatomic semiconductor layer, e.g., sputtering of germanium or silicon. As will be apparent, each of these selected fabrication techniques can be performed at temperatures below 300° C., so that there is no impact on previously fabricated devices and structures in the FEOL process.

[0136] Furthermore, as will be apparent by now, the present invention provides novel thin film semiconductor switching devices that have good performance even when fabricated with semiconductor or channel lengths less than 1000 nm, and particularly less than 200 nm. Fabrication techniques and methods for the novel devices are also taught, which may allow the novel devices to be fabricated as BEOL devices.

[0137] The above-described embodiments of the invention are intended to be examples of the invention, and changes and modifications may be made by those of ordinary skill in the art without departing from the scope of the invention, which is defined solely by the appended claims.

Claims

1. A thin film transistor, comprising a source disposed on a substrate or an insulating layer and including a source contact, a drain disposed on the substrate or the insulating layer and spaced apart from the source, an n-type semiconductor layer extending between the source and the drain so that a carrier channel is formed therebetween and including tin oxide, and a source-channel interface member located between the source contact and the n-type semiconductor layer and in contact with the source contact and the n-type semiconductor layer, wherein the source-channel interface member is operable to deplete the carrier channel in a region of the n-type semiconductor layer adjacent to the source contact to reduce leakage current when the thin film transistor is in an off state.

2. The thin film transistor according to claim 1, wherein the source-channel interface member includes a p-type semiconductor.

3. The thin film transistor according to claim 1, wherein the source-channel interface member includes a p-type metal oxide.

4. The thin film transistor according to claim 1, wherein the source-channel interface member includes an oxidation material of the source contact.

5. The thin film transistor according to claim 1, wherein the source-channel interface member includes a layer of material deposited on the source contact.

6. The thin film transistor according to claim 1, wherein the source contact includes ruthenium.

7. The thin film transistor according to claim 6, wherein the source-channel interface member layer includes ruthenium oxide.

8. The thin film transistor according to claim 1, wherein the source contact includes cobalt.

9. The thin film transistor according to claim 8, wherein the source-channel interface member layer includes cobalt oxide.

10. The thin film transistor according to claim 1, wherein the n-type semiconductor layer is formed by atomic layer deposition.

11. Further comprising a gate dielectric layer above the n-type semiconductor layer, and a gate contact above the gate dielectric layer.

12. The thin film transistor according to claim 11, wherein the gate dielectric layer includes hafnium oxide.

13. The drain includes a drain contact, The thin film transistor according to claim 1, wherein the source-channel interface member extends between the drain contact and the n-type semiconductor layer and is in contact with the drain contact.

14. The drain includes a drain contact, The thin film transistor according to claim 1, further comprising another channel interface member that is located between the drain contact and the n-type semiconductor layer and is in contact with the drain contact and the n-type semiconductor layer.

15. A method of manufacturing a thin film transistor, Forming a source and a drain on a substrate or an insulating layer, wherein the drain is separated from the source and the source includes a source contact; Forming a source-channel interface member that contacts the source contact at the source; Forming an n-type semiconductor layer that contains tin oxide and contacts the source-channel interface member between the source and the drain, The method, wherein the source-channel interface member is operable to deplete a carrier channel in a region of the n-type semiconductor layer adjacent to the source contact in order to reduce a leakage current when the thin film transistor is in an off state.

16. The method according to claim 15, wherein the source-channel interface member includes a p-type semiconductor.

17. The method according to claim 15, wherein the source-channel interface member includes a p-type metal oxide.

18. The method according to claim 15, wherein the step of forming the source-channel interface member includes oxidizing a material of the source contact.

19. The method according to claim 15, wherein the step of forming the source-channel interface member includes forming a layer of material on the source contact.

20. The method according to claim 15, further comprising using atomic layer deposition to form the source-channel interface member on the source contact.

21. The source contact includes ruthenium, The method according to claim 15, wherein the source-channel interface member layer includes ruthenium oxide.

22. The source contact includes cobalt, The method according to claim 15, wherein the source-channel interface member layer includes cobalt oxide.

23. The method according to claim 15, wherein the step of forming the n-type semiconductor layer includes forming the n-type semiconductor layer using atomic layer deposition.

24. The method according to claim 15, further comprising the step of forming a gate dielectric layer over the n-type semiconductor layer, and the step of forming a gate contact over the gate dielectric layer.

25. The method according to claim 24, wherein the gate dielectric layer includes hafnium oxide.

26. The method according to claim 15, further comprising the step of forming a source-channel interface member that contacts the drain contact at the drain.

27. The method according to claim 15, further comprising the step of forming another channel interface member that contacts the drain contact at the drain, and the n-type semiconductor layer is formed in contact with the another channel interface member.

28. A method of manufacturing a thin film transistor, comprising: using a wafer including a source and a drain located on a substrate or an insulating layer, and a source-channel interface member formed in contact with a source contact of the source, to deposit tin oxide using atomic layer deposition to form an n-type semiconductor layer that contacts the source-channel interface member between the source and the drain, wherein the source-channel interface member is operable to deplete a carrier channel in a region of the n-type semiconductor layer adjacent to the source to reduce leakage current when the thin film transistor is in an off state.

29. The method according to claim 28, further comprising using atomic layer deposition to form the source-channel interface member.

30. The method according to claim 28, further comprising using atomic layer deposition to deposit a gate dielectric layer over the n-type semiconductor layer.

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