Sense lines for high speed application packages

Abstract

In one aspect, a semiconductor device includes a substrate. The substrate includes a column having a conductive paste (122, 222) penetrating a plurality of metal layers, a resin sheath (124, 224) surrounding the column, a ground shield (126, 226) surrounding the resin sheath (124, 224), and a plurality of sense lines (120, 220). The plurality of sense lines (120, 220) includes a first sense line (120(1), 220(1)) connected to the column having the conductive paste (122, 222) and a second sense line (120(2), 220(2)) connected to the ground shield (126, 226). The resin includes a dielectric material.

Description

[Background technology]

[0001] 1. Field of disclosure Aspects of the present disclosure relate generally to integrated circuits (ICs), and more particularly to sense lines in semiconductors.

[0002] 2. Description of Related Technology In semiconductors (also called chips or integrated circuits (ICs)), internal connections known as sense lines may be used for sensing (e.g., testing). For example, the sense lines may connect to a Power Distribution Network (PDN), a Power Management IC (PMIC), etc. Typically, 3-4 vias, each with a size of about 100 micrometers (μm), may be used, and 10-15 jumpers with a size of about 200 μm×200 μm may be used. Thus, the area occupied by the sense lines (including the jumpers) may be about 400 μm×400 μm. Summary of the Invention

[0003]

[0003] The following provides a simplified summary of one or more aspects disclosed herein. Therefore, the following summary should not be considered as an extensive overview of all contemplated aspects, nor should the following summary be considered as identifying key or important elements of all contemplated aspects or defining the scope related to any particular aspect. Thus, the sole purpose of the following summary is to present certain concepts of one or more aspects of the mechanisms disclosed herein in a simplified form prior to the detailed description set forth below.

[0004]

[0004] In a first aspect, a semiconductor includes a substrate. The substrate includes a column including a conductive paste penetrating a plurality of metal layers, a resin sheath surrounding the column, a ground shield surrounding the resin sheath, and a plurality of sense lines. The plurality of sense lines includes a first sense line connected to the column including the conductive paste and a second sense line connected to the ground shield. The resin sheath includes a dielectric material.

[0005] In a second aspect, a method for fabricating a semiconductor device includes stacking substrates. The stacking of substrates includes forming a column including a conductive paste penetrating a plurality of metal layers, forming a resin sheath surrounding the column, forming a ground shield surrounding the resin sheath, and forming a plurality of sense lines including a first sense line and a second sense line. The first sense line is connected to the column and the second sense line is connected to the ground shield. The resin sheath includes a dielectric material.

[0006]

[0006] Other objects and advantages associated with the embodiments disclosed herein will become apparent to those skilled in the art based on the accompanying drawings and detailed description. [Brief description of the drawings]

[0007]

[0007] The accompanying drawings are presented to facilitate the description of various aspects of the present disclosure and are provided merely to illustrate the aspects, not to limit them. A more complete understanding of the present disclosure may be obtained by referring to the following detailed description in conjunction with the accompanying drawings. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same reference number in different figures indicates similar or identical items. [Figure 1]

[0008] FIG. 1 illustrates a block diagram of an exemplary package having a cored substrate according to various aspects of the present disclosure. [Diagram 2]

[0009] FIG. 1 illustrates a block diagram of an exemplary package having a coreless substrate according to various aspects of the present disclosure. [Figure 3A]

[0010] 1 illustrates different stages in the fabrication process of an exemplary package having a cored substrate according to various aspects of the present disclosure. [Figure 3B] 1 illustrates different stages in the fabrication process of an exemplary package having a cored substrate according to various aspects of the present disclosure. [Figure 3C] 1 illustrates different stages in the fabrication process of an exemplary package having a cored substrate according to various aspects of the present disclosure. [Figure 3D] 1 illustrates different stages in the fabrication process of an exemplary package having a cored substrate according to various aspects of the present disclosure. [Figure 3E] 1 illustrates different stages in the fabrication process of an exemplary package having a cored substrate according to various aspects of the present disclosure. [Figure 3F] 1 illustrates different stages in the fabrication process of an exemplary package having a cored substrate according to various aspects of the present disclosure. [Figure 3G] 1 illustrates different stages in the fabrication process of an exemplary package having a cored substrate according to various aspects of the present disclosure. [Figure 3H] 1 illustrates different stages in the fabrication process of an exemplary package having a cored substrate according to various aspects of the present disclosure. [Figure 4A]

[0011] 1 illustrates different stages in the fabrication process of an exemplary package having a cored substrate according to various aspects of the present disclosure. [Figure 4B] 1 illustrates different stages in the fabrication process of an exemplary package having a cored substrate according to various aspects of the present disclosure. [Figure 4C] 1 illustrates different stages in the fabrication process of an exemplary package having a cored substrate according to various aspects of the present disclosure. [Figure 4D] 1 illustrates different stages in the fabrication process of an exemplary package having a cored substrate according to various aspects of the present disclosure. [Figure 4E] 1 illustrates different stages in the fabrication process of an exemplary package having a cored substrate according to various aspects of the present disclosure. [Figure 4F] 1 illustrates different stages in the fabrication process of an exemplary package having a cored substrate according to various aspects of the present disclosure. [Figure 4G] 1 illustrates different stages in the fabrication process of an exemplary package having a cored substrate according to various aspects of the present disclosure. [Figure 4H] 1 illustrates different stages in the fabrication process of an exemplary package having a cored substrate according to various aspects of the present disclosure. [Diagram 5]

[0012] 1 illustrates an exemplary process including forming a column including a conductive paste according to an aspect of the present disclosure. [Figure 6]

[0013] 1 illustrates an exemplary process including depositing a conductive paste into a hole in a portion of a substrate, according to an aspect of the present disclosure. [Figure 7]

[0014] 1 illustrates an example mobile device in accordance with one or more aspects of the present disclosure. [Figure 8]

[0015] 1 illustrates various electronic devices that may be integrated with an integrated or semiconductor device according to one or more aspects of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008]

[0016] Systems and techniques are disclosed for reducing the amount of space used by sense lines within a semiconductor package ("package"). Conductive paste may be used to create cylindrical sense lines (e.g., for power rails) with an outer shield around the sense line that acts as a ground. Compared to a conventional sense line structure that occupies 400 μm×400 μm, the sense line structure described herein occupies a space of approximately 250 μm×250 μm, resulting in approximately 50% savings in space within the package.

[0009]

[0017] Aspects of the present disclosure are provided in the following description and associated drawings, which are directed to various examples provided for illustrative purposes. Alternative aspects may be devised without departing from the scope of the present disclosure. Additionally, well-known elements of the present disclosure will not be described in detail or will be omitted so as not to obscure the relevant details of the present disclosure.

[0010]

[0018] The words "exemplary" and / or "example" are used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as an "exemplary" and / or "example" is not necessarily to be construed as preferred or advantageous over other aspects. Similarly, the term "aspects of the present disclosure" does not specify that all aspects of the present disclosure include the described feature, advantage or mode of operation.

[0011]

[0019] Those skilled in the art will appreciate that the information and signals described below may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the following description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof, depending in part on the particular application, desired design, corresponding technology, etc.

[0012]

[0020] Further, many aspects are described in terms of sequences of actions performed by, for example, elements of a computing device. It will be appreciated that various actions described herein can be performed by specific circuitry (e.g., an Application Specific Integrated Circuit (ASIC)), by program instructions executed by one or more processors, or by a combination of both. In addition, the sequence(s) of actions described herein can be considered to be fully embodied in any form of non-transitory computer-readable storage medium having stored thereon a corresponding set of computer instructions that, when executed, cause or instruct an associated processor of a device to perform the functions described herein. Thus, various aspects of the present disclosure can be embodied in several different forms, all of which are contemplated to fall within the scope of the claimed subject matter. In addition, for each of the aspects described herein, the corresponding form of any such aspect may be described herein, for example, as "logic configured to" perform the described actions.

[0013]

[0021] FIG. 1 illustrates a block diagram of an exemplary package 100 having a cored substrate 102 according to various aspects of the present disclosure. The cored substrate 102 includes a core 104. An active device 106, such as a Power Management Integrated Circuit (PMIC), is electrically coupled to a top portion of the cored substrate 102 using interconnects 108, such as pins, balls, bumps, etc. A die 110, such as an Application Processor (AP) die, is electrically coupled to a bottom portion of the cored substrate 102 using interconnects 112, such as pins, balls, bumps, etc. The bottom surface of the cored substrate 102 may include interconnects 114, such as balls, pins, etc., that allow the package 100 to be attached to a printed circuit board (PCB), etc. It will be appreciated that one or more additional dies 116 may be attached to the substrate 102 using interconnects 118, such as pins, balls, bumps, etc. It will be further appreciated that the location of the die 116 may be on either side of the cored substrate 102. Thus, the various aspects disclosed herein should not be construed as limited by the exemplary configurations shown in the drawings.

[0014]

[0022] The substrate 102 includes one or more sense lines 120. For example, the sense line 120(1) may be connected to a column of conductive paste 122. While other materials such as copper, silver, etc. may be used, the conductive paste 122 provides a lower cost option for achieving electrical connection. The conductive paste 122 may be insulated by being surrounded by a resin sheath 124. A ground shield 126 surrounds the resin sheath 124 and, in some embodiments, may be coupled to a ground attached to the sense line 120(2). For illustrative purposes, the sense line 120 is shown as being coupled to a ground. However, it should be understood that the sense lines 120 described herein may be used in other ways, such as to carry power, to carry signals, etc. Thus, the sense lines 120(1), 120(2) work together, with the sense line 120(1) carrying the signal (or power) to the conductive paste 122 and the sense line 120(2) connecting to the ground shield 126. For example, the sense lines 120(1), 120(2) may be used as low current sense lines to monitor the voltage on a power rail within a portion of the substrate 102.

[0015]

[0023] The entire structure, including the conductive paste 122, the resin sheath 124, and the ground shield 126, may have a width of approximately 250 micrometers (μm). Various example dimensions are provided herein to facilitate description of the various disclosed aspects. It will be understood that the various disclosed aspects are not limited to these example dimensions.

[0016]

[0024] The ground shield 126 may be used as part of the ground sense return line (e.g., 120(2)) on one or more of the layers in the substrate 102. The ground shield 126 may be formed of copper, silver, solder, or any other suitable highly conductive material. It will be appreciated that in some aspects the ground shield 126 may function as a ground shield surrounding the sense line that passes through the conductive paste 122. The conductive paste 122 may be applied to the substrate using inkjet printing (or another means of extruding the conductive paste) and cured. The conductive paste 122 may include copper, silver, solder, or any other suitable highly conductive material.

[0017]

[0025] Technical advantages of the sense lines described herein include occupying less space, e.g., about 250 μm×250 μm, compared to conventional sense lines that occupy about 400×400 μm. By occupying less space within package 100, package 100 can be made smaller or additional functionality can be added to package 100. For example, the space savings can be used to increase the area available for routing on package 100, reduce the size of the substrate, improve the layout of package 100, improve power distribution network (PDN) connectivity, etc.

[0018]

[0026] FIG. 2 illustrates a block diagram of an exemplary package 200 having a coreless substrate 202 according to various aspects of the disclosure. An active device 206 (e.g., a PMIC) is electrically coupled to a top portion of the coreless substrate 202 using interconnects 208, such as pins, balls, bumps, etc. A die 210 (e.g., an AP die) is electrically coupled to a bottom portion of the substrate 102 using interconnects 212, such as pins, balls, bumps, etc. The bottom surface of the coreless substrate 202 may include interconnects 214, such as balls, pins, etc., that allow the package 200 to be attached to a printed circuit board (PCB), etc. Similar to the above example, a die 216 (or multiple dies) may be attached to the coreless substrate 202 using interconnects 218, such as pins, balls, bumps, etc.

[0019]

[0027] The coreless substrate 202 includes one or more sense lines 220. For example, the sense line 220(1) may be connected to a column of conductive paste 222. The conductive paste 222 may be insulated by being surrounded by a resin sheath 224. A conductive ground shield 226 surrounding the resin sheath 224 may be used as a ground to which the sense line 220(2) is attached. Thus, the sense lines 220(1), 220(2) work together, with the sense line 220(1) carrying signals (or power) to the conductive paste 222 and the sense line 220(2) connecting to the ground shield 226. For example, the sense lines 220(1), 220(2) may be used as low current sense lines for a power rail. It should be understood that the sense lines 220 described herein may be used in many different ways, such as to connect to a ground, to carry power, to carry a signal, etc.

[0020]

[0028] The ground shield 226 may be used as a ground sense return wire on one or more of the layers in the coreless substrate 202. The entire structure, including the conductive paste 222, the resin sheath 224, and the ground shield 226, may have a width of approximately 250 micrometers (μm). The conductive paste 222 may be applied to the substrate using inkjet printing (or another means of extruding the conductive paste) and cured.

[0021]

[0029] Technical advantages of the sense lines described herein include occupying less space, e.g., about 250 μm×250 μm, compared to conventional sense lines that occupy about 400 μm×400 μm. By occupying less space within package 200, package 200 can be made smaller or additional functionality can be added to package 200. For example, the space savings can be used to increase the area available for routing on package 200, reduce the size of the substrate, improve the layout of package 200, improve power distribution network (PDN) connectivity, etc.

[0022]

[0030] 3A, 3B, 3C, 3D, 3E, 3F, 3G, and 3H show different stages in an exemplary fabrication of a package 300 including a cored substrate 102, similar to the package 100 of FIG. 1. An exemplary fabrication method is shown to illustrate various aspects of the present disclosure. Other fabrication methods are possible, and the described fabrication process is shown merely to facilitate understanding of the concepts disclosed herein and is not intended to limit the scope of the present disclosure or the appended claims. Furthermore, many details in the fabrication process known to those skilled in the art may be omitted or combined in a summary process section to facilitate understanding of the various aspects disclosed without detailed description of each detail and / or all possible process variations.

[0023]

[0031] FIG. 3A illustrates a portion of a fabrication process for a package 300 having a cored substrate, similar to the package 100 of FIG. 1, according to various embodiments of the present disclosure. The package 300 is formed, in some embodiments, using a process of stacking the substrate 102 on the core 104. Multiple pads, such as representative pads 302(1), 302(2), 302(3), 302(4), may be used for via pads on multiple layers (e.g., metal 1, metal 2, metal 3, metal 4, etc.). The diameter of the pad 302 may be about 250 μm. For ease of understanding, other routing structures are not shown in FIG. 3A. Multiple layers are stacked based on the start and end points of the sense lines. The sense lines may be added approximately symmetrically around the core 104. Additional layers may be added after forming the sense lines.

[0024]

[0032] FIG. 3B illustrates further portions of the fabrication process of the package 300 according to various aspects of the disclosure. As shown in FIG. 3B, a drill (e.g., a mechanical drill, a laser, or another type of drilling device) may be used to create holes 304 to form the outer ring of the sense lines (e.g., pads 302 in FIG. 3A). The diameter of the holes 304 may be about 150-200 μm. Plating of the holes (PTH) may be performed to form the ground shield 126. In some aspects, the sheath may be formed from copper (Cu) plating with a thickness of about 10 μm. For example, a 150-350 μm via with 10 μm Cu plating may be used for the connection to the ground shield 126. The sheath may be placed on the plated Cu to avoid shorting with 124 and 126.

[0025]

[0033] 3C illustrates a further portion of the fabrication process of the package 300 according to various aspects of the present disclosure. The hole 304 is filled with a resin sheath 124 (e.g., a dielectric material). Because the sense signal traveling through the sense line 120 of FIG. 1 and FIG. 2 is not a high-speed signal, the dielectric constant (Dk) of the resin sheath 124 does not need to be considered when selecting the resin sheath 124. Therefore, a relatively inexpensive resin sheath 124 can be used (e.g., to reduce costs).

[0026]

[0034] 3D illustrates a further portion of the fabrication process of the package 300 according to various embodiments of the present disclosure. A drill (e.g., a mechanical drill, a laser, or another type of hole making device) can be used to create a hole 306 having a diameter of about 100 μm.

[0027]

[0035] 3E illustrates a further portion of the fabrication process of the package 300 according to various aspects of the present disclosure. The holes 306 of FIG. 3D are filled with conductive paste 122 and cured. For example, an inkjet printer or another type of means may be used to apply the conductive paste 122 to the holes 306. A flash lamp or another type of curing means may be used to cure (e.g., harden) the conductive paste 122.

[0028]

[0036] 3F illustrates a further portion of the fabrication process of the package 300 according to various aspects of the present disclosure. The substrate 102 is further stacked by adding a dielectric layer 308. Vias, such as representative via 310, are created using a laser, etching, or the like.

[0029]

[0037] 3G illustrates a further portion of the fabrication process of the package 300 according to various aspects of the present disclosure. Metal layers, such as layers 312(1), 312(2), may be stacked and additional steps in the manufacturing process of the substrate 102 may be performed.

[0030]

[0038] 3H illustrates a further portion of the fabrication process of a package 300 according to various aspects of the present disclosure. FIG. 3H illustrates a view of the completed package 300, including the ground shield 126, the resin sheath 124, and the conductive paste 122, similar to the package 100.

[0031]

[0039] 4A, 4B, 4C, 4D, 4E, 4F, 4G, and 4H show different stages in an exemplary fabrication of a package 400 including a coreless substrate 202, similar to the package 400 of FIG. 4. An exemplary fabrication method is shown to illustrate various aspects of the present disclosure. Other manufacturing methods are possible, and the described fabrication process is shown merely to facilitate understanding of the concepts disclosed herein, and is not intended to limit the scope of the present disclosure or the appended claims. Furthermore, many details in the fabrication process known to those skilled in the art may be omitted or combined in a summary process section to facilitate understanding of the various aspects disclosed without detailed description of each detail and / or all possible process variations.

[0032]

[0040] FIG. 4A illustrates a portion of a fabrication process for a package 400 having a cored substrate, similar to the package 200 of FIG. 2, according to various embodiments of the present disclosure. The package 400 is formed, in some embodiments, using a carrier substrate 402 and a coreless substrate 202. The coreless substrate 202 may be an embedded trace substrate (ETS) in some embodiments. Multiple pads, such as representative pads 302(1), 302(2), 302(3), 302(4), may be used for via pads on multiple layers (e.g., metal 1, metal 2, metal 3, metal 4, etc.). The diameter of the pad 302 may be about 250 μm. For ease of understanding, other routing structures are not shown in FIG. 4A. Multiple layers are stacked based on the start and end points of the sense lines. The sense lines may be added approximately symmetrically around the coreless substrate 202. Additional layers may be added after forming the sense lines.

[0033]

[0041] FIG. 4B illustrates further portions of the fabrication process of the package 400 according to various aspects of the disclosure. As shown in FIG. 4B, a drill (e.g., a mechanical drill, a laser, or another type of drilling device) may be used to create holes 304 to form the outer ring of the sense lines (e.g., pads 302 in FIG. 4A). The diameter of the holes 304 may be about 150-200 μm. Plating of the holes (PTH) may be performed to form the ground shield 226. In some aspects, the ground shield 226 may be formed from a copper (Cu) plating of about 10 μm thickness. For example, a 150-350 μm via with 10 μm Cu plating may be used to connect to the ground shield 126. A sheath may be placed on the plated Cu to avoid shorting with 124 and 126.

[0034]

[0042] 4C illustrates a further part of the fabrication process of the package 400 according to various aspects of the present disclosure. The hole 304 in FIG. 4B is filled with a resin sheath 224 (e.g., a dielectric material). Since the sense signal propagating through the sense line 220 is not a high-speed signal, the dielectric constant (Dk) of the resin sheath 224 does not need to be considered when selecting the resin sheath 224. Therefore, a relatively inexpensive resin sheath 224 can be used to reduce costs.

[0035]

[0043] 4D illustrates a further portion of the fabrication process of package 400 according to various embodiments of the present disclosure. A drill (e.g., a mechanical drill, a laser, or another type of hole making device) can be used to create hole 306. In some embodiments, hole 306 can have a diameter of about 100 μm.

[0036]

[0044] 4E illustrates a further portion of the fabrication process of the package 400 according to various aspects of the present disclosure. The holes 306 of FIG. 4D are filled with conductive paste 222 and cured. For example, an inkjet printer or another type of means may be used to apply the conductive paste 222 to the holes 306. A flash lamp or another type of curing means may be used to cure (e.g., harden) the conductive paste 222.

[0037]

[0045] 4F illustrates a further portion of the fabrication process of the package 400 according to various aspects of the present disclosure. The coreless substrate 202 is further stacked by adding a dielectric layer 308. Vias, such as representative via 310, are created using a laser, etching, or the like.

[0038]

[0046] 4G illustrates a further portion of the fabrication process of the package 400 according to various aspects of the present disclosure. Metal layers, such as the representative metal layer 312, may be stacked to perform additional steps in the manufacturing process of the coreless substrate 202 (e.g., ETS).

[0039]

[0047] 4H illustrates a further portion of the fabrication process of the package 400 according to various aspects of the present disclosure. As shown in FIG. 4H, the carrier substrate 402 may be removed to form the completed package 400.

[0040]

[0048] In the flow diagrams of Figures 5 and 6, each block represents one or more operations that can be implemented in hardware, software, or a combination thereof. In the context of software, the blocks represent computer-executable instructions that, when executed by one or more processors, cause the processors to perform the described operations. Generally, computer-executable instructions include routines, programs, objects, modules, components, data structures, etc. that perform particular functions or implement particular abstract data types. The order in which the blocks are described is not intended to be construed as limiting, and any number of the described operations can be combined in any order and / or in parallel to perform a process. For illustrative purposes, processes 500 and 600 are described with reference to Figures 1, 2, 3A-3H, and 4A-4H as described above, although other models, frameworks, systems, and environments can be used to implement these processes.

[0041]

[0049] 5 illustrates an exemplary process including forming a column including a conductive paste according to an embodiment of the present disclosure. Process 500 can be performed as part of a semiconductor manufacturing process.

[0042]

[0050] At 502, the process 500 stacks substrates. For example, Figures 3A-3H show a stack of cored substrates, and Figures 4A-4H show a stack of coreless substrates.

[0043]

[0051] At 504, the process 500 forms a column including a conductive paste through the multiple metal layers. For example, in Figures 3E and 4E, conductive paste 122 is deposited and cured in hole 306.

[0044]

[0052] At 506, the process 500 forms a resin sheath surrounding the column. The resin sheet includes a dielectric material. For example, in Figures 3C and 4C, the resin sheath 124 is deposited in the hole 304, and in Figures 3D and 4D, a hole 306 is made in the resin to form the resin sheath 124.

[0045]

[0053] At 508, the process 500 forms a ground shield that surrounds the resin sheath. For example, in Figures 3A and 3B, pads 302 may be added, with each pad 302 on a corresponding metal layer. To create the ground shield 126, holes 304 may be made.

[0046]

[0054] At 510, the process 500 forms a plurality of sense lines including a first sense line and a second sense line. The first line sense line is connected to the column and the second sense line is connected to the ground shield. For example, in FIG. 1 and FIG. 2, the sense lines 120 may be formed with the sense line 120(1) connected to the conductive paste 122 and the sense line 120(2) connected to the ground shield 126.

[0047]

[0055] Technical advantages of using process 500 to create the sense lines described herein include creating a sense line that occupies less space, e.g., about 250 μm×250 μm, compared to a conventional sense line that occupies about 400 μm×400 μm. Process 500 can be applied to both cored substrates (e.g., as shown in FIG. 1 ) and coreless substrates (e.g., as shown in FIG. 2 ). By occupying less space within a package (e.g., packages 100, 200), the package can be made smaller or additional functionality can be added.

[0048]

[0056] 6 illustrates an example process 600 that includes depositing a conductive paste into a hole in a portion of a substrate according to an embodiment of the present disclosure. Process 600 may be performed as part of a semiconductor manufacturing process.

[0049]

[0057] At 602, the process 600 forms a plurality of pads (e.g., for via pads). Each pad of the plurality of pads is disposed on a corresponding metal layer of a plurality of metal layers. For example, in Figures 3A and 4A, a plurality of pads may be formed, such as representative pads 302(1), 302(2), 302(3), 302(4), etc. The multiple pads may be used for via pads on multiple layers (e.g., metal 1, metal 2, metal 3, metal 4, etc.).

[0050]

[0058] At 604, the process 600 drills holes to form the outer ring of the sense lines. For example, in Figures 3B and 4B, a drill (e.g., a mechanical drill, a laser, or another type of drilling device) may be used to create holes 304 to form the outer ring of the sense lines (e.g., pads 302 in Figures 3A and 4A), as shown in Figures 4A and 4B.

[0051]

[0059] At 606, the process 600 performs plating of the holes (PTH). For example, in Figures 3B and 4B, the PTH may be performed using copper (Cu) or another type of metal (or metal alloy). For example, the Cu plating may have a thickness of about 10 μm.

[0052]

[0060] At 608, the process 600 fills the hole with a resin (e.g., a dielectric material). For example, in Figures 3C and 4C, the hole 304 (of Figures 3B, 4B) is filled with a resin sheath 124 (e.g., a dielectric material).

[0053]

[0061] At 610, the process 600 drills holes through the resin. For example, in Figures 3D and 4D, a drill (e.g., a mechanical drill, a laser, or another type of hole-making device) can be used to create holes 306. Holes 306 can have a diameter of about 100 μm in some embodiments.

[0054]

[0062] At 612, the process 600 deposits a conductive paste in the hole and cures the conductive paste. For example, in Figures 3E and 4E, the hole 306 of Figures 3D, 4D is filled with conductive paste 122 and cured. An inkjet printer or another type of deposition means may be used to deposit the conductive paste 122 in the hole 306. A flash lamp or another type of curing means may be used to cure (e.g., harden) the conductive paste 122.

[0055]

[0063] At 614, the process 600 adds a dielectric layer. For example, in Figures 3F and 4F, the substrate 102 and the coreless substrate 202 are further stacked by adding a dielectric layer 308.

[0056]

[0064] At 616, the process 600 creates (e.g., using a laser, etching, or another type of means) one or more openings for vias. For example, in Figures 3F and 4F, a via, such as representative via 310, is made (e.g., using a laser, etching, etc.) in dielectric layer 308.

[0057]

[0065] At 618, the process 600 stacks multiple metal layers. For example, in Figures 3G and 4G, a metal layer such as representative metal layer 312 is stacked and additional steps in the manufacturing process are performed on the substrate 102, 202.

[0058]

[0066] Technical advantages of using process 600 to create the sense lines described herein include creating a sense line that occupies less space, e.g., about 250 μm×250 μm, compared to a conventional sense line that occupies about 400 μm×400 μm. Process 600 can be applied to both cored substrates (e.g., as shown in FIG. 1 ) and coreless substrates (e.g., as shown in FIG. 2 ) with minimal modifications. By occupying less space within a package (e.g., packages 100, 200), the package can be made smaller or additional functionality can be added.

[0059]

[0067] It will be understood that the foregoing fabrication processes are provided merely as general illustrations of some of the aspects of the present disclosure, and are not intended to limit the scope of the present disclosure or the appended claims. Furthermore, many details in the fabrication processes known to those skilled in the art may be omitted or combined in summary process sections to facilitate understanding of the various aspects disclosed without detailed descriptions of each detail and / or every possible process variation.

[0060]

[0068] FIG. 7 illustrates an exemplary mobile device 700 according to some examples of the present disclosure. Referring now to FIG. 7, a block diagram of a mobile device configured according to an exemplary aspect is depicted, generally designated as mobile device 700. In some aspects, the mobile device 700 may be configured as a wireless communication device. As shown, the mobile device 700 includes a processor 701. The processor 701 is communicatively coupled to a memory 732 via a link, which may be an inter-die link or an inter-chip link. The processor 701 is a hardware device capable of executing logical instructions. The mobile device 700 also includes a display 728 and a display controller 726, which is coupled to the processor 701 and the display 728.

[0061]

[0069] In some aspects, FIG. 7 may include a Coder / Decoder (CODEC) 734 (e.g., an audio and / or voice codec) coupled to the processor 701, a speaker 736 and a microphone 738 coupled to the CODEC 734, and a wireless circuit 740 (which may include a modem, RF circuitry, filters, etc., any of which may be implemented using package 100 or package 200 as described herein) coupled to a wireless antenna 742 and the processor 701.

[0062]

[0070] In certain aspects in which one or more of the above-mentioned blocks are present, the processor 701, the display controller 726, the memory 732, the codec 734, and the wireless circuitry 740 may comprise package 100 or package 200 and may be implemented in whole or in part using the techniques disclosed herein. The input device 730 (e.g., a physical or virtual keyboard), the power source 744 (e.g., a battery), the display 728, the input device 730, the speaker 736, the microphone 738, the wireless antenna 742, and the power source 744 may be external to the mobile device 700 and coupled to components of the mobile device 700, such as an interface or controller.

[0063]

[0071] It should be noted that although FIG. 7 shows a mobile device 700, the processor 701 and memory 732 may also be integrated into a set-top box, a music player, a video player, an entertainment unit, a navigation device, a Personal Digital Assistant (PDA), a stationary data unit, a computer, a laptop, a tablet, a communications device, a mobile phone, or other similar device.

[0064]

[0072] FIG. 8 illustrates various electronic devices that may be integrated with the aforementioned integrated devices, semiconductor devices, or packages according to various examples of the present disclosure. For example, a mobile phone device 802, a laptop computer device 804, and a fixed terminal device 806 may each generally be considered as User Equipment (UE) and may include a semiconductor 800 (e.g., including either package 100 or package 200). The semiconductor 800 may be included in, for example, any of the integrated circuits, dies, integrated devices, integrated device packages, integrated circuit devices, device packages, integrated circuit (IC) packages, and package-on-package devices described herein. The devices 802, 804, 806 illustrated in FIG. 8 are merely examples. Other electronic devices may also incorporate semiconductor 800, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, handheld Personal Communication System (PCS) units, portable data units such as personal digital assistants, Global Positioning System (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, stationary data units such as meter readers, communication devices, smartphones, tablet computers, computers, wearable devices, servers, base stations, access points, routers, electronic devices mounted on automobiles (e.g., autonomous vehicles), Internet of things (IoT) devices, or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0065]

[0073] It should be noted that although specific frequencies, integrated circuits (ICs), hardware, and other features are described in the embodiments herein, alternative embodiments may vary. That is, alternative embodiments may utilize additional or alternative frequencies (e.g., other 60 GHz and / or 28 GHz frequency bands), antenna elements (e.g., having antenna element arrays of different sizes / shapes), scanning periods (including both static and dynamic scanning periods), electronic devices (e.g., WLAN APs, cellular base stations, smart speakers, IoT devices, mobile phones, tablets, personal computers (PCs), etc.), and / or other features. Those skilled in the art will appreciate such variations.

[0066]

[0074] It should be understood that any reference to an element herein using a designation such as "first," "second," etc., does not generally limit the quantity or order of those elements. Rather, these designations may be used herein as a convenient way of distinguishing between two or more elements or instances of an element. Thus, reference to a first element and a second element does not imply that only two elements may be employed therein, or that the first element must precede the second element in some manner. Also, unless otherwise stated, a set of elements may include one or more elements. In addition, a term of the form "at least one of A, B, or C" or "one or more of A, B, or C" or "at least one of the group consisting of A, B, and C" as used in this description or claims means "A or B or C or any combination of these elements." For example, the term may include A, or B, or C, or A and B, or A and C, or A and B and C, or 2A, or 2B, or 2C, etc.

[0067]

[0075] As used herein, terms such as "user equipment" (or "UE"), "user device", "user terminal", "client device", "communication device", "wireless device", "wireless communication device", "handheld device", "mobile device", "mobile terminal", "mobile station", "handset", "access terminal", "subscriber device", "subscriber terminal", "subscriber station", "terminal", and variations thereof may interchangeably refer to any suitable mobile or fixed device capable of receiving wireless communication and / or navigation signals. These terms include, but are not limited to, music players, video players, entertainment units, navigation devices, communication devices, smartphones, personal digital assistants, stationary terminals, tablet computers, computers, wearable devices, laptop computers, servers, automotive devices in automobiles, and / or other types of portable electronic devices that are typically carried by a person and / or have communication capabilities (e.g., wireless, cellular, infrared, short-range radio, etc.). These terms are also intended to include a device that communicates with another device that can receive wireless communication and / or navigation signals by a short-range wireless connection, infrared connection, wired connection, or other connection, etc., regardless of whether the satellite signal reception, assistance data reception, and / or location-related processing is performed on that device or on another device. A UE may be embodied by any of several types of devices, including, but not limited to, Printed Circuit (PC) cards, Compact Flash devices, external or internal modems, wireless or wired phones, smartphones, tablets, consumer tracking devices, asset tags, etc.

[0068]

[0076] It should be noted that the terms "connected" and "coupled," or any variation thereof, mean any direct or indirect connection or coupling between elements, unless the connection is expressly disclosed as being directly connected, and may encompass the presence of intermediate elements between two elements that are "connected" or "coupled" together through intermediary elements.

[0069]

[0077] One or more of the components, processes, features, and / or functions shown in FIGS. 1-8 may be rearranged and / or combined into a single component, process, feature, or function, or incorporated into several components, processes, or functions. Additional elements, components, processes, and / or functions may be further added without departing from this disclosure. It is also noted that FIGS. 1-8 and their corresponding descriptions in this disclosure are not limited to dies and / or ICs. In some implementations, FIGS. 1-8 and their corresponding descriptions may be used to manufacture, create, provide, and / or produce an integrated device. In some implementations, the device may include a die, an integrated device, a die package, an integrated circuit (IC), a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a system in package (SiP), a system on chip (SoC), a package on package (PoP) device, etc.

[0070]

[0078] The devices and functions disclosed above may be designed and configured in computer files (e.g., Register-Transfer Level (RTL), Geometric Data Stream (GDS) Gerbers, etc.) stored on a computer-readable medium. Some or all of such files may be provided to a fabricator who fabricates devices based on such files. The resulting products may include semiconductor wafers, which are then cut into semiconductor dies and packaged into semiconductor packages, integrated devices, system-on-chip devices, etc., which may then be used in the various devices described herein.

[0071]

[0079] It will be understood that the various embodiments disclosed herein can be described as functional equivalents of structures, materials, and / or devices described and / or recognized by those skilled in the art. For example, in one embodiment, an apparatus may include means for performing the various functions described above. It will be understood that the foregoing embodiments are provided merely as examples, and that the various embodiments claimed are not limited to the specific content and / or figures cited as examples.

[0072]

[0080] In the above detailed description, it can be seen that various features are grouped in examples. This mode of disclosure should not be understood as an intention that the exemplary clauses have more features than are expressly stated in each clause. Rather, various aspects of the disclosure may include fewer than all features of each disclosed exemplary clause. Thus, the following clauses should be considered as incorporated in the description, and each clause can be a separate example in itself. Although each dependent clause may refer to a specific combination with one of the other clauses in the clause, the aspect(s) of that dependent clause are not limited to that specific combination. It will be understood that other exemplary clauses may also include combinations of the aspect(s) of the dependent clause with the subject matter of any other dependent clause or independent clause, or combinations of any features with other dependent clauses and independent clauses. Unless a specific combination is expressly stated or readily inferred to be not intended (e.g., conflicting aspects such as defining an element as both an insulator and a conductor), the various aspects disclosed herein expressly include these combinations. It is further contemplated that aspects of a clause may be included in any other independent clause, even if the clause is not directly dependent on the independent clause. Example implementations are described in the following numbered clauses.

[0081] Clause 1. An apparatus comprising: a semiconductor device having a substrate, the semiconductor device comprising: a column including a conductive paste penetrating a plurality of metal layers; a resin sheath surrounding the column, the resin sheath comprising a dielectric material; a ground shield surrounding the resin sheath; and a plurality of sense lines including a first sense line and a second sense line, the first sense line connected to the column and the second sense line connected to the ground shield.

[0073] Clause 2. The apparatus of clause 1, wherein the substrate comprises a cored substrate.

[0074] Clause 3. The apparatus of clause 1 or 2, wherein the substrate comprises a coreless substrate.

[0075] Clause 4. The apparatus of any one of clauses 1-3, wherein at least a portion of the sense line is coupled to a power management integrated circuit (PMIC).

[0076] Clause 5. The apparatus of any one of clauses 1-4, wherein the column containing the conductive paste has a diameter of about 100 micrometers.

[0077] Clause 6. The apparatus of any one of clauses 1-5, wherein the combination of the column, resin sheath, and ground shield occupies an area of ​​about 250 micrometers by about 250 micrometers.

[0078] Clause 7. The apparatus of any one of clauses 1-6, further comprising a die coupled to the semiconductor device.

[0079] Clause 8. The apparatus of any one of clauses 1-7, wherein the apparatus is selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, an access point, a stationary terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, a base station, and a device in an automobile.

[0080] Clause 9. A method of fabricating a semiconductor device, comprising stacking substrates, the stacking substrates comprising: forming columns including a conductive paste penetrating a plurality of metal layers; forming a resin sheath surrounding the columns, the resin sheath comprising a dielectric material; forming a ground shield surrounding the resin sheath; and forming a plurality of sense lines including a first sense line and a second sense line, the first sense line connected to the columns and the second sense line connected to the ground shield.

[0081] Clause 10. The method of clause 9, wherein the substrate comprises a cored substrate.

[0082] Clause 11. The method of clause 9 or 10, wherein the substrate comprises a coreless substrate.

[0083] Clause 12. The method of any one of clauses 9-11, wherein at least a portion of the sense lines are coupled to a power management integrated circuit (PMIC).

[0084] Clause 13. The method of any one of clauses 9 to 12, wherein the column containing the conductive paste has a diameter of about 100 micrometers.

[0085] Clause 14. The method of any one of clauses 9-13, wherein the combination of the column, resin sheath, and ground shield occupies an area of ​​about 250 micrometers by about 250 micrometers.

[0086] Clause 15. The method of any one of clauses 9-14, further comprising bonding a die to a semiconductor device.

[0087] Clause 16. The method of any one of clauses 9-15, further comprising including the semiconductor device within an apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, an access point, a stationary terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, a base station, and a device within an automobile.

[0088]

[0082] Thus, it will be understood that, for example, a device or any component of a device may be configured (or enabled or adapted) to provide functionality as taught herein. This may be accomplished, for example, by manufacturing (e.g., fabricating) the device or component to provide the functionality, by programming the device or component to provide the functionality, or through the use of some other suitable implementation technique. As one example, an integrated circuit may be fabricated to provide the requisite functionality. As another example, an integrated circuit may be fabricated to support the requisite functionality and then configured (e.g., by programming) to provide the requisite functionality. As yet another example, a processor circuit may execute code to provide the requisite functionality.

[0089]

[0083] Although the above disclosure shows various exemplary aspects, it should be noted that various changes and modifications may be made to the illustrated examples without departing from the scope defined by the appended claims. The present disclosure is not limited to only the specifically illustrated examples. For example, unless otherwise specified, the functions, steps, and / or actions of the method claims according to the aspects of the present disclosure described herein need not be performed in a particular order. Furthermore, although a particular aspect may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is expressly stated.

Claims

1. A semiconductor device having a substrate, a column provided with a conductive paste that penetrates a plurality of metal layers, a resin sheath surrounding the column, the resin sheath comprising a dielectric material, a ground shield surrounding the resin sheath, a plurality of sense lines including a first sense line and a second sense line, the first sense line being connected to the column, the second sense line being connected to the ground shield, and the first sense line being located in a metal layer different from the second sense line among the plurality of metal layers, comprising a semiconductor device, comprising an apparatus.

2. The apparatus according to claim 1, wherein the substrate comprises a substrate with a core.

3. The apparatus according to claim 1, wherein the substrate comprises a coreless substrate.

4. The apparatus according to claim 1, wherein at least a part of the sense line is coupled to a power management integrated circuit (PMIC).

5. The apparatus according to claim 1, wherein the column provided with the conductive paste has a diameter of about 100 micrometers.

6. The apparatus according to claim 1, wherein the combination of the column, the resin sheath, and the ground shield occupies an area of about 250 micrometers × about 250 micrometers.

7. The apparatus according to claim 1, further comprising a die coupled to the substrate.

8. The apparatus according to claim 1, wherein the apparatus is selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, an access point, a stationary terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, a base station, and a device in an automobile.

9. A method of manufacturing a semiconductor device, comprising: stacking substrates, where stacking the substrates comprises: forming a column provided with a conductive paste that penetrates a plurality of metal layers, forming a resin sheath surrounding the column, the resin sheath comprising a dielectric material, forming a ground shield surrounding the resin sheath, Forming a plurality of sense lines including a first sense line and a second sense line, wherein the first sense line is connected to the column, the second sense line is connected to the ground shield, and the first sense line is located in a metal layer different from the second sense line among the plurality of metal layers. Method. **Claim 10** The method according to claim 9, wherein the substrate comprises a substrate with a core. **Claim 11** The method according to claim 9, wherein the substrate comprises a coreless substrate. **Claim 12** The method according to claim 9, wherein at least a portion of the sense line is coupled to a power management integrated circuit (PMIC). **Claim 13** The method according to claim 9, wherein the column comprising the conductive paste has a diameter of about 100 micrometers. **Claim 14** The method according to claim 9, wherein the combination of the column, the resin sheath, and the ground shield occupies an area of about 250 micrometers × about 250 micrometers. **Claim 15** The method according to claim 9, further comprising bonding a die to the substrate.

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