Transistors, electrical devices, and methods for producing transistors - Patents.com

Abstract

A transistor (1) including a source (10), a body (12), and a drain (14), the transistor (1) further including a plurality of semiconductor layers (20), the layers of the plurality of semiconductor layers (20) being fabricated from AlGaN or GaN, the plurality of semiconductor layers (20) being configured such that the aluminum content varies between each successive layer such that every other layer has a lower aluminum content than adjacent opposing layers of the plurality of semiconductor layers, the transistor (1) being either an N-channel metal oxide semiconductor (NMOS) transistor (1'), where a portion of the plurality of semiconductor layers (20) is p-doped and forms a portion of the body (12) of the NMOS transistor (1'), or a P-channel metal oxide semiconductor (PMOS) transistor (1''), where a portion of the plurality of semiconductor layers (20) is p-doped and forms a portion of the source (10) or the drain (14) of the PMOS transistor (1'').

Description

[Technical field]

[0001] The inventive concepts relate generally to transistors, electrical devices, and methods for producing transistors. [Background technology]

[0002] GaN transistors are often used for electrical devices that operate at high power and / or high frequencies. Due to the large bandgap of GaN, such transistors can function at higher temperatures than, for example, Si transistors. However, there is still room for further improvement. Summary of the Invention

[0003] An object of the inventive concept is to enable a new type of GaN-based transistor. A further object of the inventive concept is to enable a power-efficient electrical device. A further object of the inventive concept is to enable a power-efficient electrical device operating at high power and / or high frequency. These and other objects of the inventive concept are at least partially met by the present invention as defined in the independent claims. Preferred embodiments are specified in the dependent claims.

[0004] In this document, abbreviations of natural elements are used according to the periodic table, e.g., Al means aluminum, Ga means gallium, As means arsenic, Mg means magnesium, O means oxygen, and Si means silicon.

[0005] According to a first aspect, there is provided a transistor including a source, a body, and a drain, the transistor comprising: The transistor further includes a plurality of semiconductor layers, the layers of the plurality of semiconductor layers being fabricated from AlGaN or GaN, the plurality of semiconductor layers being configured such that the aluminum content varies between each successive layer such that every other layer has a lower aluminum content than adjacent opposing layers of the plurality of semiconductor layers, the transistor comprising: an N-channel metal oxide semiconductor (NMOS) transistor, where a portion of the plurality of semiconductor layers is p-doped and forms a portion of the body of the NMOS transistor; or A transistor is provided, which is either a P-channel metal oxide semiconductor (PMOS) transistor, where some of the semiconductor layers are p-doped and form part of a source or drain of the PMOS transistor.

[0006] An NMOS transistor may include a source / body / drain that is doped n / p / n, e.g., n+ / p / n+. Thus, the source may be n-doped (e.g., strongly n-doped, indicated by n+), the body may be p-doped, and the drain may be n-doped (e.g., strongly n-doped, indicated by n+). An NMOS transistor may further include a gate contact and an electrical insulator between the gate contact and the body. An applied bias to the gate contact may create an electric field in the body, below the electrical insulator. The applied bias may thus control the conduction of electrons between the source and drain through the body.

[0007] A PMOS transistor may include a source / body / drain that are doped p / n / p, e.g., p+ / n / p+. Thus, the source may be p-doped (e.g., strongly p-doped, indicated by p+), the body may be n-doped, and the drain may be p-doped (e.g., strongly p-doped, indicated by p+). A PMOS transistor may further include a gate contact and an electrical insulator between the gate contact and the body. An applied bias to the gate contact may create an electric field in the body, below the electrical insulator. The applied bias may thus control the conduction of holes between the source and drain through the body.

[0008] P doping can be difficult to achieve in GaN-based materials. Doping atoms such as Mg used for P doping are often passivated by hydrogen impurities or nitrogen vacancies. Thus, the free hole concentration can be low even when the doping concentration is high. To remove the passivation (or activate the doping atoms), post-growth annealing, for example in an atmosphere with low hydrogen concentration, can be used.

[0009] It is recognized that multiple semiconductor layers may eliminate or reduce the need for post-growth annealing of p-doped GaN-based materials. This enables new types of transistors, such as NMOS and PMOS transistors according to the first embodiment. Transistors that include both n-doped and p-doped regions (n / p / n or p / n / p doped source / body / drain) may degrade during post-growth annealing. For example, material diffusion due to post-growth annealing may change the doping profile (n-dopants may, for example, diffuse into nominally p-doped regions and vice versa) and / or change the material profile (Al may diffuse from an Al-rich region into a Ga-rich region, or Ga may diffuse from a Ga-rich region into an Al-rich region).

[0010] The semiconductor layers may enhance p-doping through the variation of the valence band edge, as explained by Kozodoy et al. [Appl. Phys. Lett. 75,2444 (1999)]. The variation of the valence band edge is caused here by the variation of the Al content in the semiconductor layers. If the band edge is far below the Fermi energy, the acceptors may be ionized, and if the band edge is close to the Fermi level, the resulting holes may accumulate. The valence band edge may vary in a direction perpendicular to the layers of the semiconductor layers. As a result of the variation of the valence band edge, the hole concentration may also vary. However, the average hole concentration may be higher than in a bulk film where the valence band edge does not vary. It should be understood that the variation of the valence band edge may be due to the varying band gap in the semiconductor layers, as well as the polarization effect due to band bending.

[0011] Multiple semiconductor layers can also enhance hole mobility, as further explained by Kozodoy et al. [Appl. Phys. Lett. 75, 2444-2446 (1999)].

[0012] The transistor according to the first aspect may have one or more advantages over conventional transistors. Because the need for post-growth annealing may be eliminated or reduced, the transistor may be based on a combination of n-doped and p-doped regions. This allows for great flexibility in transistor design. Furthermore, because the need for post-growth annealing may be eliminated or reduced, the size of the transistor may be smaller without diffusion degrading the transistor's performance. The smaller the features, e.g., the smaller the doped regions, the more severe the effects of diffusion may be.

[0013] Furthermore, a high hole concentration in the p-doped regions resulting from the multiple semiconductor layers may have some advantages for the transistor. In the case of an NMOS transistor, where some of the multiple semiconductor layers are p-doped and form the body of the transistor, a high hole concentration in the body of the transistor may have an advantageous effect. As explained by Ziabari et al. [Chinese Journal of Physics, 51(4), 844-853], a high hole concentration in the body of the transistor may improve, for example, short channel effects. In the case of a PMOS transistor, where some of the multiple semiconductor layers are p-doped and form the source or drain of the transistor, a high hole concentration in the source and / or drain of the transistor may have an advantageous effect. A high hole concentration may facilitate making an ohmic contact to the source and / or drain.

[0014] Furthermore, high hole mobility can facilitate fast switching and / or high operating frequencies of transistors. The switching speed and / or high operating frequencies can be further improved by ballistic transport. Through ballistic transport, the mobility can be improved by nine orders of magnitude compared to bulk GaN films at room temperature. Ballistic transport can be achieved by superlattices of AlGaN / GaN heterostructures at certain alloy compositions of AlGaN.

[0015] It is further recognized that the NMOS or PMOS transistor according to the first aspect facilitates complementary metal oxide semiconductor (CMOS) technology, which may provide power-efficient electrical devices. In a CMOS device, PMOS and NMOS transistors may be connected in pairs such that when one type of transistor (e.g., NMOS) is turned on, the other type of transistor (e.g., PMOS) is turned off, and vice versa. Thus, power may be consumed primarily during switching and not during static operation. A CMOS device may be fabricated from an NMOS transistor according to the first aspect and a PMOS transistor according to the first aspect. Alternatively, a CMOS device may be fabricated from an NMOS transistor according to the first aspect and any type of PMOS transistor. Alternatively, a CMOS device may be fabricated from any type of NMOS transistor and a PMOS transistor according to the first aspect.

[0016] It should be understood that the source, body, and drain of a transistor may be part of the same semiconductor structure, however, the semiconductor structure may include separate portions of multiple semiconductor layers.

[0017] The plurality of semiconductor layers may include a repeating pair of semiconductor layers, each pair of semiconductor layers comprising: a low Al-containing layer having an Al content of less than 10%, and The high Al-containing layer has an Al content of more than 15%.

[0018] Therefore, the low Al content layer is x Ga 1-x Similarly, the high Al content layer may be a layer of Al. x Ga 1-xIt may be a layer of N, and x > 0.15. It is preferable that all the low Al-containing layers have the same composition and that they have a zero Al content, that is, that they contain GaN, that is, x = 0. It is preferable that all the high Al-containing layers have the same composition and that they have an Al content of 20% to 40%, that is, that they contain a material ranging from Al 0.2 Ga 0.8 N to Al 0.4 Ga 0.6 N, that is, 0.2 < x < 0.4. An example of a plurality of semiconductor layers including four layers is Al 0.2 Ga 0.8 N / GaN / Al 0.2 Ga 0.8 N / GaN, or Al 0.3 Ga 0.7 N / GaN / Al 0.3 Ga 0.7 N / GaN.

[0019] Alternatively, each pair of semiconductor layers may include low and high Al-containing layers, but not all the low Al-containing layers necessarily have the same Al content. Similarly, not all the high Al-containing layers necessarily have the same Al content. Thus, the plurality of semiconductor layers may be, for example, Al 0.2 Ga 0.8 N / Al 0.05 Ga 0.95 N / Al 0.16 Ga 0.84 N / GaN, or Al 0.3 Ga 0.7 N / Al 0.09 Ga 0.91 N / Al 0.22 Ga 0.78 N / Al 0.02 Ga 0.98 N / Al 0.2 Ga 0.8 N / Al 0.07 Ga 0.93 N.

[0020] A layer with a low Al content has, to a first approximation, a smaller band gap than a layer with a high Al content. This may result in a variation in the valence band edge. However, polarization and / or strain effects between the low and high Al content layers may modify the variation in the valence band edge. For example, local energy minima and local energy maxima at the varying valence band edge may exist at the interface between the high and low Al content layers. To illustrate, assuming that the surface of the quartz crystal is a Ga face proceeding upwards from the substrate through multiple semiconductor layers (this may be the case when MOCVD is used to initiate growth on sapphire), a local energy minimum may appear at the interface in the conduction band where the low Al content layer transitions to the high Al content layer (label this region A) and a local energy maximum may appear at the interface where the high Al content layer transitions to the low Al content layer (label this region B). The above explanation is similar to that given on page 2445 of Appl. Phys. Lett. 75, 2444-2446 (1999), which is incorporated herein by reference.

[0021] It should be noted that when this document refers to the semiconductor layers being p-doped, it may be that the semiconductor layers are constructed such that they are p-doped in the A regions but not in the B regions. Such doping may result in the highest hole mobility. However, it may also be understood that the semiconductor layers are constructed such that they are p-doped throughout the entire layer of the semiconductor layers.

[0022] The transistor may be configured such that each layer of the plurality of semiconductor layers has a thickness between 3 nm and 10 nm. The layers may all have the same thickness, e.g., all layers have a thickness of 3 nm, all layers have a thickness of 6 nm, or all layers have a thickness of 10 nm. Alternatively, the plurality of semiconductor layers may include layers of different thicknesses. For example, all low Al-containing layers may have a thickness between 3 nm and 10 nm, and all high Al-containing layers may have a thickness between 3 nm and 10 nm, with the thickness of the low Al-containing layers being different from the thickness of the high Al-containing layers. For example, each pair of semiconductor layers may include, for example, a 6 nm thick low Al-containing layer and a 5 nm thick high Al-containing layer.

[0023] In the thickness range of 3 to 10 nm, the enhancement of p-doping may be most efficient, for example, the polarization effect and / or strain effect between the low Al-containing layer and the high Al-containing layer may be most effective in the above thickness range.

[0024] The transistor may be configured to pass current in a direction that is primarily parallel to the layers of the multiple semiconductor layers. Thus, the current may flow unhindered by any variations in the band edges. Such a transistor may be referred to as a lateral transistor. The lateral transistor is compatible with conventional processing techniques, e.g., conventional CMOS techniques, and therefore may be produced in a cost-effective manner. The lateral transistor may include a source contact connected to the source, a gate contact connected to the body, and a drain contact connected to the drain. The source contact, gate contact, and drain contact may be disposed side-by-side, e.g., in the same plane, on the semiconductor structure that includes the transistor.

[0025] Alternatively, the transistor may be configured to pass current primarily in a direction perpendicular to the layers of the semiconductor layers. Charge carriers may now pass over the large band gap layer in the semiconductor layers, for example, by thermal activation. Alternatively, or in addition, charge carriers may pass through the large band gap layer in the semiconductor layers, for example, by quantum tunneling. Thus, current may flow vertically, i.e., in the epitaxial growth direction, of the semiconductor structure including the transistor. For example, current may flow vertically through an integrated circuit (IC) chip including the transistor. Such a transistor may be called a vertical transistor. A vertical transistor may have a small footprint because it may be easier to arrange the source, gate, and drain contacts in a non-side-by-side manner. For example, one contact may be on the top side of the semiconductor structure, while another contact may be on the back side of the semiconductor structure. It should be understood that although vertical transistors may be manufactured differently than lateral transistors, the manufacturing methodology may still be largely based on conventional CMOS technology.

[0026] Further, the transistor may be configured such that the nanowire confines at least a portion of the body of the transistor. For example, a semiconductor structure including a source, body, and drain may be epitaxially grown. One or more nanowires may then be etched from above through at least a portion of the body. Thus, the body of the transistor may be confined within the nanowire. Thus, the nanowire may preferably be a top-down fabricated nanowire. However, it may be understood that the nanowire may alternatively be a bottom-up fabricated nanowire, for example, fabricated through selective area growth or nanoparticle-assisted growth. Doping profiles, material interfaces, surface states, etc. may be more controllable in top-down nanowires than bottom-up nanowires. The nanowire may have a diameter smaller than 100 nm, for example, 5 nm to 100 nm or 10 nm to 50 nm. The axial length of the nanowire may be 200 to 1000 nm. Ballistic transport of 200 nm has been demonstrated in gallium nitride at room temperature. Such a diameter may give rise to quantum confinement effects within the body of the transistor.

[0027] It can be advantageous to have the body of a transistor confined to a nanowire. For example, charge carriers can have increased mobility due to quantum confinement effects. The transistor can thus have short switching times and / or be operated at high frequencies. Furthermore, the transistor can have a small footprint when the body of the transistor is confined to a nanowire. Thus, many transistors can be placed in a small area.

[0028] A first example of a transistor with a nanowire that confines part of the body is A transistor including a source, a body, and a drain, the transistor comprising: The transistor further includes a plurality of semiconductor layers, the layers of the plurality of semiconductor layers being made of AlGaN having an aluminum content greater than or equal to 0%, the plurality of semiconductor layers being configured such that the aluminum content varies between each successive layer such that every other layer has a lower aluminum content than adjacent opposing layers of the plurality of semiconductor layers, a portion of the plurality of semiconductor layers being p-doped, and the transistor further includes A P-channel metal oxide semiconductor (PMOS) transistor, where the semiconductor layers form a portion of the source or drain of the PMOS transistor, the transistor is configured to pass current primarily in a direction perpendicular to the layers of the semiconductor layers, and the nanowire confines at least a portion of the body of the transistor. A first example may be fabricated, for example, as in FIG.

[0029] A second example of a transistor with a nanowire that confines part of the body is A transistor including a source, a body, and a drain, the transistor comprising: The semiconductor device further includes a plurality of semiconductor layers, the layers of the plurality of semiconductor layers being made of AlGaN having an aluminum content of 0% or greater, the plurality of semiconductor layers being configured such that the aluminum content varies between each successive layer such that every other layer has a lower aluminum content than adjacent opposing layers of the plurality of semiconductor layers, a portion of the plurality of semiconductor layers being p-doped, the transistor being an N-channel metal oxide semiconductor (NMOS) transistor, the plurality of semiconductor layers forming a portion of a body of the NMOS transistor, the transistor being configured to conduct current primarily in a direction perpendicular to the layers of the plurality of semiconductor layers, and the nanowire confining at least a portion of the body of the transistor. A second example may be fabricated, for example, as in FIG.

[0030] In the first and second examples above, the nanowire may additionally confine at least a portion of the semiconductor layers. Thus, the confinement effect in the semiconductor layers may further enhance the performance of the transistor. By confining at least a portion of the semiconductor layers to the nanowire, the current may be assisted to flow orthogonally to the semiconductor layers by the quantum confinement effect. Here, the quantum confinement effect may bring the energy state of the charge carrier closer to the band edge of the large band gap layer, so that the large band gap layer may be more easily traversed. Such enhancement is relevant when multiple semiconductor layers are present in the source or drain of the transistor. Such enhancement is also relevant when multiple semiconductor layers are present in the body of the transistor.

[0031] In the first and second examples above, the nanowires may extend in a direction perpendicular to the layers of the multiple semiconductor layers.

[0032] In the first and second examples above, the nanowire may additionally confine at least a portion of the source or drain of the transistor, and thus the confinement effect at the source or drain of the transistor may further enhance the performance of the transistor.

[0033] It should be understood that an alternative to confining the body of the transistor to a nanowire could be to confining the body of the transistor to a micropillar. The micropillar could have a diameter smaller than 1 μm, for example, between 5 nm and 500 nm. Even if the confinement effect is small, there could still be other advantages, such as a transistor with a small footprint.

[0034] The transistor may be configured such that the gate contact wraps around the nanowire enclosing at least a portion of the body of the transistor, thereby forming a wrap-around gate. The wrap-around gate may surround the body along the periphery of the nanowire. Thus, the wrap-around gate may efficiently control charge carriers in the body. The wrap-around gate may ensure low leakage current and / or overcome other short channel effects.

[0035] A nanowire that confines at least a portion of the body of a transistor may also confine at least a portion of the source and drain of the transistor. Again, the confinement effect may provide advantages such as producing high mobility and ballistic transport. Furthermore, having the source and drain of the transistor confined to a nanowire may facilitate single nanowire transistors, which may result in a small footprint of the transistor.

[0036] The source, drain, and body of a transistor may all include multiple semiconductor layers. Thus, the n-doped region of a transistor may also include multiple semiconductor layers. It is possible that multiple semiconductor layers may cause high mobility for electrons as well as holes. Furthermore, when manufacturing CMOS circuits, where an NMOS transistor includes multiple semiconductor layers in the body and a PMOS transistor includes multiple semiconductor layers in the source and drain, it may be advantageous for the material structure to be the same for both NMOS and PMOS transistors. Thus, for example, one single semiconductor structure including multiple semiconductor layers may be epitaxially grown, and creating an NMOS or PMOS transistor may simply be a matter of which doping sequence is selected (e.g., n / p / n or p / n / p). Doping may now be performed after epitaxial growth. As a result, an efficient manufacturing process may be achieved.

[0037] The transistor may be an NMOS transistor; the source of the NMOS transistor comprises an n-doped GaN layer; The drain of the NMOS transistor comprises an n-doped GaN layer.

[0038] Such a transistor may have various advantages, for example, it may be easier to make high quality ohmic contacts to the n-doped GaN.

[0039] According to a second aspect, there is provided an electrical device comprising: at least one N-channel metal oxide semiconductor (NMOS) transistor, the at least one NMOS transistor including a plurality of semiconductor layers, each layer of the plurality of semiconductor layers being fabricated from AlGaN or GaN, the plurality of semiconductor layers of the NMOS transistor being configured such that an aluminum content varies between each successive layer such that every other layer has a lower aluminum content than adjacent opposing layers of the plurality of semiconductor layers, the plurality of semiconductor layers of the NMOS transistor forming a portion of a p-doped body of the NMOS transistor; at least one P-channel metal oxide semiconductor (PMOS) transistor, the at least one PMOS transistor comprising a plurality of semiconductor layers, each layer of the plurality of semiconductor layers being fabricated from AlGaN or GaN, the plurality of semiconductor layers of the PMOS transistor being configured such that the aluminum content varies between each successive layer such that every other layer has a lower aluminum content than adjacent opposing layers of the plurality of semiconductor layers, the plurality of semiconductor layers of the PMOS transistor forming a portion of a p-doped source or drain of the PMOS transistor; An electrical device is provided in which at least one NMOS transistor and at least one PMOS transistor are connected to form a complementary metal-oxide semiconductor (CMOS) circuit.

[0040] Thus, a CMOS circuit may be provided in which multiple semiconductor layers (though not necessarily the same multiple semiconductor layers) are used in both NMOS and PMOS transistors to enhance p-doping. When the PMOS and NMOS transistors are connected in pairs such that when one type of transistor (e.g., NMOS) is turned on, the other type of transistor (e.g., PMOS) is turned off, and vice versa, at least one NMOS transistor and at least one PMOS transistor may be connected to form a CMOS circuit. Thus, power may be consumed mainly during switching and not during static operation. As a result, the electrical device according to the second aspect may be a power-efficient electrical device.

[0041] It should be appreciated that advantages may also be achieved for CMOS circuits in which multiple semiconductor layers are used in either the NMOS or PMOS transistors to enhance p-doping, and such CMOS circuits may be more power efficient than corresponding CMOS circuits in which, for example, neither the NMOS nor the PMOS transistors include multiple semiconductor layers.

[0042] The device may be configured such that at least one NMOS transistor and at least one PMOS transistor of the CMOS circuit share the same semiconductor layers.

[0043] Thus, for example, one single semiconductor structure including multiple semiconductor layers can be epitaxially grown, and both the NMOS and PMOS transistors of a CMOS circuit can be manufactured from the same multiple semiconductor layers. As a result, an efficient manufacturing process can be achieved. For example, the shared multiple semiconductor layers can pass through the source, body, and drain of the NMOS transistor, and the source, body, and drain of the PMOS transistor, for example, in a lateral transistor. Thus, the source, body, and drain of each transistor can share multiple semiconductor layers, and the NMOS and PMOS transistors also share multiple semiconductor layers. Alternatively, the shared multiple semiconductor layers can pass through the body of the NMOS transistor and the source or drain of the PMOS transistor. Thus, the NMOS and PMOS transistors can share multiple semiconductor layers, even though the source, body, and drain do not necessarily include the same multiple semiconductor layers in each individual transistor.

[0044] An NMOS transistor and a PMOS transistor may share the same semiconductor layers if the shared semiconductor layers were originally epitaxially grown as one single semiconductor layer. Even if the transistors are separated by removing a portion of the semiconductor layers between them, for example by etching, the transistors may still be considered to share the same semiconductor layers.

[0045] It should be understood that at least one of the at least one PMOS transistor and / or at least one of the at least one NMOS transistor of the CMOS circuit of the electrical device may be a transistor according to the first aspect.

[0046] According to a third aspect, there is provided a method for producing a transistor, comprising the steps of: epitaxially growing a first n-doped layer of AlGaN or GaN; epitaxially growing a plurality of semiconductor layers, the plurality of semiconductor layers being grown on a first n-doped layer, each layer of the plurality of semiconductor layers being made of AlGaN or GaN, the plurality of semiconductor layers being configured such that the aluminum content varies between each successive layer such that every other layer has a lower aluminum content than adjacent opposing layers of that layer, and the plurality of semiconductor layers being grown p-doped; epitaxially growing a second n-doped layer of AlGaN or GaN, the second n-doped layer being grown on the plurality of semiconductor layers, whereby the first n-doped layer, the plurality of semiconductor layers, and the second n-doped layer form part of a semiconductor structure, the method comprising: electrically connecting one of the first and second n-doped layers to a source contact and the other of the first and second n-doped layers to a drain contact, whereby a transistor source and a transistor drain are formed by the first and second n-doped layers; The method further includes disposing a gate contact on the semiconductor structure, the gate contact configured to apply an electric field to the plurality of semiconductor layers such that electrical conduction between a source and a drain through the plurality of semiconductor layers is controllable by the gate contact, whereby a transistor body is formed by the plurality of semiconductor layers.

[0047] The method can thus produce NMOS transistors.

[0048] The structure may be epitaxially grown by metalorganic vapor phase epitaxy (MOVPE). However, other epitaxial growth methods, such as molecular beam epitaxy (MBE), may alternatively be used. The structure may be epitaxially grown in one growth session or in several growth sessions. For example, part of the structure may be epitaxially grown in one session, then partially etched, and then epitaxial growth may continue in a second session.

[0049] The method may further include etching nanowires from the multiple semiconductor layers.

[0050] Thus, multiple semiconductor layers within a transistor body can be confined to a nanowire.

[0051] For example, a nanowire can be etched from the second n-doped layer, the multiple semiconductor layers, and the first n-doped layer, such that the nanowire extends from the second n-doped layer, through the multiple semiconductor layers, and into the first n-doped layer.

[0052] Thus, the source and drain of the transistor can be confined to the nanowire in addition to the body of the transistor.

[0053] The electrical device according to the second aspect may have the same or similar advantages as the transistor according to the first aspect. Similarly, the method according to the third aspect may have the same or similar advantages as the transistor according to the first aspect.

[0054] The above, as well as additional objects, features, and advantages of the inventive concept will become better understood through the following illustrative and non-limiting description, taken in conjunction with the accompanying drawings, in which like reference numerals will be used for like elements unless otherwise noted, in which: [Brief description of the drawings]

[0055] [Figure 1]FIG. 2 illustrates a PMOS transistor. [Diagram 2] FIG. 1 illustrates an NMOS transistor. [Diagram 3] FIG. 1 illustrates an electrical device. [Figure 4] FIG. 1 illustrates an NMOS transistor. [Diagram 5] FIG. 1 illustrates an NMOS transistor. [Figure 6] FIG. 2 illustrates a PMOS transistor. [Figure 7] FIG. 2 illustrates source and gate contacts. [Figure 8] FIG. 2 illustrates source, drain, and gate contacts. [Figure 9] FIG. 1 illustrates an NMOS transistor. [Figure 10] FIG. 2 illustrates a PMOS transistor. [Figure 11] FIG. 1 illustrates an electrical device. [Figure 12] FIG. 2 illustrates a flow chart. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0056] In conjunction with the accompanying drawings, the technical contents and detailed description of the present invention will be described hereinafter according to preferred embodiments, which are not used to limit the scope of the claims. The present invention can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein, but rather these embodiments are provided for thoroughness and completeness, to fully convey the scope of the present invention to those skilled in the art.

[0057] 1 and 2 illustrate cross-sectional views of a lateral transistor 1. FIG. 1 illustrates an NMOS transistor 1′, and FIG. 2 illustrates a PMOS transistor 1″. Each of the illustrated transistors 1 includes a plurality of semiconductor layers 20. The plurality of semiconductor layers 20 includes layers of AlGaN or GaN. The aluminum content varies between each successive layer such that every other layer has a lower aluminum content than their adjacent, opposing layers. Every other layer, e.g., the even-numbered layers, may be low Al-containing layers 22, and the layers in between, e.g., the odd-numbered layers, may be high Al-containing layers 24. The terms “high” and “low” should be interpreted in relative terms herein. The low Al-containing layers 22 may have an Al content less than 10% and the high Al-containing layers 24 may have an Al content greater than 15%. For example, each low Al-containing layer 22 may be a GaN layer or an AGaN layer. l0.05 Ga 0.95 Further, each high Al-containing layer 24 may be an AlN layer. 0.2 Ga 0.8 N, or Al 0.3 Ga 0.7 N, or any composition in between. Thus, the plurality of semiconductor layers 20 may include a repeating pair of semiconductor layers, each pair of semiconductor layers including a low Al-containing layer 22 and a high Al-containing layer 24. The repeating may be a cyclic repeat.

[0058] Each layer 22, 24 of the plurality of semiconductor layers 20 may have a thickness of 3 nm to 10 nm. For example, each layer may have a thickness of 6 nm or 8 nm.

[0059] The semiconductor layers 20 illustrated in Figures 1 and 2 may be epitaxially grown on a substrate (not shown), e.g., a Si, SiC, or sapphire substrate, e.g., by MOVPE. The semiconductor layers 20 may be doped with n-type or p-type dopants during epitaxial growth. The semiconductor layers 20 may be further doped, e.g., in specific regions, after epitaxial growth. The specific regions may be doped, e.g., through diffusion from the gas phase or through ion implantation, and such regions are illustrated by dashed lines in Figures 1 and 2.

[0060] FIG. 1 illustrates a semiconductor structure including a plurality of semiconductor layers 20 that are p-doped during epitaxial growth. The n-doped regions are then created after epitaxial growth to form the source 10 and drain 14 of an NMOS transistor 1′. The n-doped regions are separated by p-doped regions that form the body 12 of the NMOS transistor 1. A source contact 60 electrically connects to the source 10, and a drain contact 64 electrically connects to the drain 14. A gate contact 62 is disposed on the semiconductor structure and configured to apply an electric field to the body 12 of the NMOS transistor 1′ such that electrical conduction between the source 10 and the drain 14 through the body 12 is controllable by the gate contact 62. In the illustrated example, the source contact 60, the gate contact 62, and the drain contact 64 are disposed side-by-side on the semiconductor structure including the NMOS transistor 1′. In the illustrated example, the gate contact 62 is disposed between the source contact 60 and the drain contact 64. The source contact 60 and the drain contact 64 may comprise a metal, for example a metal partially diffused into the source 10 and the drain 14, respectively. The gate contact 62 may comprise a metal or another conductive material, for example doped polysilicon. An electrical insulator, for example an oxide, may separate the semiconductor structure from the metal (or other conductive material) of the gate contact 62.

[0061] FIG. 2 illustrates a semiconductor structure including a plurality of semiconductor layers 20 that are n-doped during epitaxial growth. P-doped regions are then created after epitaxial growth to form the source 10 and drain 14 of the PMOS transistor 1″. The p-doped regions are separated by n-doped regions that form the body 12 of the NMOS transistor 1′. A source contact 60 electrically connects to the source 10, and a drain contact 64 electrically connects to the drain 14. A gate contact 62 is disposed on the semiconductor structure and configured to apply an electric field to the body 12 of the PMOS transistor 1″ such that electrical conduction between the source 10 and the drain 14 through the body 12 is controllable by the gate contact 62. In the illustrated example, the source contact 60, the gate contact 62, and the drain contact 64 are disposed side-by-side on the semiconductor structure that includes the PMOS transistor 1″. In the illustrated example, the gate contact 62 is disposed between the source contact 60 and the drain contact 64. The source contact 60 and the drain contact 64 may comprise a metal, for example a metal partially diffused into the source 10 and the drain 14, respectively. The gate contact 62 may comprise a metal or another conductive material, for example doped polysilicon. An electrical insulator, for example an oxide, may separate the semiconductor structure from the metal (or other conductive material) of the gate contact 62.

[0062] In FIG. 1 and FIG. 2, the source 10, drain 14, and body 12 of the transistor 1′, 1″ all include multiple semiconductor layers 20. Furthermore, the illustrated transistor 1′, 1″ is configured to pass current mainly in a direction parallel to the layers of the multiple semiconductor layers 20. For example, the current may enter the source 10 from the source contact 60. A portion of the current may then flow at least some distance perpendicular to the layers of the multiple semiconductor layers 20, and after the layers of the multiple semiconductor layers 20, the current may flow mainly laterally. Thus, the current may flow mainly in a direction parallel to the layers of the multiple semiconductor layers 20 through the body of the transistor 1′, 1″. In fact, the current may flow in a direction parallel to the layers of the multiple semiconductor layers 20 through the body of the transistor 1′, 1″. The current may exit through the drain 14 and the drain contact 64. A portion of the current may then flow at least some distance perpendicular to the layers of the multiple semiconductor layers 20 in the drain 14 of the transistor 1′, 1″.

[0063] FIG. 3 illustrates a cross-sectional view of an electrical device 50 including a CMOS circuit 52. The CMOS circuit 52 includes an NMOS transistor 1′ and a PMOS transistor 1″. The NMOS transistor 1′ includes a plurality of semiconductor layers 20, and the PMOS transistor 1″ includes a plurality of semiconductor layers 20. In the illustration, the NMOS transistor 1′ and the PMOS transistor 1″ of the CMOS circuit 52 share the same plurality of semiconductor layers 20. The NMOS transistor 1′ and the PMOS transistor 1″ are both lateral transistors. In the illustration, each layer of the shared plurality of semiconductor layers 20 passes through both the NMOS transistor 1′ and the PMOS transistor 1″. Furthermore, within each transistor 1′, 1″ of the CMOS circuit 52, the source 10, the body 12, and the drain 14 share the plurality of semiconductor layers 20.

[0064] The shared semiconductor layers 20 in the CMOS circuit 52 in Figure 3 may be epitaxially grown as n-doped. A PMOS transistor 1'' may then be produced by p-doping the source 10 and drain 14 as described in conjunction with Figure 2. An NMOS transistor 1' may be produced by first p-doping a region to form the body of the NMOS transistor 1', and second n-doping two regions within the p-doped region to form the source 10 and drain 14 of the NMOS transistor 1', as shown in the figure.

[0065] Figures 4 to 6 illustrate cross-sectional views of a vertical transistor 1. Figures 4 and 5 illustrate an NMOS transistor 1', and Figure 6 illustrates a PMOS transistor 1''.

[0066] 4 illustrates an NMOS transistor 1′ in which the p-doped body 12 includes multiple semiconductor layers 20 of varying Al content, and the n-doped source 10 and drain 14 do not include multiple semiconductor layers 20. Instead, the source 10 and drain 14 may include one single material, e.g., GaN. Thus, as illustrated, the source 10 of the NMOS transistor 1′ may include an n-doped GaN layer 30, The drain 14 of the NMOS transistor 1 ′ may include an n-doped GaN layer 30 .

[0067] FIG. 5 illustrates an NMOS transistor 1 ′ in which the p-doped body 12 comprises multiple semiconductor layers 20 of varying Al content, and both the n-doped source 10 and drain 14 also comprise the same multiple semiconductor layers 20 .

[0068] FIG. 6 illustrates a PMOS transistor 1 ″ in which both the p-doped source 10 and drain 14 include multiple semiconductor layers 20 of varying Al content, and the n-doped body also includes the same multiple semiconductor layers 20 .

[0069] As illustrated in Figures 4-6, the nanowire 40 may confine at least a portion of the body 12 of the transistor 1. The figures show a plurality of nanowires 40 within the body 12 of the transistor 1. The nanowire 40 may be configured such that at least a portion of the current through the body 12 passes through the nanowire 40. Thus, the nanowire 40 of the plurality of nanowires may confine at least a portion of the body 12 of the transistor 1. In each of Figures 4-6, the body 12 of the transistor 1 may be seen as being confined by the plurality of nanowires 40. The nanowire 40 may be etched, for example, after epitaxial growth of the body 12, but before epitaxial growth of the source 10 or drain 14. The nanowire 40 may have a diameter smaller than 100 nm. The intermediate spaces between the nanowires 40 may be filled with an electrically insulating material, for example, an oxide or iron-doped gallium nitride GaN:Fe. Such filling of the intermediate spaces may be performed after etching the nanowires 40 and after further epitaxial growth. In the figure, the nanowires 40 extend only into the body 12. Alternatively, the nanowires 40 may of course also extend into the source 10 and / or drain 14. As can be seen in the figure, multiple semiconductor layers 20 may be stacked in the axial direction of the nanowires 40.

[0070] The transistors 1 illustrated in Figures 4-6 are all configured to pass current primarily in a direction perpendicular to the layers of the semiconductor layers 20. In the figures, this is implemented by having a source contact 60 and a drain contact 64 on opposite sides of the semiconductor layers 20. The gate contact 62 may then be located on the same side as the source contact 60 or the drain contact 64 (on the same side as the source contact 60 in the figures). Nevertheless, the gate contact 62 may be located in close proximity to both the body 12 and (in this case) the source contact 60 such that electrical conduction, such as current, between the source 10 and the drain 14 through the semiconductor layers 20 is controllable by the gate contact. In the figures, the proximity of the gate contact 62 to the source contact 60 may be such that an electric field created by the gate contact 62 may open or close a current path between the source contact 60 and the drain contact 64.

[0071] FIG. 7 illustrates a top view of a gate contact 62 and two source contacts 60. The contacts are interdigitated with the fingers of each contact intertwined with the fingers of the other contact. FIG. 7 may be viewed as illustrating a top view of any one of the transistors 1 shown in FIGS. 4-6. The two source contacts 60 shown in the cross-sectional views of FIGS. 4-6 may be viewed as a cross-section of two of the interdigitated source contact 60 fingers shown in the top view of FIG. 7. Similarly, the gate contact 62 shown in the cross-sectional views of FIGS. 4-6 may be viewed as a cross-section of the fingers of the gate contact 62 shown in the top view of FIG. 7. In addition or as an alternative to the contact configuration shown in FIG. 7, the gate contact 62 may surround the source contact 60.

[0072] 8 illustrates a top view of the gate contact 62, the source contact 60, and the drain contact 64. The contacts are interdigitated with the fingers of each contact intertwined with the fingers of the other contact. FIG. 8 may be viewed as illustrating a top view of any one of the transistors 1 shown in FIGS. 1-2.

[0073] 9 and 10 each illustrate a cross-sectional view of a transistor 1, where a nanowire 40 confines the body 12 of the transistor 1. Thus, in the figures, the body 12 is part of a single nanowire 40. Such a transistor 1 may be referred to as a single nanowire transistor. Furthermore, in the figures, the nanowire 40 that confines the body 12 of the transistor 1 also confines the source 10 and drain 14 of the transistor 1. Thus, in the figures, the source 10, body 12, and drain 14 are part of a single nanowire 40.

[0074] 9 illustrates a single nanowire NMOS transistor 1′ where the p-doped body 12 includes multiple semiconductor layers 20 of varying Al content, and the n-doped source 10 and drain 14 do not include multiple semiconductor layers 20. The source 10 and drain 14 may each include one single material, in this case an n-doped GaN layer 30. Alternatively, the multiple semiconductor layers 20 of the single nanowire NMOS transistor 1′ may of course extend into the source 10 and / or drain 14.

[0075] FIG. 10 illustrates a single nanowire PMOS transistor 1″ where both the p-doped source 10 and drain 14 include multiple semiconductor layers 20 of varying Al content, and the n-doped body 12 does not include multiple semiconductor layers 20. In the example, the n-doped body 12 includes a single layer, e.g., a GaN layer. Alternatively, the p-doped body 12 may include multiple semiconductor layers 20.

[0076] Figures 9 and 10 further illustrate a gate contact 62 that wraps around the nanowire 40 confining the body 12 of the transistor 1. Thus, in both Figures 9 and 10, the gate contact 62 is a wrap-around gate 42. The figures further show that the source contact 60 and the drain contact 64 wrap around the nanowire 40.

[0077] FIG. 11 illustrates a cross-sectional view of an electrical device 50 including a CMOS circuit 52. The CMOS circuit 52 includes an NMOS transistor 1′ and a PMOS transistor 1″. The NMOS transistor 1′ includes multiple semiconductor layers 20 in a p-doped body, and the PMOS transistor 1″ includes multiple semiconductor layers 20 in a p-doped source 10 and multiple semiconductor layers 20 in a p-doped drain 14. The illustrated CMOS circuit 52 is an inverter. An inverter, such as the illustrated inverter, may include an NMOS transistor 1′ and a PMOS transistor 1″. Additionally, an input may be connected to the gate contacts 62 of both the NMOS transistor 1′ and the PMOS transistor 1″. The source contact 60 of the NMOS transistor 1′ may be connected to a V ss , and the source contact 60 of the PMOS transistor 1″ may be connected to V DD The drain contacts 64 of the NMOS1' and PMOS1'' transistors may be connected to each other and to the output. Thus, the signal at the input may be inverted at the output.

[0078] FIG. 12 illustrates a flow chart of a method 100 for producing transistor 1. Method 100 is described herein as including steps S102-S112. However, it should be understood that some of the steps are optional as shown in the figure. It should be understood that at least some of the steps may be performed in a different order than as shown in the figure, as would be readily understood by one of ordinary skill in the art. Method 100 may be used to produce, for example, any one of NMOS transistors 1′ of FIG. 4, FIG. 5, or FIG. 9.

[0079] According to the method, the first n-doped layer, the plurality of semiconductor layers 20, and the second n-doped layer are epitaxially grown, for example, by MOVPE. The epitaxial growth can occur on a substrate, for example, a Si, SiC, or sapphire substrate.

[0080] According to the method 100, a first n-doped layer of AlGaN or GaN is epitaxially grown S102. The n-type dopant may be introduced in the gas phase of MOVPE. For example, precursors such as trimethylgallium (TMG), trimethylaluminum (TMA), and NH3 may be used for growth.

[0081] A plurality of semiconductor layers 20 are epitaxially grown S104 on the first n-doped layer, each layer 20 of the plurality of semiconductor layers being made of AlGaN or GaN, the plurality of semiconductor layers 20 being configured such that the aluminum content varies between each successive layer such that every other layer has a lower aluminum content than adjacent opposing layers of the plurality of semiconductor layers, and the plurality of semiconductor layers 20 are grown p-doped. Herein, a p-type dopant may be introduced in the gas phase of the MOVPE. The aluminum content may be varied by varying the precursor flow during epitaxial growth, for example, by varying the TMG / TMA ratio.

[0082] At this point, the epitaxial growth may optionally be stopped. The substrate may be removed from the growth chamber. The nanowire(s) 40 may then be etched S106 from the semiconductor layers 20. The nanowire(s) 40 may be etched perpendicularly to the semiconductor layers 20 such that the axis of the nanowire 40 is perpendicular to the semiconductor layers 20. This may be done by lithographically patterning the top surface of the semiconductor layers 20, for example by nanoimprint lithography, and then etching the exposed areas. The etching may be done by wet etching, for example using hydrofluoric acid, or by dry etching, for example by reactive ion etching. The etched nanowire 40 may confine a portion of the body 12 of the NMOS transistor 1'.

[0083] If the nanowires 40 are to be used freestanding, the substrate can be returned to the growth chamber and epitaxial growth can continue. In some cases, it can be advantageous to embed the nanowires 40 before continued epitaxial growth, for example embedding them in an oxide or semi-insulating iron-doped gallium nitride. The metal grown during continued epitaxial growth can then be supported by the embedded material and spread out laterally to connect several nanowires 40, for example to connect several nanowires 40 to the same source 10, as illustrated in Figures 4 to 6.

[0084] The method 100 further includes epitaxially growing S108 a second n-doped layer of AlGaN or GaN, the second n-doped layer being grown over the plurality of semiconductor layers 20. The epitaxial growth S108 may thus be performed in the same growth session as the previous growth steps S102, S104 if etching S106 is not performed. Alternatively, if etching S106 is performed, the epitaxial growth S108 may be performed in a separate growth session.

[0085] The first n-doped layer, the plurality of semiconductor layers 20 and the second n-doped layer form part of a semiconductor structure.

[0086] After epitaxial growth S102, S104, S108, one of the first and second n-doped layers is electrically connected to a source contact 60 and the other of the first and second n-doped layers is electrically connected to a drain contact 64 S110. For example, a backside contact to the substrate can be used to electrically connect the first n-doped layer. Alternatively, a trench can be etched down to the first n-doped layer and an electrical contact such as a source 60 or drain 64 contact can be placed in the trench. The second n-doped layer can be electrically connected from above. Electrically connecting the n-doped layers can include evaporating or sputtering one or more suitable metals onto the n-doped layers. Furthermore, the metal can be annealed to diffuse the metal into the n-doped layers. Thus, a high quality ohmic contact can be provided. The metal can be, for example, Ag, Au, Ti, Ni, Al, or a combination thereof. For example, Ni / Au or Ti / Al / NiV may be used.

[0087] A gate contact 62 is disposed S112 on the semiconductor structure, the gate contact 62 configured to apply an electric field to the plurality of semiconductor layers 20 such that electrical conduction between the source 10 and the drain 14 through the plurality of semiconductor layers 20 is controllable by the gate contact 62. Disposing the gate contact 62 on the semiconductor structure may include depositing an electrical insulator, e.g., an oxide, on the semiconductor structure and then depositing a metal on the insulator.

[0088] The gate contact 62 may be disposed on the semiconductor layers 20, for example, on an outer surface of the nanowire 40 that confines the semiconductor layers 20 (e.g., to form a wrap-around gate). Alternatively, the gate contact 62 may be disposed proximate to the semiconductor layers 20 such that the electric field applied from the gate is strong enough to control electrical conduction in the semiconductor layers. For example, the gate contact 62 may be disposed proximate to the semiconductor layers 20, on the second n-doped layer, or on the top surface of the semiconductor structure. The gate contact 62 may further be disposed proximate to the source contact 60 or the drain contact 64.

[0089] The transistors described above may be implemented in many different ways, as will be readily appreciated by those of skill in the art. As further guidance, note the following. It should be understood that when p-doping is described, it may refer to doping with Mg, for example from the precursor bis(cyclopentadienyl)magnesium (Cp2Mg). Doping enhancement may be seen when the semiconductor layers 20 are p-doped with Mg. However, the same enhancement mechanism may apply to other p-dopants.

[0090] It should be understood that when n-doping is described, it may refer to doping with Si, for example from the precursor SiH4. However, GaN-based materials may, at least in some circumstances, be essentially n-type. Thus, n-doped regions may not necessarily be actively doped.

[0091] The source contacts 60 and drain contacts 64 to the n-doped regions may include one or more metals. One example of such a contact is Ti / Al / NiV. Another example of such a contact is a multilayer with a contact layer of Ti or Ta, a cladding layer of Al or an aluminum-copper alloy with less than 5 wt. % copper, a barrier layer of Ni, Ti, Pt, Pd, Mo, and a cap layer of Au.

[0092] The source and drain contacts 60, 64 to the p-doped regions may include one or more metals, such as a Ni / Au bilayer or Ni / Ti / Au.

[0093] The gate contact 62 to the n-GaN may include, for example, Ti / Al / NiV, and the gate contact to the p-GaN may include a Ni / Au bilayer or Ni / Ti / Au. However, it should be understood that another conductive material may be used, for example, doped polysilicon. An electrical insulator, for example, an oxide, may separate the semiconductor structure from the metal (or other conductive material) of the gate contact. The electrical insulator may be, for example, Al2O3, HfO2, or Y2O3.

[0094] In the above, the inventive concept has been primarily described with reference to a limited number of examples. However, as will be readily appreciated by those skilled in the art, examples other than those disclosed above are equally possible within the scope of the inventive concept as defined by the appended claims.

Claims

1. A transistor (1) including a source (10), a body (12), and a drain (14), the transistor (1) comprising: The transistor further comprises a plurality of semiconductor layers (20), the layers of the plurality of semiconductor layers (20) being made of AlGaN having an aluminum content of 0% or greater, the plurality of semiconductor layers (20) being configured such that the aluminum content varies between each successive layer such that every other layer has a lower aluminum content than adjacent opposing layers of the plurality of semiconductor layers, the transistor comprising: an N-channel metal oxide semiconductor (NMOS) transistor (1'), in which some of the semiconductor layers (20) are p-doped and form part of the body (12) of the NMOS transistor (1'); or A transistor (1) is either a P-channel metal oxide semiconductor (PMOS) transistor (1''), where some of the semiconductor layers (20) are p-doped and form part of the source (10) or the drain (14) of the PMOS transistor (1'').

2. The plurality of semiconductor layers (20) includes a repeating pair of semiconductor layers, each pair of semiconductor layers having: a low Al-containing layer (22) having an Al content of less than 10%; and The transistor (1) of claim 1, comprising a high Al-containing layer (24) having an Al content greater than 15%.

3. The transistor (1) according to claim 1 or 2, wherein each layer of the plurality of semiconductor layers (20) has a thickness of between 3 nm and 10 nm.

4. The transistor (1) of claim 1, wherein the transistor (1) is configured to conduct current in a direction parallel to the layers of the plurality of semiconductor layers (20).

5. The transistor (1) of claim 1, wherein the transistor (1) is configured to conduct current in a direction perpendicular to the layers of the plurality of semiconductor layers (20).

6. The transistor (1) of claim 5, wherein a nanowire (40) confines at least a portion of the body (12) of the transistor (1).

7. 7. The transistor (1) of claim 6, wherein a gate contact (62) wraps around the nanowire (40) enclosing at least a portion of the body (12) of the transistor (1), such that the gate contact (62) forms a wrap-around gate (42).

8. The transistor (1) of claim 6, wherein the nanowire (40) confining at least a portion of the body (12) of the transistor (1) also confining at least a portion of the source (10) and the drain (14) of the transistor (1).

9. The transistor (1) of claim 1, wherein the source (10), the drain (14), and the body (12) of the transistor (1) all comprise the plurality of semiconductor layers (20).

10. The transistor (1) is an NMOS transistor (1′), The source (10) comprises an n-doped GaN layer (30); The transistor (1) of claim 1, wherein the drain (14) comprises an n-doped GaN layer (30).

11. An electrical device (50), at least one N-channel metal oxide semiconductor (NMOS) transistor (1'), the at least one NMOS transistor (1') comprising a plurality of semiconductor layers (20), each layer of the plurality of NMOS semiconductor layers (20) of the NMOS transistor (1') being made of AlGaN having an aluminum content equal to or greater than 0%, the plurality of NMOS semiconductor layers (20) of the NMOS transistor (1') being configured such that the aluminum content varies between each successive layer such that every other layer has a lower aluminum content than adjacent opposing layers of the layer, the plurality of NMOS semiconductor layers (20) of the NMOS transistor (1') forming a portion of a p-doped body (12) of the NMOS transistor (1'); at least one P-channel metal oxide semiconductor (PMOS) transistor (1'), the at least one PMOS transistor (1') comprising a plurality of PMOS semiconductor layers (20), each layer of the plurality of PMOS semiconductor layers (20) of the PMOS transistor (1') being made of AlGaN having an aluminum content equal to or greater than 0%, the plurality of PMOS semiconductor layers (20) of the PMOS transistor (1') being configured such that the aluminum content varies between each successive layer such that every other layer has a lower aluminum content than adjacent opposing layers of the layer, the plurality of PMOS semiconductor layers (20) of the PMOS transistor (1') forming a portion of a p-doped source (10) or drain (14) of the PMOS transistor (1'); The at least one NMOS transistor (1') and the at least one PMOS transistor (1'') of the electrical device (50) are connected to form a complementary metal-oxide semiconductor (CMOS) circuit (52).

12. 12. The electrical device (50) of claim 11, wherein the at least one NMOS transistor (1') and the at least one PMOS transistor (1'') of the CMOS circuit (52) share the same plurality of semiconductor layers (20).

13. The electrical device (50) of claim 11 or 12, wherein at least one of the at least one PMOS transistor (1'') and / or at least one of the at least one NMOS transistor (1') of the CMOS circuit (52) of the electrical device (50) is a transistor according to claim 2.

14. A method (100) for producing a transistor, the method (100) comprising: epitaxially growing (S102) a first n-doped layer of AlGaN having an aluminum content of 0% or greater; epitaxially growing (S104) a plurality of semiconductor layers (20), the plurality of semiconductor layers (20) being grown on the first n-doped layer, each layer of the plurality of semiconductor layers (20) being made of AlGaN having an aluminum content equal to or greater than 0%, the plurality of semiconductor layers (20) being configured such that the aluminum content varies between each successive layer such that every other layer has a lower aluminum content than adjacent opposing layers of the plurality of semiconductor layers, the plurality of semiconductor layers (20) being grown p-doped; and epitaxially growing (S108) a second n-doped layer of AlGaN having an aluminum content of 0% or greater, the second n-doped layer being grown on the plurality of semiconductor layers (20), whereby the first n-doped layer, the plurality of semiconductor layers (20), and the second n-doped layer form part of a semiconductor structure, the method (100) comprising: electrically connecting (S110) one of the first and second n-doped layers to a source contact (60) and the other of the first and second n-doped layers to a drain contact (64), whereby a transistor source (10) and a transistor drain (14) are formed by the first and second n-doped layers; The method (100) further includes disposing (S112) a gate contact (62) on the semiconductor structure, the gate contact (62) configured to apply an electric field to the plurality of semiconductor layers (20) such that electrical conduction between the transistor source (10) and the transistor drain (14) through the plurality of semiconductor layers (20) is controllable by the gate contact (62), whereby a transistor body (12) is formed by the plurality of semiconductor layers (20).

15. The method (100) of claim 14, further comprising etching (S106) nanowires (40) from the plurality of semiconductor layers (20).

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