Sandwich-type multilayer structures for cooling high-power electronics

Abstract

The systems, methods, and devices disclosed herein relate to a sandwich-type multi-layer structure for cooling electronic devices. In some embodiments, a computing assembly can include a first cooling system, a first electronics layer, a second cooling system, and a second electronics layer. The first cooling system can be disposed on top of and in thermal communication with the first electronics layer, the first electronics layer can be disposed on top of and in thermal communication with the second cooling system, and the second cooling system can be disposed on top of and in thermal communication with the second electronics layer. In some embodiments, at least one layer can use system-on-wafer packaging.

Description

[Technical field]

[0001] [CROSS REFERENCE TO RELATED APPLICATIONS] This application claims the benefit of U.S. Provisional Application No. 63 / 234602, filed August 18, 2021, entitled "A SANDWICHED MULTI-LAYER STRUCTURE FOR COOLING HIGH POWER ELECTRONICS," the disclosure of which is incorporated by reference in its entirety and for all purposes.

[0002] The present disclosure relates to electronic assemblies, and more particularly, to cooling of electronic assemblies. [Background technology]

[0003] High performance computing systems are important for many applications, but traditional computing system designs suffer from significant cooling challenges and inefficient space utilization, which can lead to reduced performance and increased physical space requirements.

[0004] High-performance computing fields such as artificial intelligence, machine learning, and data mining can benefit from high compute density. For example, placing computing dies close to each other can reduce the physical space occupied for a given computing capacity, and can also improve communication bandwidth and latency between dies. Packaging techniques such as System on Wafer (SoW) have made it possible to build ultra-dense computing systems with almost no area between dies. While such packaging methods can greatly increase compute density, they also pose significant challenges. When dies are placed very close together, a large amount of power can be dissipated in a relatively small area, and cooling the dies and other nearby components can pose significant challenges.

[0005] As electronic systems improve in performance and electronic components shrink in size, significant amounts of heat can be generated in smaller volumes. Furthermore, in applications such as high-density neural network training systems and other large-scale distributed computing applications, performance can be improved by placing computing nodes physically closer to each other. Some conventional systems operate with cooling solutions that are single-sided (e.g., cooled only from the top or only from the bottom) and occupy a much larger area than the electronic device to be cooled, but some high-performance, high-density systems do not work well with such an approach. For example, a typical central processing unit (CPU) cooler in a desktop computer or server may occupy an area tens or hundreds of times the CPU die to provide adequate cooling, but when the dies are placed adjacent to each other with little space between them, there is insufficient area available for such a solution. Summary of the Invention

[0006] Each of the claimed innovations has several aspects, none of which is solely responsible for its desirable properties. Without limiting the scope of the claims, some of the more prominent features of the disclosure will now be discussed briefly.

[0007] In some aspects, the technology described herein relates to a computing assembly including a first cooling system, a first electronics layer having a first surface and a second surface, the first surface in thermal communication with the first cooling system, a second cooling system in thermal communication with the second surface of the first electronics layer, and a second electronics layer having a third surface and a fourth surface, the third surface in thermal communication with the second cooling system.

[0008] In some aspects, the technology described herein relates to a computing assembly, where a first cooling system is disposed on top of a first electronics layer, the first electronics layer is disposed on top of a second cooling system, and the second cooling system is disposed on top of the second electronics layer.

[0009] In some aspects, the technology described herein relates to a computing assembly, the computing assembly further including a third electronics layer having a third cooling system and a fifth surface and a sixth surface, the fifth surface being in thermal communication with the third cooling system, and the fourth surface being in thermal communication with the third cooling system.

[0010] In some aspects, the technology described herein relates to a computing assembly, where a first electronics layer is in electrical communication with a second electronics layer.

[0011] In some aspects, the technology described herein relates to a computing assembly, wherein the first electronics layer comprises a system-on-wafer layer.

[0012] In some aspects, the technology described herein relates to a computing assembly, where a first electronics layer includes an array of integrated circuit dies and a second electronics layer includes an array of power supply modules.

[0013] In some aspects, the technology described herein relates to a computing assembly, in which each power supply module of an array of power supply modules includes a voltage regulation module.

[0014] In some aspects, the technology described herein relates to a computing assembly, wherein the number of integrated circuit dies in a first electronics tier equals the number of power supply modules in a second electronics tier, and each integrated circuit die is in electrical communication with only one power supply module.

[0015] In some aspects, the technology described herein relates to a computing assembly in which power is delivered vertically from a second electronics layer to a first electronics layer, and integrated circuit dies of an array of integrated circuit dies are in electronic communication with each other in a plane orthogonal to the power supply.

[0016] In some aspects, the technology described herein relates to a computing assembly, where a first type of cooling system and a second type of cooling system include one or more of a cold plate, a heat sink, and a liquid cooling block.

[0017] In some aspects, the technology described herein relates to a computing assembly, wherein a first cooling system of the type described above is the same as a second cooling system of the type described above.

[0018] In some aspects, the technology described herein relates to a computing assembly, wherein a first cooling system of the type described above is different from a second cooling system of the type described above.

[0019] In some aspects, the technology described herein relates to a computing assembly, where a first cooling system includes a first liquid cooling block and a second cooling system includes a second liquid cooling block.

[0020] In some aspects, the technology described herein relates to a computing assembly, where a first liquid cooling block is configured to receive a first coolant and a second liquid cooling block is configured to receive a second coolant.

[0021] In some aspects, the technology described herein relates to a computing assembly, wherein the first coolant and the second coolant comprise one or more of water, propylene glycol, ethylene glycol, or combinations thereof.

[0022] In some aspects, the technology described herein relates to a computing assembly, wherein the first coolant is the same as the second coolant.

[0023] In some aspects, the technology described herein relates to a computing assembly, wherein the first coolant is different from the second coolant.

[0024] In some aspects, the technology described herein relates to a method of cooling an electronic assembly, the method including attaching a first cooling layer on top of and in thermal communication with a first electronics layer, attaching the first electronics layer on top of and in thermal communication with a second cooling system, and attaching the second cooling system on top of and in thermal communication with the second electronics layer.

[0025] In some aspects, the technology described herein relates to a method, the method further including outputting heat vertically from a first electronics layer to a first cooling system, outputting heat vertically from the first electronics layer to a second cooling system, and outputting heat vertically from the second electronics layer to a second cooling system.

[0026] In some aspects, the technology described herein relates to a method, the method further comprising delivering power vertically from the second electronics layer to the first electronics layer.

[0027] In some aspects, the technology described herein relates to a computing assembly including a first cooling system, a first electronics layer in thermal communication with the first cooling system, a second cooling system in thermal communication with the first electronics layer, a second electronics layer in thermal communication with the second cooling system, a third cooling system in thermal communication with the second electronics layer, and a third electronics layer in thermal communication with the third cooling system, wherein the first electronics layer includes a processing electronics layer, the second electronics layer includes a power supply layer, and the third electronics layer includes a control electronics layer. [Brief description of the drawings]

[0028] The present disclosure is described herein with reference to drawings of certain embodiments that are intended to be illustrative and not limiting of the disclosure. It is to be understood that the accompanying drawings, which are incorporated in and constitute a part of this specification, are for the purpose of illustrating the concepts disclosed herein and may not be to scale.

[0029] [Figure 1] FIG. 1 is a schematic diagram showing an example integrated circuit die array, as well as power, cooling and control signals running perpendicular to the computational load and signaling.

[0030] [Diagram 2] FIG. 1 is a block diagram illustrating an example of a prior art single sided cooling system with a single cooling system on top of an electronics layer.

[0031] [Diagram 3] FIG. 1 is a block diagram illustrating an example of a prior art double-sided cooling system with a cooling system between two electronics layers, according to one embodiment.

[0032] [Figure 4]FIG. 2 is a block diagram illustrating an example embodiment of a vertical cooling solution with two cooling systems and two electronics layers, according to one embodiment.

[0033] [Diagram 5] FIG. 2 is a block diagram illustrating another example embodiment of a vertical cooling solution with two cooling systems and three electronics layers, according to one embodiment.

[0034] [Figure 6] FIG. 2 is a block diagram illustrating another example embodiment of a vertical cooling solution with three cooling systems and three electronics layers, according to one embodiment.

[0035] [Figure 7A] FIG. 1 is a perspective exploded view of a computing assembly including a system-on-wafer according to one embodiment.

[0036] [Figure 7B] FIG. 1 is an exploded block diagram of a computing assembly showing cooling inlets and outlets according to one embodiment.

[0037] [Figure 7C] FIG. 7B is an assembled block diagram of the system shown in FIG. 7A including a system-on-wafer layer according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0038] The following description of certain embodiments provides various descriptions of the specific embodiments. However, the innovations described herein may be embodied in many different ways, for example, as defined and covered by the claims. In this description, reference is made to the drawings, where like reference numbers may indicate identical or functionally similar elements. It will be understood that the elements illustrated in the drawings are not necessarily drawn to scale. It will further be understood that a particular embodiment may include more elements than are illustrated in the drawings and / or a subset of the elements illustrated in the drawings. Furthermore, some embodiments may incorporate any suitable combination of features from two or more drawings.

[0039] When the computing dies are in close proximity, it may be advantageous to configure the system such that some components are arranged vertically. For example, power supplies, control circuits, etc. may be located under the die, power and cooling may be delivered vertically, and signals and computational loads may move horizontally from die to die in the array. In some cases, the array of dies and associated power, control, and cooling hardware may be assembled into a computing assembly, and the computing assemblies may be located near (e.g., next to) each other with little space between them. In some embodiments, the computing assemblies may be configured with high-speed communication interfaces so that the computing assemblies can communicate with each other. Thus, on the other hand, in traditional computing systems where density is not a primary concern or there may be only one or a few CPU dies, horizontal power supplies and / or cooling solutions with large horizontal areas may be feasible. However, in high density environments, such as when using SoW or other high density packaging techniques, there may not be horizontal space to route power, clock signals, etc. horizontally. The limited horizontal space can be used to enable communication between nodes in the array.

[0040] This disclosure describes a cooling architecture that allows for multiple levels of single-sided and double-sided cooling solutions to be used between high power electronic components. Using the cooling solutions described herein, high density cooling structures can be manufactured that allow for cooling of multiple electronic systems within a compact structure. Such structures are effective in increasing computational density. In some embodiments, placing electronic components on both sides of the cooling structure can help increase density and reduce packaging volume.

[0041] In some embodiments, the structure may include a heterogeneous combination of cooling solutions. For example, the cooling structure may include a combination of liquid-cooled components, air-cooled components, immersion cooling, etc. In some embodiments, different coolants may be used. For example, some components may be liquid-cooled with water, while other components may be liquid-cooled with oil, propylene glycol, etc. The particular cooling components, coolants, etc. may be based on the cooling needs of the various components. For example, the voltage regulator module may withstand temperatures substantially exceeding the thermal limits of the computing die, and thus, in some embodiments, may be cooled by a cooling component having a lower cooling capacity than the cooling component used to cool the die.

[0042] In some embodiments, the cooling structures described herein can be used to cool system-on-wafer (SoW) systems, which may include multiple processors or processor dies arranged in close physical proximity on a single substrate. These cooling structures for SoW systems can include sandwich-type structures that can provide efficient double-sided cooling for high-power SoW layers. In some embodiments, the cooling structures can include one or more components that provide mechanical support to the SOW layer and can further enhance the mechanical integrity of the SoW layer.

[0043] In some embodiments, the cooling structures described herein allow for cross-flow of heat and information, for example, power and heat can flow from bottom to top and / or top to bottom, and information and computational workloads can flow in a horizontal plane orthogonal to the heat and power.

[0044] 1 illustrates an example array 100. The array 100 may include multiple integrated circuit (IC) dies 102. The dies 102 may receive power and / or control signals vertically. The dies 102 may be cooled vertically. The dies 102 may communicate with each other via horizontal communication links. For example, an SoW layer may include one or more routing layers, e.g., 4, 5, 6, 8, 10 routing layers. The routing layers may provide signal connections between the IC dies 102 within the SoW layer and / or to external components.

[0045] In some embodiments, the SoW layer can include an array of IC dies disposed on a wafer. In some embodiments, the IC dies can include sensor dies, memory dies, application specific integrated circuits (ASIC) dies, central processing units (CPU) dies, graphic processing units (GPU) dies, field programmable gate array (FPGA) dies, and / or microelectromechanical systems (MEMS) dies. In some embodiments, the IC dies can communicate with each other within the SoW through redistribution layers (RDLs) formed therein. The RDL layers and / or other electrical connections with the SoW can beneficially provide, for example, relatively low communication latency between the IC dies, relatively high bandwidth density, and / or relatively low power distribution network (PDN) impedance.

[0046] It should also be understood that each array 100 may include connections for communicating between multiple SoW arrays in a larger system. For example, array 100 may be part of a system including 4, 8, 12, 16 or more SoW arrays, each communicating with each other through connectors located in the same or a similar plane as the SoW array.

[0047] FIG. 2 illustrates an exemplary prior art single-sided cooling system 200. The cooling system 201 may be attached on top of the electronics layer 202. A thermal interface material (TIM) may be disposed between the cooling system 201 and the electronics layer 202 to facilitate heat transfer. The TIM may be, for example, a thermal pad, a thermal adhesive, a thermal pad, or the like. The electronics layer 202 may include, for example, a printed circuit board (PCB) with various integrated circuits or other components attached (e.g., soldered) to the PCB. All or a portion of the ICs and / or other components may be in thermal contact with the cooling system 201. The cooling system 201 may be any type of cooling solution, such as a heat sink, a cold plate, a vapor chamber, a liquid cooling block, or the like. The cooling solution may be active or passive. In some cases, a fan may be used to dissipate heat from the electronics layer 202.

[0048] FIG. 3 is an exemplary prior art showing a double-sided cooling system 300. As seen in FIG. 3, density can be improved by placing electronics in thermal communication with both sides (e.g., top and bottom) of the cooling solution. As seen in FIG. 3, electronics layer 301 and electronics layer 302 are placed on opposite sides of and in thermal communication with cooling system 303. If cooling system 303 has enough thermal capacity to cool both electronics layer 301 and electronics layer 302, such a configuration can save space by avoiding the use of a second cooling solution.

[0049] As briefly discussed above, high density computing presents challenges with cooling, power delivery, signaling, etc. By stacking components vertically, density can be increased. Effectively cooling a vertical stack of components presents several challenges. For example, some components have more or less heat output than other components, some components are hotter or colder than other components, etc. As described herein, some embodiments of cooling solutions can take into account the differences in cooling requirements of different components in order to efficiently cool vertically stacked components.

[0050] In some embodiments, a high density computing system can include an SoW assembly having multiple cooling systems disposed beneath and on top of, coupled with, or between electronics layers for efficient double-sided cooling of heat generating electronic devices. Such an architecture not only provides efficient cooling for the SoW layer and / or other electronics layers, but can also provide enhanced mechanical support to enhance the mechanical integrity of the fragile SoW layer.

[0051] The SoW assembly can include a SoW layer and a cooling system integrated or sandwiched within the SoW assembly. The SoW assembly can include an array of IC dies. The IC dies of the SoW assembly can generate significant heat during operation. The cooling system can dissipate heat generated within the SoW assembly by the IC dies and / or other electronic components within the SoW assembly.

[0052] Some embodiments herein relate to an SoW assembly that includes an integrated cooling system or structure that provides efficient thermal management of heat-generating components within the SoW assembly. In some embodiments, the SoW assembly may include multiple different cooling systems, for example, three cooling systems, although more or fewer cooling systems are contemplated.

[0053] The systems and methods described herein can be used in computationally dense processing systems to dissipate heat generated by the processing systems. In some embodiments, in certain applications, the processing systems can perform trillions of operations per second. In some embodiments, the processing systems can be used and / or specially configured for high performance computing and computationally intensive applications, such as neural network processing, machine learning, artificial intelligence, etc. In some embodiments, the processing systems can incorporate redundancy. For example, the processing systems can include redundant dies, redundant power supplies, redundant storage, or other failover mechanisms that can be used to minimize operational interruptions. In some embodiments, the processing systems can be used in vehicle (e.g., automobile) autopilot systems, implementing other autonomous vehicle functions, implementing advanced driver assistance systems (ADAS) functions, etc.

[0054] In some embodiments, the coolers and electronic components can be stacked alternately to form a vertical structure. In some embodiments, a thermal interface material can be disposed between the electronic layers and the cooler to facilitate heat transfer from the electronic components to the cooler. As previously discussed, the TIM can be thermal paste, thermal adhesive, thermal pad, or other suitable material. In some embodiments, the components can be cooled from one side (e.g., top or bottom) or from both sides (e.g., top and bottom). In some embodiments, the cooler can have components on one side (e.g., top or bottom) or both sides. In some embodiments, an electronics layer can be adjacent to another electronics layer without an intervening cooling system. In some embodiments, a cooling system can be adjacent to another cooling system without an intervening electronics layer.

[0055] In some embodiments, all coolers in a stack may be the same, but this is not necessary. For example, electronic components that require higher cooling can be cooled by coolers with higher heat dissipation capabilities (e.g., liquid cooling), while some of the other components that can operate at higher temperatures and / or generate less heat can be cooled by components with lower cooling capabilities, such as cold plates, heat sinks, or vapor chambers. In some embodiments, one or more of the electronics layers can be cooled using immersion cooling, e.g., immersion in a hydrocarbon or fluorocarbon based fluid.

[0056] In some embodiments, different liquid cooling blocks in a stack can use different coolants. For example, the liquid cooling blocks can use water, propylene glycol, ethylene glycol, mineral oil, refrigerant, isopropyl alcohol, ethanol, methanol, glycerin, and / or mixtures of the above, such as a 1:1 mixture of propylene glycol and water, or ethylene glycol and water, or other ratios deemed desirable for cooling. In some embodiments, the cooling liquid can include an amount of antimicrobial and / or anticorrosive compounds to prevent microbial growth and / or corrosion of the cooling components.

[0057] In some embodiments, when a system includes multiple liquid chillers, they may share some common components, such as a reservoir, a radiator, and / or a pump, etc. In some embodiments, different liquid chillers may not share common components.

[0058] Stacked structures can present special cooling challenges. For example, inlets and outlets for liquid cooling may be difficult to access and configuration room may be limited due to lack of space to route pipes, hoses, etc. on the sides of the cooling solution, especially when stacked structures are placed next to each other. Thus, the inlets and outlets are preferably configured to supply and return coolant vertically. In some embodiments, the size (i.e., horizontal dimension) of layers in a vertical stack may vary from layer to layer. In some embodiments, the horizontal size of a layer may be limited due to cooling lines for other layers, space occupied by electrical connectors to connect one computing assembly to an adjacent computing assembly, etc.

[0059] In some embodiments, the cooling solution can include one or more fans. For example, the cooling solution can include one or more fans disposed at the top and / or bottom of the vertical stack. In some embodiments, one or more fans may be disposed within the vertical stack. In some embodiments, the vertical stack can be installed in a housing or chassis (e.g., a computer enclosure, a rack mount enclosure, etc.), which can include one or more fans.

[0060] As briefly mentioned above, different cooling solutions can be provided for the various layers, such as type of cooler, single-sided or double-sided cooling, etc. The type of cooler and / or coolant can be selected based at least in part on the component, the computational load, the relative location of the component in the vertical stack, the location of the component in the enclosure or chassis, adjacent components (e.g., adjacent computing assemblies, storage, controllers, etc.), etc. Some components, such as voltage regulator modules (VRMs), can operate at relatively high temperatures (e.g., up to about 125° C., up to about 110° C., up to about 90° C., etc., or any temperature between these temperatures, or even higher depending on the characteristics of the component), while other components (e.g., IC dies) have a relatively lower maximum operating temperature or may be cooled more, for example, to operate more efficiently and consume less power. For example, an IC die may have a maximum operating temperature of about 105° C., about 95° C., about 85° C., or more or less, depending on the characteristics of the IC die (e.g., a die made according to one manufacturing process may be capable of operating in a different temperature range than a die made by another process). Similarly, other components in the stack, such as control circuitry, may have maximum operating temperatures or other constraints on operating temperatures.

[0061] In some embodiments, the cooling systems described herein may include materials with relatively high coefficients of thermal expansion (CTE). For example, the cooling system may include copper (Cu) and / or aluminum (Al). In some embodiments, the cooling system may include materials with CTEs ranging from about 10 ppm / °C to about 20 ppm / °C. For example, the cooling system may include copper with a CTE of about 17 ppm / °C. In some embodiments, the SoW layer may include a silicon (Si) wafer. In some embodiments, the SoW layer may include materials with CTEs ranging from about 1 ppm / °C to about 10 ppm / °C. For example, the CTE of silicon may be about 2.6 ppm / °C. In some embodiments, the CTE of the cooling system is about 2 to about 7 times higher than the CTE of the SoW layer.

[0062] Thermal stresses that may arise, at least in part, due to different thermal expansion coefficients of components in a stack, may predispose the components to premature failure. It is therefore important to ensure that the components are kept in a temperature range that avoids excessive stress due to non-uniform thermal expansion coefficients. In some embodiments, careful alignment of the components in the stack can reduce the effects of thermal stresses. For example, a cooler can be centrally located with respect to the IC die such that stress on the die is uniform (e.g., substantially uniform).

[0063] To obtain desirable heat dissipation and / or mitigate potential thermal stress issues, it may be beneficial to align the SoW layer and the cooling system with a relatively high degree of precision. For example, it may be beneficial to align the SoW layer and the cooling system such that a reference point (e.g., a center point) of the SoW layer coincides with a reference point (e.g., a center point) of the cooling system. In some embodiments, there may be multiple alignment markers that can be used to align the SoW layer and the cooling system.

[0064] In some embodiments, various electronic components in the vertical stack may include temperature sensors. For example, an IC die may have one or more temperature sensors, power delivery hardware such as a VRM may have one or more temperature sensors, and control circuitry may have one or more temperature sensors. In some embodiments, temperature data from multiple sensors may be aggregated at various levels. In some embodiments, the aggregated data may be used to adjust cooling, such as changing fan speed, increasing or decreasing coolant flow rate, etc. In some embodiments, all temperature sensors on a particular IC die may be aggregated. In some embodiments, all temperature sensors on all IC dies of an SoW layer may be aggregated. In some embodiments, all temperature sensors on power delivery components may be aggregated. In some embodiments, all temperature sensors in a computing assembly may be aggregated. In some embodiments, all temperature sensors in a larger cabinet or structure that includes multiple computing assemblies may be aggregated.

[0065] The desired level of aggregation may depend on the particular cooling implementation. For example, a lower level of aggregation may be desirable if different cooling systems, different computing assemblies, etc. can be cooled independently, whereas a higher level of aggregation may be desirable if cooling is controlled at a higher level, e.g., per computing assembly or per cabinet. In some embodiments, a low level of aggregation may be desirable even if only a high level of cooling control is possible. For example, in some embodiments, an IC die may be particularly sensitive to temperature, while other components may be relatively resilient. Thus, it may be advantageous to monitor the temperature of the IC die without aggregating it with other temperature data and / or by evaluating the temperature of the IC die higher than the temperatures of other components.

[0066] In some embodiments, the cooling can be adjusted by adjusting the opening of mechanical valves, adjusting the speed of mechanical fans, etc. Such adjustments can take a significant amount of time, during which the IC die and other components may continue to heat up. Thus, in some embodiments, the system can be configured to predict future thermal demands, e.g., based on computational load, ambient temperature, etc., and can also adjust the cooling based on the predicted thermal demands, thereby preventing components from overheating.

[0067] FIG. 4 illustrates an exemplary vertical cooling solution 400 according to some implementations. As seen in FIG. 4, the cooling system 401 can be disposed on top of a double-sided electronics layer 402. The double-sided electronics layer can be disposed on top of the cooling system 403. The cooling system 403 can be disposed on top of an electronics layer 404. As shown in FIG. 4, the cooling system 401 can be single-sided, i.e., there is an electronics layer 402 in contact with the bottom surface of the cooling system 401, but no electronics layer in contact with the top surface of the cooling system 401. On the other hand, the cooling system 403 can be double-sided, i.e., the cooling system 403 is thermally coupled to the electronics layer 402 on the top side and the electronics layer 404 on the bottom side of the cooling system 403. The electronic device components can be single-sided or double-sided. For example, the electronics layer 402 is double-sided, with electronic components disposed on both sides of the substrate (e.g., PCB, wafer, etc.). The electronics layer 404 is single-sided, with electronic components located only on the top surface of the substrate.

[0068] FIG. 5 illustrates another example vertical cooling solution 500 according to some implementations. FIG. 5 is substantially similar to FIG. 4, but with the addition of an electronics layer 501. The electronics layer 501 is a single-sided electronics layer disposed on top of a double-sided cooling system 502. The cooling system 502 is disposed on top of a double-sided electronics layer 503. The electronics layer 503 is disposed on top of a double-sided cooling system 504, which is disposed on top of a single-sided electronics layer 505. The layers illustrated in FIG. 5 can be in direct thermal communication with adjacent layers. The layers illustrated in FIG. 5 can be in indirect thermal communication with non-adjacent layers.

[0069] 6 illustrates another example embodiment of a vertical cooling solution 600. As seen in FIG. 6, a cooling system 601 can be thermally coupled to an electronics layer 602 on one side. The electronics layer 602 can also be in thermal contact with a cooling system 603 on both sides. A bottom side of the cooling system 603 can be thermally coupled to a top surface of a double-sided electronics layer 604. A bottom side of the electronics layer 604 can be thermally coupled to a cooling system 605. A bottom surface of the cooling system 605 can be in thermal communication with a single-sided electronics layer 606.

[0070] 4-6 depict coolers disposed on both sides of an electronics layer having electronic components disposed on both sides, other configurations are possible. For example, a double-sided electronics layer may be provided with cooling on only one side, e.g., because the components on the other side generate enough heat and / or can withstand high enough temperatures that they can operate without cooling and / or with indirect cooling provided by a cooling system on the other side of the electronics layer. In some embodiments, a single-sided electronics layer may be provided with cooling on both sides. Such a configuration may be desirable, for example, when components in the electronics layer generate particularly large amounts of heat or act as a heat shield to protect more sensitive components in other layers of the stack.

[0071] In some embodiments, the electronics layer may include a PCB with components disposed thereon. However, other configurations are possible. For example, as described above, the electronics layer may be an SoW layer. The SoW layer may have multiple IC dies disposed adjacent to one another. For example, the SoW layer may be fabricated from a 300 mm wafer and have multiple IC dies disposed thereon (e.g., an array of 4 dies, 9 dies, 16 dies, 25 dies, 36 dies, 49 dies, etc., or an array of other IC dies that may or may not be a square array). Typically, current SoW layers are fabricated from 300 mm wafers, but the systems, methods, and devices disclosed herein may also be applied to larger or smaller wafers, e.g., 200 mm, 450 mm, etc.

[0072] 7A, 7B, and 7C illustrate an example computing assembly 700 including an SoW layer according to some embodiments. The assembly can include a top cold plate 701 thermally coupled to an SoW layer 702. The SoW layer 702 can have a number of IC dies 703 disposed therein. Below the IC dies 703, the assembly can have a number of power supply modules 704. Each IC die can have an associated power supply module and can be electrically connected to the associated power supply module. A bottom cold plate 705 can be thermally coupled to the power supply modules. Additionally, the bottom cold plate 705 can also be thermally coupled to a control board 706 that can be used to provide signaling and control functions to the IC dies. The control board can be in thermal contact with a heat sink 707. Below the heat sink 707, additional electronics 708 can be disposed.

[0073] The top cold plate 701 can have an inlet 709 for allowing liquid coolant to enter the top cold plate 701 and an outlet 710 for removing heated liquid coolant from the top cold plate 701. The bottom cold plate can have a cooling inlet 711 for receiving liquid contents and a coolant outlet 712 for removing coolant from the bottom cold plate 705. The SoW layer 702 can have a communication interface 713 located at an edge of the SoW layer 702. The communication interface 713 can be used to connect the SoW layer 702 to adjacent SoW layers of other assemblies.

[0074] 7C is an assembled view of the disassembled assembly shown in FIG. 7B. When assembled, the computing assembly can have a vertical height H of about 1 inch to about 5 inches, such as about 1 inch, about 2 inches, about 3 inches, about 4 inches, about 5 inches, or any value between these values. The number of layers in the vertical stack is not necessarily limited. Thus, the height of the vertical stack is not necessarily limited.

[0075] In some embodiments, rigidity and mechanical strength may be obtained from a cooling system. In some embodiments, mechanical reinforcement may alternatively or additionally be provided by a support layer, such as support layer 714 shown in FIG. 7A. Support layer 714 may be a structure made of a rigid material, such as metal, plastic, ceramic, or the like.

[0076] In the foregoing specification, the system and process have been described with reference to specific embodiments thereof. It will be apparent, however, that various modifications and changes may be made thereto without departing from the broader spirit and scope of the embodiments disclosed herein. The specification and drawings are therefore to be regarded in an illustrative rather than a restrictive sense.

[0077] Indeed, while the systems and processes have been disclosed in the context of certain embodiments and examples, those skilled in the art will appreciate that the various embodiments of the systems and processes extend beyond the specifically disclosed embodiments to other alternative embodiments and / or uses of the systems and processes, as well as obvious modifications and equivalents thereof. Moreover, while several variations on the system and process embodiments have been shown and described in detail, other modifications within the scope of the present disclosure will be readily apparent to those skilled in the art based on the present disclosure. It is also contemplated that various combinations or subcombinations of specific features and aspects of the embodiments may be made and still fall within the scope of the present disclosure. It should be understood that various features and aspects of the disclosed embodiments may be combined with or substituted for one another to form various modes of embodiments of the disclosed systems and processes. The methods disclosed herein need not be performed in the order described. Thus, it is intended that the scope of the systems and processes disclosed herein should not be limited by the specific embodiments described above.

[0078] It will be understood that the systems and methods of the present disclosure each have several innovative aspects, none of which function alone or are required for the desired properties disclosed herein. The various features and processes described above may be used independently of one another or may be combined in various ways. All contemplated combinations and subcombinations are intended to be within the scope of the present disclosure.

[0079] Certain features that are described herein in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as operating in certain combinations and may initially be claimed as such, in some cases one or more features may be excluded from the claimed combination, and the claimed combination may be directed to a subcombination or variation of the subcombination. No feature or group of features is required or essential for all embodiments.

[0080] Additionally, it will be understood that conditional language such as "can," "could," "might," "may," "for example," and the like, as used herein, unless otherwise specified or understood within the context of use, is generally intended to convey that a particular embodiment includes certain features, elements, and / or steps, and other embodiments do not include them. Thus, such conditional language does not generally imply that features, elements, and / or steps are in any way required by one or more embodiments, or that one or more embodiments necessarily include logic that determines, with or without author input or direction, whether those features, elements, and / or steps are included or performed in any particular embodiment. Words such as "comprising," "including," "having," and the like, are synonymous and are used in an inclusive, non-limiting manner and do not exclude additional elements, features, acts, operations, etc. Additionally, the term "or" is used in an inclusive (rather than exclusive) sense, so that, for example, when used to join a list of elements, the term "or" means one, some, or all of the elements in the list. Additionally, the articles "a," "an," and "the" as used in this application and the appended claims are to be construed to mean "one or more" or "at least one," unless otherwise specified. Similarly, although operations may be depicted in the figures in a particular order, it is understood that such operations need not be performed in the particular order depicted, or in sequential order, or that all of the depicted operations need not be performed to achieve desirable results. Additionally, the figures may generally depict one or more exemplary processes in the form of a flow diagram. However, other operations not depicted may be incorporated into the generally depicted exemplary methods and processes. For example, one or more additional operations may be performed before, after, simultaneously with, or during the depicted operations.Moreover, in other embodiments, operations may be rearranged or reordered. In some situations, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems may generally be integrated together in a single software product or packaged in multiple software products. Moreover, other embodiments are within the scope of the following claims. In some cases, desirable results can be obtained even when the actions recited in the claims are performed in a different order.

[0081] Furthermore, the methods and devices described herein are susceptible to various modifications and alternatives, specific examples of which are shown in the drawings and described in detail herein. However, it should be understood that the embodiments are not limited to the specific forms or methods disclosed, but rather, the embodiments are intended to cover all modifications, equivalents, and alternatives within the spirit and scope of the various implementations described and the appended claims. Furthermore, the disclosure herein of specific features, aspects, methods, properties, characteristics, qualities, attributes, elements, etc. associated with an implementation or embodiment can be used in all other implementations or embodiments defined herein. The methods disclosed herein do not have to be performed in the order described. Although the methods disclosed herein may include certain operations performed by the practitioner, the methods may also include, explicitly or implicitly, any third-party instructions for these operations. The scope disclosed herein also covers all overlaps, subranges, and combinations thereof. Words such as "up to," "at least," "greater than," "less than," "between," and the like, are inclusive of the referenced figure. Figures preceded by words such as "about" or "approximately" are inclusive of the referenced figure and are to be interpreted in the context (e.g., to the maximum extent reasonably possible under the circumstances, e.g., ±5%, ±10%, ±15%). For example, "about 3.5 mm" includes "3.5 mm". Words preceded by words such as "substantially" are inclusive of the referenced figure and are to be interpreted in the context (e.g., to the maximum extent reasonably possible under the circumstances). For example, "substantially constant" includes "constant". Unless otherwise specified, all measurements are conducted under standard conditions, including temperature and pressure.

[0082] As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items, including single members. As an example, "at least one of A, B, C" is intended to include A, B, C, A and B, A and C, B and C, and A, B, and C. Unless otherwise specified, conjunctions such as "at least one of X, Y, Z" are intended to be understood in context as they are generally used to convey that an item, term, etc. may be at least one of X, Y, Z. Thus, such conjunctions do not generally imply that a particular embodiment requires that at least one of X, at least one of Y, and at least one of Z, respectively, be present. Headings, if provided herein, are for convenience only and do not necessarily affect the scope or meaning of the devices and methods disclosed herein.

[0083] Thus, the scope of the claims is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the present disclosure, the principles and novel features disclosed herein.

Claims

1. 1. A computing assembly comprising: a first cooling system; a first electronics layer having a first surface and a second surface, the first surface in thermal communication with the first cooling system; a second cooling system in thermal communication with the second surface of the first electronics layer; a second electronics stratum having a third surface and a fourth surface, the third surface in thermal communication with the second cooling system; Equipped with the first cooling system type and the second cooling system type include one or more of a cold plate, a heat sink, and a liquid cooled block; A computing assembly, wherein the type of the first cooling system is different from the type of the second cooling system.

2. the first cooling system is disposed on top of the first electronics layer; the first electronics layer is disposed on top of the second cooling system; The computing assembly of claim 1 , wherein the second cooling system is disposed on top of the second electronics layer.

3. a third cooling system; and a third electronics layer having a fifth surface and a sixth surface; the fifth surface is in thermal communication with the third cooling system; The computing assembly of claim 1 , wherein the fourth surface is in thermal communication with a third cooling system.

4. The computing assembly of claim 1 , wherein the first electronics layer is in electrical communication with the second electronics layer.

5. The computing assembly of claim 1 , wherein the first electronics layer comprises a system-on-wafer layer.

6. The computing assembly of claim 1 , wherein the first electronics layer includes an array of integrated circuit dies and the second electronics layer includes an array of power supply modules.

7. The computing assembly of claim 6 , wherein each power supply module in the array of power supply modules includes a voltage regulation module.

8. 7. The computing assembly of claim 6, wherein the number of integrated circuit dies in the first electronics layer is equal to the number of power supply modules in the second electronics layer, and each integrated circuit die is in electrical communication with only one power supply module.

9. 7. The computing assembly of claim 6, wherein power is delivered vertically from the second electronics layer to the first electronics layer, and the integrated circuit dies of the array of integrated circuit dies are in electronic communication with each other in a plane orthogonal to the power supply.

10. 1. A method of cooling an electronic assembly, comprising: attaching a first cooling layer on top of and in thermal communication with the first electronics layer; mounting the first electronics tier on top of and in thermal communication with the second cooling system; mounting a second cooling system on top of and in thermal communication with the second electronics layer; Including, the type of the first cooling system (601) and the type of the second cooling system (603) include one or more of a cold plate, a heat sink, and a liquid cooling block; The method, wherein the type of the first cooling system (601) is different from the type of the second cooling system (603).

11. outputting heat vertically from the first electronics layer to the first cooling system; outputting heat vertically from the first electronics layer to the second cooling system; 11. The method of claim 10, further comprising: outputting heat vertically from the second electronics layer to the second cooling system.

12. further comprising vertically delivering power from the second electronics layer to the first electronics layer. The method of claim 10.

13. a third cooling system in thermal communication with the second electronics layer; a third electronics layer in thermal communication with the third cooling system; The computing assembly of claim 1 , wherein the first electronics layer comprises a processing electronics layer, the second electronics layer comprises a power supply layer, and the third electronics layer comprises a control electronics layer.

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