Symmetrical Coupling of Coils for Direct Drive Radio Frequency Power Supplies

Abstract

The coil is disposed next to the plasma processing chamber. A first direct drive radio frequency (RF) power supply includes an output, and a first shaped amplified square waveform signal is transmitted through the output. A first reactive circuit is connected between the output of the first direct drive RF power supply and a first end of the coil. The first reactive circuit converts the first shaped amplified square waveform signal to a first shaped sine wave signal on its way to the first end of the coil. A second direct drive RF power supply includes an output, and a second shaped amplified square waveform signal is transmitted through the output. A second reactive circuit is connected between the output of the second direct drive RF power supply and a second end of the coil. The second reactive circuit converts the second shaped amplified square waveform signal to a second shaped sine wave signal on its way to the second end of the coil.

Description

[Background technology]

[0001] [Inventor] John Drewery; Alexander Miller Paterson Plasma processing systems are used to manufacture semiconductor devices, e.g., chips / dies, on semiconductor wafers. In plasma processing systems, semiconductor wafers are exposed to various types of plasma to cause predetermined changes in the state of the semiconductor wafer, such as through material deposition and / or material removal and / or material implantation and / or material modification. Conventionally, plasma processing systems include a radio frequency (RF) source, an RF transmission cable, an RF impedance matching network, an electrode, and a plasma generation chamber. The RF source is connected to the RF impedance matching network through the RF transmission cable. The RF impedance matching network is connected to the electrode through a conductor. RF power generated by the RF source is transmitted to the electrode through the RF transmission cable and the RF impedance matching network. The RF power transmitted from the electrode transforms the process gas into a plasma in the plasma generation chamber. It is in this context that the embodiments described in the present disclosure arise. Summary of the Invention

[0002] In an exemplary embodiment, a plasma processing system is disclosed. The plasma processing system includes a plasma processing chamber and a coil disposed next to the plasma processing chamber. The coil includes a first end and a second end. The plasma processing system also includes a first direct drive RF power supply having an output. The first shaped amplified square waveform signal is transmitted through the output. The plasma processing system also includes a first reactance circuit connected between the output of the first direct drive RF power supply and the first end of the coil. The first reactance circuit is configured to convert the first shaped amplified square waveform signal to a first shaped sinusoidal signal on the way to the first end of the coil. The plasma processing system also includes a second direct drive RF power supply having an output. The second shaped amplified square waveform signal is transmitted through the output. The plasma processing system also includes a second reactance circuit connected between the output of the second direct drive RF power supply and the second end of the coil. The second reactance circuit is configured to convert the second shaped amplified square waveform signal to a second shaped sine wave signal en route to the second end of the coil.

[0003] In an exemplary embodiment, a method of operating a plasma processing system is disclosed. The method includes operating a first direct drive RF signal generator to generate a first shaped amplified square waveform signal. The method also includes transmitting the first shaped amplified square waveform signal to a first reactance circuit. The method also includes operating the first reactance circuit to convert the first shaped amplified square waveform signal to a first shaped sine wave signal. The method also includes transmitting the first shaped sine wave signal to a first end of a coil of a plasma processing chamber. The first shaped sine wave signal conveys RF power to the coil. The method also includes operating a second direct drive RF signal generator to generate a second shaped amplified square waveform signal. The method also includes transmitting the second shaped amplified square waveform signal to a second reactance circuit. The method also includes operating the second reactance circuit to convert the second shaped amplified square waveform signal to a second shaped sine wave signal. The method also includes transmitting a second shaped sine wave signal to a second end of a coil of the plasma processing chamber, the second shaped sine wave signal delivering RF power to the coil.

[0004] In an exemplary embodiment, a plasma processing system is disclosed. The plasma processing system includes a plasma processing chamber and a coil disposed adjacent to the plasma processing chamber. The coil includes a first end and a second end. The plasma processing system also includes a direct drive RF power supply having an output. The shaped amplified square waveform signal is transmitted through the output. The plasma processing system also includes a reactance circuit connected between the output of the direct drive RF power supply and the first end of the coil. The reactance circuit is configured to convert the shaped amplified square waveform signal to a shaped sinusoidal signal on its way to the first end of the coil. The plasma processing system also includes a variable capacitor having an input terminal connected to the second end of the coil. The variable capacitor has an output terminal connected to a reference ground potential.

[0005] In an exemplary embodiment, a method of operating a plasma processing system is disclosed. The method includes operating a direct drive RF signal generator to generate a shaped amplified square waveform signal. The method also includes transmitting the shaped amplified square waveform signal to a reactance circuit. The method also includes operating the reactance circuit to convert the shaped amplified square waveform signal to a shaped sine wave signal. The method also includes transmitting the shaped sine wave signal to a first end of a coil of a plasma processing chamber. The shaped sine wave signal delivers RF power to the coil. The method also includes adjusting a capacitance setting of a variable capacitor connected between a second end of the coil and a reference ground potential to achieve a predetermined condition associated with delivering RF power from the coil to a plasma in the plasma processing chamber.

[0006] Other aspects and advantages of the present embodiments will become more apparent from the following detailed description and accompanying drawings. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 shows a diagram of a plasma processing system implementing a symmetrically coupled direct drive RF power supply, according to some embodiments.

[0008] [Diagram 2] FIG. 2 shows a schematic diagram of a first direct drive RF power supply and a second direct drive RF power supply, respectively, according to some embodiments.

[0009] [Diagram 3] FIG. 3 shows a circuit schematic of a half-bridge transistor circuit implementing a voltage limiter across a first transistor and a second transistor, according to some embodiments.

[0010] [Figure 4A] FIG. 4A shows a plot of parameters of an example shaped amplified square waveform generated at the output of the first / second direct drive RF power supplies as a function of time, according to some embodiments.

[0011] [Figure 4B] FIG. 4B shows a plot of parameters of an example shaped sine waveform generated at the output of the first / second reactance circuit as a function of time, according to some embodiments.

[0012] [Figure 5A] FIG. 5A shows a plot of parameters of an example shaped sine waveform generated at the output of the first / second reactance circuit as a function of time, according to some embodiments.

[0013] [Figure 5B] FIG. 5B illustrates a plot of parameters of an example shaped sine waveform generated at the output of the first / second reactance circuit as a function of time, according to some embodiments.

[0014] [Figure 5C] FIG. 5C shows a plot of parameters of an example shaped sine waveform generated at the output of the first / second reactance circuit as a function of time, according to some embodiments.

[0015] [Figure 5D] FIG. 5D shows a plot of parameters of an example shaped sine waveform generated at the output of the first / second reactance circuit as a function of time, according to some embodiments.

[0016] [Figure 6] FIG. 6 illustrates a flowchart of a method for delivering RF power from first / second direct drive RF power sources to a plasma processing chamber, according to some embodiments.

[0017] [Figure 7] FIG. 7 shows a diagram of a plasma processing system having a first direct drive RF power supply connected to a first end of a coil and a variable capacitor connected to a second end of the coil, in accordance with some embodiments.

[0018] [Figure 8] FIG. 8 shows a flowchart of a method for delivering RF power to a plasma processing chamber, according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that embodiments of the present invention may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the present disclosure.

[0020] 1 shows a diagram of a plasma processing system 100 implementing symmetrically coupled direct drive radio frequency (RF) power supplies 101A and 101B according to some embodiments. The plasma processing system 100 includes a first direct drive RF power supply 101A connected to a first end of a coil 105 through a first reactance circuit 103A as shown as connection 120A. The plasma processing system 100 also includes a second direct drive RF power supply 101B connected to a second end of the coil 105 through a second reactance circuit 103B as shown as connection 120B. In this manner, the coil 105 is symmetrically connected to the first direct drive RF power supply 101A and the second direct drive RF power supply 101B. Each of the first direct drive RF power supply 101A and the second direct drive RF power supply 101B generates RF power and delivers the RF power to the plasma processing chamber 111 through the coil 105, but is configured to eliminate the need to deliver the RF signal through an RF cable and an impedance matching network in its path to the plasma processing chamber 111. Each of the direct drive RF power supplies 101A and 101B is also referred to as a matchless plasma source (MPS).

[0021] In some embodiments, the coil 105 is positioned above a window 112 of the plasma processing chamber 111. In various embodiments, the window 112 is formed of a dielectric material, such as quartz or other similar material, that allows RF power to be transmitted from the coil 105 through the window 112 to the plasma processing chamber 111. The plasma processing chamber 111 is electrically connected to a reference ground potential 108. When RF power is transmitted into and through the plasma processing chamber 111, the RF power transforms a process gas into a plasma in the plasma processing chamber 111 upon exposure to a semiconductor wafer 109. The semiconductor wafer 109 is supported in the plasma processing chamber 111 on a substrate holder 107, such as an electrostatic chuck. In various embodiments, the plasma is used to control the alteration of the state of the semiconductor wafer 109, such as through material deposition and / or material removal and / or material implantation and / or material modification. Additionally, in some embodiments, a plasma is generated in the plasma processing chamber 111 to clean the plasma processing chamber 111. The direct drive RF power supplies 101A and 101B are described in detail below with respect to Figure 2. For the purposes of this discussion, it should be understood that each of the direct drive RF power supplies 101A and 101B is configured to generate an RF signal having a predetermined waveform as a function of time, and to deliver the generated RF signal to the coil 105.

[0022] Within the plasma processing chamber 111, the RF power transforms the process gas into a plasma upon exposure to a wafer 109 held on the substrate holder 107. Additionally, during operation of the plasma processing chamber 111, exhaust gases and by-products resulting from processing of the wafer 109 are exhausted from the plasma processing chamber 111. It should be appreciated that in various embodiments, operation of the plasma processing chamber 111 can include many other additional operations, such as generating a bias voltage at the wafer 109 level to attract or repel charged components of the plasma towards or away from the wafer 109, and / or controlling the temperature of the wafer 109, and / or generating additional plasma by applying additional RF power to one or more electrodes disposed within the substrate holder 107, among other additional operations. Further, in various embodiments, the plasma processing chamber 111 is operated according to a pre-defined recipe that specifies a time schedule for controlling one or more of the following: supply of one or more process gases to the plasma processing chamber 111, pressure and temperature within the plasma processing chamber 111, supply of RF power to the coil 105, supply of a bias voltage at the wafer 109 level, supply of RF power to one or more electrodes in the substrate holder 107, among essentially any number of processing parameters associated with the operation of the process processing chamber 111.

[0023] The plasma processing system 100 includes a controller 113 for controlling the operation of the first direct drive RF power supply 101A and the second direct drive RF power supply 101B. In some embodiments, the controller 113 includes a processor and a memory device. In some embodiments, the controller 113 includes one or more of a microprocessor, an application specific integrated circuit (ASIC), a central processing unit, a processor, a programmable logic device (PLD), and a field programmable gate array (FPGA). The controller 113 is connected to transmit a waveform generator control signal for the first direct drive RF power supply 101A through connection 121A. Similarly, the controller 113 is connected to transmit a waveform generator control signal for the second direct drive RF power supply 101B through connection 121B. The controller 113 is connected to transmit a signal generator control signal for the first direct drive RF power supply 101A through connection 123A. Similarly, the controller 113 is connected to transmit a signal generator control signal for the second direct drive RF power supply 101B over connection 123B. The controller 113 is connected to transmit a frequency input control signal for the first direct drive RF power supply 101A over connection 125A. Similarly, the controller 113 is connected to transmit a frequency input control signal for the second direct drive RF power supply 101B over connection 125B. The controller 113 is connected to transmit a reactance circuit control signal for at least one variable capacitor 104A in the first reactance circuit 103A over connection 127A. Similarly, the controller 113 is connected to transmit a reactance circuit control signal for at least one variable capacitor 104B in the first reactance circuit 103B over connection 127B.

[0024] Resistance 115A is seen by the output O1 of the first direct drive RF power supply 101A. Resistance 115A represents a combination of the resistance in the coil 105, the resistance seen by the plasma if plasma is present in the plasma processing chamber 111, and the resistance of the RF power transmission path from the output of the first direct drive RF power supply 101A to the coil 105. Similarly, resistance 115B is seen by the output O2 of the second direct drive RF power supply 101B. Resistance 115B represents a combination of the resistance in the coil 105, the resistance seen by the plasma if plasma is present in the plasma processing chamber 111, and the resistance of the RF power transmission path from the output of the first direct drive RF power supply 101B to the coil 105.

[0025] In some embodiments, a first voltage and current (VI) probe 117A is coupled to the output O1 of the first direct drive RF power supply 101A, as shown by connection 116A. The VI probe 117A is a sensor that measures the complex current at the output O1, the complex voltage at the output O1, and the phase difference between the complex voltage and the complex current at the output O1. The complex current has a magnitude and a phase. Similarly, the complex voltage has a magnitude and a phase. The VI probe 117A is coupled to the controller 113 to transmit a feedback signal 129A to the controller 113. In some embodiments, a voltage (V) probe is used instead of the VI probe 117A. In these embodiments, a current (I) probe 119A is coupled to the output of the first reactance circuit 103A, as shown by connection 118A. In these embodiments, the V probe is a sensor that measures the magnitude and phase of the time-varying complex voltage at the output O1. The I-Probe 119A is a sensor that measures the magnitude and phase of the time-varying complex current at the output of the first reactance circuit 103A. The I-Probe 119A is coupled to the controller 113 to transmit a feedback signal 131A to the controller 113.

[0026] In some embodiments, a second voltage and current (VI) probe 117B is coupled to the output O2 of the second direct drive RF power supply 101B, as shown by connection 116B. The VI probe 117B is a sensor that measures the complex current at the output O2, the complex voltage at the output O2, and the phase difference between the complex voltage and the complex current at the output O2. The complex current has a magnitude and a phase. Similarly, the complex voltage has a magnitude and a phase. The VI probe 117B is coupled to the controller 113 to transmit a feedback signal 129B to the controller 113. In some embodiments, a voltage (V) probe is used instead of the VI probe 117B. In these embodiments, a current (I) probe 119B is coupled to the output of the second reactance circuit 103B, as shown by connection 118B. In these embodiments, the V probe is a sensor that measures the magnitude and phase of the time-varying complex voltage at the output O2. The I-Probe 119B is a sensor that measures the magnitude and phase of the time-varying complex current at the output of the second reactance circuit 103B. The I-Probe 119B is coupled to the controller 113 to transmit a feedback signal 131B to the controller 113.

[0027] FIG. 2 shows a schematic diagram of the configuration of the first direct drive RF power supply 101A and the second direct drive RF power supply 101B, respectively, according to some embodiments. It should be understood that the first direct drive RF power supply 101A and the second direct drive RF power supply 101B have the same configuration. In FIG. 2, the suffix "A" of a given reference number indicates that the component / feature corresponding to the given reference number is that of the first direct drive RF power supply 101A. Similarly, the suffix "B" of a given reference number indicates that the component / feature corresponding to the given reference number is that of the second direct drive RF power supply 101B. For example, the connection 121A / B represents the connection 121A present in the first direct drive RF power supply 101A and the connection 121B present in the second direct drive RF power supply 101B.

[0028] Each of the first direct drive RF power supply 101A and the second direct drive RF power supply 101B includes an input section 201A / B and an output section 203A / B. The input section 201A / B includes an electrical signal generator 209A / B and a portion of the gate driver 207A / B. The output section 203A / B includes the remaining portion of the gate driver 207A / B and a half-bridge transistor (e.g., field effect transistor (FET)) circuit 233A / B. The half-bridge transistor circuit 233A / B, also referred to as an amplifier circuit / tree, is coupled to the gate driver 207A / B. In some embodiments, the input section 201A / B includes a control board 205A / B on which the electrical signal generator 209A / B, the waveform generator 213A / B, and the frequency input controller 211A / B are implemented. Electrical signal generator 209A / B is connected to receive signal generator control signals from controller 113 over connections 123A / B. Waveform generator 213A / B is connected to receive waveform generator control signals from controller 113 over connections 121A / B. Frequency input controller 211A / B is connected to receive frequency input control signals from controller 113 over connections 125A / B. Frequency input controller 211A / B is connected to provide frequency input to electrical signal generator 209A / B over connections 212A / B.

[0029] In some embodiments, the entire gate driver 207A / B is implemented on the control board 205A / B. The input section 201A / B generates a plurality of square wave signals and provides the square wave signals to the output section 203A / B. The output section 203A / B generates an amplified square waveform from the plurality of square wave signals received from the input section 201A / B. The output section 203A / B also shapes the envelope, such as the peak-to-peak magnitude, of the amplified square waveform. For example, the envelope is generated by providing a shaped control signal 214A / B from a waveform generator 213A / B in the input section 201A / B to a half-bridge transistor circuit 233A / B in the output section 203A / B. The shaped control signal 214A / B has a plurality of voltage values ​​for shaping the amplified square waveform to generate a shaped amplified square waveform. For the first direct drive RF power supply 101A, the shaped amplified square waveform is transmitted from the output 203A to the first reactance circuit 103A. For the second direct drive RF power supply 101B, the shaped amplified square waveform is transmitted from the output 203B to the second reactance circuit 103B.

[0030] Each of the first reactance circuit 103A and the second reactance circuit 103B generates a shaped sinusoidal waveform having a fundamental frequency by removing, for example, by filtering out, higher-order harmonics of the shaped amplified rectangular waveform. The shaped sinusoidal waveform has the same envelope as the shaped amplified rectangular waveform. For the first direct drive RF power source 101A, RF power is transmitted from the first reactance circuit 103A to a first end of the coil 105 in the form of a shaped sinusoidal waveform having a fundamental frequency. For the second direct drive RF power source 101B, RF power is transmitted from the second reactance circuit 103B to a second end of the coil 105 in the form of a shaped sinusoidal waveform having a fundamental frequency. The RF power transmitted to the coil 105 is transmitted into the plasma processing chamber 111 to transform one or more process gases in the plasma processing chamber 111 into a plasma for processing the wafer 109, as described above with respect to FIG. 1.

[0031] In some embodiments, for the first direct drive RF power supply 101A, the reactance of the first reactance circuit 103A is modified by transmitting a first Q-factor control signal from the controller 113 to the first reactance circuit 103A over connection 127A. The first Q-factor control signal directs the implementation of a particular change in the reactance of the first reactance circuit 103A, such as by directing the implementation of a change in the capacitance setting of at least one variable capacitor 104A in the first reactance circuit 103A. In some embodiments, for the second direct drive RF power supply 101B, the reactance of the second reactance circuit 103B is modified by transmitting a second Q-factor control signal from the controller 113 to the second reactance circuit 103B over connection 127B. The second Q-factor control signal 127B directs the execution of a particular change in the reactance of the second reactance circuit 103B, such as by directing the execution of a change in the capacitance setting of at least one variable capacitor 104B in the second reactance circuit 103B.

[0032] In some embodiments, the feedback signal 129A / B is transmitted from the VI probe 117A / B to the controller 113. In some embodiments, the feedback signal 129A / B is used to determine a phase difference between the time-varying voltage and the time-varying current of the shaped amplified rectangular waveform at the output O1 / O2 of the output 203A / B, thereby making it possible to control the output 203A / B to reduce or eliminate the phase difference. In some embodiments, for the first direct drive RF power supply 101A, in addition to or instead of the feedback signal 129A, a feedback signal 131A is transmitted from the I probe 119A to the controller 113. In some embodiments, the phase difference between the time-varying voltage and the time-varying current of the shaped sinusoidal waveform at the output O1 of the first reactance circuit 103A is determined from the feedback signal 131A, thereby making it possible to control the output 203A and / or control the first reactance circuit 103A to reduce or eliminate the phase difference. In some embodiments, for the second direct drive RF power supply 101B, in addition to or instead of the feedback signal 129B, a feedback signal 131B is transmitted from the I-probe 119B to the controller 113. In some embodiments, a phase difference between the time-varying voltage and the time-varying current of the shaped sinusoidal waveform at the output O2 of the second reactance circuit 103B is determined from the feedback signal 131B, thereby enabling controlling the output 203B and / or controlling the second reactance circuit 103B to reduce or eliminate the phase difference.

[0033] The electrical signal generator 209A / B is a square wave oscillator that generates a square wave signal, such as a digital waveform or a pulse train. The square wave signal output by the electrical signal generator 209A / B pulses between a first logic level, such as high (or 1), and a second logic level, such as low (or 0). The electrical signal generator 209A / B generates a square wave signal at a predetermined operating frequency, such as 400 kilohertz (kHz), or 2 MHz, or 13.56 MHz, or 27 MHz, or 60 MHz, among other operating frequencies, according to a frequency input provided to the electrical signal generator 209A / B from a frequency input controller 211A / B.

[0034] The gate driver 207A / B includes a first portion in the input section 201A / B, the first portion including the gate driver sub-section 215A / B, the capacitor 223A / B, the resistor 225A / B, and the primary winding 227A / B of the pulse transformer 217A / B. The gate driver 207A / B also includes a second portion in the output section 203A / B, the second portion including the secondary windings 229A / B and 231A / B of the pulse transformer 217A / B. The gate driver sub-section 215A / B includes a plurality of gate drivers 219A / B and 221A / B. Each of the gate drivers 219A / B and 221A / B has one end coupled to a positive voltage source (+) and an opposite end coupled to a negative voltage source (-).

[0035] In some embodiments, the half-bridge transistor circuit 233A / B includes a direct current (DC) rail 235A / B including a voltage source Vdc electrically connected to a first terminal of a first transistor 239A / B through a conductor 237A / B, a second terminal of the first transistor 239A / B electrically connected to a first terminal of a second transistor 241A / B, and a second terminal of the second transistor 241A / B electrically connected to a reference ground potential 242A / B. Thus, the half-bridge transistor circuit 233A / B includes a first transistor 239A / B and a second transistor 241A / B coupled to each other in a push-pull manner. In some embodiments, the first transistor 239A / B and the second transistor 241A / B are n-type FETs that are turned on when at least a threshold voltage is applied to their gate conductors. However, in other embodiments, the first transistor 239A / B and the second transistor 241A / B are p-type FETs that are turned off when at least a threshold voltage is applied to their gate conductors. In some embodiments, each of the first transistor 239A / B and the second transistor 241A / B is implemented as a metal oxide semiconductor field effect transistor (MOSFET). In some embodiments, the first transistor 239A / B and the second transistor 241A / B may be implemented as another type of transistor, such as an insulated gate bipolar transistor (IGBT), or a metal semiconductor field effect transistor (MESFET), or a junction field effect transistor (JFET), among others. In some embodiments, each of the first transistor 239A / B and the second transistor 241A / B is made of silicon carbide, or silicon, or gallium nitride. Each of the first transistor 239A / B and the second transistor 241A / B has an output impedance within a predetermined range, such as within a range spanning from about 0.01 Ohms to about 10 Ohms. The output O1 of the first direct drive RF power supply 101A is a node connection between the second terminal (source terminal) of the first transistor 239A and the first terminal (drain terminal) of the second transistor 241A.Similarly, the output O2 of the second direct drive RF power supply 101B is the node connection between the second terminal (the source terminal) of the first transistor 239B and the first terminal (the drain terminal) of the second transistor 241B.

[0036] The controller 113 is coupled to the frequency input controller 211A / B through connection 125A / B to provide a frequency input (operating frequency) to the electrical signal generator 209A / B. The controller 113 is further coupled to the waveform generator 213A / B to control the shaped control signal 214A / B provided to the DC rail 235A / B. The electrical signal generator 209A / B has outputs connected to the gate drivers 219A / B and 221A / B, respectively. The output of the gate driver 219A / B is coupled to an input terminal of the capacitor 223A / B. The output of the gate driver 221A / B is coupled to an input terminal of the resistor 225A / B. The capacitor 223A / B is coupled to a first end of the primary winding 227A / B of the pulse transformer 217A / B. The resistor 225A / B is coupled to a second end of the primary winding 227A / B of the pulse transformer 217A / B. The capacitor 223A / B has a function of canceling or nullifying the inductance of the primary winding 227A / B. Canceling or nullifying the inductance of the primary winding 227A / B promotes the generation of a rectangular shape of the gate drive signal output by the gate drivers 219A / B and 221A / B. Furthermore, the resistor 225A / B reduces the oscillation of the rectangular wave signal generated by the electrical signal generator 209A / B.

[0037] A first end of the secondary winding 229A / B of the pulse transformer 217A / B is electrically connected to the gate terminal of the first transistor 239A / B. A second end of the secondary winding 229A / B is electrically connected to both the second terminal of the first transistor 239A / B and the first terminal of the second transistor 241A / B, and both the second terminal of the first transistor 239A / B and the first terminal of the second transistor 241A / B are electrically connected to the output O1 / O2 of the half-bridge transistor circuit 233A / B. A first end of the secondary winding 231A / B of the pulse transformer 217A / B is electrically connected to the gate terminal of the second transistor 241A / B. A second end of the secondary winding 231A / B is electrically connected to the reference ground potential 242A / B. The outputs O1 / O2 of the half-bridge transistor circuits 233A / B are electrically connected to the inputs of the first / second reactance circuits 103A / B. The resistors 115A / B are seen by the outputs O1 / O2 of the half-bridge transistor circuits 233A / B. The resistors 115A / B represent a combination of the resistance in the coils 105 to which the first / second direct drive RF power supplies 101A / B are connected, the resistance seen by the plasma if a plasma is present in the plasma processing chamber 111, and the resistance of the RF power transmission path from the outputs O1 / O2 to the coils 105.

[0038] The controller 113 generates settings such as a frequency input provided to the electrical signal generator 209A / B through the frequency input controller 211A / B. The frequency input is a value of a target operating frequency such as 2 MHz, 13.56 MHz, etc. The electrical signal generator 209A / B generates an input RF signal having the target operating frequency. The input RF signal is a square wave signal. The gate drivers 219A / B and 221A / B generate an amplified RF signal by amplifying the input RF signal and provide the amplified RF signal to the primary winding 227A / B of the pulse transformer 217A / B.

[0039] Based on the direction of the amplified RF signal current at a given time, secondary winding 229A / B or secondary winding 231A / B generates a gate drive signal having a threshold voltage at a given time. For example, if the amplified RF signal current flows from the positively charged terminal of primary winding 227A / B to the negatively charged terminal of primary winding 227A / B, secondary winding 229A / B generates a gate drive signal having at least the threshold voltage to turn first transistor 239A / B on and secondary winding 231A / B generates a gate drive signal having at least the threshold voltage to turn second transistor 241A / B off. Conversely, when current of the amplified RF signal flows from the negatively charged terminal to the positively charged terminal of the primary windings 227A / B, the secondary windings 231A / B generate a gate drive signal having at least the threshold voltage to turn on the second transistor 241A / B, and the secondary windings 229A / B generate less than the threshold voltage so that the first transistor 239A / B is turned off.

[0040] Each of the gate drive signals transmitted to the gates of the first transistors 239A / B and the second transistors 241A / B is a square wave signal, for example, a digital signal or a pulse signal, having a target operating frequency. For example, each of the gate drive signals transmitted to the gates of the first transistors 239A / B and the second transistors 241A / B transitions between a low level and a high level. The gate drive signals transmitted to the gates of the first transistors 239A / B and the second transistors 241A / B have a target operating frequency and are inversely synchronous with each other. More specifically, during the time interval or at the time when the gate drive signal transmitted to the gates of the first transistors 239A / B transitions from a low level to a high level, the gate drive signal transmitted to the gates of the second transistors 241A / B transitions from a high level to a low level at the same time. Similarly, during the time interval or at the time when the gate drive signal transmitted to the gate of the first transistor 239A / B transitions from high to low, the gate drive signal transmitted to the gate of the second transistor 241A / B transitions from low to high at the same time. This inverse synchronization of the gate drive signals allows the first transistor 239A / B and the second transistor 241A / B to be successively turned on and successively turned off in a repetitive manner according to the target operating frequency of the square wave signal that varies over time. The first transistor 239A / B and the second transistor 241A / B are operated successively. For example, when the first transistor 239A / B is turned on, the second transistor 241A / B is turned off. Furthermore, when the second transistor 241A / B is turned on, the first transistor 239A / B is turned off. The first transistor 239A / B and the second transistor 241A / B are not on at the same time or for the same period of time. At frequencies other than the target operating frequency, the first / second reactance circuits 103A / B are responsible for providing a high load so that high currents do not exit the first / second direct drive RF power supplies 101A / B at other non-target operating frequencies.

[0041] When the first transistor 239A / B is on and the second transistor 241A / B is off, a current flows between the voltage source Vdc and the output O1 / O2, generating a voltage at the output O1 / O2. The voltage at the output O1 / O2 is generated according to the shaped control signal 214A / B received from the controller 113 through the waveform generator 213A / B. When the second transistor 241A / B is off, no current flows from the output O1 / O2 to the reference ground potential 242A / B connected to the second terminal of the second transistor 241A / B. When the first transistor 239A / B is on, a current flows from the voltage source Vdc through the output O1 / O2 of the half-bridge transistor circuit 233A / B to the input of the first / second reactance circuit 103A / B. Furthermore, when the second transistor 241A / B is on and the first transistor 239A / B is off, current flows from the output O1 / O2 of the half-bridge transistor circuit 233A / B to the reference ground potential 242A / B connected to the second terminal of the second transistor 241A / B. When the first transistor 239A / B is off, no current flows from the voltage source Vdc to the output O1 / O2 of the half-bridge transistor circuit 233A / B.

[0042] In some embodiments, the controller 113 directs the waveform generator 213A / B to generate a shaped control signal 214A / B that indicates a voltage value used to control the DC rail 235A / B. The shaped control signal 214A / B is transmitted to the voltage source Vdc through an electrical conductor. The DC rail 235A / B is agile in that there is fast control of the voltage source Vdc by the controller 113 (and optionally by the waveform generator 213A / B). Both the controller 113 and the voltage source Vdc are electronic circuits, which allows the controller 113 to control the voltage source Vdc substantially instantaneously. For example, when the controller 113 sends the voltage value in the shaped control signal 214A / B to the voltage source Vdc (either directly or through the waveform generator 213A / B), the voltage source Vdc changes its output voltage level substantially instantaneously in response. In some embodiments, the voltage value indicated by the shaped control signal 214A / B is in a range spanning from about 0 volts to about 80 volts, and thus the DC rail 235A / B operates within this voltage range. The voltage value indicated by the shaped control signal 214A / B is the magnitude of the voltage signal generated by the voltage source Vdc to define the shaped envelope of the shaped amplified rectangular waveform at the output O1 / O2 of the half-bridge transistor circuit 233A / B, i.e., at the output of the first / second direct drive RF power supply 101A / B. For example, when the first / second direct drive RF power supply 101AB is operated to generate a continuous waveform, the voltage value indicated by the shaped control signal 214A / B controls the peak-to-peak magnitude of a parameter of the continuous waveform generated at the output O1 / O2 of the half-bridge transistor circuit 233A / B as a function of time. The parameter is, by way of example, one or more of power, voltage, and current. The peak-to-peak magnitude of the continuous waveform defines the shaped envelope of the continuous waveform at the outputs O1 / O2 of the half-bridge transistor circuits 233A / B as a function of time.

[0043] In another example, when the first / second direct drive RF power supplies 101A / B are operated to generate a shaped amplified rectangular waveform having a pulse-shaped shaped envelope at the output O1 / O2 of the half-bridge transistor circuit 233A / B, the voltage value indicated by the shaped control signal 214A / B is changed substantially instantaneously (in a step function-like manner) at a given time or during a given predetermined period of time, whereby the peak-to-peak magnitude of the shaped amplified rectangular waveform changes from a first parameter level (e.g., a high level) to a second parameter level (e.g., a low level) or from the second parameter level to the first parameter level. The parameters are, by way of example, one or more of power, voltage, and current. In another example, when the first / second direct drive RF power supply 101A / B is operated to generate a shaped amplified rectangular waveform with a shaped envelope of any shape at the output O1 / O2 of the half-bridge transistor circuit 233A / B, the voltage value indicated by the shaped control signal 214A / B is changed in any predetermined and controlled manner as directed by the controller 113 through the waveform generator 213A / B. Thereby, the peak-to-peak magnitude of the shaped amplified rectangular waveform is changed in any predetermined and controlled manner. In another example, when the first / second direct drive RF power supply 101A / B is operated to generate a shaped amplified rectangular waveform with a multi-state pulse shape at the output O1 / O2 of the half-bridge transistor circuit 233A / B, the voltage value indicated by the shaped control signal 214A / B is changed substantially instantaneously (in a step function-like manner) at a given time or for a given predetermined period of time. Thereby, the peak-to-peak magnitude of the shaped amplified rectangular waveform is changed between different states. Each of the different states has a different peak-to-peak magnitude of a particular parameter level, such as a power level, a voltage level, and / or a current level, among others. In various embodiments, the number of different states is two or more and is specified by the controller 113.

[0044] The shaped amplified rectangular waveform generated at the output O1 / O2 of the half-bridge transistor circuit 233A / B is based on the operation (as a function of time) of the first transistor 239A / B and the second transistor 241A / B according to the gate drive signals output by the gate drivers 219A / B and 221A / B and the supply of a voltage (as a function of time) by the voltage source Vdc according to the shaped control signal 214A / B. The amount of amplification of the shaped amplified rectangular waveform is based on the output impedance of the first transistor 239A / B and the second transistor 241A / B of the half-bridge transistor circuit 233A / B, the voltage value supplied to the voltage source Vdc by the controller 113 (and optionally by the waveform generator 213A / B) in the shaped control signal 214A / B, and the maximum achievable voltage value at the voltage source Vdc. The first / second reactance circuit 103A / B receives the shaped amplified rectangular waveform and functions to reduce or eliminate higher harmonics of the shaped amplified rectangular waveform, thereby generating a shaped sinusoidal waveform having a fundamental frequency. It should be understood that the shaped sinusoidal waveform output by the first / second reactance circuit 103A / B has the same shaped envelope as the shaped amplified rectangular waveform input to the first / second reactance circuit 103A / B. The shaped sinusoidal waveform output by the first / second reactance circuit 103A / B is provided to the coil 105 as an RF signal for generating plasma in the plasma processing chamber 111.

[0045] In some embodiments, the VI probe 117A / B measures the complex voltage and complex current of the shaped amplified rectangular waveform at the output O1 / O2 of the half-bridge transistor circuit 233A / B and provides a corresponding feedback signal to the controller 113 through the connection 129A / B. The feedback signal indicates the complex voltage and the complex current. The controller 113 determines a phase difference between the complex voltage of the shaped amplified rectangular waveform and the complex current of the shaped amplified rectangular waveform from the feedback signal, and determines whether the phase difference is within a predetermined tolerance range. For example, the controller 113 determines whether the phase difference is zero or within a predetermined tolerance range (percentage) away from zero. If the controller 113 determines that the phase difference is not within the predetermined tolerance range, the controller 113 changes the frequency value of the operating frequency and changes the frequency input provided to the electrical signal generator 209A / B through the frequency input controller 211A / B. The modified frequency value is provided from the frequency input controller 211A / B to the electrical signal generator 209A / B to modify the operating frequency of the electrical signal generator 209A / B. In some embodiments, the operating frequency is modified for about 10 microseconds or less. The operating frequency of the electrical signal generator 209A / B is modified until the controller 113 determines that the phase difference between the complex voltage and the complex current measured by the VI probe 117A / B is within a predetermined tolerance. Upon determining that the phase difference between the complex voltage and the complex current is within a predetermined tolerance, the controller 113 does not further modify the frequency input to the electrical signal generator 209A / B. When the phase difference is within the predetermined tolerance, a predetermined amount of power is provided from the output O1 / O2 of the first / second direct drive RF power supply 101A / B through the first / second reactance circuit 103A / B to the coil 105.

[0046] In some embodiments, in addition to or instead of changing the frequency input to the electrical signal generator 209A / B, the voltage value in the shaped control signal 214A / B provided to the voltage source Vdc is changed to change the voltage signal generated by the voltage source Vdc. The voltage source Vdc changes the voltage level according to the voltage value indicated by the shaped control signal 214A / B. The controller 113 continues to change the voltage value in the shaped control signal 214A / B until the shaped amplified square waveform achieves a predetermined power set point. In some embodiments, the predetermined power set point is stored in a memory device of the controller 113. In various embodiments, instead of changing the voltage of the shaped amplified square waveform at the output O1 / O2, the current in the shaped amplified square waveform is changed. For example, by directing the change in the voltage value in the shaped control signal 214A / B, the controller 113 changes the current of the shaped amplified square waveform at the output O1 / O2 until the shaped amplified square waveform achieves a predetermined current set point. In some embodiments, the predetermined current set point is stored in a memory device of the controller 113. In some embodiments, instead of changing the voltage or current of the shaped amplified square waveform at the output O1 / O2, the power of the shaped amplified square waveform is changed. For example, by directing the change of the voltage value in the shaped control signal 214A / B, the controller 113 changes the power of the shaped amplified square waveform at the output O1 / O2 until the shaped amplified square waveform achieves a predetermined power setting value. In some embodiments, the predetermined power setting value is stored in the memory device of the controller 113. It should be noted that any change in the voltage, current, or power of the shaped amplified square waveform generated at the output O1 / O2 will result in the same change in the voltage, current, or power of the shaped sinusoidal waveform output by the first / second reactance circuit 103A / B, respectively.

[0047] In some embodiments, the controller 113 is coupled to the first / second reactance circuit 103A / B through a motor driver and a motor (e.g., a stepper motor). In some embodiments, the motor driver is implemented as an integrated circuit device including one or more transistors. The controller 113 sends a Q-value control signal to the motor driver in the first / second reactance circuit 103A / B through connection 127A / B, thereby directing the generation of an electrical signal transmitted from the motor driver to the motor. The motor operates according to the electrical signal received from the motor driver to vary the reactance of the first / second reactance circuit 103A / B. For example, in some embodiments, the motor operates to vary the reactance of the first / second reactance circuit 103A / B by varying the area (or spacing) between conductive plates in the variable capacitor 104A / B. In some embodiments, the reactance of the first / second reactance circuit 103A / B is varied to maintain a predetermined Q value of the first / second reactance circuit 103A / B.

[0048] The first / second reactance circuit 103A / B in combination with the inductance of the coil 105 has a high quality factor (Q). For example, the amount of power of the shaped amplified rectangular waveform generated at the output O1 / O2 that is lost in the first / second reactance circuit 103A / B is less than the amount of power of the shaped sinusoidal waveform transferred from the output of the first / second reactance circuit 103A / B to the coil 105. The high quality factor (Q) of the first / second reactance circuit 103A / B promotes fast ignition of the plasma in the plasma processing chamber 111. Furthermore, the first / second reactance circuit 103A / B is configured and set to resonate with the inductive reactance of the coil 105 and the plasma, so that the output O1 / O2 of the first / second direct drive RF power supply 101A / B sees the resistance 115A / B but essentially does not involve any reactance. For example, the first reactance circuit 103A is controlled to have a reactance that reduces, such as nulls or cancels, the reactance of the coil 105, the plasma, and the RF power transmission connection between the first reactance circuit 103A and the coil 105. In some embodiments, the reactance of the first reactance circuit 103A is controlled by controlling the capacitance setting of the variable capacitor 104A. Similarly, the second reactance circuit 103B is controlled to have a reactance that reduces, such as nulls or cancels, the reactance of the coil 105, the plasma, and the RF power transmission connection between the second reactance circuit 103B and the coil 105. In some embodiments, the reactance of the second reactance circuit 103B is controlled by controlling the capacitance setting of the variable capacitor 104B.

[0049] In some embodiments, the first transistor 239A / B and the second transistor 241A / B are fabricated from silicon carbide to have low internal resistance and fast switching time and to facilitate cooling of the first transistor 239A / B and the second transistor 241A / B. The low internal resistance of the silicon carbide first transistor 239A / B and the silicon carbide second transistor 241A / B reduces the amount of heat generated by the first transistor 239A / B and the second transistor 241A / B, thereby facilitating cooling of the first transistor 239A / B and the second transistor 241A / B with a cooling plate or heat sink. Furthermore, the low internal resistance of the first transistor 239A / B and the second transistor 241A / B provides high efficiency, thereby enabling the first transistor 239A / B and the second transistor 241A / B to be almost instantaneously turned on and instantly turned off, such as in less than 10 microseconds. In some embodiments, each of the first transistor 239A / B and the second transistor 241A / B is configured to be on and off within less than a predetermined period, such as less than 10 microseconds. In some embodiments, each of the first transistor 239A / B and the second transistor 241A / B is configured to be on and off within a period ranging from about 0.5 microseconds to about 10 microseconds. In some embodiments, each of the first transistor 239A / B and the second transistor 241A / B is configured to be on and off within a period ranging from about 1 microsecond to about 5 microseconds. In some embodiments, each of the first transistor 239A / B and the second transistor 241A / B is configured to be on and off within a period ranging from about 3 microseconds to about 7 microseconds. It should be appreciated that there is essentially no delay in the transition between the on and off states of each of the first transistor 239A / B and the second transistor 241A / B. In this manner, when the first transistors 239A / B are turned on, the second transistors 241A / B are turned off essentially simultaneously.Additionally, when the first transistor 239A / B is turned off, the second transistor 241A / B is turned on essentially simultaneously. The first transistor 239A / B and the second transistor 241A / B are configured to switch on and off fast enough to ensure that the first transistor 239A / B and the second transistor 241A / B are not on at the same time to avoid current flowing directly from the voltage source Vdc through the first transistor 239A / B and the second transistor 241A / B to the reference ground potential 242A / B.

[0050] It is understood that components such as transistors of the first / second direct drive RF power supplies 101A / B are electronic components. Furthermore, it is not understood that there is no RF impedance matching network and no RF cable in the RF power transmission path from the first / second direct drive RF power supplies 101A / B to the coil 105. In combination with the electronic components in the first / second direct drive RF power supplies 101A / B, the absence of an RF impedance matching network and no RF cable in the RF power transmission path from the first / second direct drive RF power supplies 101A / B to the coil 105 provides repeatability and consistency in terms of fast ignition of plasma and plasma sustainability across / between different plasma processing chambers 111.

[0051] 3 shows a circuit schematic diagram of a half-bridge transistor circuit 233A / B implementing a voltage limiter across the first transistor 239A / B and the second transistor 241A / B, according to some embodiments. A diode 303A / B is connected between the drain terminal (D) and the source terminal (S) of the first transistor 239A / B to limit the voltage across the first transistor 239A / B. When the first transistor 239A / B is turned on and the second transistor 241A / B is turned off, the voltage across the first transistor 239A / B increases until the voltage is limited by the diode 303A / B. The diode 303A / B serves to prevent current from shooting adversely through the first transistor 239A / B directly from the voltage source Vdc to the reference ground potential 242A / B. Similarly, a diode 305A / B is connected between the drain terminal (D) and the source terminal (S) of the second transistor 241A / B to limit the voltage across the second transistor 241A / B. When the second transistor 241A / B is turned on and the first transistor 239A / B is turned off, the voltage across the second transistor 241A / B increases until the voltage is limited by the diode 305A / B. The diode 305A / B serves to prevent current from shooting adversely through the second transistor 241A / B directly from the voltage source Vdc to the reference ground potential 242A / B. A capacitor 301A / B is connected between the drain terminal (D) of the first transistor 239A / B and the source terminal (S) of the second transistor 241A / B. If there is a delay in turning the first transistor 239A / B and / or the second transistor 241A / B off and on, current will flow from the voltage source Vdc through the capacitor 301A / B to the reference ground potential 242A / B, thereby reducing the chance of having an adverse and potentially damaging amount of current flow through the outputs O1 / O2 of the first / second direct drive RF power supplies 101A / B to the coil 105.

[0052] FIG. 4A shows a plot as a function of time of a parameter of an example shaped amplified square waveform 401 generated at the output O1 / O2 of the first / second direct drive RF power supply 101A / B according to some embodiments. The parameter of the shaped amplified square waveform 401 is either power, voltage, or current. The shaped amplified square waveform 401 has a shaped envelope 403 generated according to a voltage value indicated by the shaped control signal 214A / B as directed by the controller 113 and / or the waveform generator 213A / B. The shaped envelope 403 is controlled such that the absolute magnitude of the parameter of the shaped amplified square waveform 401 transitions between a first level L1 (low level) and a second level L2 (high level). The parameter has a lower peak-to-peak magnitude at the first level L1 than at the second level L2. It should be understood that the shaped envelope 403 can have a different shape than that shown in Figure 4A depending on the voltage values ​​indicated by the shaped control signals 214A / B. For example, the shaped control signals 214A / B can be generated to direct the shaped envelope 403 to have a continuous wave shape, a triangular shape, a multi-level pulse shape, or essentially any predetermined and controlled arbitrary shape.

[0053] FIG. 4B shows a plot of parameters of an example shaped sine waveform 405 generated at the output of the first / second reactance circuit 103A / B as a function of time, according to some embodiments. The parameters of the shaped sine waveform 405 are either power, voltage, or current. The shaped sine waveform 405 is based on a shaped amplified square waveform 401 input to the first / second reactance circuit 103A / B as a function of time. The shaped amplified square waveform 401 is a combination of a fundamental frequency sine waveform 405A and multiple higher harmonic sine waveforms 405B, 405C, etc. For example, the sine waveform 405B represents the second harmonic of the fundamental frequency sine waveform 405A. Furthermore, the sine waveform 405C represents the third harmonic of the fundamental frequency sine waveform 405A. The first / second reactance circuit 103A / B functions to remove higher harmonic sinusoidal waveforms 405B, 405C from the shaped amplified square waveform 405, thereby providing only the fundamental frequency sinusoidal waveform 405A as a function of time at the output of the first / second reactance circuit 103A / B. The high Q value of the first / second reactance circuit 103A / B facilitates the removal of higher harmonic sinusoidal waveforms 405B, 405C from the shaped amplified square waveform 401 output from the first / second direct drive RF power source 101A / B. The fundamental frequency sinusoidal waveform 405A is delivered to the coil 105 as a shaped sinusoidal waveform, thus delivering RF power to the coil 105.

[0054] FIG. 5A illustrates a plot of a parameter of an example shaped sinusoidal waveform 501 generated at the output of the first / second reactance circuit 103A / B as a function of time, according to some embodiments. The parameter of the shaped sinusoidal waveform 501 is either power, voltage, or current. The shaped sinusoidal waveform 501 has a shaped envelope 503 generated according to a voltage value indicated by the shaped control signal 214A / B as directed by the controller 113 and / or the waveform generator 213A / B. The shaped envelope 503 defines a peak-to-peak change in the parameter of the shaped sinusoidal waveform 501 as a function of time. The example shaped envelope 503 represents a substantially rectangular envelope, such as a pulse shaped envelope.

[0055] FIG. 5B illustrates a plot of a parameter of an example shaped sine waveform 505 generated at the output of the first / second reactance circuit 103A / B as a function of time, according to some embodiments. The parameter of the shaped sine waveform 505 is either power, voltage, or current. The shaped sine waveform 505 has a shaped envelope 507 generated according to a voltage value indicated by the shaped control signal 214A / B as directed by the controller 113 and / or the waveform generator 213A / B. The shaped envelope 507 defines a peak-to-peak change in the parameter of the shaped sine waveform 505 as a function of time. The example shaped envelope 505 represents a substantially triangular shaped envelope.

[0056] FIG. 5C illustrates a plot of parameters as a function of time of an example shaped sine waveform 509 generated at the output of the first / second reactance circuit 103A / B, according to some embodiments. The parameters of the shaped sine waveform 509 are either power, voltage, or current. The shaped sine waveform 509 has a shaped envelope 511 generated according to the voltage values ​​indicated by the shaped control signals 214A / B as directed by the controller 113 and / or the waveform generators 213A / B. The shaped envelope 511 defines the peak-to-peak change in the parameters of the shaped sine waveform 509 as a function of time. The example shaped envelope 511 represents a multi-state shape envelope including three different states S1, S2, and S3. The shaped envelope 511 is defined such that the peak-to-peak change in the parameters of the shaped sine waveform 509 in the first state S1 is greater than the peak-to-peak change in the parameters of the shaped sine waveform 509 in the second state S2. The shaped envelope 511 is also defined such that the peak-to-peak change in the parameters of the shaped sine waveform 509 in the second state S2 is greater than the peak-to-peak change in the parameters of the shaped sine waveform 509 in the third state S3. The shaped envelope 511 returns to the first state S1 after the third state S3. The states S1, S2, and S3 are repeated at a frequency less than the frequency of the shaped amplified rectangular waveform output by the first / second direct drive RF power supplies 101A / B. Thus, the states S1, S2, and S3 are repeated at a frequency less than the frequency of the shaped sine waveform 509. In various embodiments, the multi-state shape envelope includes four or more distinct states, each of which corresponds to a different peak-to-peak change as a function of time in a parameter of the shaped sine waveform 509. Further, in various embodiments, the multi-state shape envelope is controllable such that any of the three or more distinct states of the shaped envelope has a peak-to-peak magnitude of the parameter of the shaped sine waveform 509 that is lower or higher relative to the next state in the shaped envelope.

[0057] FIG. 5D illustrates a plot of a parameter of an example shaped sine waveform 513 generated at the output of the first / second reactance circuit 103A / B as a function of time, according to some embodiments. The parameter of the shaped sine waveform 513 is either power, voltage, or current. The shaped sine waveform 513 has a shaped envelope 515 generated according to a voltage value indicated by the shaped control signal 214A / B as directed by the controller 113 and / or the waveform generator 213A / B. The shaped envelope 515 defines a peak-to-peak change in a parameter of the shaped sine waveform 513 as a function of time. The example shaped envelope 515 is substantially flat, and thus the shaped sine waveform 513 represents a continuous wave signal with a substantially fixed peak-to-peak magnitude.

[0058] 6 shows a flow chart of a method for delivering RF power from a first / second direct drive RF power source 101A / B to a plasma processing chamber 111 according to some embodiments. The method includes an operation 601A for transmitting a first shaped amplified square waveform signal from an output of the first direct drive RF power source 101A to a first reactance circuit 103A, which operates to convert the first shaped amplified square waveform signal into a first shaped sine wave signal. In some embodiments, the first direct drive RF power source 101A has a non-50 ohm output impedance. The method also includes an operation 603A for transmitting the first shaped sine wave signal from an output of the first reactance circuit 103A to a first end of a coil 105 of the plasma processing chamber 111. The first shaped sine wave signal conveys RF power to the coil 105.

[0059] The method also includes an optional operation 605A for adjusting a capacitance setting in the first reactance circuit 103A such that a peak amount of RF power is transferred from the first direct drive RF power source 101A through the first reactance circuit 103A to the coil 105. In some embodiments, adjusting the capacitance setting in operation 605A essentially cancels the inductive component of the load to which the first direct drive RF power source 101A is connected through the coil 105 such that the load to which the first direct drive RF power source 101A is connected through the coil 105 is primarily a resistive load. In some embodiments, adjusting the capacitance setting in operation 605A removes non-fundamental harmonic components of the first shaped amplified square waveform signal transferred from the output of the first direct drive RF power source 101A to the first reactance circuit 103A.

[0060] The method includes an operation 601B for transmitting a second shaped amplified square waveform signal from an output of the second direct drive RF power supply 101B to a second reactance circuit 103B, the second reactance circuit 103B being operative to convert the second shaped amplified square waveform signal to a second shaped sine wave signal. In some embodiments, the second direct drive RF power supply 101B has a non-50 ohm output impedance. The method also includes an operation 603B for transmitting the second shaped sine wave signal from an output of the second reactance circuit 103B to a second end of the coil 105 of the plasma processing chamber 111. The second shaped sine wave signal delivers RF power to the coil 105.

[0061] The method also includes an optional operation 605B for adjusting a capacitance setting in the second reactance circuit 103B such that a peak amount of RF power is transferred from the second direct drive RF power source 101B through the second reactance circuit 103B to the coil 105. In some embodiments, operation 605B includes adjusting a capacitance setting of a variable capacitor 104B in the second reactance circuit 103B to substantially match a capacitance setting of a variable capacitor 104A in the first reactance circuit 103A. In some embodiments, adjusting the capacitance setting in operation 605B essentially cancels the inductive component of a load to which the second direct drive RF power source 101B is connected through the coil 105 such that the load to which the second direct drive RF power source 101B is connected through the coil 105 is primarily a resistive load. In some embodiments, adjusting the capacitance setting in operation 605B removes non-fundamental harmonic components of the second shaped amplified square waveform signal transmitted from the output of the second direct drive RF power supply 101 B to the second reactance circuit 103 B. It is understood that method operations 601A, 601B, 603A, 603B, and optionally 605A and 605B, are performed in parallel with one another.

[0062] In some embodiments, the first shaped amplified square waveform signal output by the first direct drive RF power supply 101A has a frequency of about 2 megahertz (MHz), and the capacitance setting of the variable capacitor 104A in the first reactance circuit 103A is adjusted in operation 605A to within a range spanning from about 2500 picofarads (pF) to about 4500 pF. Furthermore, the second shaped amplified square waveform signal output by the second direct drive RF power supply 101B also has a frequency of about 2 MHz, and the capacitance setting of the variable capacitor 104B in the second reactance circuit 103B is adjusted in operation 605B to have substantially the same capacitance setting as the variable capacitor 104A in the first reactance circuit 103A. In some embodiments, the first shaped amplified square waveform signal output by the first direct drive RF power supply 101A has a frequency of about 13.56 MHz, and the capacitance setting of the variable capacitor 104A in the second reactance circuit 103A is adjusted in operation 605A to within a range ranging from about 5 pF to about 1000 pF. Furthermore, the second shaped amplified square waveform signal output by the second direct drive RF power supply 101B also has a frequency of about 13.56 MHz, and the capacitance setting of the variable capacitor 104B in the second reactance circuit 103B is adjusted in operation 605B to have substantially the same capacitance setting as the variable capacitor 104A in the first reactance circuit 103A.

[0063] In some embodiments, the first direct drive RF power supply 101A is configured to provide a first shaped amplified square waveform signal having a frequency of about 2 MHz to a first end of the coil 105, and the second direct drive RF power supply 101B is configured to simultaneously provide a second shaped amplified square waveform signal also having a frequency of about 2 MHz to a second end of the coil 105. In some of these embodiments, the first reactance circuit 103A is configured to provide a capacitance between the output O1 of the first direct drive RF power supply 101A and the first end of the coil 105 in a range spanning from about 2500 pF to about 4500 pF. Additionally, the second reactance circuit 103B is configured to provide a capacitance between the output O2 of the second direct drive RF power supply 101B and the second end of the coil 105 that is substantially equal to the capacitance provided by the first reactance circuit 103A. In some of these embodiments, the first reactance circuit 103A includes a variable capacitor 104A and a fixed capacitor connected in parallel with each other, and the second reactance circuit 103B includes a variable capacitor 104B and a fixed capacitor connected in parallel with each other. In some of these embodiments, the capacitance settings of each of the variable capacitors 104A and 104B are adjustable within a range ranging from about 100 pF to about 2000 pF. Furthermore, the capacitance settings of each of the fixed capacitors in the first reactance circuit 103A and the second reactance circuit 103B are within a range ranging from about 2000 pF to about 3500 pF, and the second reactance circuit 103B is configured in a manner substantially similar to the first reactance circuit 103A.

[0064] In some embodiments, the first direct drive RF power supply 101A is configured to provide a first shaped amplified square waveform signal having a frequency of about 13.56 MHz to a first end of the coil 105, and the second direct drive RF power supply 101B is configured to simultaneously provide a second shaped amplified square waveform signal also having a frequency of about 13.56 MHz to a second end of the coil 105. In some of these embodiments, the first reactance circuit 103A is configured to provide a capacitance between the output O1 of the first direct drive RF power supply 101A and the first end of the coil 105 in a range ranging from about 5 pF to about 1000 pF. Furthermore, the second reactance circuit 103B is configured to provide a capacitance between the output O2 of the second direct drive RF power supply 101B and the second end of the coil 105 that is substantially equal to the capacitance provided by the first reactance circuit 103A.

[0065] In the plasma processing system 100, RF power is driven in a substantially symmetrical manner through the coil 105 by a combination of a first direct drive RF power supply 101A and a second direct drive RF power supply 101B. The first direct drive RF power supply 101A delivers half of the RF power setting to the coil 105, and the second direct drive RF power supply 101B delivers half of the RF power setting to the coil 105. The connection of a first end of the coil 105 to an output O1 of the half bridge transistor circuit 233A of the first direct drive RF power supply 101A in conjunction with the connection of a second end of the coil 105 to an output O2 of the half bridge transistor circuit 233B of the second direct drive RF power supply 101B allows the coil 105 to be driven at a particular RF power level using half of the DC rail 235A / B voltage (Vdc). The DC rail 235A / B voltage (Vdc) is the voltage that would otherwise be required if the coil 105 were driven by only one of the first direct drive RF power supply 101A and the second direct drive RF power supply 101B. A higher voltage is generated across the coil 105 at a given DC rail 235A / B voltage (Vdc). Thus, by symmetrically coupling opposite ends of the coil 105 to the first direct drive RF power supply 101A and the second direct drive RF power supply 101B, the plasma processing system 100 can double the RF power driven through the coil 105 at a given DC rail 235A / B voltage (Vdc). This allows the DC rail 235A / B to be operated at a lower voltage (Vdc) for a given RF level, which is useful in meeting (below) the maximum voltage ratings of the first transistor 239A / B and the second transistor 241A / B in the DC rail 235A / B.In some embodiments, with the first and second direct drive RF power sources 101A and 101B symmetrically connected to provide RF power to the coil 105, the total RF power delivered to the coil 105 is greater than about 8 kilowatts (kW) or greater than about 10 kW without exceeding the voltage limits of the first and second transistors 239A / B and 241A / B in the DC rails 235A / B. Furthermore, the first and second reactance circuits 103A and 103B are configured to provide substantially equal capacitance levels to maintain voltage balance across the coil 105. The symmetric coupling of the first and second direct drive RF power sources 101A and 101B to the coil 105 is particularly beneficial in applications with high inductance and low current.

[0066] FIG. 7 shows a diagram of a plasma processing system 700 having a first direct drive RF power supply 101A connected to a first end of the coil 105 and a variable capacitor 701 connected to a second end of the coil 105, according to some embodiments. In the plasma processing system 700, the variable capacitor 701 is an alternative to the second direct drive RF power supply 101B described with respect to FIGS. 1-6. The second end of the coil 105 is connected to a first terminal of the variable capacitor 701. The second terminal of the variable capacitor 701 is connected to a terminal reference ground potential 703. In some embodiments, the capacitance setting of the variable capacitor 701 is adjusted to achieve a voltage balance across the coil 105, such that the voltage at the first end of the coil 105 is substantially equal to the voltage at the second end of the coil 105. In some embodiments, the capacitance setting of the variable capacitor 701 is adjusted to achieve a balanced RF power supply condition in which the reactance of the variable capacitor 701 is substantially equal to half the reactance of the coil 105. In some embodiments, the capacitance setting of the variable capacitor 701 is adjusted to optimize (e.g., maximize) the plasma density in the plasma processing chamber 111. In some embodiments, the capacitance setting of the variable capacitor 701 is adjusted to optimize (e.g., minimize) the plasma potential in the plasma processing chamber 111. In some embodiments, the capacitance setting of the variable capacitor 701 is adjusted to optimize (e.g., minimize) the voltage drop across the plasma sheath in the plasma processing chamber 111. In some embodiments, the capacitance setting of the variable capacitor 701 is adjusted to optimize the electron temperature in the plasma in the plasma processing chamber 111.

[0067] 8 shows a flow chart of a method of delivering RF power to a plasma processing chamber 700 according to some embodiments. The method includes an operation 801 for transmitting a shaped amplified square waveform signal from an output of a first direct drive RF power source 101A to a first reactance circuit 103A, the first reactance circuit 103A operative to convert the shaped amplified square waveform signal to a shaped sine wave signal. The method also includes an operation 803 for transmitting the shaped sine wave signal from an output of the first reactance circuit 103A to a first end of a coil 105 of the plasma processing chamber 111, the shaped sine wave signal conveying RF power to the coil 105. The method also includes an optional operation 805 for adjusting a capacitance setting using the first reactance circuit 103A such that a peak amount of RF power is transmitted from the first direct drive RF power source 101A through the first reactance circuit 103A to the coil 105. The method also includes an operation 807 of achieving a predetermined condition associated with delivery of RF power from the coil to a plasma in the plasma processing chamber 111 by adjusting a capacitance setting of a variable capacitor 701 connected between a second end of the coil 105 and a reference ground potential 703. In some embodiments, the operation 807 is performed to achieve a substantial balance of voltage across the coil 105 (between the first and second ends of the coil 105). In some embodiments, the operation 807 is performed to achieve a balanced RF power delivery condition in which the reactance of the variable capacitor 701 is substantially equal to half the reactance of the coil 105. In some embodiments, the operation 807 is performed to optimize (e.g., maximize) the plasma density in the plasma processing chamber 111. In some embodiments, the operation 807 is performed to optimize (e.g., minimize) the plasma potential in the plasma processing chamber 111. In some embodiments, the operation 807 is performed to optimize (e.g., minimize) the voltage drop across a plasma sheath in the plasma processing chamber 111. In some embodiments, operation 807 is performed to optimize the electron temperature in the plasma in the plasma processing chamber 111 .

[0068] The various embodiments described herein may be practiced in conjunction with a variety of computer system configurations, including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, etc. The various embodiments described herein may also be practiced in conjunction with distributed computing environments where tasks are performed by remote processing hardware units that are linked through a computer network.

[0069] In some embodiments, a control system, such as, for example, a host computer system, is provided for control of the plasma processing systems 100 and 700. In various embodiments, the plasma processing systems 100 and 700 include semiconductor processing equipment, such as one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (such as a wafer pedestal and a gas flow system, among others). In various embodiments, the plasma processing systems 100 and 700 are integrated with electronic components to control the operation of those systems before, during, and after processing of a semiconductor wafer or substrate. The electronic components are implemented in a controller configured and connected to control the various components and / or subcomponents of the plasma processing systems 100 and 700. The controller is programmed to control any of the processes and / or components disclosed herein, including, among others, delivery of one or more process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, first / second direct drive RF power sources 101A / 101B settings, first / second reactance circuit 103A / B settings, variable capacitor 701 settings, electrical signal frequency settings, gas flow rate settings, fluid delivery settings, position and motion settings, substrate / wafer loading / unloading into the plasma processing chamber 111 and / or into load locks connected or interfaced with the plasma processing systems 100 and 700, depending on the substrate / wafer processing requirements and / or the particular configuration of the plasma processing systems 100 and 700.

[0070] Generally, in various embodiments, the controller connected to control the operation of the plasma processing system 100 and 700 is defined as an electronic component having various integrated circuits, logic, memory, and / or software that direct and control various tasks / operations such as receiving instructions, issuing instructions, controlling device operations, enabling cleaning operations, enabling endpoint measurements, enabling metrology measurements (light, heat, electricity, etc.), among other tasks / operations. In some embodiments, the integrated circuits in the controller include one or more firmware that stores program instructions, digital signal processors (DSPs), application specific integrated circuit (ASIC) chips, programmable logic devices (PLDs), one or more microprocessors and / or microcontrollers that execute program instructions (e.g., software), among other computing devices. In some embodiments, the program instructions are communicated to the controller in the form of various individual settings (or program files), and the program instructions define operational parameters for performing processes on substrates / wafers in the plasma processing system 100 and 700. In some embodiments, the operational parameters are included in a recipe defined by a process engineer to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or die on a substrate / wafer.

[0071] In some implementations, the controller is part of or connected to a computer that is integrated with or otherwise networked to the plasma processing systems 100 and 700, or a combination thereof. For example, in some embodiments, the controller is implemented in the "cloud" or in whole or in part on a host computer system at a fabrication facility, thereby allowing remote access to control substrate / wafer processing by the plasma processing systems 100 and 700. The controller allows remote access to the plasma processing systems 100 and 700 to monitor the current progress of a fabrication run, review the history of past fabrication runs, review trends or performance criteria across multiple fabrication runs, modify process parameters, set up subsequent processing steps, and / or begin new substrate / wafer fabrication runs.

[0072] In some examples, a remote computer, such as a server computer system, provides process recipes to the controllers of the plasma processing systems 100 and 700 over a computer network, the network including a local network and / or the Internet. The remote computer includes a user interface that allows for entry or programming of parameters and / or settings, which are then communicated from the remote computer to the controllers of the plasma processing systems 100 and 700. In some examples, the controllers receive instructions in the form of settings for processing substrates / wafers in the plasma processing systems 100 and 700. It should be understood that the settings are specific to the type of processing to be performed on the substrates / wafers and the type of tools / devices / components that the controller interfaces with or controls. In some embodiments, the controllers are distributed, such as by including one or more discrete controllers that are networked and synchronized with each other to work toward a common purpose (such as operating the plasma processing systems 100 and 700 to perform a given processing on the substrates / wafers). An example of a distributed controller for such purposes includes one or more integrated circuits on the chamber that are located remotely (such as at the platform level or as part of the remote computer) and communicate with one or more integrated circuits that cooperate to control processing in the chamber. Depending on the processing operations being performed by plasma processing systems 100 and 700, the controller communicates with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used for material transport to transport containers of substrates / wafers in and out of tool locations and / or load ports within a semiconductor manufacturing factory.

[0073] It should be understood that in some embodiments, the operation of the plasma processing systems 100 and 700 includes the execution of various computer-implemented operations involving data stored in a computer system. These computer-implemented operations manipulate physical quantities. In various embodiments, the computer-implemented operations are performed by either a general-purpose computer or a special-purpose computer. In some embodiments, the computer-implemented operations are performed by a selectively activated computer and / or are directed by one or more computer programs stored in a computer memory or obtained over a computer network. When the computer programs and / or digital data are obtained over a computer network, the digital data may be processed by other computers on the computer network, e.g., a cloud of computing resources. The computer programs and digital data are stored as computer-readable code on a non-transitory computer-readable medium. A non-transitory computer-readable medium is any data storage hardware unit (e.g., a memory device, etc.) that stores data, which is subsequently readable by a computer system. Examples of non-transitory computer readable media include hard drives, network attached storage (NAS), ROM, RAM, compact disc ROM (CD-ROMs), CD recordables (CD-Rs), CD re-writeables (CD-RWs), digital video / versatile discs (DVDs), magnetic tape, and other optical and non-optical data storage hardware units. In some embodiments, computer programs and / or digital data are distributed among multiple computer readable media located on different computer systems within a network of coupled computer systems, such that the computer programs and / or digital data are executed and / or stored in a distributed fashion.

[0074] Although the above disclosure includes certain details for clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of the appended claims. For example, it should be understood that one or more features from any embodiment disclosed herein may be combined with one or more features of any other embodiment disclosed herein. Therefore, the present embodiments should be considered as illustrative rather than restrictive, and the claims should not be limited to the details set forth herein, but may be modified within the scope and equivalents of the described embodiments.

[0075] The claims are as follows:

Claims

1. 1. A plasma processing system comprising: a plasma processing chamber; a coil disposed adjacent to the plasma processing chamber and having a first end and a second end; a first direct drive radio frequency power supply having an output through which a first shaped amplified square waveform signal is transmitted; a first reactive circuit connected between the output of the first direct drive radio frequency power source and the first end of the coil, the first reactive circuit configured to convert the first shaped amplified square waveform signal to a first shaped sinusoidal signal en route to the first end of the coil; a second direct drive radio frequency power supply having an output through which the second shaped and amplified square waveform signal is transmitted; a second reactive circuit connected between the output of the second direct drive radio frequency power source and the second end of the coil, the second reactive circuit configured to convert the second shaped amplified square waveform signal to a second shaped sinusoidal signal en route to the second end of the coil; 1. A plasma processing system comprising:

2. 2. The plasma processing system of claim 1, wherein the first direct drive radio frequency power supply and the second direct drive radio frequency power supply have matching configurations, and the first reactance circuit and the second reactance circuit have matching configurations.

3. 3. The plasma processing system of claim 2, wherein the first direct drive radio frequency power supply includes an electrical signal generator connected to transmit a first electrical signal through a first gate driver to a first end of a primary winding of a pulse transformer; the electrical signal generator is further connected to transmit a second electrical signal through a second gate driver to a second end of the primary winding of the pulse transformer; the first direct drive radio frequency power supply includes a half-bridge transistor circuit including a first transistor and a second transistor connected in series between a voltage source and a reference ground potential; the first transistor has a gate connected to a first secondary winding of the pulse transformer; the second transistor has a gate connected to a second secondary winding of the pulse transformer; The system, wherein the output of the first direct drive radio frequency power source is provided to a connection between the first transistor and the second transistor.

4. 3. The plasma processing system of claim 2, wherein the first reactance circuit includes a variable capacitor.

5. 1. A method of operating a plasma processing system, comprising: operating a first direct drive radio frequency signal generator to generate a first shaped and amplified square waveform signal; transmitting the first shaped amplified rectangular waveform signal to a first reactance circuit; operating the first reactance circuit to convert the first shaped amplified rectangular waveform signal into a first shaped sine wave signal; transmitting the first shaped sine wave signal to a first end of a coil of a plasma processing chamber, the first shaped sine wave signal carrying radio frequency power to the coil; operating a second direct drive radio frequency signal generator to generate a second shaped and amplified square waveform signal; transmitting the second shaped and amplified rectangular waveform signal to a second reactance circuit; operating the second reactance circuit to convert the second shaped amplified rectangular waveform signal into a second shaped sine wave signal; transmitting the second shaped sine wave signal to a second end of the coil of the plasma processing chamber, the second shaped sine wave signal carrying radio frequency power to the coil; and 10. A method of operating a plasma processing system, comprising:

6. 6. The method of claim 5, wherein the first shaped sine wave signal delivers approximately half of the total amount of radio frequency power to the coil and the second shaped sine wave signal delivers approximately half of the total amount of radio frequency power to the coil.

7. 6. The method of claim 5, wherein the first direct drive radio frequency signal generator and the second direct drive radio frequency signal generator have matching configurations, and the first reactance circuit and the second reactance circuit have matching configurations.

8. 6. The method of claim 5, wherein the first direct drive radio frequency signal generator and the second direct drive radio frequency signal generator are operated from the same DC rail voltage.

9. 9. The method of claim 8, wherein the same DC rail voltage is less than the voltage across the coil.

10. 6. The method of claim 5, adjusting a capacitance setting in the first reactance circuit such that a peak amount of radio frequency power is transferred from the first direct drive radio frequency signal generator through the first reactance circuit to the first end of the coil; adjusting a capacitance setting in the second reactance circuit such that a peak amount of radio frequency power is transferred from the second direct drive radio frequency signal generator through the second reactance circuit to the second end of the coil; The method further comprises:

11. 1. A plasma processing system comprising: a plasma processing chamber; a coil disposed adjacent to the plasma processing chamber and having a first end and a second end; a direct drive radio frequency power supply having an output through which a shaped and amplified square waveform signal is transmitted; a reactive circuit connected between the output of the direct drive radio frequency power supply and the first end of the coil, the reactive circuit configured to convert the shaped amplified square waveform signal to a shaped sine wave signal en route to the first end of the coil; a variable capacitor having an input terminal connected to the second end of the coil and an output terminal connected to a reference ground potential; 1. A plasma processing system comprising:

12. 12. The plasma processing system of claim 11, wherein the second end of the coil is connected to an electrical component capable of affecting the transfer of radio frequency power from the coil to a plasma in the plasma processing chamber, the electrical component being the variable capacitor.

13. 12. The plasma processing system of claim 11, wherein the direct drive radio frequency power supply includes an electrical signal generator connected to transmit a first electrical signal through a first gate driver to a first end of a primary winding of a pulse transformer; the electrical signal generator is further connected to transmit a second electrical signal through a second gate driver to a second end of the primary winding of the pulse transformer; the direct drive radio frequency power supply includes a half-bridge transistor circuit including a first transistor and a second transistor connected in series between a voltage source and another reference ground potential; the first transistor has a gate connected to a first secondary winding of the pulse transformer; the second transistor has a gate connected to a second secondary winding of the pulse transformer; The system, wherein the output of the direct drive radio frequency power source is provided to a connection between the first transistor and the second transistor.

14. 1. A method of operating a plasma processing system, comprising: operating a direct drive radio frequency signal generator to generate a shaped amplified square waveform signal; transmitting the shaped and amplified rectangular waveform signal to a reactance circuit; operating the reactance circuit to convert the shaped amplified rectangular waveform signal into a shaped sine wave signal; transmitting the shaped sine wave signal to a first end of a coil of a plasma processing chamber, the shaped sine wave signal carrying radio frequency power to the coil; and adjusting a capacitance setting of a variable capacitor connected between a second end of the coil and a reference ground potential to achieve a predetermined condition associated with conducting radio frequency power from the coil to a plasma in the plasma processing chamber; A method comprising:

15. 15. The method of claim 14, wherein the predetermined condition is a substantial balance of voltages across the coils.

16. 15. The method of claim 14, wherein the predetermined state is a balanced radio frequency power supply state in which the reactance of the variable capacitor is substantially equal to one-half the reactance of the coil.

17. 15. The method of claim 14, wherein the predetermined condition is an optimization of plasma density within the plasma processing chamber.

18. 15. The method of claim 14, wherein the predetermined condition is an optimization of a plasma potential within the plasma processing chamber.

19. 15. The method of claim 14, wherein the predetermined condition is an optimization of a voltage drop across a plasma sheath in the plasma processing chamber.

20. 15. The method of claim 14, wherein the predetermined condition is an optimization of electron temperature in the plasma in the plasma processing chamber.

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