Integrated circuit (IC) package employing auxiliary metal layer coupled to buried metal traces in a die-side buried trace substrate (ETS) layer and related manufacturing method - Patents.com

Abstract

An integrated circuit (IC) package and associated manufacturing method employing an auxiliary metal layer coupled to buried metal traces in a die-side buried trace substrate (ETS) layer to reduce metal density mismatch. The IC package includes a semiconductor die ("die") electrically coupled to a package substrate. The package substrate includes a die-side ETS metallization layer coupled adjacent to the die. An auxiliary metal layer having additional metal interconnects is disposed adjacent to the die-sized ETS metallization layer to reduce or avoid metal density mismatch between the die-side ETS metallization layer and another metallization layer(s) in the package substrate. The additional metal interconnects are vertically coupled to the buried metal traces in the die-side ETS metallization layer to increase the metal density of the die-side metal interconnects formed by the additional metal interconnects coupled to the buried metal traces in the die-side ETS metallization layer.

Description

[Technical field]

[0001] Priority Application

[0001] This application claims priority to U.S. patent application Ser. No. 17 / 451,302, filed on October 18, 2021, and entitled "INTEGRATED CIRCUIT (IC) PACKAGES EMPLOYING SUPPLEMENTAL METAL LAYER COUPLED TO EMBEDDED METAL TRACES IN A DIE-SIDE EMBEDDED TRACE SUBSTRATE (ETS) LAYER, AND RELATED FABRICATION METHODS," which is incorporated by reference in its entirety into this specification. [Background technology]

[0002] I. Field of Disclosure The field of the disclosure relates to integrated circuit (IC) packages, and more particularly to the design and manufacture of package substrates that support signal routing to the semiconductor die(s) within the IC package.

[0003] II. Background

[0003] Integrated circuits (ICs) are the basis of electronic devices. ICs are packaged in IC packages, also called "semiconductor packages" or "chip packages." An IC package includes one or more semiconductor dice ("die" or "dice") mounted and electrically coupled to a package substrate for providing physical support and an electrical interface to the die as an IC. The package substrate includes one or more metallization layers including metal interconnects (e.g., metal traces, metal lines), and vertical interconnect accesses (vias) couple the metal interconnects together between adjacent metallization layers to provide an electrical interface between the die(s). To electrically couple the die(s) to the metal interconnects of the package substrate, the die(s) are electrically interfaced to the metal interconnects exposed on the top die-side metallization layer of the package substrate. The package substrate also includes a bottom outer metallization layer that includes metal interconnects that are bonded to external metal interconnects (e.g., ball grid array (BGA) interconnects) to provide an external interface between the die(s) in the IC package. The external metal interconnects can also be bonded (e.g., soldered) to traces in a printed circuit board (PCB) to attach the package to the PCB and interface its die(s) with the circuitry of the PCB.

[0004]

[0004] As an example, the package substrate of an IC package may be an embedded trace substrate (ETS) based package substrate. The ETS based package substrate includes one or more metallization layers, which are ETS metallization layers having embedded metal traces as metal interconnects. The embedded metal traces are embedded in an insulating layer (i.e., a dielectric layer) that is part of the ETS metallization layer. The ETS metallization layer facilitates providing a higher density bump / solder joint with reduced line-and-space ratio (L / S) for electrically coupling the die to the package substrate for signal routing. Metal embedded traces are formed in the ETS metallization layer that are electrically coupled to the die and metal interconnects in other metallization layers of the package substrate to provide signal routing paths for signal routing. For example, when the package substrate is a two-layer (2L) ETS based package substrate, the package substrate may include a top die-side ETS metallization layer having embedded metal traces coupled to the die interconnects of the die, and a bottom external interconnect-side ETS metallization layer having embedded metal traces coupled to the external interconnects to provide an external interface to the IC package.

[0005]

[0005] The routing and interconnect design of an IC package dictates the number of buried metal traces provided in the die-side ETS metallization layer of the package substrate. This affects the area of ​​the metal traces provided in the die-side ETS metallization layer in the horizontal direction (i.e., along the X-axis and Y-axis). This can cause a mismatch in metal (e.g., copper) area, and therefore a mismatch in metal density, between the buried metal traces in the die-side ETS metallization layer and the metal traces in other metallization layers in the package substrate. For example, the metal density of the buried metal traces in the die-side ETS metallization layer may be ten percent (10%) lower than the metal density of the metal traces in another metallization layer(s) in the package substrate. One reason that a mismatch in metal density can occur is due to the metal in the die-side ETS metallization layer being dominated by metal traces, as opposed to, for example, pads and / or ground planes. This asymmetric metal density between the die-size ETS metallization layer and other metallization layers of the package substrate causes a mismatch in coefficient of thermal expansion (CTE) in the package substrate. This CTE mismatch can cause warpage in response to differential expansion and contraction in the horizontal directions (X and Y axis directions) between the die-side ETS metallization layer and another metallization layer(s) in the package substrate. Summary of the Invention

[0006]

[0006] Aspects disclosed herein include an integrated circuit (IC) package employing an auxiliary metal layer coupled to embedded metal traces in a die-side embedded trace substrate (ETS) layer to reduce metal density mismatch. Related manufacturing methods are also disclosed. An IC package is provided that includes a semiconductor die ("die") electrically coupled to a package substrate. The package substrate includes a die-side ETS metallization layer that is adjacently coupled to die interconnects (e.g., raised interconnect bumps) of the die to provide electrical coupling between the die and the package substrate. The die-side ETS metallization layer facilitates providing higher density bump / solder joints with reduced line-and-space ratio (L / S) to provide a higher density electrical interface to the die for higher density signal routing. The embedded metal traces in the die-side ETS metallization layer may be of smaller area than the area of ​​metal interconnects in other metallization layers in the package substrate due to the metal in the die-side ETS metallization layer being occupied by metal traces as opposed to, for example, metal pads or ground planes. This difference in metal area causes a mismatch in metal density between the die-side ETS metallization layer and other metallization layers, which causes a mismatch in their coefficient of thermal expansion (CTE). This mismatch in CTE between the die-side ETS metallization layer and other metallization layers in the package substrate can contribute to increased warpage of the package substrate. Thus, in an exemplary embodiment, to reduce or avoid this mismatch in metal density, an auxiliary (i.e., additional) metal layer having additional metal interconnects formed therein is disposed adjacent to the die-side ETS metallization layer. The additional metal interconnects are vertically bonded to the embedded metal traces in the die-side ETS metallization layer to form increased thickness / density die-side metal interconnects in the package substrate. This can reduce or avoid the need to reduce the thickness of the metal layer in another metallization layer(s) in the package substrate to reduce the mismatch in metal density between the die-side ETS metallization layer and other metallization layer(s) in the package substrate.For example, reducing the thickness of the metal layer in the external metallization layer of a package substrate that supports the external interconnects can lead to increased dimple depth in the metal interconnects therein, which in turn increases the risk of voids in the solder joints that join the metal interconnects to the external interconnects.

[0007]

[0007] As an example, the additional metal interconnects may be provided in an auxiliary metal layer (e.g., an additional copper layer) formed adjacent to an outer surface of the die-sized ETS metallization layer in the manufacture of the IC package. The additional metal interconnects may be bonded to the exposed outer surface of each of the buried metal traces in the die-side ETS metallization layer of the package substrate in the vertical direction such that the additional metal interconnects are disposed between the die-sized ETS metallization layer and the die. As one non-limiting example, the additional metal interconnects may be formed as additional metal plating, such as additional copper plating, on the buried metal traces in the die-sized ETS metallization layer. As another non-limiting example, the additional metal interconnects may also be formed as additional metal traces or metal lines bonded to the buried metal traces in the die-sized ETS metallization layer. The additional metal interconnects bonded to the buried metal traces of the die-side ETS metallization layer that form the die-side metal interconnects of the package substrate may be exposed for connection through openings patterned in a solder resist layer disposed on the auxiliary metal layer. Providing an auxiliary metal layer in the IC package may add height to the IC package in the vertical direction. However, this added height provides the advantage of not having to increase the thickness of one or more metallization layers in the package substrate to avoid or reduce metal density imbalances between the die-side ETS metallization layer and another metallization layer(s) in the package substrate.

[0008]

[0008] In this regard, in one exemplary aspect, an IC package is provided. The IC package includes a package substrate. The package substrate includes a first metallization layer including a first insulating layer, and a first metal layer including one or more first metal traces embedded in the first insulating layer. The IC package also includes a second metal layer disposed adjacent to the first metallization layer. The second metal layer includes one or more second metal interconnects each coupled to a first metal trace of the one or more first metal traces in the first metal layer of the first metallization layer.

[0009]

[0009] In another exemplary aspect, a method for manufacturing an IC package is provided. The method includes forming a package substrate. Forming the package substrate includes forming a first metallization layer, including forming a first insulating layer, and embedding one or more first metal traces in the first insulating layer and forming a first metal layer in the first insulating layer. The method also includes forming one or more second metal interconnects in a second metal layer adjacent to the first metallization layer. The method also includes coupling each of the one or more second metal interconnects in the second metal layer to a first metal trace of the one or more first metal traces in the first metal layer of the first metallization layer. [Brief description of the drawings]

[0010] [Figure 1]

[0010] This is a side view of an integrated circuit (IC) package that includes a semiconductor die ("die") mounted on a package substrate that includes an embedded trace substrate (ETS) metallization layer for providing an electrical interface between the package substrate and the die. [Figure 2A]

[0011] FIG. 1 is a side view of a portion of a package substrate including a die-side ETS metallization layer and an exterior metallization layer having dimples formed in the exterior metal interconnect pads. [Figure 2B]

[0012] FIG. 2B is a side view of a portion of a package substrate having a reduced thickness metal layer in the die-side ETS metallization layer across the thickness of the metal layer in the die-side ETS metallization layer of FIG. 2A and a reduced thickness metal layer in the exterior metallization layer with dimples formed in exterior metal interconnect pads that are deeper than the exterior metal interconnect pads of FIG. 2A . [Figure 3A]

[0013] FIG. 1 is a side view of an exemplary IC package that employs an auxiliary metal layer having additional metal interconnects coupled to embedded metal traces in the die-side ETS metallization layer of a package substrate to avoid or reduce metal density mismatch between the die-side ETS metallization layer and an external metallization layer supporting the external interconnects. [Figure 3B]

[0014] FIG. 3B is an enlarged left side view of the IC package of FIG. 3A. [Figure 3C] FIG. 3B is an enlarged left side view of the IC package of FIG. 3A. [Figure 4]

[0015] FIG. 1C is a top view of an example auxiliary metal layer disposed on a die-side ETS metallization layer of a package substrate showing an additional metal interconnect coupled to a buried metal trace in the die-side ETS metallization layer of the package substrate, the additional metal interconnect being offset inwardly in a vertical direction from the buried metal trace. [Diagram 5]

[0016] FIG. 13 is a side view of another exemplary IC package, which is a stacked die IC package having a second die package stacked on a first die package and electrically connected to the first die package through an interposer substrate in the first die package, wherein the IC package employs an auxiliary metal layer having additional metal interconnects coupled to embedded metal traces in the die-side ETS metallization layer of the package substrate to avoid or reduce metal density mismatch between the die-side ETS metallization layer and an external metallization layer supporting the external interconnects. [Figure 6A]

[0017] 6 is a side view of a first die package of the stacked die IC package of FIG. 5. [Figure 6B]

[0018] FIG. 6B is an enlarged left side view of a first die package of the stacked die IC package of FIG. 6A. [Figure 7]

[0019] FIG. 5 is a flowchart illustrating an exemplary manufacturing process for manufacturing an ETS metallization layer having embedded metal traces, and an auxiliary metal layer having additional metal interconnects coupled to the embedded metal traces in the ETS metallization layer to increase the metal density of the embedded metal traces, including but not limited to the ETS metallization layer packages and auxiliary metal layer packages of FIGS. 3A-6B. [Figure 8A]

[0020] FIG. 5 is a flowchart illustrating another exemplary manufacturing process for fabricating an ETS metallization layer having embedded metal traces and an auxiliary metal layer having additional metal interconnects coupled to the embedded metal traces in the ETS metallization layer to increase the metal density of the embedded metal traces, including but not limited to the ETS metallization layer packages and auxiliary metal layer packages of FIGS. 3A-6B . [Figure 8B] FIG. 5 is a flowchart illustrating another exemplary manufacturing process for fabricating an ETS metallization layer having embedded metal traces and an auxiliary metal layer having additional metal interconnects coupled to the embedded metal traces in the ETS metallization layer to increase the metal density of the embedded metal traces, including but not limited to the ETS metallization layer packages and auxiliary metal layer packages of FIGS. 3A-6B . [Figure 8C] FIG. 5 is a flowchart illustrating another exemplary manufacturing process for fabricating an ETS metallization layer having embedded metal traces and an auxiliary metal layer having additional metal interconnects coupled to the embedded metal traces in the ETS metallization layer to increase the metal density of the embedded metal traces, including but not limited to the ETS metallization layer packages and auxiliary metal layer packages of FIGS. 3A-6B . [Figure 8D]FIG. 5 is a flowchart illustrating another exemplary manufacturing process for fabricating an ETS metallization layer having embedded metal traces and an auxiliary metal layer having additional metal interconnects coupled to the embedded metal traces in the ETS metallization layer to increase the metal density of the embedded metal traces, including but not limited to the ETS metallization layer packages and auxiliary metal layer packages of FIGS. 3A-6B . [Figure 8E] FIG. 5 is a flowchart illustrating another exemplary manufacturing process for fabricating an ETS metallization layer having embedded metal traces and an auxiliary metal layer having additional metal interconnects coupled to the embedded metal traces in the ETS metallization layer to increase the metal density of the embedded metal traces, including but not limited to the ETS metallization layer packages and auxiliary metal layer packages of FIGS. 3A-6B . [Figure 9A]

[0021] 8A-8E depict exemplary manufacturing stages during the manufacture of an ETS metallization layer having an auxiliary additional metal layer according to the manufacturing process of FIGS. 8A-8E. [Figure 9B] 8A-8E depict exemplary manufacturing stages during the manufacture of an ETS metallization layer having an auxiliary additional metal layer according to the manufacturing process of FIGS. 8A-8E. [Figure 9C] 8A-8E depict exemplary manufacturing stages during the manufacture of an ETS metallization layer having an auxiliary additional metal layer according to the manufacturing process of FIGS. 8A-8E. [Figure 9D] 8A-8E depict exemplary manufacturing stages during the manufacture of an ETS metallization layer having an auxiliary additional metal layer according to the manufacturing process of FIGS. 8A-8E. [Figure 9E] 8A-8E depict exemplary manufacturing stages during the manufacture of an ETS metallization layer having an auxiliary additional metal layer according to the manufacturing process of FIGS. 8A-8E. [Figure 9F] 8A-8E depict exemplary manufacturing stages during the manufacture of an ETS metallization layer having an auxiliary additional metal layer according to the manufacturing process of FIGS. 8A-8E. [Figure 9G]8A-8E depict exemplary manufacturing stages during the manufacture of an ETS metallization layer having an auxiliary additional metal layer according to the manufacturing process of FIGS. 8A-8E. [Figure 9H] 8A-8E depict exemplary manufacturing stages during the manufacture of an ETS metallization layer having an auxiliary additional metal layer according to the manufacturing process of FIGS. 8A-8E. [Figure 9I] 8A-8E depict exemplary manufacturing stages during the manufacture of an ETS metallization layer having an auxiliary additional metal layer according to the manufacturing process of FIGS. 8A-8E. [Figure 10]

[0022] FIG. 3 is a block diagram of an exemplary processor-based system that may include components that may include an IC package employing an auxiliary metal layer having additional metal interconnects coupled to embedded metal traces in a die-side ETS metallization layer of a package substrate to avoid or reduce metal density mismatch between the die-side ETS metallization layer and another metallization layer(s), including, but not limited to, the package substrates of FIGS. 3A-6B and 9A-9I, and package substrates according to the exemplary manufacturing processes of FIGS. 7-8E. [Figure 11]

[0023] FIG. 3 is a block diagram of an exemplary wireless communication device including radio frequency (RF) components that may include an IC package employing an auxiliary metal layer having additional metal interconnects coupled to embedded metal traces in a die-side ETS metallization layer of a package substrate to avoid or reduce metal density mismatch between the die-side ETS metallization layer and another metallization layer(s), including, but not limited to, the package substrates of FIGS. 3A-6B and 9A-9I, and package substrates according to the exemplary manufacturing processes of FIGS. 7-8E. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011]

[0024] Some exemplary aspects of the present disclosure will now be described with reference to the drawings. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0012]

[0025] Embodiments disclosed herein include an integrated circuit (IC) package that employs an auxiliary metal layer coupled to embedded metal traces in a die-side embedded trace substrate (ETS) layer to reduce metal density mismatch. Related manufacturing methods are also disclosed. An IC package is provided that includes a semiconductor die ("die") electrically coupled to a package substrate. The package substrate includes a die-side ETS metallization layer coupled adjacent to die interconnects (e.g., raised interconnect bumps) of the die to provide electrical coupling between the die and the package substrate. The die-side ETS metallization layer facilitates providing higher density bump / solder joints with reduced line-and-space ratio (L / S) to provide a higher density electrical interface to the die for higher density signal routing. The embedded metal traces in the die-side ETS metallization layer may be of smaller area than the area of ​​metal interconnects in other metallization layers in the package substrate due to the metal in the die-side ETS metallization layer being occupied by metal traces as opposed to, for example, metal pads or ground planes. This difference in metal area causes a mismatch in metal density between the die-side ETS metallization layer and other metallization layers, which causes a mismatch in their coefficient of thermal expansion (CTE). This mismatch in CTE between the die-side ETS metallization layer and other metallization layers in the package substrate can contribute to increased warpage of the package substrate. Thus, in an exemplary embodiment, to reduce or avoid this mismatch in metal density, an auxiliary (i.e., additional) metal layer having additional metal interconnects formed therein is disposed adjacent to the die-side ETS metallization layer. The additional metal interconnects are vertically bonded to the buried metal traces in the die-side ETS metallization layer to form increased thickness / density die-side metal interconnects in the package substrate. This can reduce or avoid the need to reduce the thickness of the metal layer in another metallization layer(s) in the package substrate to reduce the mismatch in metal density between the die-side ETS metallization layer and other metallization layer(s) in the package substrate.For example, reducing the thickness of the metal layer in the external metallization layer of a package substrate that supports the external interconnects can lead to increased dimple depth in the metal interconnects therein, which in turn increases the risk of voids in the solder joints that join the metal interconnects to the external interconnects.

[0013]

[0026] To avoid or reduce metal density mismatch between the die-side ETS metallization layer and another metallization layer(s) in the package substrate, examples of IC packages employing an auxiliary metal layer having additional metal interconnects coupled to buried metal traces in the die-side ETS metallization layer of the package substrate begin in Figure 3A. Before describing these IC packages, IC packages employing a package substrate having a die-side ETS metallization layer including buried metal traces, but not including an auxiliary metal layer having additional metal interconnects coupled to the buried metal traces, are first described below with reference to Figures 1-2B.

[0014]

[0027] In this regard, FIG. 1 illustrates a cross-sectional schematic side view of an IC assembly 100 including an IC package 102 mounted to a printed circuit board (PCB) 104 using external interconnects 106, such as solder balls. The IC package 102 includes a semiconductor die 108 (also referred to as "IC die 108" or "die 108"), which is mounted to a package substrate 110 via die-to-die bonding and / or an underfill adhesive. The external interconnects 106 are bonded to metal interconnects in the package substrate 110 to provide an electrical interface to the die 108 when the IC package 102 is mounted to the PCB 104. The package substrate 110 includes multiple metallization layers 112(1)-112(3) that include metal interconnects 114(1)-114(3) (e.g., metal traces, metal lines). The metal interconnects 114(1)-114(3) are interconnected to each other to provide signal routing to the die 108 and between the external interconnects 106 and the die 108. Each of the metallization layers 112(1)-112(3) includes an insulating layer 116(1)-116(3) for insulating the metal interconnects 114(1)-114(3). The package substrate 110 includes a first solder resist layer 118 and a second solder resist layer 120. The external interconnects 106 are formed in openings in the first solder resist layer 118 that are coupled to the metal interconnects 114(3) in the bottom metallization layer 112(3).

[0015]

[0028] In this example, the top metallization layer 112(1) is an ETS metallization layer, and the metal interconnects 114(1) are formed as buried metal traces in the insulating layer 116(1). Thus, the metal interconnects 114(1) are also referred to as buried metal traces 114(1). The ETS metallization layer 112(1) facilitates providing a higher density bump / solder joint with a reduced line-and-space ratio (L / S) for electrically coupling the die 108 to the package substrate 110 for signal routing. A raised metal interconnect 122 (e.g., an interconnect solder / metal bump) is formed in contact with the buried metal traces 114(1) embedded in the ETS metallization layer 112(1). Die interconnects 124 (e.g., raised interconnect bumps) disposed on an active surface 126 of die 108 are coupled to metal interconnects 114(1) as buried metal traces 114(1) to provide electrical coupling between die 108 and package substrate 110.

[0016]

[0029] 2A and 2B are provided to further illustrate buried metal traces in an ETS metallization layer, such as buried metal trace 114(1) in ETS metallization layer 112(1) of FIG. 1, coupled to underlying metal interconnects. FIG. 2A is a side view of a portion of a package substrate 200 including an ETS metallization layer 202 configured to be coupled to a die (not shown). Thus, ETS metallization layer 202 may be considered a "die-side" ETS metallization layer. ETS metallization layer 202 includes buried metal traces 204(1)-204(4) embedded in insulating layer 206, which is a layer made of a dielectric material. The embedding of buried metal traces 204(1)-204(4) in insulating layer 206 forms a first metal layer 208 in ETS metallization layer 202. Buried metal traces 204(1)-204(4) are recessed from a top surface 210 of insulating layer 206 as a result of etching during the manufacturing process. A solder resist layer 212 is disposed on the top surface 210 of the insulating layer 206 to insulate and protect the portions of the buried metal traces 204(1)-204(4) that are not connected. Openings 214 are formed in the solder resist layer 212 to expose the buried metal traces 204(3), 204(4) that are to be connected as part of an IC package.

[0017]

[0030] 2A , the package substrate 200 also includes a second metallization layer 216 disposed in a vertical direction (Z-axis direction) below the ETS metallization layer 202. The second metallization layer 216 includes a second metal layer 218 including a second metal interconnect 220 formed on a bottom surface 222 of the insulating layer 206 of the ETS metallization layer 202. The second metal interconnect 220 is coupled to the buried metal trace 204(1) through a vertical interconnect access (via) 224 (e.g., a metal pillar, metal trace, or other metal interconnect) that extends in a vertical direction (Z-axis direction) between the second metal interconnect 220 and the buried metal trace 204(1). Signals may be routed within the package substrate 200 between the buried metal trace 204(1) and the second metal interconnect 220. In this example, the second metallization layer 216 is configured to facilitate the formation of external interconnects (e.g., solder bumps, ball grid array (BGA) interconnects) to provide an external interface to the package substrate 200 and its IC package. The second metallization layer 216 is an external metallization layer of the package substrate 200. In this regard, an opening 226 is formed to expose a bottom surface 228 of the second metal interconnect 220 such that an external interconnect may be formed within the opening 226 and a solder joint may be formed between the external interconnect and the second metal interconnect 220. As shown in FIG. 2A, a dimple 230 is formed in the bottom surface 228 of the second metal interconnect 220 as a result of etching in the manufacture of the package substrate 200.

[0018]

[0031] In the example package substrate 200 of FIG. 2A, the dimple 230 is not deep enough D1 from the bottom surface 228 to risk voids in the solder joints coupling the second metal interconnects 220 to the external interconnects, which may risk the integrity of the connection between the second metal interconnects 220 and the external interconnects. This is because the height H1 (i.e., thickness) of the second metal interconnects 220 in the vertical direction (Z-axis direction) is not low enough, so that etching during manufacturing would form the dimples 230 at a greater depth D1 that would risk solder joint voids. The height H1 of the second metal interconnects 220 is based on the height H2 (i.e., thickness) of the first metal layer 208 of the ETS metallization layer 202 in the vertical direction (Z-axis direction). This is to reduce or mitigate the metal density mismatch between the first metal layer 208 in the ETS metallization layer 202 and the second metal interconnects 220 in the second metallization layer 216. In this example, because the ETS metallization layer 202 is a die-side metallization layer bonded to the die, the area of ​​the buried metal traces 204(1)-204(4) may be smaller than the area of ​​the second metal interconnects 220 in the second metallization layer 216 due to the metal in the ETS metallization layer 202 being dominated by metal traces as opposed to, for example, metal pads or ground planes. This metal density mismatch may cause a coefficient of thermal expansion (CTE) mismatch between the ETS metallization layer 202 and the second metallization layer 216, which may contribute to increased warpage of the package substrate 200. To reduce or avoid this metal density mismatch between the ETS metallization layer 202 and the second metallization layer 216, the height H1 of the second metal layer 218 of the second metallization layer 216 is reduced from the height H2 of the first metal layer 208 of the ETS metallization layer 202. The reduction in height H1 of the second metal layer 218 of the second metallization layer 216 reduces the metal density (volume) of the second metallization layer 216 to attempt to balance the metal density between the second metallization layer 216 and the ETS metallization layer 202. For example, the height H2 of the first metal layer 208 may be 18 micrometers (μm) and the height H1 of the second metal layer 218 may be 15 μm.

[0019]

[0032] As it becomes desirable to further reduce the L / S ratio of the buried metal traces 204(1)-204(4) in the ETS metallization layer 202 to support denser interconnections with the die, it may become necessary to reduce the height H2 (i.e., thickness) of the first metal layer 208 in the ETS metallization layer 202. This is due to limitations of the patterning process during the manufacture of the ETS metallization layer 202. This is illustrated in a side view of an example package substrate 240 in FIG. 2B, which is similar to the package substrate 200 in FIG. 2A. As shown in FIG. 2B, the package substrate 240 includes buried metal traces 244(1)-244(4) embedded in an insulating layer 246, which is a layer made of a dielectric material that includes the ETS metallization layer 242. The embedding of the buried metal traces 244(1)-244(4) in the insulating layer 246 forms a first metal layer 248 in the ETS metallization layer 242(1). A solder resist layer 252 is disposed on the insulating layer 246 to insulate and protect the portions of the buried metal traces 204(1)-204(4) that are not connected. The package substrate 240 also includes a second metallization layer 256 disposed in the vertical direction (Z-axis direction) below the ETS metallization layer 242. The second metallization layer 256 includes a second metal layer 258 that includes a second metal interconnect 260 formed on a bottom surface 262 of the insulating layer 206 of the ETS metallization layer 202. The second metal interconnect 220 is coupled to the buried metal trace 204(1) through a vertical interconnect access (via) 264 (e.g., a metal pillar, metal trace, or other metal interconnect) that extends in the vertical direction (Z-axis direction) between the second metal interconnect 220 and the buried metal trace 244(1).

[0020]

[0033] 2B, the second metal interconnect 260 has a height H3 (i.e., thickness) based on the height H4 (i.e., thickness) of the first metal layer 248 of the ETS metallization layer 242 in the vertical direction (Z-axis direction). To reduce or avoid this metal density mismatch between the ETS metallization layer 242 and the second metallization layer 256, the height H3 of the second metal layer 258 of the second metallization layer 256 is reduced from the height H4 of the first metal layer 248 of the ETS metallization layer 242. The reduction in the height H3 of the second metal layer 258 of the second metallization layer 256 reduces the metal density (volume) of the second metallization layer 256 to attempt to balance the metal density between the second metallization layer 256 and the ETS metallization layer 242. For example, the height H4 of the first metal layer 248 may be 12 micrometers (μm) and the height H3 of the second metal layer 218 may be 10 μm.

[0021]

[0034] As shown in FIG. 2B, as a result of etching in the manufacture of the package substrate 240, the dimple 270 is formed on the bottom surface 268 of the second metal interconnect 260. However, in this case, the dimple 270 is at a sufficient depth D2 from the bottom surface 268 of the second metallization layer 256 to risk voids in the solder joint coupling the second metal interconnect 260 to the external interconnect, which may risk the integrity of the connection between the second metal interconnect 260 and the external interconnect. This is because the height H3 (i.e., thickness) of the second metal interconnect 260 in the vertical direction (Z-axis direction) is reduced, making the second metal interconnect 260 thinner. The metal etch that occurs in the manufacture of the package substrate 200 and etches the bottom surface 268 of the second metal interconnect 260 provides the dimple 270 with a greater depth D2 from the bottom surface 268 of the second metal interconnect 260. This increases the risk of voids in the solder joint formed in contact with the second metal interconnect 260. If the height H3 (i.e., thickness) of the second metal interconnect 260 is increased to reduce the depth D2 of the dimple 270, this will increase any metal density mismatch between the second metallization layer 256 and the ETS metallization layer 242 unless the height H4 (i.e., thickness) of the first metal layer 248 in the ETS metallization layer 242 is increased. This may not be possible, but still achieve the desired L / S of the embedded metal traces 244(1)-244(4) in the ETS metallization layer 242.

[0022]

[0035] In this regard, while it may be desirable to reduce the thickness of metal layers in ETS metallization layers, such as the die-side ETS metallization layers of a package substrate, it is also desirable to avoid the need to overly reduce the thickness of metal layers in other metallization layers, including in exterior metallization layers, to reduce or avoid metal density mismatches. As discussed above in the example package substrate 240 of FIG. 2B, reducing the thickness of the exterior metallization layers may carry the risk of voids in solder joints formed in contact with metal interconnects in the exterior metallization layers that are coupled to external interconnects (e.g., BGA interconnects).

[0023]

[0036] In this regard, Figures 3A and 3B are side views of an exemplary IC package 300 including a package substrate 302 employing a second metal layer 304 (e.g., a copper layer), referred to herein as "auxiliary metal layer 304," having additional second metal interconnects 306 to reduce or avoid metal density mismatch between the ETS metallization layer 308 and a third exterior metallization layer 310. The auxiliary metal layer 304, in this example, is external to the package substrate 302 and is formed adjacent to and in contact with the ETS metallization layer 308. In this example, as shown in Figure 3A, the ETS metallization layer 308 is a die-side metallization layer disposed adjacent to a bonded die 312 within the IC package 300. Also in this example, the third metallization layer 310 is an external interconnect side metallization layer that facilitates the formation of external interconnects 314 (e.g., solder bumps, metal pillars, BGA interconnects) coupled to the second metal interconnects 316(1), 316(2) in the third external metallization layer 310. As described in more detail below and shown in FIG. 3A , the additional metal interconnects 306(1)-306(3) in the auxiliary metal layer 304 are vertically (Z-axis direction) coupled to respective buried metal traces 318(1)-318(3) embedded in the insulating layer 320 of the die-side ETS metallization layer 308 to form die-side metal interconnects 322(1)-322(3) of increased thickness / density in the package substrate 302. This may reduce or avoid the need to reduce the height H5 (i.e., thickness) of the third metal layer 323 of the third exterior metallization layer 310 to avoid or reduce a metal density mismatch between the die-side ETS metallization layer 308 and the third exterior metallization layer 310 in the package substrate 302. For example, reducing the height H5 of the third metal layer 323 in the third exterior metallization layer 310 may lead to an increase in dimple depth in the second metal interconnects 316(1), 316(2) in the third metal layer 323, which in turn increases the risk of voids in the solder joints coupling the second metal interconnects 316(1), 316(2) to the exterior interconnects 314.

[0024]

[0037] 3A and 3B, the buried metal traces 318(1)-318(3) embedded in the insulating layer 320 of the ETS metallization layer 308 form a metal layer 324 within the insulating layer 320. The height H6 (i.e., thickness) of the metal layer 324 controls the maximum height of the buried metal traces 318(1)-318(3). Thus, the height H6 of the metal layer 324 of the ETS metallization layer 308 affects the metal density of the buried metal traces 318(1)-318(3). In this example, the height H6 of the metal layer 324 of the ETS metallization layer 308 is less than the height H5 of the third metal layer 323 of the third outer metallization layer 310. This may allow for tighter (lower L / S) of the formed buried metal traces 318(1)-318(3) embedded in the insulating layer 320 in the ETS metallization layer 308 to support a higher connection density to the package substrate 302. However, this also causes the metal density of the ETS metallization layer 308 to be lower than the metal density of the third exterior metallization layer 310. Therefore, instead of increasing the height H5 of the third metal layer 323 of the third exterior metallization layer 310 to compensate for this metal density imbalance, an auxiliary metal layer 304 is provided and disposed above the ETS metallization layer 308 in the vertical direction (Z-axis direction), and the additional metal interconnects 306 of the auxiliary metal layer 304 are disposed above the ETS metallization layer 308 in the vertical direction (Z-axis direction), respectively. The additional metal interconnects 306 of the auxiliary metal layer 304 are bonded to the respective buried metal traces 318(1)-318(3) of the ETS metallization layer 308 in the vertical direction (Z-axis direction). The combination of the additional metal interconnects 306 of the auxiliary metal layer 304 bonded to the respective buried metal traces 318(1)-318(3) of the ETS metallization layer 308 forms die-side metal interconnects 322(1)-322(3) with increased metal density to avoid or reduce metal density mismatch, and therefore CTE mismatch, between the ETS metallization layer 308 and the third exterior metallization layer 310 to reduce or avoid warpage of the package substrate 302.

[0025]

[0038] 3A, the IC package 300 includes a die 312. As shown in FIG. 3B, the die 312 is coupled to the package substrate 302 through a die interconnect 326 (e.g., a raised interconnect bump). More specifically, the die interconnect 326 extending from an active side 328 of the die 312 is coupled to another embedded metal trace 330 embedded in an insulating layer 320 of the ETS metallization layer 308. Selected die interconnects 326 designated to provide an external signal interface to the IC package 300 may be coupled through the ETS metallization layer 308 to second metal interconnects 316(1), 316(2) in the third external metallization layer 310 to provide a signal routing path between the die 312 and the external interconnect 314. In this example, as shown in FIG. 3A, the auxiliary metal layer 304 is disposed both inside and outside the vertical region in the vertical direction (Z-axis direction) between the die 312 and the package substrate 302. The additional metal interconnects 306(1), 306(2) of the auxiliary metal layer 304 are disposed outside the vertical region in the vertical direction (Z-axis direction) between the die 312 and the package substrate 302. This may be because the buried metal traces 318(1), 318(2) coupled to the additional metal interconnects 306(1), 306(2) are for providing a connection that is not directly coupled to the die 312, such as for a ground plane. The additional metal interconnect 306(3) of the auxiliary metal layer 304 is disposed inside the vertical region in the vertical direction (Z-axis direction) between the die 312 and the package substrate 302. This may be because the buried metal traces 318(3) coupled to the additional metal interconnects 306(3) are for providing a connection to the die 312 through the die interconnect 326.

[0026]

[0039] 3A and 3B, in this example, the solder resist layer 332 is disposed adjacent to the first outer surface 334 of the insulating layer 320 of the ETS metallization layer 308. The auxiliary metal layer 304 is also disposed adjacent to the first outer surface 334 of the insulating layer 320 of the ETS metallization layer 308. The solder resist layer 332 is disposed above the additional metal interconnects 306(1)-306(3) in the auxiliary metal layer 304. Thus, the auxiliary metal layer 304 may be considered to be disposed within the solder resist layer 332. The additional metal interconnects 306(1)-306(3) are not included in or embedded in the insulating layer 320 of the ETS metallization layer 308 in this example.

[0027]

[0040] As explained above, the height H6 of the metal layer 324 (or its buried metal traces 318(1)-318(3)) of the ETS metallization layer 308 is less than the height H5 of the third metal layer 323 (or its second metal interconnects 316(1)-316(3)) of the third outer metallization layer 310. The coupling of the additional metal interconnects 306(1)-306(3) to the respective buried metal traces 318(1)-318(3) avoids or reduces the metal density imbalance between the ETS metallization layer 308 and the third outer metallization layer 310. For example, the height H6 of the metal layer 324 of the ETS metallization layer 308 in the vertical direction (Z-axis direction) can be 8-14 micrometers (μm). As another example, the height H5 of the third metal layer 323 in the third outer metallization layer 310 can be 10-20 μm. 3B, the height H7 of auxiliary metal layer 304 (or its additional metal interconnects 306(1)-306(3)) in the vertical direction (Z-axis direction) can be 1-5 μm. Thus, as an example, the ratio of height H6 of metal layer 324 of ETS metallization layer 308 to height H7 of auxiliary metal layer 304 can be at least 8 / 5. As yet another example, the ratio of height H6 of metal layer 324 of ETS metallization layer 308 to height H5 of third metal layer 323 in third outer metallization layer 310 can be at least 8 / 20.

[0028]

[0041] Thus, in these examples, the additional metal interconnects 306(1)-306(3) coupled to the buried metal traces 318(1)-318(3) increase the effective height of the buried metal traces 318(1)-318(3) to a combination of height H6 and height H7 (e.g., 20 μm) to provide effective die-side metal interconnects 322(1)-322(3) with increased metal density. In a 7 / 9 L / S example of the buried metal traces 318(1)-318(3) in the metal layer 323 of the ETS metallization layer 308, the height H6 of the metal layer 324 of the ETS metallization layer 308 may be 14 μm, the height H5 of the third metal layer 324 in the third outer metallization layer 310 may be 15 μm, and the height H7 of the auxiliary metal layer 304 may be 4 μm. In an example of 6 / 8 L / S of buried metal traces 318(1)-318(3) in metal layer 324 of ETS metallization layer 308, height H6 of metal layer 324 of ETS metallization layer 308 may be 12 μm, height H5 of third metal layer 323 in third outer metallization layer 310 may be 15 μm, and height H7 of auxiliary metal layer 304 may be 4 μm.

[0029]

[0042] It should be noted that the ends of the buried metal traces 318(1)-318(2) may be recessed below the outer top surface 334 of the insulating layer 320 as a result of the metal etching of the auxiliary metal layer 304 to form the additional metal interconnects 306(1)-306(3) in the fabrication of the ETS metallization layer 308 in the package substrate 302 of FIGS. 3A and 3B. As described in more detail below in the fabrication process, these recesses formed in the buried metal traces 318(1)-318(3) are the result of using the buried metal traces 318(1)-318(3) as an alignment feature for etching the auxiliary metal layer 504 to leave portions present to form the additional metal interconnects 306(1)-306(3). The other buried metal traces 518(2), 518(3) in the ETS metallization layer also have inner and outer metal portions that form recesses like the buried metal trace 518(1).

[0030]

[0043] As shown in FIG. 3C , the first outer surface 334 of the insulating layer 320 is disposed in a first horizontal plane P1 in the horizontal direction (X-axis and Y-axis directions). The embedded metal trace 318(1) has an inner metal portion 336(1) having a top outer surface 338 that extends vertically (Z-axis direction) to the first horizontal plane P1, and the inner metal portion 336(1) may be flush with the top outer surface 334 of the insulating layer 320. The inner metal portion 336(1) of the embedded metal trace 318(1) has a height H6 from a bottom surface 338 of the embedded metal trace 318(1). The bottom surface 338 of the embedded metal trace 318(1) is disposed in a second horizontal plane P2 in the horizontal direction (X-axis and Y-axis directions). The embedded metal trace 318(1) also has an outer metal portion 336(2) that surrounds the inner metal portion 336(1). The outer metal portion 336(2) of the embedded metal trace 318(1) has a top outer surface 340 that does not extend vertically (in the Z-axis direction) to the first horizontal plane P1, but extends vertically (in the Z-axis direction) to a third horizontal plane P3 below the first horizontal plane P1. The outer metal portion 336(2) of the embedded metal trace 318(1) also shares a same bottom surface 338 with the inner metal portion 336(1) disposed in the second horizontal plane P2. The outer metal portion 336(2) of the embedded metal trace 318(1) has a height H8 from the bottom surface 338 to its top outer surface 340, which is less than the height H6 of the inner metal portion 336(1) of the embedded metal trace 318(1). In this manner, a recess 342 is formed between the intersection of the inner metal portion 336(1) and the outer metal portion 336(2) of the embedded metal trace 318(1). The recess 342 has a width W1 in the horizontal direction (X-axis and / or Y-axis direction), which may be 10 μm, as an example.

[0031]

[0044] Figure 4 is a top view of the auxiliary metal layer 304 in the package substrate 302 of Figures 3A-3C disposed on the die-side ETS metallization layer 308. Figure 4 shows the additional metal interconnect 306 disposed on and above the buried metal trace 318 in the die-side ETS metallization layer 308. In Figure 4, the die-side ETS metallization layer 308 is disposed below the auxiliary metal layer 304 in the vertical direction (Z-axis direction). Figure 4 also shows the offset and recess 342 between the additional metal interconnect 306 and the outer metal portion 336(2) of the buried metal trace 318.

[0032]

[0045] IC packages including package substrates employing auxiliary metal layers having additional metal interconnects coupled to embedded metal traces in the die-side ETS metallization layer to avoid or reduce metal density mismatches may also be provided in other types of IC packages. For example, FIG. 5 is a side view of a stacked-die IC package 500 that may include an auxiliary metal layer having additional metal interconnects coupled to embedded metal traces in the die-side ETS metallization layer 508 to avoid or reduce metal density mismatches between the die-side ETS metallization layer 508 and a third external metallization layer 510 that supports external interconnects 514.

[0033]

[0046] 5, a stacked-die IC package 500 includes multiple dies 512(1), 512(2) contained in respective die packages 550(1), 550(2) and stacked on top of each other in a vertical direction (Z-axis direction). A first die package 550(1) of the stacked-die IC package 500 includes a die 512(1) coupled to a package substrate 502. In this example, the package substrate 502 includes a first top ETS metallization layer 508(1) disposed on a core substrate 509. The core substrate 509 is disposed on a bottom third exterior metallization layer 510. The ETS metallization layer 508 provides an electrical interface for signal routing to the first die 512(1). The first die 512(1) is coupled to die interconnects 526 (e.g., raised metal bumps) electrically coupled to embedded metal traces 518(1) in the ETS metallization layer 508. Buried metal traces 518 in the ETS metallization layer 508 are coupled to metal interconnects 519 in the core substrate 509, which are in turn coupled to metal interconnects 516 in the third external metallization layer 510. In this manner, the package substrate 502 provides interconnects between its metallization layers 508, 510 and the core substrate 509 to provide signal routing to the first die 512(1). External interconnects 514 (e.g., ball grid array (BGA) interconnects) are coupled to metal interconnects 516 in the third external metallization layer 510 to provide interconnects through the package substrate 502 to the first die 512(1) through die interconnects 526. In this example, a first active side 552(1) of the first die 512(1) is adjacent to and coupled to the package substrate 502, and more specifically, to the ETS metallization layer 508 of the package substrate 502.

[0034]

[0047] In the example stacked die IC package 500 of FIG. 5, a second die package 550(2) is provided and coupled to the first die package 550(1) to support multiple dies. For example, the first die 512(1) in the first die package 550(1) may include an application processor, and the second die 512(2) may be a memory die, such as a dynamic random access memory (DRAM) die, that provides memory support for the application processor. In this regard, in this example, the first die package 550(1) also includes an interposer substrate 554 disposed adjacent to a second non-active side 552(2) of the first die 512(1) and on a package mold 556 that encapsulates the first die 512(1). The interposer substrate 554 also includes one or more metallization layers 558, each including an external metal interconnect 560, to provide interconnection to the second die 512(2) in the second die package 550(2). Second die package 550(2) is physically and electrically coupled to first die package 550(1) by being coupled to interposer substrate 554 through external metal interconnects 560 (e.g., solder bumps, BGA interconnects). External interconnects 562 are coupled to external metal interconnects 560 in interposer substrate 554.

[0035]

[0048] Vertical interconnects 564 (e.g., metal vertical interconnect accesses (vias), such as metal pillars, metal posts, through-mold vias (TMVs), etc.) are disposed within the package mold 556 of the first die package 550(1) to provide interconnects for routing signals from the second die 512(2) through the external interconnects 562 and the interposer substrate 554 to the first die 512(1). The vertical interconnects 564 extend in the vertical direction (Z-axis direction) in this example from a first bottom surface 566 of the interposer substrate 554 to a first top surface 568 of the package substrate 502. The vertical interconnects 564 are coupled to external metal interconnects 560 within the interposer substrate 554 adjacent to the bottom surface 566 of the interposer substrate 554. The vertical interconnects 564 are also coupled to buried metal traces 518 in the ETS metallization layer 508 of the package substrate 502 adjacent a first top surface 568 of the package substrate 502. In this manner, the vertical interconnects 564 provide a bridge for an interconnect, such as an input / output (I / O) connection, between the interposer substrate 554 and the package substrate 502. This provides a signal routing path between the second die 512(2) in the second die package 550(2) and the first die 512(1) in the first die package 550(1) through the package substrate 502 to the external interconnects 514.

[0036]

[0049] A second auxiliary metal layer may also be provided in the stacked die IC package 500 of FIG. 5 and disposed adjacent to the ETS metallization layer 508 of the package substrate 502 between the ETS metallization layer 508 and the first die 512(1). The auxiliary metal layer may include additional metal interconnects each coupled to embedded metal traces 518 in the ETS metallization layer 508 to provide connectivity while increasing the metal density of the ETS metallization layer 508. For example, the die interconnects 526 may be coupled to the additional metal interconnects to the auxiliary metal layer to couple the first die 512(1) to the ETS metallization layer 508 of the package substrate 502. As another example, the vertical interconnects 564 may be coupled to the additional metal interconnects and the auxiliary metal layer to couple the second die 512(2) in the second die package 550(2) to the ETS metallization layer 508 of the package substrate 502 through the interposer substrate 554.

[0037]

[0050] In this regard, Figures 6A and 6B are side views of the stacked-die IC package 500 of Figure 5 showing a package substrate 502 employing an auxiliary metal layer 504 (e.g., a copper layer) having additional metal interconnects 506 to reduce or avoid metal density mismatch between the ETS metallization layer 508 and a third outer metallization layer 510. The second auxiliary metal layer 504, in this example, is external to the package substrate 502 and is formed adjacent to and in contact with the ETS metallization layer 508. In this example, as shown in Figure 6A, the ETS metallization layer 508 is a die-side metallization layer disposed adjacent to a bonded first die 512(1) in the IC package 500. Also in this example, the third exterior metallization layer 510 is an exterior interconnect side metallization layer that facilitates the formation of exterior interconnects 514 (e.g., solder bumps, metal pillars, BGA interconnects) that are coupled to the second metal interconnects 516(1), 516(2) in the third exterior metallization layer 510. As described in more detail below and shown in FIG. 6A , the additional metal interconnects 506(1)-506(3) in the auxiliary metal layer 504 are vertically (Z-axis direction) coupled to buried metal traces 518(1)-518(3) embedded in the insulating layer 520 of the die-side ETS metallization layer 508 to form die-side metal interconnects 522(1)-522(3) of increased thickness / density in the package substrate 502. This may reduce or avoid the need to reduce the height H9 (i.e., thickness) of the third metal layer 523 of the third exterior metallization layer 510 to avoid or reduce a metal density mismatch between the die-side ETS metallization layer 508 and the third exterior metallization layer 510 in the package substrate 502. For example, reducing the height H9 of the third metal layer in the third exterior metallization layer 510 may lead to an increase in dimple depth in the second metal interconnects 516(1), 516(2) in the third metal layer 523, which in turn increases the risk of voids in the solder joints coupling the second metal interconnects 516(1), 516(2) to the exterior interconnects 514.

[0038]

[0051] 6A and 6B, buried metal traces 518(1)-518(3) embedded in insulating layer 520 of ETS metallization layer 508 form metal layer 524 within insulating layer 520. The height H 10 (i.e., thickness) controls the maximum height of the buried metal traces 518(1)-518(3). Thus, the height H of the metal layer 524 of the ETS metallization layer 508 10 affects the metal density of the buried metal traces 518(1)-518(3). In this example, the height H 10 is lower than the height H9 of the third metal layer 523 of the third outer metallization layer 510. This may allow tighter (lower) L / S of the formed buried metal traces 518(1)-518(3) embedded in the insulating layer 520 in the ETS metallization layer 508 to support a higher connection density to the package substrate 502. However, this also causes the metal density of the ETS metallization layer 508 to be lower than the metal density of the third outer metallization layer 510. Therefore, instead of increasing the height H9 of the third metal layer 523 of the third outer metallization layer 510 to compensate for this metal density imbalance, an auxiliary metal layer 504 is provided and disposed on the ETS metallization layer 308 in the vertical direction (Z-axis direction), and the additional metal interconnects 506 of the auxiliary metal layer 504 are coupled to the respective buried metal traces 518(1)-518(3). For example, the additional metal interconnects 506 of the auxiliary metal layer 504 may be directly bonded in the vertical direction (Z-axis direction) to respective buried metal traces 518(1)-518(3) of the ETS metallization layer 508. The combination of the additional metal interconnects 506 of the auxiliary metal layer 504 bonded to respective buried metal traces 518(1)-518(3) forms die-side metal interconnects 522(1)-522(3) with increased metal density to avoid or reduce metal density mismatch, and therefore CTE mismatch, between the ETS metallization layer 508 and the third exterior metallization layer 510 to reduce or avoid warpage of the package substrate 502.

[0039]

[0052] Referring to FIG. 6A, the stacked die IC package 500 includes a first die 512(1). As shown in FIG. 6B, the first die 512(1) is coupled to the package substrate 502 through die interconnects 526 (e.g., raised interconnect bumps). More specifically, the die interconnects 526 extending from an active side 528 of the first die 512(1) are coupled to other embedded metal traces 530 embedded in an insulating layer 520 of the ETS metallization layer 508. Selected die interconnects 526 designated to provide an external signal interface to the stacked die IC package 500 may be coupled through the ETS metallization layer 508 to second metal interconnects 516(1), 516(2) in the third external metallization layer 510 to provide a signal routing path between the first die 512(1) and the external interconnects 514. In this example, as shown in FIG. 6A, the auxiliary metal layer 504 is disposed both inside and outside the vertical region in the vertical direction (Z-axis direction) between the first die 512(1) and the package substrate 502. The additional metal interconnects 506(1), 506(2) of the auxiliary metal layer 504 are disposed outside the vertical region in the vertical direction (Z-axis direction) between the first die 512(1) and the package substrate 502. This may be because the buried metal traces 518(1), 318(2) coupled to the additional metal interconnects 506(1), 506(2) are for providing a non-direct connection to the first die 512(1), such as for a ground plane. The additional metal interconnects 506(3) of the auxiliary metal layer 504 are disposed inside the vertical region in the vertical direction (Z-axis direction) between the first die 512(1) and the package substrate 502. This may be because the buried metal trace 518(3), which is coupled to the additional metal interconnect 506(3), is for providing a connection to the first die 512(1) through the die interconnect 526.

[0040]

[0053] 6A and 6B, in this example, a solder resist layer 532 is disposed adjacent to a first outer surface 534 of an insulating layer 520 of an ETS metallization layer 508. An auxiliary metal layer 504 is also disposed adjacent to a first outer surface 534 of an insulating layer 520 of an ETS metallization layer 508. The solder resist layer 532 is disposed over additional metal interconnects 506(1)-506(3) in the auxiliary metal layer 504. Thus, the auxiliary metal layer 504 may be considered to be disposed within the solder resist layer 532. The additional metal interconnects 506(1)-506(3) are not included in or embedded in the insulating layer 520 of an ETS metallization layer 508 in this example.

[0041]

[0054] As explained above, the height H of the metal layer 524 (or its embedded metal traces 518(1)-518(3)) of the ETS metallization layer 508 10 is less than the height H9 of the third metal layer 523 (or its second metal interconnects 516(1)-516(3)) of the third outer metallization layer 510. The coupling of the additional metal interconnects 506(1)-506(3) to their respective buried metal traces 518(1)-518(3) avoids or reduces a metal density imbalance between the ETS metallization layer 508 and the third outer metallization layer 510. For example, the height H 10 As another example, the height H9 of the third metal layer 523 in the third outer metallization layer 510 can be 10 to 20 μm. As another example, the height H of the auxiliary metal layer 504 (or its additional metal interconnects 506(1)-506(3)) in the vertical direction (Z-axis direction) can be 10 to 20 μm, as shown in FIG. 5B. 11 Therefore, for example, the height H of the auxiliary metal layer 504 may be 1 to 5 μm. 11 5. Height H of metal layer 524 of ETS metallization layer 508 relative to 10 As yet another example, the ratio of the height H9 of the third metal layer 523 in the third metallization layer 510 to the height H of the metal layer 524 in the ETS metallization layer 508 may be at least 8 / 5. 10 The ratio may be at least 8 / 20.

[0042]

[0055] Thus, in these examples, the additional metal interconnects 506(1)-506(3) coupled to the buried metal traces 518(1)-518(3) increase the effective height of the buried metal traces 518(1)-518(3) by a height H 10 and height H 11 (e.g., 20 μm) to provide effective die-side metal interconnects 522(1)-522(3) with increased metal density. In an example of 7 / 9 L / S of buried metal traces 518(1)-518(3) in metal layer 524 of ETS metallization layer 508, the height H 10 In the example of a 6 / 8 L / S of buried metal traces 518(1)-518(3) in metal layer 524 of ETS metallization layer 508, height H 10 may be 12 μm, the height H9 of the third metal layer 523 in the third outer metallization layer 510 may be 15 μm, and the height H 11 can be 4 μm.

[0043]

[0056] Using the buried metal trace 518(1) of FIG. 6B as an example, it should be noted that as a result of the metal etching of the auxiliary metal layer 504 to form the additional metal interconnect 506(1) in the fabrication of the ETS metallization layer 508 in the package substrate 502, the outer metal portion 536(1) of the buried metal trace 518(1) may be recessed below the first outer surface 534 of the insulating layer 520. The inner metal portion 536(2) of the buried metal trace 518(1) extends in the same plane as the first outer surface 534 of the insulating layer 520. This provides a recess 542 in the buried metal trace 518(1), as described above with respect to the buried metal traces 318(1)-318(3) in the ETS metallization layer 508 of FIGS. 3B and 3C. The recess 542 formed in the buried metal trace 518(1) is a result of using the buried metal trace 518(1) as an alignment feature for etching the auxiliary metal layer 504 to leave a portion present to form the additional metal interconnect 506(1). The other buried metal traces 518(2), 518(3) in the ETS metallization layer 508 also have inner and outer metal portions that form recesses like the buried metal trace 518(1), and the additional metal interconnects 506(2), 506(3) are formed by etching the auxiliary metal layer 504 in openings formed over the buried metal traces 518(2), 518(3).

[0044]

[0057] It should be noted that other details discussed above with respect to the buried metal traces 318(1)-318(3) in the ETS metallization layer 308 of FIGS. 3A-3C are also applicable to the buried metal traces 518(1)-518(3) in the ETS metallization layer 508 of FIGS. 6A and 6B.

[0045]

[0058] A manufacturing process may be employed to fabricate package substrates and their ETS metallization layers having buried metal traces coupled to metal interconnects to reduce impedance of signal paths, including but not limited to the package substrates 302 and 502 of Figures 3-6B, respectively. In this regard, Figure 7 is a flow chart illustrating an exemplary manufacturing process 700 for fabricating an ETS metallization layer having an auxiliary metal layer that may be included as a die-side ETS metallization structure in a package substrate of an IC package, where additional metal interconnects are formed in the auxiliary metal layer and coupled to the buried metal traces in the ETS metallization layer to increase the metal density of the buried metal traces, including but not limited to the package substrates 302, 502 of Figures 3A-6B. The manufacturing process 700 of Figure 7 will be described with respect to the IC packages 300, 500 of Figures 3A-3C and 6A-6B.

[0046]

[0059] In this regard, and with reference to FIG. 7, a step in a manufacturing process 700 includes forming a package substrate 302, 502 (block 702 of FIG. 7). Forming the package substrate 302, 502 may include forming a first ETS metallization layer 308, 508 (block 704 of FIG. 7). The first metallization layer 308, 508 is an ETS metallization layer. Forming the first metallization layer 308, 508 includes forming a first insulating layer 320, 520 of a dielectric material (block 706 of FIG. 7) and then embedding the first metal traces 318(1)-318(3), 518(1)-518(3) in the first insulating layer 320, 520, thereby forming a first metal layer 324, 524 in the first insulating layer 320, 520 (block 708 of FIG. 7). The next step in the manufacturing process 700 includes forming one or more second additional metal interconnects 306(1)-306(3), 506(1)-506(3) in the second auxiliary metal layer 304, 504 as an auxiliary metal layer 304, 504 adjacent to the first metallization layer 308, 508 (block 710 of FIG. 7 ). The next step in the manufacturing process 700 includes bonding each of the one or more second additional metal interconnects 306(1)-306(3), 506(1)-506(3) in the second auxiliary metal layer 304, 504 to a first metal trace 318(1)-318(3), 518(1)-518(3) of the one or more first metal traces 318(1)-318(3), 518(1)-518(3) in the first metal layer 324, 524 of the first metallization layer 308, 508 (block 712 of FIG. 7 ).

[0047]

[0060] Other manufacturing processes can also be employed to fabricate an ETS metallization layer with an auxiliary metal layer that may be included as a die-side ETS metallization structure of a package substrate of an IC package, where additional metal interconnects are formed in the auxiliary metal layer and coupled to the buried metal traces in the ETS metallization layer to increase the metal density of the buried metal traces, including but not limited to, the package substrates 302, 502 of Figures 3A-6B. In this regard, Figures 8A-8E are a flow chart illustrating another exemplary manufacturing process 800 for fabricating an ETS metallization layer with an auxiliary metal layer that may be included as a die-side ETS metallization structure in a package substrate of an IC package, where additional metal interconnects are formed in the auxiliary metal layer and coupled to the buried metal traces in the ETS metallization layer to increase the metal density of the buried metal traces, including but not limited to, the package substrates 302, 502 of Figures 3A-6B. Figures 9A-9I are exemplary manufacturing stages 900A-900I during the fabrication of an ETS metallization layer with an auxiliary metal layer as part of a package substrate according to the manufacturing process 800 of Figures 8A-8E. The manufacturing process 800 shown in manufacturing steps 900A-900I of Figures 9A-9I refers to the ETS metallization 308 having the auxiliary metal layer 304 in the package substrate 302 of Figures 3A-3C. However, the manufacturing process 800 of Figures 8A-8E is also applicable to fabricating the ETS metallization 508 having the auxiliary metal layer 504 in the package substrate 502 of Figures 6A-6B, as shown in manufacturing steps 900A-900I of Figures 9A-9I.

[0048]

[0061] In this regard, as shown in manufacturing stage 900A of FIG. 9A, a first exemplary step in manufacturing process 800 is to prepare to fabricate ETS metallization layer 308. The first step in forming ETS metallization layer 308 involves forming raw metal layers 902, 904, 906, 908 on a carrier 910 that will be processed to form ETS metallization layer 308 and auxiliary metal layers (block 802 of FIG. 8A). Metal layers 902, 904, 906, 908 may be, for example, copper layers. Metal layers 904, 906 are disposed on opposing sides 912(1), 910(2) of carrier 912. Metal layers 904, 906 may form seed layers on which metal layers 902, 908 (e.g., metal foils such as copper foils) are formed. As described below, metal layers 902, 908 will be reused throughout the process to form additional metal interconnects 306(1)-306(3) as part of the auxiliary metal layer 304 to increase the metal density of the buried metal traces 318(1)-318(3) in the insulating layer 320. In this example, metal layer 902 will be used to form the auxiliary metal layer 304 for the die-side ETS metallization layer 308.

[0049]

[0062] As shown in manufacturing stage 900B of FIG. 9B , the next exemplary step in manufacturing process 800 is to form metal traces 318(1), 318(3), 330 that will be embedded in insulating layer 320 of the formed die-side ETS metallization layer 308 in a later processing step (block 804 of FIG. 8A ). Metal traces 318(1), 318(3), 330 are formed by depositing another metal layer 324 (e.g., a copper layer) on metal layer 908, patterning metal layer 324 (e.g., using a photoresist layer exposed through a mask) to form openings 914 in metal layer 324, and forming the metal traces 318(1), 318(3), 330 in the remaining metal portions of metal layer 324. As shown in manufacturing stage 900C of FIG. 9C, the next exemplary step in manufacturing process 800 is to laminate metal traces 318(1), 318(3), 330 formed in metal layer 324 with a dielectric material 916 (block 806 of FIG. 9B) to form insulating layer 320, thereby embedding metal traces 318(1), 318(3), 330 in insulating layer 320 and forming ETS metallization layer 308.

[0050]

[0063] As shown in manufacturing stage 900D of FIG. 9D , the next exemplary step in the manufacturing process 800 is to remove the carrier 910 and metal layer 906 to prepare the metal layer 908 to be etched to expose the buried metal traces 318(1), 318(3), 330 of the ETS metallization layer 308 so that interconnections can be made (block 808 of FIG. 8B ). The metal layer 906 is typically completely etched away as part of the manufacturing process to fabricate the ETS metallization layer 308. However, in this manufacturing process 800, the metal layer 906 will be reused only by being selectively etched to form additional metal interconnects 306(1)-306(3) to increase the metal density of the ETS metallization layer 308. Thus, the metal layer 906 will form the auxiliary metal layer 304. Because the buried metal traces 318(1)-318(3) are already formed in contact with the metal layer 906, when the metal layer 906 is selectively etched, the remaining metal material of the metal layer 906 that is not etched and forms the additional metal interconnects 306(1)-306(3) will already be bonded to the buried metal traces 318(1)-318(3).

[0051]

[0064] As shown in fabrication stage 900E of FIG. 9E, the next exemplary step in fabrication process 800 is to place (i.e., deposit) a masking layer 918 of a masking material on metal layer 908 to prepare for selectively etching metal layer 908 to form additional metal interconnects 306(1)-306(3) in auxiliary metal layer 304 (block 810 of FIG. 8C). For example, masking layer 918 may be made from a material that is resistant to a metal etching process, such as a chemical or mechanical etching process. Then, as shown in fabrication stage 900F of FIG. 9F, the next exemplary step in fabrication process 800 is to expose masking layer 918 through a mask to form openings 920 in masking layer 918 (block 812 of FIG. 8D). Openings 920 are formed above areas in metal layer 908 that will be etched away in a subsequent etching process, with the remaining metal portions of metal layer 908 protected by masking layer 918, to form additional metal interconnects 306(1)-306(3) in metal layer 908 as auxiliary metal layer 304.

[0052]

[0065] As shown in manufacturing stage 900G of FIG. 9G, the next exemplary step in the manufacturing process 800 is to etch inside the openings 920 formed in the masking layer 918 to etch away metal material in the metal layer 908 exposed by the openings 920 (block 814 of FIG. 8D). The masking layer 918 that is not removed over the areas of the metal layer 908 protects those areas from being etched away so that the metal layer 908 can be reused. The areas of the metal layer 908 protected by the masking layer 918 are not etched away to form additional metal interconnects 306(1)-306(3) of the auxiliary metal layer 304. Note that the openings 920 are formed in a processing step as shown in manufacturing stage 900F of FIG. 9F, leaving the additional metal interconnects 306(1)-306(3) shorter by a width W1 than extend completely above the buried metal traces 318(1)-318(3), as previously described. This forms recesses 342 in the buried metal traces 318(1)-318(3), as shown in fabrication stage 900G of FIG. 9G. As shown in fabrication stage 900H of FIG. 9H, the next exemplary step in fabrication process 800 is to form a solder resist layer 332 over the additional metal interconnects 306(1)-306(3) in the auxiliary metal layer 304 and inside the recesses 342 (block 816 of FIG. 8D). As shown in fabrication stage 900I of FIG. 9I, the next exemplary step in fabrication process 800 is to finish (e.g., polish) a top surface 922 of the solder resist layer 332 (block 818 of FIG. 8E).

[0053]

[0066] Any processor-based device may be provided with or integrated with an IC package that employs an auxiliary metal layer having additional metal interconnects coupled to embedded metal traces in the die-side ETS metallization layer of the package substrate to avoid or reduce metal density mismatch between the die-side ETS metallization layer and another metallization layer(s) in the package substrate, including but not limited to the package substrates of Figures 3A-6B and 9A-9I, and with the exemplary manufacturing processes of Figures 7-8E, and with the exemplary manufacturing processes of Figures 8-9C. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, mobile phones, smartphones, session initiation protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smart watches, health or fitness trackers, eyewear, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multicopters.

[0054]

[0067] In this regard, FIG. 10 illustrates an example of a processor-based system 1000 including circuitry that may be provided in an IC package 1002 that includes a die or die. The IC package 1002 employs an auxiliary metal layer having additional metal interconnects coupled to embedded metal traces in a package substrate die-side ETS metallization layer to avoid or reduce metal density mismatch between the die-side ETS metallization layer and another metallization layer or layers in the package substrate, including but not limited to the package substrates of FIGS. 3A-6B and 9A-9I, and according to the exemplary manufacturing process of FIGS. 7-8E, and according to any aspect disclosed herein. In this example, the processor-based system 1000 may be formed as an IC 1004 in the IC package 1002 and as a system-on-a-chip (SoC) 1006. The processor-based system 1000 includes a central processing unit (CPU) 1008 including one or more processors 1010, which may be referred to as CPU cores or processor cores. The CPU 1008 may have a cache memory 1012 coupled to the CPU 1008 for rapid access to temporarily stored data. The CPU 1008 is coupled to a system bus 1014, which may interconnect master and slave devices included within the processor-based system 1000. As is well known, the CPU 1008 communicates with these other devices by exchanging address, control, and data information via the system bus 1014. For example, the CPU 1008 may communicate bus transaction requests to a memory controller 1016, as an example of a slave device. Although not shown in FIG. 10, multiple system buses 1014 may be provided, with each system bus 1014 constituting a different fabric.

[0055]

[0068] Other master and slave devices may be connected to the system bus 1014. As shown in FIG. 10, these devices may include, by way of example, a memory system 1020 including a memory controller 1016 and a memory array(s) 1018, one or more input devices 1022, one or more output devices 1024, one or more network interface devices 1026, and one or more display controllers 1028. Each of the memory system(s) 1020, the one or more input devices 1022, the one or more output devices 1024, the one or more network interface devices 1026, and the one or more display controllers 1028 may be provided in the same or different IC packages 1002. The input device(s) 1022 may include any type of input device, including, but not limited to, input keys, switches, voice processors, and the like. The output device(s) 1024 may include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The network interface device(s) 1026 may be any device configured to enable the exchange of data to and from the network 1030. The network 1030 may be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The network interface device(s) 1026 may be configured to support any type of communication protocol desired.

[0056]

[0069] The CPU 1008 may also be configured to access a display controller(s) 1028 via the system bus 1014 to control information sent to one or more displays 1032. The display controller(s) 1028 send information to the display(s) 1032 to be displayed via one or more video processors 1034, which process the information to be displayed into a format suitable for the display(s) 1032. The display controller(s) 1028 and the video processor(s) 1034 may be included as ICs in the same or different IC package 1002, as an example, in the same or different IC package 1002 that includes the CPU 1008. The display(s) 1032 may include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc.

[0057]

[0070] FIG. 11 illustrates an exemplary wireless communication device 1100 including a radio frequency (RF) component formed from one or more ICs 1102, any of which may be included in an IC package 1103 including a die(s). The IC package 1103 employs an auxiliary metal layer having additional metal interconnects coupled to embedded metal traces in the die-side ETS metallization layer of a package substrate, including but not limited to the package substrates of FIGS. 3A-6B and 9A-9I according to the exemplary manufacturing process of FIGS. 7-8E and according to any aspect disclosed herein, to avoid or reduce metal density mismatch between the die-side ETS metallization layer and another metallization layer(s) in the package substrate. The wireless communication device 1100 may include or be provided within any of the above devices, as examples. As shown in FIG. 11, the wireless communication device 1100 includes a transceiver 1104 and a data processor 1106. The data processor 1106 may include a memory for storing data and program codes. The transceiver 1104 includes a transmitter 1108 and a receiver 1110 supporting bidirectional communication. In general, the wireless communication device 1100 may include any number of transmitters 1108 and / or receivers 1110 for any number of communication systems and frequency bands. All or a portion of the transceiver 1104 may be implemented in one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0058]

[0071] The transmitter 1108 or the receiver 1110 may be implemented with a super-heterodyne architecture or a direct-conversion architecture. In a super-heterodyne architecture, the signal is frequency converted between RF and baseband in multiple stages, for example, from RF to an intermediate frequency (IF) in one stage and then from IF to baseband in another stage, for the receiver 1110. In a direct-conversion architecture, the signal is frequency converted between RF and baseband in one stage. The super-heterodyne architecture and the direct-conversion architecture may use different circuit blocks and / or have different requirements. In the wireless communication device 1100 of FIG. 11, the transmitter 1108 and the receiver 1110 are implemented with a direct-conversion architecture.

[0059]

[0072] On the transmit path, a data processor 1106 processes data to be transmitted and provides I and Q analog output signals to a transmitter 1108. In the exemplary wireless communication device 1100, the data processor 1106 includes digital-to-analog converters (DACs) 1112(1) and 1112(2) to convert digital signals generated by the data processor 1106 to I and Q analog output signals, e.g., I and Q output currents, for further processing.

[0060]

[0073] Within the transmitter 1108, low pass filters 1114(1) and 1114(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 1116(1), 1116(2) amplify the signals from low pass filters 1114(1), 1114(2), respectively, and provide I and Q baseband signals. An upconverter 1118 upconverts the I and Q baseband signals using I and Q TX local oscillator (LO) signals from a transmit (TX) LO signal generator 1122 through mixers 1120(1), 1120(2) to provide an upconverted signal 1124. A filter 1126 filters the upconverted signal 1124 to remove unwanted signals caused by frequency upconversion as well as noise in the receive frequency band. A power amplifier (PA) 1128 amplifies the upconverted signal 1124 from filter 1126 to obtain a desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 1130 and transmitted via an antenna 1132.

[0061]

[0074] In the receive path, an antenna 1132 receives a signal transmitted by a base station and provides a received RF signal, which is routed through a duplexer or switch 1130 and provided to a low noise amplifier (LNA) 1134. The duplexer or switch 1130 is designed to operate at a specific RX to TX duplexer frequency separation such that the receive (RX) signal is separated from the TX signal. The received RF signal is amplified by the LNA 1134 and filtered by a filter 1136 to obtain a desired RF input signal. Downconversion mixers 1138(1), 1138(2) mix the output of the filter 1136 with I and Q RX LO signals (i.e., LO_I and LO_Q) from a RX LO signal generator 1140 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1142(1), 1142(2) and further filtered by low pass filters 1144(1), 1144(2) to obtain I and Q analog input signals, which are provided to data processor 1106. In this example, data processor 1106 includes analog-to-digital converters (ADCs) 1146(1), 1146(2) for converting the analog input signals to digital signals for further processing by data processor 1106.

[0062]

[0075] In the wireless communication device 1100 of FIG. 11, a TX LO signal generator 1122 generates I and Q TX LO signals used for frequency up-conversion, while a RX LO signal generator 1140 generates I and Q RX LO signals used for frequency down-conversion. Each LO signal is a periodic signal having a particular fundamental frequency. A TX phase-locked loop (PLL) circuit 1148 receives timing information from the data processor 1106 and generates a control signal used to adjust the frequency and / or phase of the TX LO signal from the TX LO signal generator 1122. Similarly, a RX PLL circuit 1150 receives timing information from the data processor 1106 and generates a control signal used to adjust the frequency and / or phase of the RX LO signal from the RX LO signal generator 1140.

[0063]

[0076] Those skilled in the art will further appreciate that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, as instructions stored in a memory or in another computer-readable medium and executed by a processor or other processing device, or as a combination of both. The memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various exemplary components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0064]

[0077] The various example logic blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but alternatively the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0065]

[0078] Aspects disclosed herein may be embodied in hardware and instructions stored in the hardware and may reside in, for example, a random access memory (RAM), a flash memory, a read-only memory (ROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a register, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and the storage medium may reside as discrete components in a remote station, a base station, or a server.

[0066]

[0079] It should also be noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and explanations. The described operations may be performed in many different orders other than the order shown. Furthermore, an operation described in a single operational step may actually be performed in several different steps. In addition, one or more operational steps described in the exemplary aspects may be combined. It should be understood that many different modifications may be made to the operational steps shown in the flowchart diagrams, as would be readily apparent to one of ordinary skill in the art. Those skilled in the art will also appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0067]

[0080] The above description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other examples. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0068]

[0081] Example implementations are described in the following numbered aspects / clauses. 1. An integrated circuit (IC) package comprising: A package substrate, a first metallization layer, A first insulating layer; a first metallization layer including one or more first metal traces embedded in a first insulating layer; and a second metal layer disposed adjacent to the first metallization layer, the second metal layer including one or more second metal interconnects each coupled to a first metal trace of the one or more first metal traces in the first metal layer of the first metallization layer. 2. a second metal layer is disposed vertically adjacent to the first side of the first metallization layer; The package substrate is further comprising one or more vertical interconnect accesses (vias) each coupled to a first metal trace of the one or more first metal traces on the second side of the first metallization layer in a vertical direction; An IC package as described in clause 1. 3. The package substrate further comprises a third metallization layer comprising a third metal layer including one or more third metal interconnects; 3. The IC package of claim 2, wherein each via of the one or more vias is coupled to a third metal interconnect of the one or more third metal interconnects. 4. The IC package of clause 3, further comprising one or more external interconnects each coupled to a third metal interconnect of the one or more third metal interconnects in the third metallization layer. 5. the one or more first metal traces each have a first vertical height of 12 to 14 micrometers (μm); The one or more third metal interconnects each have a second height in a vertical direction of 10 μm to 20 μm. 1. An IC package as defined in clause 3 or 4. 6. the one or more first metal traces have a first vertical height; the one or more third metal interconnects have a second height in the vertical direction; a ratio of the first height to the second height is at least 8 / 20; 6. An IC package according to any one of clauses 3 to 5. 7. The IC package of clause 1, wherein the one or more second metal interconnects are each in direct contact with a first metal trace of the one or more first metal traces. 8. Further comprising a solder resist layer adjacent to the first metallization layer; 8. The IC package of any of clauses 1-7, wherein the second metal layer is disposed within the solder resist layer. 9. the first insulating layer includes a first surface; a second metal layer disposed adjacent to the first surface; 9. An IC package according to any one of clauses 1 to 8. 10. a first surface of the first insulating layer is disposed in a horizontal plane in a horizontal direction; at least a portion of the one or more first metal traces each include a second surface that extends vertically into the horizontal plane; An IC package as described in clause 9. 11. The IC package of any of clauses 1-10, wherein the one or more second metal interconnects are not embedded in the first insulating layer. 12. One or more first metal traces include: an outer metal portion having a first vertical height; an inner metal portion disposed inside the outer metal portion, the inner metal portion having a second vertical height that is smaller than the first height; 12. The IC package according to any one of clauses 1 to 11, each comprising: 13. the first insulating layer includes a first surface adjacent to the second metal layer, the first surface being horizontally disposed in a first horizontal plane; For each of the one or more first metallic traces: The outer metal part a second surface disposed horizontally in a second horizontal plane; a third surface vertically opposite the second surface and adjacent to the second metal layer, the third surface being disposed in a third horizontal plane in a horizontal direction between the first and second horizontal planes in the vertical direction; Including, The inner metal part is a fourth surface disposed in the second horizontal plane; a fifth surface vertically opposite the fourth surface and adjacent to the second metal layer, the fifth surface being disposed in the first horizontal plane; 13. The IC package of claim 12, comprising: 14. the one or more first metal traces have a first vertical height of between 8 and 14 micrometers (μm); the one or more second metal interconnects have a second height in a vertical direction of between 1 μm and 5 μm; 14. An IC package according to any one of clauses 1 to 13. 15. the one or more first metal traces each have a first height in a vertical direction; the one or more second metal interconnects each have a second height in the vertical direction; a ratio of the first height to the second height is at least 8 / 5; 15. An IC package according to any one of clauses 1 to 14. 16. The one or more first metal traces each have a first width in a horizontal direction of 7 micrometers (μm) or less; and further comprising one or more spaces between adjacent first metal traces of the one or more first metal traces having a second horizontal width of 9 μm or less. 16. An IC package according to any one of clauses 1 to 15. 17. The IC package of any of clauses 1-16, further comprising a die coupled to the package substrate. 18. The IC package of clause 17, wherein the die includes one or more die interconnects each coupled to a first metal trace of the one or more first metal traces. 19. The IC package of clause 17 or 18, wherein the one or more die interconnects are each coupled to a second metal interconnect of the one or more second metal interconnects in the second metal layer. 20. An IC package as described in any of clauses 17-19, wherein at least a portion of the second metal layer is disposed vertically between the die and the first metallization layer. 21. An IC package as described in any of clauses 17-20, wherein the second metal layer is disposed on the outside of the die in the vertical direction. 22. The IC package of any of clauses 1-21 integrated into a device selected from the group consisting of a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a Global Positioning System (GPS) device, a mobile phone, a mobile phone, a smartphone, a Session Initiation Protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multicopter. 23. A method for manufacturing an integrated circuit (IC) package, comprising: Forming a package substrate, comprising: forming a first metallization layer, forming a first insulating layer; forming a first metallization layer, the first metallization layer including embedding one or more first metal traces in the first insulating layer to form a first metal layer within the first insulating layer; forming a package substrate, forming one or more second metal interconnects in a second metal layer adjacent to the first metallization layer; coupling each of the one or more second metal interconnects in the second metal layer to a first metal trace of the one or more first metal traces in the first metal layer of the first metallization layer; A method comprising: twenty four. forming one or more second metal interconnects in the second metal layer includes forming one or more second metal interconnects in the second metal layer adjacent to a first side of the first metallization layer in a vertical direction; forming a package substrate, forming one or more vertical interconnect accesses (vias) each coupled to a first metal trace of the one or more first metal traces on the second side of the first metallization layer in a vertical direction; The method described in clause 23. 25. Forming the package substrate further includes forming a third metallization layer including a third metal layer including one or more third metal interconnects; 25. The method of clause 24, further comprising coupling each of the one or more third metal interconnects in the third metal layer to a via of the one or more vias. 26. The method of claim 23, wherein bonding each of the one or more second metal interconnects includes placing each of the one or more second metal interconnects in the second metal layer in contact with a first metal trace of the one or more first metal traces in the first metal layer of the first metallization layer. 27. The method of any of clauses 23-26, further comprising forming a solder resist layer over the second metal layer and adjacent to the first metallization layer, such that the second metal layer is disposed within the solder resist layer. 28. forming the first insulating layer further includes forming a first surface disposed in a horizontal plane in a horizontal direction; 28. The method of any of clauses 23-27, wherein embedding the one or more first metal traces in the first insulating layer further comprises forming a second surface on at least a portion of the one or more first metal traces that extend in a vertical direction in the horizontal plane. 29. The method of any of clauses 23-28, further comprising not embedding the one or more second metal interconnects in the first insulating layer. 30. The method of any of clauses 23-29, further comprising bonding a die bonded to a package substrate. 31. The method of clause 30, wherein bonding the die includes bonding at least one die interconnect of the die to a second metal interconnect of one or more second metal interconnects in the second metal layer. 32. Establishing a career and forming a second metal layer on the carrier; forming one or more first metal traces in a first metal layer disposed on a second metal layer; 32. The method of any one of clauses 23 to 31, further comprising: 33. Embedding one or more first metal traces in a first insulating layer; forming one or more first metal traces in a first metal layer; Clause 33. The method of clause 32, comprising laminating one or more first metal traces in the first metal layer with a dielectric material forming a first insulating layer. 34. disposing a masking layer over the second metal layer; forming one or more openings in a masking layer over the second metal layer; exposing the masking layer; etching inside one or more openings in the second metal layer exposed from the one or more openings to form one or more second metal interconnects in the unetched second metal layer; 34. The method of claim 33, further comprising: 35. The method of claim 34, further comprising forming a solder resist layer on the second metal layer.

Claims

1. 1. An integrated circuit (IC) package comprising: a package substrate extending in a first direction, wherein the package substrate comprises: a first metallization layer, a first insulating layer having a first surface; a first metal layer including one or more first metal traces embedded in the first insulating layer; a first metallization layer comprising: a die comprising one or more die interconnects each coupled to the first metallization layer; a second metal layer exterior to the package substrate and adjacent to the first surface of the first insulating layer, the second metal layer being between the die and the first metallization layer in a second direction orthogonal to the first direction and including one or more second metal interconnects each coupled to a first metal trace of the one or more first metal traces in the first metal layer of the first metallization layer; An IC package comprising:

2. The one or more first metal traces each have a second surface adjacent to the second metal layer and a third surface opposite the second surface in the second direction; The package substrate is one or more vias each coupled to a third surface of a first metal trace of the one or more first metal traces in the second direction; a third metallization layer including a third metal layer including one or more third metal interconnects; Further comprising:

2. The IC package of claim 1, wherein each via of the one or more vias is coupled to a third metal interconnect of the one or more third metal interconnects.

3. 3. The IC package of claim 2, further comprising one or more external interconnects each coupled to a third metal interconnect of the one or more third metal interconnects in the third metallization layer.

4. the one or more first metal traces each have a first height in the second direction of 12 to 14 micrometers (μm) in the second direction; the one or more third metal interconnects each have a second height in the second direction of 10 μm to 20 μm; 3. The IC package of claim 2.

5. the one or more first metal traces have a first height in the second direction; the one or more third metal interconnects have a second height in the second direction; a ratio of the first height to the second height of at least 8 / 20; 3. The IC package of claim 2.

6. 2. The IC package of claim 1, wherein the one or more second metal interconnects each directly contact a first metal trace of the one or more first metal traces.

7. 2. The IC package of claim 1, wherein the second metal layer is disposed on the outside of the die in the second direction.

8. set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, mobile phones, smartphones, session initiation protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices, desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, multicopters, 10. The IC package of claim 1 integrated into a device selected from the group consisting of:

9. 1. A method for manufacturing an integrated circuit (IC) package, comprising: forming a package substrate extending in a first direction; and wherein forming the package substrate comprises: forming a first metallization layer; forming a first insulating layer having a first surface; embedding one or more first metal traces in the first insulating layer to form a first metal layer within the first insulating layer; forming a first metallization layer comprising: forming one or more second metal interconnects in a second metal layer external to the package substrate and adjacent the first surface of the first insulating layer, the second metal layer forming one or more second metal interconnects between the die and the first metallization layer in a second direction orthogonal to the first direction; coupling each of the one or more second metal interconnects in the second metal layer to a first metal trace of the one or more first metal traces in the first metal layer of the first metallization layer; respectively coupling one or more die interconnects of the die to the first metallization layer; A method comprising:

10. forming the one or more second metal interconnects in the second metal layer includes forming the one or more second metal interconnects in the second metal layer vertically adjacent a first side of the first metallization layer; forming the package substrate, forming one or more vertical interconnect accesses (vias) each coupled to a first metal trace of the one or more first metal traces on a second side of the first metallization layer in the vertical direction; forming a third metallization layer including a third metal layer including one or more third metal interconnects; 10. The method of claim 9, further comprising coupling each of the one or more third metal interconnects in the third metal layer to a via of the one or more vias.

11. 10. The method of claim 9, wherein coupling each of the one or more second metal interconnects comprises placing each of the one or more second metal interconnects in the second metal layer in contact with a first metal trace of the one or more first metal traces in the first metal layer of the first metallization layer.

12. Establishing a career and forming a second metal layer on the carrier; forming the one or more first metal traces in the first metal layer disposed on the second metal layer; The method of claim 9 further comprising:

13. embedding one or more first metal traces in the first insulating layer; forming the one or more first metal traces in the first metal layer; laminating the one or more first metal traces in the first metal layer with a dielectric material that forms the first insulating layer; 13. The method of claim 12, comprising:

14. disposing a masking layer over the second metal layer; exposing the masking layer to light to form one or more openings in the masking layer over the second metal layer; etching inside the one or more openings in the second metal layer exposed from the one or more openings to form the one or more second metal interconnects in the unetched second metal layer; The method of claim 13 further comprising:

15. The method of claim 14 further comprising forming a solder resist layer on the second metal layer.

Images