Light emitting diode based display pixels for display screens - Patents.com

Abstract

This specification relates to a display pixel (12 i,j For the display pixel, the pixel comprises a light emitting diode (LED), a driver circuit (40) for driving the light emitting diode, and first, second, third and fourth conductive pads (36). The light emitting diode is powered by a first voltage (Vcc) received between the first and second conductive pads. The driver circuit receives a first binary signal (Com i ) and a second binary signal (Data j ) to control the light emitting diode based on the first binary signal (Com i A second binary signal (Data) is received between the third conductive pad and the second conductive pad and alternates between a second voltage (Vdd) lower than the first voltage and a third voltage (Gnd) lower than the second voltage. j A power supply voltage (Vdd) is received between the fourth conductive pad and the second conductive pad and alternates between a second voltage (Vdd) and a third voltage (Gnd). The display pixel includes a circuit (60) for providing a power supply voltage (Vdd) to a drive circuit based on the first binary signal and the second binary signal.

Description

[Technical field]

[0001] The present disclosure relates generally to display pixels comprising light emitting diodes for display screens. [Background technology]

[0002] A pixel of an image corresponds to a unit element of an image displayed by a display screen. To display a color image, a display screen generally comprises at least three elements, also called display sub-pixels, each emitting radiation light in a substantially single color (e.g. red, green and blue) to display each pixel of the image. The superposition of the radiation emitted by the three display sub-pixels gives the observer a sense of coloring corresponding to the pixel of the displayed image. In this case, the ensemble formed by the three display sub-pixels used to display a pixel of the image is called a display pixel of the display screen. Each display sub-pixel may have a light source, in particular a light-emitting diode.

[0003] The display pixels may be distributed in an array, with each display pixel located at the intersection of a row (or line) and a column of the array. Typically, each row of display pixels is selected in succession and the display pixels of the selected row are programmed to display a desired image pixel.

[0004] An active array is a screen driving configuration that can keep all pixel rows active for the entire duration of an image, as opposed to an array called passive, where each row is only active for T=Tframe / N (where Tframe is the duration of the image and N is the number of rows on the screen). This allows for increased brightness of the display screen. Furthermore, lower voltage or current levels can be sent to the control lines of the array, thus allowing a larger data flow to be displayed. Summary of the Invention [Problem to be solved by the invention]

[0005] In screens based on micrometer-sized light-emitting diodes formed on electronic circuits, the size of the light-emitting diode circuit is generally smaller than the size of the image pixel, due to the high inherent brightness of the light-emitting diodes. One solution used is therefore to deposit these unit light-emitting diodes on a support (also called a panel) that contains the driving electronics. Another solution uses display pixels that comprise a light-emitting diode and a circuit for controlling the light-emitting diode. Such display pixels are called smart pixels. This allows the formation of an active array to be simplified, in particular because the control electronics of the light-emitting diode of the display pixel are largely embedded in the display pixel. An example of a smart pixel is described in the document WO 2018 / 185433.

[0006] In a smart pixel, the size of the smart pixel is determined by the number of conductive pads of the smart pixel used to electrically connect the smart pixel to the support, in particular by the minimum size of these conductive pads and the minimum space provided between these conductive pads. In order to limit the number of conductive pads, it is known to supply one power supply voltage to the display pixels, each display pixel generating one or more reduced power supply voltages internally, in particular for biasing components of the control electronics.

[0007] The static power consumption of a display pixel corresponds to the power consumed by the display pixel when it is not emitting light. Such power may consist of component leakage current or current required for the internal operation of the display pixel's control circuitry. In a smart pixel, the majority of the static power consumption is due to the generation of the power supply voltage within the smart pixel.

[0008] In order to avoid generating the power supply voltage within the smart pixels, it may be envisaged to provide an additional conductive pad for each smart pixel to supply a reduced power supply voltage to the smart pixels, however this may increase the size of the smart pixels, which is undesirable.

[0009] There is a trend to increase the number of display pixels in a display screen. Therefore, the static power consumption of a display pixel can become an important factor. In fact, for a so-called 4K display screen having a resolution of 2,160 x 3,840 display pixels, the static power consumption of the display screen can exceed 150 W.

[0010] There is a need to reduce the static power consumption of display screens.

[0011] It is an object of the embodiments to provide a display screen with light emitting diodes that overcomes all or part of the disadvantages of existing display screens with light emitting diodes.

[0012] Another object of an embodiment is to limit the number of interconnects between the display pixels and the display pixel support so that the display pixels have dimensions less than 200 μm. [Means for solving the problem]

[0013] An embodiment provides a display pixel for a display screen comprising at least one light emitting diode, a drive circuit for driving the light emitting diode, and a first conductive pad, a second conductive pad, a third conductive pad and a fourth conductive pad, the light emitting diode being powered with a first voltage received between the first conductive pad and the second conductive pad, the drive circuit being configured to control the light emitting diode based on a first binary signal and a second binary signal, the first binary signal being received between the third conductive pad and the second conductive pad and alternating between a second voltage lower than the first voltage and a third voltage lower than the second voltage, the second binary signal being received between the fourth conductive pad and the second conductive pad and alternating between the second voltage and the third voltage, the display pixel further comprising a circuit for providing a power supply voltage for powering the drive circuit based on the first binary signal and the second binary signal and equal to within 10% of the second voltage.

[0014] This advantageously enables a reduced power supply voltage to be generated within the display pixels whilst reducing the static power consumption of the display pixels, as the reduced power supply voltage is not generated from the first power supply voltage of the light emitting diode within each display pixel.

[0015] According to the embodiment, the circuit for supplying the power supply voltage includes a first switch connecting the third conductive pad and a node for supplying the power supply voltage, and a second switch connecting the fourth conductive pad and the node. Therefore, the structure of the circuit for supplying the power supply voltage is simple.

[0016] According to an embodiment, the circuit for supplying the power supply voltage comprises a first circuit for controlling the first switch configured to control the first switch to ON when the first binary signal is at the second voltage and to control the first switch to OFF when the first binary signal is at the third voltage, and a second circuit for controlling the second switch configured to control the second switch to OFF when the second binary signal is at the third voltage. Thus, as soon as the first binary signal becomes the second voltage, the power supply voltage of the drive circuit is preferentially obtained from the first binary signal.

[0017] According to an embodiment, a second circuit for controlling the second switch is configured to control the second switch to ON when the second binary signal is at the second voltage and the first binary signal is at the third voltage, and to control the second switch to OFF when the first binary signal is at the second voltage. Thus, the power supply voltage of the drive circuit is derived from the second binary signal only when the first binary signal is at the third voltage or the second voltage.

[0018] According to the embodiment, the first switch is a first MOS transistor and the second switch is a second MOS transistor, which makes it possible to easily form a circuit that supplies a power supply voltage integrally.

[0019] According to the embodiment, the gate of the first MOS transistor is connected to the third conductive pad, and the gate of the second MOS transistor is connected to the fourth conductive pad. Since the first MOS transistor and the second MOS transistor are directly controlled by the first binary signal and the second binary signal, the circuit for supplying the power supply voltage is simplified.

[0020] According to an embodiment, the circuit for providing the power supply voltage comprises a capacitor having a first plate connected to the node and a second plate coupled to the second conductive pad, thereby ensuring a substantially constant power supply voltage even when both the first binary signal and the second binary signal are at a third voltage.

[0021] According to an embodiment, the circuit for supplying a supply voltage does not comprise a capacitor having a plate connected to the node, so that the circuit for supplying a supply voltage has a particularly simple construction.

[0022] According to an embodiment, the driving circuit is configured to determine a digital signal from the value of the second binary signal it receives during each first pulse during which the first binary signal is at the second voltage, and to control the light emitting diode based on the digital signal. The first binary signal is advantageously used to clock the driving circuit to obtain the value of the second binary signal.

[0023] According to an embodiment, the driver circuit is configured to determine a digital signal from the value of the second binary signal received during each first pulse during which the first binary signal is at the third voltage and to control the light emitting diode based on the digital signal. The first pulses during which the first binary signal is at the third voltage make it possible to clock the driver circuit to obtain the value of the second binary signal, so that it is advantageously possible to deliver the first binary signal at the second voltage during the first pulses.

[0024] According to an embodiment, the driving circuit is configured to determine a digital signal from the value of the second binary signal received immediately after each first pulse during which the first binary signal is at the third voltage, and to control the light emitting diode based on the digital signal, so that the second binary signal is emitted at the second voltage during the first pulse.

[0025] According to an embodiment, the drive circuit is configured to control the light emitting diode by pulse width modulation based on the digital signal, so that the light emitting diode can be controlled at an optimum operating point.

[0026] According to an embodiment, the display pixel comprises only the first conductive pad, the second conductive pad, the third conductive pad and the fourth conductive pad. Advantageously, the number of conductive pads of a display pixel is reduced.

[0027] According to an embodiment, the drive circuit is configured to turn the light emitting diode on or off with a period of a second pulse where the first binary signal is at the second voltage or at the third voltage, the first binary signal being advantageously used to clock the drive circuit to control the light emitting diode.

[0028] An embodiment further provides a display screen comprising an array of display pixels as previously defined, and further comprising circuitry for providing, for each of said display pixels, the first voltage between the first conductive pad and the second conductive pad, sending the first binary signal between the third conductive pad and the second conductive pad, and sending the second binary signal to the fourth conductive pad.

[0029] An embodiment further provides a method for controlling a display screen comprising an array of display pixels as previously defined, comprising for each said display pixel providing said first voltage between said first conductive pad and said second conductive pad, sending said first binary signal between said third conductive pad and said second conductive pad and sending said second binary signal to said fourth conductive pad, thus reducing the number of signals / voltages sent to each display pixel for controlling and powering the display pixel.

[0030] According to an embodiment, the method comprises delivering the first and second binary signals such that during operation a ratio of an average duration during which at least one of the first and second binary signals is at the second voltage to a sum of an average duration during which the first and second binary signals are at the third voltage and an average duration during which at least one of the first and second binary signals is at the second voltage is higher than 75%, thereby advantageously making it possible to provide a stable power supply voltage within a display pixel.

[0031] According to an embodiment, the method comprises delivering the first and second binary signals such that during operation at least one of the first and second binary signals is at the second voltage at all times, which advantageously makes it possible to provide a stable supply voltage within a display pixel for each display pixel without the need for compression within the display pixel.

[0032] According to an embodiment, the method comprises sending, for each display pixel, a first pulse during which the first binary signal is at the second voltage, and the drive circuit of the display pixel is configured to determine a digital signal based on the value of the second binary signal it receives during each first pulse during which the first binary signal is at the second voltage, and to control the light emitting diode based on the digital signal. The first binary signal is advantageously used to clock the drive circuit for controlling the light emitting diode.

[0033] According to an embodiment, the method comprises sending, for each display pixel, a first pulse during which the first binary signal is at the third voltage, and the drive circuit of the display pixel is configured to determine a digital signal based on the value of the second binary signal it receives during each first pulse during which the first binary signal is at the third voltage, and to control the light emitting diode based on the digital signal. The first pulses during which the binary signal is at the third voltage make it possible to clock the drive circuit to obtain the value of the second binary signal, so that it is advantageously possible to send the first binary signal at the second voltage during the first pulse.

[0034] According to an embodiment, the method comprises sending, for each display pixel, a first pulse during which the first binary signal is at the third voltage, and the drive circuit is configured to determine a digital signal based on the value of the second binary signal received immediately after each first pulse during which the first binary signal is at the third voltage, and to control the light-emitting diode based on the digital signal, so that a second binary signal at a second voltage is sent during a first pulse. [Brief description of the drawings]

[0035] The foregoing and other features and advantages are described in detail in the remainder of the present disclosure of specific embodiments, given by way of non-limiting example with reference to the accompanying drawings, in which:

[0036] [Figure 1] FIG. 2 illustrates, partially and diagrammatically, an example of a display screen. [Diagram 2] 1 is a highly schematic cross-sectional view of an example display pixel; FIG. [Diagram 3] 3 is a bottom view showing the display pixel of FIG. 2. [Figure 4] 3 is a block diagram showing an example of a display pixel of FIG. 2; [Diagram 5] 2 is a block diagram of a display pixel of the display screen of FIG. 1 according to an embodiment of the present invention; [Figure 6] 6 is a block diagram illustrating an embodiment of a circuit for providing reduced voltages for the display pixels of FIG. 5. [Figure 7] 6 is a block diagram illustrating another embodiment of a circuit for providing a reduced voltage for the display pixel of FIG. 5. [Figure 8] 6 is a timing diagram illustrating example signals of the display pixel of FIG. 5 according to an embodiment of a method of operating the display screen. [Figure 9] 6 is a timing diagram illustrating example signals of the display pixel of FIG. 5 according to another embodiment of a method of operating the display screen. [Figure 10]6 is a timing diagram illustrating signals of the display pixel of FIG. 5 according to another embodiment of a method of operating the display screen. [Figure 11] FIG. 6 is an electrical circuit diagram illustrating an embodiment of a current source for the display pixel of FIG. 4 or FIG. 5; [Figure 12] FIG. 6 is an electrical circuit diagram illustrating another embodiment of a current source for the display pixel of FIG. 4 or FIG. 5. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0037] In the various figures, similar features are indicated by similar reference numerals. In particular, structural and / or functional features common to the various embodiments may have the same reference numerals and may have identical structural, dimensional and material characteristics. For clarity, only those steps and elements useful for understanding the embodiments described herein are shown and described in detail.

[0038] In the following description, when reference is made to terms defining absolute positions such as "front", "back", "top", "bottom", "left", "right", or relative positions such as "above", "below", "upper" and "lower", or terms defining directions such as "horizontal" and "vertical", the terms refer to the display screen in its drawing orientation or normal position of use, unless otherwise specified.

[0039] Unless otherwise indicated, when referring to two elements connected together, this refers to a direct connection without any intermediate elements other than conductors, and when referring to two elements coupled together, this refers to the two elements being either connected or coupled through one or more other elements.

[0040] Furthermore, a signal that alternates between a first constant state, e.g., a low state denoted as "0," and a second constant state, e.g., a high state denoted as "1," is referred to as a "binary signal." The high and low states of different binary signals of the same electronic circuit may be different. In fact, a binary signal may correspond to a voltage that may not be perfectly constant in the high or low state.

[0041] Furthermore, in the following description, the source and drain of an insulated gate field effect transistor, or MOS transistor, are referred to as the "power terminals" of the insulated gate field effect transistor, or MOS transistor.

[0042] Furthermore, unless otherwise indicated, when referring to the voltage of a conductive pad, the difference between the potential of said conductive pad and a reference potential, e.g. ground, which is taken as 0V, is taken into account.

[0043] Further, as used herein, the terms "insulating" and "conducting" are deemed to refer to "electrically insulating" and "electrically conducting," respectively.

[0044] The terms "about," "approximately," "substantially," and "to the extent of" refer to within 10%, preferably within 5%, of the corresponding value, unless otherwise specified.

[0045] 1 partially and diagrammatically illustrates a known example of a display screen 10. The display screen 10 comprises display pixels 12 arranged, for example, in M ​​rows and N columns. i,j where M is an integer ranging from 1 to 8,000, N is an integer ranging from 1 to 16,000, i is an integer ranging from 1 to M, and j is an integer ranging from 1 to N. As an example, in FIG. 1, M and N are 6. Each display pixel 12 i,j Electrode 14 i via a low reference potential source Gnd, e.g., ground, and the electrode 16 j 1. The electrode 14 is connected to a high reference potential source Vcc via i are shown aligned along a row in FIG. 1, and electrodes 16 jare shown aligned along a column in FIG. 1, although an inverse arrangement is possible. The power supply voltage of the display screen corresponds to a voltage between a high reference potential Vcc and a low reference potential Gnd, and is denoted Vcc as high reference potential. The power supply voltage Vcc depends inter alia on the arrangement of the light emitting diodes and the manufacturing technology of the light emitting diodes. By way of example, the power supply voltage Vcc may be around 4V to 5V.

[0046] For each row, 12 display pixels in the row i,j Row electrode 18 i For each column, the display pixels 12 in the column are connected to i,j is column electrode 20 j The display screen 10 is connected to row electrodes 18. i The selection circuit 22 is coupled to each row electrode 18. i Select Timing Signal Com i The display screen 10 is adapted to transmit column electrodes 20. j The data supply circuit 24 is coupled to each column electrode 20. j Data signal j The selection circuit 22 and the data supply circuit 24 are controlled by a circuit 26 which includes, for example, a processor.

[0047] FIG. 2 shows a display pixel 12 i,j FIG. 3 is a highly schematic cross-sectional view of a known example of a display pixel 12. i,j FIG. 1 is a bottom view showing each display pixel 12 i,j2. The display pixel comprises a control circuit 30 covered by a display circuit 32. The display circuit 32 comprises at least one light emitting diode LED, preferably at least three light emitting diodes LED. The display pixel has a bottom surface 34 and a top surface 35 opposite the bottom surface 34, the bottom surface 34 and the top surface 35 being preferably planar and parallel. The control circuit 30 further comprises conductive pads 36, not shown in FIG. 2, on the bottom surface 34. The control circuit 30 may correspond to an integrated circuit comprising electronic components, in particular insulated gate field effect transistors, also called MOS transistors, or thin film transistors, also called TFTs. The display circuit 32 preferably comprises only the light emitting diodes LED and the conductive elements of these light emitting diodes LED, the control circuit 30 comprising all the electronic components necessary to control the light emitting diodes LED of the display circuit 32. As a variant, the display circuit 32 may further comprise other electronic components in addition to the light emitting diodes LED. The light emitting diodes LED may be two-dimensional light emitting diodes, also called planar light emitting diodes, having a stack of planar layers, or three-dimensional light emitting diodes, each having a three-dimensional semiconductor element covered with an active area. In FIG. 2, the light emitting diodes LED are shown as being connected to a common anode. However, it may be desirable to arrange the light emitting diodes LED according to another configuration. By way of example, the light emitting diodes LED may be connected to a common cathode or may be connected independently of each other.

[0048] According to an embodiment, the display pixel 12 i,j has three display sub-pixels emitting light at a first wavelength, a second wavelength and a third wavelength. According to an embodiment, the first wavelength corresponds to blue light and is in the range of 430 nm to 490 nm. According to an embodiment, the second wavelength corresponds to green light and is in the range of 510 nm to 570 nm. According to an embodiment, the third wavelength corresponds to red light and is in the range of 600 nm to 720 nm.

[0049] Each conductive pad 36 corresponds to an electrode 14 shown diagrammatically in FIG. i , 16j , 18 i , 20 j The first conductive pad 36 is connected to a low reference potential source Gnd. The second conductive pad 36 is connected to a high reference potential source Vcc. The third conductive pad 36 is connected to a row electrode 18. i The selection and timing signal Com i The fourth conductive pad 36 is connected to the column electrode 20 j , and a data signal Data j The size of the conductive pads 36 and their arrangement on the lower surface 34 are particularly i,j Design rules and display pixels 12 in a display screen 10 i,j This is determined by the assembly method.

[0050] FIG. 4 shows a display pixel 12 of a display screen 10. i,j 4 is a block diagram showing an example of a power supply voltage used to power the electronics of the block, shown above each block in FIG.

[0051] According to the example, display pixel 12 i,j has at least three light emitting diodes, one light emitting diode LED is shown in Fig. 4. Each light emitting diode LED is connected in series to a controllable current source CS, which may for example comprise a MOS transistor. In this example, for each light emitting diode LED, the anode of the light emitting diode LED is connected to a conductive pad 36 receiving for example a high reference potential Vcc, the cathode of the light emitting diode LED is connected to a terminal of the controllable current source CS, and the other terminal of the controllable current source CS is connected to the conductive pad 36 receiving a low reference potential Gnd.

[0052] Display pixels 12 i,jThe display pixel 12 further comprises a drive circuit 40 for driving the controllable current source CS. The drive circuit 40 may in particular comprise electronic components such as MOS transistors. It may be desirable to use a low supply voltage of less than 4V, for example around 1V or 1.8V, to power the electronic components of the drive circuit 40, which low supply voltage corresponds for example to a voltage that may be applied across the power terminals of a MOS transistor. To this end, the display pixel 12 i,j It comprises a circuit 42 (Vdd generation) for providing, based on the supply voltage Vcc, a reduced supply voltage Vdd which is used in particular to power the driver circuit 40. The circuit 42 comprises, for example, a voltage divider.

[0053] According to an embodiment, each display pixel 12 i,j The selection and timing signal Com is received at one of the conductive pads 36 of i is a binary signal that alternates between a low state "0" and a high state "1", where the low state corresponds to a low reference potential Gnd and the high state "1" corresponds to a low voltage substantially equal to the reduced power supply voltage Vdd. j is a binary signal that alternates between a low state "0" and a high state "1", where the low state corresponds to a low reference potential Gnd and the high state "1" corresponds to a low voltage substantially equal to the reduced power supply voltage Vdd.

[0054] The driving circuit 40 receives the data signal Data j 3, which is connected to a conductive pad 36 that receives a data signal Data j The drive circuit 40 has a circuit 44 (Clk and Data separation) for sending out a clock signal Clk and data Data based on the selection timing signal Com. The drive circuit 40 has a circuit 46 (mode selection) for receiving the signal Clk and the signal Data. The circuit 46 is connected to a selection timing signal Com. iThe circuit 48 is coupled to the conductive pad 36 receiving the Clk and Data signals and is configured to send the signal Clk and the signal Data to a storage circuit 48 (color data register) or to send a PWM signal to a circuit 50 (LED driver) for controlling a controllable current source CS associated with each light emitting diode LED. The storage circuit 48 is configured to store the color signals R, G and B representing an image pixel to be displayed. The circuit 50 is adapted to control the controllable current sources CS coupled to the light emitting diodes LED with the signals I_red, I_green and I_blue derived from the color signals R, G and B and the signal PWM.

[0055] As described below, display pixel 12 i,j In order to limit the number of conductive pads 36 per data signal, j , a clock signal and color signals R, G and B representing the desired light intensities of the emitted light of the first, second and third wavelengths are transmitted to each display pixel 12. i,j According to another embodiment, the clock signal Clk is determined by the selection timing signal Com i is obtained from.

[0056] Display pixels 12 i,j A significant portion of the static power consumption of the display screen 10 is due to the non-MOS transistor electronic components of the drive circuit 40, in particular the circuit 42 for supplying the reduced power supply voltage Vdd. i,j There is a trend towards increasing the number of display pixels. Therefore, the static power consumption of a display pixel can become an important factor. Indeed, for a so-called 4K display screen 10 having a resolution of 2,160 x 3,840 display pixels, the static power consumption of the display screen 10 can exceed 150 W.

[0057] Lower power supply voltage Vdd Display pixel 12 i,j To prevent this from happening within the display pixels i,jIn addition to the conductive pads shown in FIG. 3, an additional conductive pad 36 is provided at each display pixel 12 to provide an additional high reference potential Vdd to the i,j However, a configuration in which the display pixel 12 i,j It may not be possible to add additional conductive pads 36 without increasing the lateral dimensions of the substrate, which may be undesirable.

[0058] According to an embodiment of the present invention, the reduced voltage Vdd is connected to the signal Com i and data signal Data j Therefore, the total number of conductive pads 36 is not changed. i,j This reduces the static power consumption of the display screen. i,j The lateral dimensions of the may not be changed.

[0059] FIG. 5 shows a display pixel 12 i,j 5 is a block diagram showing an embodiment of the display pixel 12 of FIG. i,j A circuit 42 for supplying a reduced power supply voltage Vdd receives a selection timing signal Com i and data signal Data j 4 except that it has been replaced with a circuit 60 for receiving the reduced power supply voltage Vdd and providing i,j It has the same structure as that of

[0060] FIG. 6 shows the display pixel 12 of FIG. i,j 1 is a block diagram showing an embodiment of a circuit 60 for providing a reduced voltage Vdd at the input of the select and timing signal Com. i a first switch T1 connecting the conductive pad 36 receiving the data signal Data jCircuit 60 includes a second switch T2 coupling a conductive pad 36 receiving a low reference signal Gnd to node Q. Circuit 60 includes a circuit 64 for delivering a signal GT1 for controlling switch T1, and a circuit 66 for delivering a signal GT2 for controlling switch T2. Circuit 60 includes a capacitor C having a first plate coupled, preferably connected, to node Q, and a second plate coupled to conductive pad 36 receiving a low reference signal Gnd. Node Q represents the output of circuit 60 for providing a reduced voltage Vdd.

[0061] Switch T1 selects the timing signal Com i is in state "1", i.e., at voltage Vdd, and the selection timing signal Com i is in the state "0", which is equal to 0V for example. When the switch T1 is on, the capacitor C is charged with the voltage Vdd through the switch T1. The selection and timing signal Com i Turning off switch T1 when is in state "0" prevents switch T1 from discharging capacitor C. Switch T2 is turned on when data signal Data j is in state "1", i.e., at voltage Vdd, and the data signal Data j is in the state "0" which is equal to 0V. When the switch T2 is on, the capacitor C is charged with the voltage Vdd through the switch T2. j Turning switch T2 off when is in state “0” prevents switch T2 from discharging capacitor C.

[0062] Each switch T1, T2 may correspond to a MOS transistor, for example an N-channel MOS transistor having its source coupled, preferably connected, to node Q. Thus, signal GT1 corresponds to a voltage for controlling the gate of transistor T1, and signal GT2 corresponds to a voltage for controlling the gate of transistor T2.

[0063] In the embodiment shown in FIG. 6, the circuit 64 outputs the signal Com i The circuit 64 includes a buffer circuit having an input for receiving the signal Com and an output for delivering the signal GT1. i At the output, the circuit 66 copies the data signal Data j The first input receives the selection and timing signal Com i 1, and an output that delivers the signal GT2. i When the selection timing signal Com is in the "1" state, i.e., at voltage Vdd, the transistor T1 is on and the transistor T2 is off. Therefore, the capacitor C is charged with the voltage Vdd through the switch T1. i is in a state "0" which is equal to 0V, and the data signal Data j When the select timing signal Com is in state "1", i.e., at voltage Vdd, the transistor T1 is off and the transistor T2 is on. Therefore, the capacitor C is charged with the voltage Vdd through the switch T2. i is in a state "0" which is equal to 0V, and the data signal Data j is in state "0", e.g., equal to 0V, transistor T1 is off and transistor T2 is off. Capacitor C does not discharge through transistor T1 and transistor T2.

[0064] Therefore, the selection timing signal Com i or data signal Data j As soon as either of these goes to state "1", the capacitor C is charged to the reduced voltage Vdd. This makes it possible to use a capacitor C with a reduced capacitance, for example in the range of 10 fF to 10 pF.

[0065] FIG. 7 shows the display pixel 12 of FIG. i,j7 is a block diagram showing another embodiment of a circuit 60 for providing a drop voltage Vdd at 10 V. The circuit 60 shown in FIG. 7 has all the elements of the circuit 60 shown in FIG. 6, except that a circuit 64 corresponds to a conductive track connecting the gate of transistor T1 to the drain of transistor T1 (transistor T1 is therefore constructed with a diode) and a circuit 66 corresponds to a conductive track connecting the gate of transistor T2 to the drain of transistor T2 (transistor T2 is therefore constructed with a diode). The embodiment of FIG. 7 advantageously has a better response than the embodiment of FIG. 6.

[0066] According to another embodiment, the circuit 64 is not provided and the switch T1 is connected to the anode of the select timing signal Com i 3. The switch T2 corresponds to a diode having its anode coupled, preferably connected, to the conductive pad 36 receiving the data signal Data j 3. The input of the input of the input of the present invention is coupled, preferably connected, to a conductive pad 36 receiving the input of the input of the present invention and corresponds to a diode having its cathode coupled, preferably connected, to node Q.

[0067] FIG. 8 illustrates an embodiment of a method for displaying an image on a display screen 10 using a display pixel 12 having the structure shown in FIG. i,j FIG. 1 is a timing diagram of a signal received by

[0068] The potentials Vcc and Gnd are substantially constant. The image pixels of the new image to be displayed are displayed successively from the row with rank 1 to the row with rank M. The duration between two successive selections of the same row of the display screen 10 is called the frame duration T. The signal Com i The timing diagrams of the signals Com1 and Data1 will now be described in detail for a row of rank 1, with the understanding that the timing diagram of the signal Com1 is similar to the timing diagram of the signal Com2, albeit shifted over time. 1,jThe display of a new image pixel according to (j ranges from 1 to N) includes a first stage P1 followed by a second stage P2. During the first stage P1, the data signal Data j But for each display pixel in the row of rank 1, 1,j Only the data signal Data1 is shown in FIG. 8. During the second phase P2, each display pixel 12 1,j The light emitting diode is the data signal j The control is based on the R, G and B color signals which are determined based on the above.

[0069] During the first phase P1, the selection and timing signal Com1 is set to the state "1". The setting of the selection and timing signal Com1 to the state "1" for a long period of time causes each display pixel 12 of the row of rank 1 to 1,j Since the display pixel 12 of this row is detected by the circuit 46, 1,j During the first phase P1, the data signal Data j is column electrode 20 j Display pixel 12 1,j Each time, the circuit 44 outputs a data signal Data j The clock signal Clk and the data Data are determined based on the pulses of the data signal Data. j Each pulse of the signal Clk may have a first duration or a second duration longer than the first duration. j The data Data may correspond to a series of pulses of the same duration that coincide with the rising edge of the pulse of the signal Data within a certain possible deviation. j When the pulse of has a first duration, it is in state "0" and the signal Data jmay correspond to a binary signal which is in state "1" when the pulse of signal Com1 has a second duration. Circuit 46 selected by signal Com1 in state "1" delivers data Data, which is stored in circuit 50 in the form of digital signals R, G and B whose bits are given by successive values ​​of signal Data, at periods of clock signal Clk. The end of the first period P1 of a row corresponds to the start of the first period P1 of the next row.

[0070] According to an embodiment, the display pixel 12 1,j The light emitting diodes LED are controlled by pulse width modulation, i.e. PWM control. For this purpose, during the second phase P2, the selection and timing signal Com1 exhibits a repetitive series of pulses of state "1", which pulses are supplied to each display pixel 12 of the row of rank 1 in order to clock the operation of the circuit 50 for controlling the light emitting diodes LED by pulse width modulation. 1,j The circuit 46 sends (as a PWM signal) to the circuit 50 a series of pulses, the number of successive pulses corresponding to the number of bits of the digital signal R, the digital signal G and the digital signal B, respectively. By way of example, if the current source CS corresponds to a MOS transistor, this transistor is switched on or off in a period of the PWM pulses depending on the value "0" or "1" of each bit of the color signal R, the color signal G or the color signal B, starting from the most significant bit, and remains on or off until the next pulse of the signal Com1. The duration between two successive pulses of the signal Com1 is divided by two each time, so that the total duration during which the light-emitting diode is on is determined depending on the value of the color signal R, the color signal G or the color signal B. The series of pulses of the signal Com1 is repeated until the next first stage P1 of the row of rank 1, one repetition being shown as an example in FIG. 8.

[0071] FIG. 9 illustrates another embodiment of a method for displaying an image on a display screen 10, using a display pixel 12 having the structure shown in FIG. i,j FIG. 1 is a timing diagram of a signal received by

[0072] The signals Vcc, Gnd and Data in the embodiment shown in FIG.j The timing diagram of the signal Com in the embodiment shown in FIG. i (i is in the range of 1 to M) is the signal Com i 8, i.e., the signal Com i When is in state "0", the signal Com i (i ranges from 1 to M) is in state “1”, and the signal Com i When is in state "1", the signal Com i is in state "0". For this reason, pixel 12 i,j is the signal Com i is in state "0" for a long period of time, and the pulse width modulation or PWM control detects the signal Com in state "0" during phase P2. i This is done by a pulse of

[0073] Signal Com i is mostly in state "1" in the embodiment described in connection with Fig. 9 compared to the embodiment described in connection with Fig. 8. This allows the capacitor C of circuit 60 to be recharged more frequently to provide the reduced voltage Vdd, thus further reducing the capacitance of capacitor C.

[0074] Generally, according to an embodiment, the signal Com i and signal Data j The average duration that at least one of the signals Com is at a reduced voltage Vdd. i and signal Data j The average duration of the signal Com at the low reference potential Gnd i and the second signal Data j to the sum of the average durations during which at least one of the first and second power supplies is at the reduced voltage Vdd is greater than 75%, preferably greater than 85%, and more preferably greater than 95%.

[0075] According to another embodiment, the selection circuit 22, the data supply circuit 24 and the circuit 26 are i,j Every 12 display pixels i,j The selection timing signal Com is received by i and data signal Data j Therefore, in this embodiment, the capacitor C of the circuit 60 for supplying the reduced voltage Vdd does not need to be provided.

[0076] FIG. 10 illustrates another embodiment of a method for displaying an image on a display screen 10, using a display pixel 12 having the structure shown in FIG. i,j FIG. 1 is a timing diagram of a signal received by

[0077] In FIG. 10, the timing diagrams of signals Com1, Com2, Com3 and Data1 for rows of rank 1, rank 2 and rank 3 and columns of rank 1 are shown relative to the timing diagrams of other signals Com i 10. The timing diagram of the signal Com1 is shown with the understanding that the timing diagram of the signal Vcc and the signal Gnd, which are not shown in the embodiment shown in FIG. i The timing diagram of the data signal Data in the embodiment shown in FIG. j The timing diagram of is the same as that shown in FIG. 8, except that each stage P1 has two successive stages P1.1 and P1.2. During stage P1.1, to select a row of rank i, the signal Com i (where i is in the range of 1 to N) is in the state "0" for a long time, j (j ranges from 1 to N) is kept in state "1". During a stage P1.2 after stage P1.1, the data signal Data j Column electrode 20 j is sent to display pixel 12 of row i of rank i,j It is obtained by

[0078] This embodiment is particularly adapted for the case where the capacitor C of the circuit 60 for providing the reduced voltage Vdd is not provided. In fact, even if the capacitor C is not provided, the display pixel 12 i,j Always display pixels 12 i,j Signal received by Com i and data signal Data j Since at least one of the gates 11 and 12 is in state "1", the node Q always supplies the voltage Vdd.

[0079] In the above-described embodiment, the display pixel 12 1,j The light emitting diode LED of the display pixel 12 is controlled by pulse width modulation. 1,j The control of the light emitting diode LED may be different from that by pulse width modulation. According to an embodiment, the control of the light emitting diode LED is a current level control.

[0080] FIG. 11 shows an embodiment of a current source CS, which in this embodiment is made up of N controllable basic current sources CS1 to CS N Here, N is an integer equal to or greater than 2. It is preferable that N is equal to the number of bits of the digital color signal R, the digital color signal G, or the digital color signal B. In this embodiment, the basic current source CS j (j is in the range of 1 to N) are assembled in parallel between node A1 and node A2. As shown in FIG. 4 or 5, when the light emitting diodes LED are assembled with a common anode, the node A1 is linked, preferably connected, to the cathode of the light emitting diode LED corresponding to the color of interest, and the node A2 is linked, preferably connected, to the conductive pad 36 connected to the low reference potential source Gnd. When the light emitting diodes LED are assembled with a common cathode, the node A1 is linked, preferably connected, to the conductive pad 36 connected to the high reference potential source Vcc, and the node A2 is linked, preferably connected, to the anode of the light emitting diode LED corresponding to the color of interest, for each color.

[0081] Each basic current source CS j is outputted by the circuit 50 as a control signal C j For example, the control signal C j is a binary signal corresponding to the bit of rank j of the digital color signal R, the digital color signal G, or the digital color signal B. j When is in a first state, e.g., a low state, the basic current source CS j is off, and the control signal C j When is in a second state, e.g., a high state, the current source CS j works.

[0082] Activated current source CS j The greater the number of LEDs, the higher the intensity of the current ICS. According to an embodiment, the current source CS is capable of providing a current ICS having an intensity of one of a number of constant levels, the level being determined according to the number of conducting general light-emitting diodes. j The currents provided by each basic current source CS may be the same or different. j is capable of supplying a current of intensity I×2j-1. Therefore, the current source CS is controlled by the control signal C j The current I C S is adapted to supply a current I C S having a magnitude which may take any value k×I depending on the input of the current I S , where k lies in the range 0 to 2M−1.

[0083] According to an embodiment, the control of the light emitting diode LED is an analog control.

[0084] Fig. 12 shows an embodiment of a current source CS, in which the current source comprises a MOS transistor T assembled in series with a resistor Rs between nodes A1 and A2, the nodes A1 and A2 being defined as previously described in relation to Fig. 11. The current source CS further comprises a digital-to-analog converter DAC for receiving the digital color signal R, the digital color signal G or the digital color signal B, and an operational amplifier, the operational amplifier having an inverting input (-) coupled, preferably connected, to the midpoint between the resistor Rs and the MOS transistor, and a non-inverting input (+) for receiving the analog signal delivered by the digital-to-analog converter DAC. The transistor T is substantially turned on in response to the digital color signal R, the digital color signal G or the digital color signal B sent to the digital-to-analog converter DAC.

[0085] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations may be combined, and other variations will occur to those skilled in the art. In particular, PWM modulation is performed on the signal Com i To avoid this, use display pixel 12 i,j The modulation may be generated within the control circuit 30. Other embodiments may not use PWM modulation and may use linear driving of the light emitting diodes LED. Other embodiments may use other electro-optical components such as organic light emitting diodes.

[0086] Finally, the actual implementation of the described embodiments and variants is within the skill of the person skilled in the art based on the functional representations given above. In particular, with respect to the second embodiment shown in Figure 5, it may be advantageous to use a SOI (Silicon-on-Insulator) type structure to facilitate the management of negative voltages.

[0087] This patent application claims priority from French Patent Application No. 21 / 13487, which is incorporated herein by reference.

Claims

1. Display pixels (12) for a display screen (10) i,j ) where at least one light emitting diode (LED), a drive circuit (40) for driving the light emitting diode, a first conductive pad (36), a second conductive pad (36), a third conductive pad (36), and a fourth conductive pad (36); the light emitting diode is powered by a first voltage (Vcc) received between the first conductive pad and the second conductive pad; The driving circuit outputs a first binary signal (Com i ) and a second binary signal (Data j ) to control the light emitting diode based on the The first binary signal (Com i ) is received between the third conductive pad and the second conductive pad and alternates between a second voltage (Vdd) lower than the first voltage and a third voltage (Gnd) lower than the second voltage; The second binary signal (Data j ) is received between the fourth conductive pad and the second conductive pad and alternates between the second voltage (Vdd) and the third voltage (Gnd); The display pixel further comprises a circuit (60) for providing a power supply voltage (Vdd) for powering the drive circuitry, the power supply voltage (Vdd) being equal to within 10% of the second voltage based on the first binary signal and the second binary signal.

2. 2. The display pixel of claim 1, wherein the circuit (60) for supplying a power supply voltage (Vdd) comprises a first switch (T) connecting the third conductive pad (36) and a node (Q) for supplying the power supply voltage (Vdd), and a second switch (T2) connecting the fourth conductive pad (36) and the node (Q).

3. The circuit (60) for supplying the power supply voltage (Vdd) receives the first binary signal (Com i ) is at the second voltage (Vdd), and controls the first switch to be on when the first binary signal (Com i a first circuit (64) for controlling the first switch (T1) configured to control the first switch (T1) to be off when the second binary signal (Data j and a second circuit (66) for controlling the second switch (T2) configured to control the second switch (T2) to be off when the first voltage Vcc is at the third voltage.

4. A second circuit (66) for controlling the second switch (T2) receives the second binary signal (Data j ) is at the second voltage (Vdd) and the first binary signal (Com i ) is at the third voltage (Gnd), and controls the second switch to be on when the first binary signal (Com i 4. The display pixel of claim 3, configured to control the second switch to be off when the first voltage (Vdd) is at the second voltage (Vdd).

5. Display pixel according to any one of claims 2 to 4, wherein the first switch (T1) is a first MOS transistor and the second switch (T2) is a second MOS transistor.

6. the gate of the first MOS transistor is connected to the third conductive pad (36); 6. A display pixel according to claim 5, wherein the gate of the second MOS transistor is connected to the fourth conductive pad (36).

7. 7. A display pixel according to claim 2, wherein the circuit (60) for supplying a power supply voltage (Vdd) comprises a capacitor (C) having a first plate connected to the node (Q) and a second plate coupled to the second conductive pad (36).

8. 7. A display pixel according to claim 2, wherein the circuit (60) for supplying a supply voltage (Vdd) does not comprise a capacitor (C) having a plate connected to the node (Q).

9. The drive circuit (40) outputs the first binary signal (Com i The second binary signal (Data j 9. The display pixel of claim 1 , configured to determine a digital signal (R, G, B) from the value of each of the first and second pixel elements (P, P, R, G, B) and to control the light emitting diode (LED) based on the digital signal.

10. The drive circuit (40) outputs the first binary signal (Com i ) is received during each of the first pulses at the second voltage (Vdd), or the first binary signal (Com i ) is at the third voltage (Gnd) during each of the first pulses, or i The second binary signal (Data) received immediately after each first pulse at the third voltage (Gnd) j 10. The display pixel of claim 9, configured to determine digital signals (R, G, B) from the values ​​of the first, second, third, and fourth pixels, and to control the light emitting diode (LED) based on the digital signals.

11. 11. Display pixel according to claim 9 or 10, wherein the driver circuit (40) is configured to control the light emitting diode (LED) by pulse width modulation based on the digital signals (R, G, B).

12. 12. The display pixel of claim 1, comprising only the first conductive pad (36), the second conductive pad (36), the third conductive pad (36) and the fourth conductive pad (36).

13. The drive circuit (40) outputs the first binary signal (Com i 13. The display pixel of claim 1, wherein a first pulse period of said first voltage (Vdd) or said third voltage (Gnd) is configured to turn said light emitting diode (LED) on or off during a second pulse period of said first pulse period of said second voltage (Vdd) or said third voltage (Gnd).

14. The first binary signal (Com i ) is a first binary voltage, and the second binary signal (Data j 14. The display pixel of claim 1, wherein n is a second binary voltage.

15. A display pixel (12) according to any one of claims 1 to 14. i,j ) array, For each of the display pixels, the first voltage (Vcc) is supplied between the first conductive pad and the second conductive pad, and the first binary signal (Com i ) to the fourth conductive pad, and the second binary signal (Data j The display screen (10) further comprises circuitry (22, 24) for transmitting a

16. A display pixel (12) according to any one of claims 1 to 14. i,j 1. A method for controlling a display screen (10) comprising an array of The display pixel (12 i,j ), the first voltage (Vcc) is supplied between the first conductive pad and the second conductive pad, and the first binary signal (Com i ) to the fourth conductive pad, and the second binary signal (Data j ) method.

17. In operation, the first binary signal (Com i ) and the second binary signal (Data j ) is at the second voltage (Vdd), and i ) and the second binary signal (Data j The average duration of the first binary signal (Com) at the third voltage (Gnd) i ) and the second binary signal (Data j The first binary signal (Com) is at the second voltage (Vdd) such that the ratio of the average duration of at least one of the first binary signal (Com) to the sum of the average durations of the second voltage (Vdd) is higher than 75%. i ) and the second binary signal (Data j 17. The method of claim 16, further comprising transmitting

18. During operation, the first binary signal (Com i ) and the second binary signal (Data j ) is at the second voltage (Vdd). i ) and the second binary signal (Data j 20. The method of claim 17, further comprising transmitting

19. The display pixel (12 i,j ) for each of the first binary signals (Com i ) delivers a first pulse at the second voltage (Vdd); The drive circuit (40) of the display pixel outputs the first binary signal (Com i The second binary signal (Data) received during each of the first pulses at the second voltage (Vdd) j 19. The method according to claim 16, further comprising: determining digital signals (R, G, B) based on the values ​​of the first, second, third, and fourth light emitting diodes (LEDs) based on the digital signals.

20. The display pixel (12 i,j ) for each of the first binary signals (Com i ) sends a first pulse at the third voltage (Gnd); The drive circuit (40) of the display pixel outputs the first binary signal (Com i The second binary signal (Data) received during each of the first pulses at the third voltage (Gnd) j 19. The method according to claim 16, further comprising: determining digital signals (R, G, B) based on the values ​​of the first, second, third, and fourth light emitting diodes (LEDs) based on the digital signals.

21. The display pixel (12 i,j ) for each of the first binary signals (Com i ) sends a first pulse at the third voltage (Gnd); The drive circuit (40) outputs the first binary signal (Com i The second binary signal (Data) received immediately after each first pulse at the third voltage (Gnd) j 19. The method according to claim 16, further comprising: determining digital signals (R, G, B) based on the values ​​of the first, second, third, and fourth light emitting diodes (LEDs) based on the digital signals.

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