Multilevel Programming of Phase-Change Memory Devices

Abstract

The phase change memory includes a phase change structure. There is a heater coupled to a first side of the phase change structure. A first electrode is coupled to a second side of the phase change structure. A second electrode is coupled to the second side of the heater. A third electrode is connected to a first lateral end of the phase change structure and a fourth electrode is connected to a second lateral end of the phase change structure.

Description

[Technical field]

[0001] The present invention relates generally to semiconductor devices, and more particularly to phase change memory devices and methods for fabricating the same. [Background technology]

[0002] In recent years, phase change memory (PCM) has emerged as a viable memory technology and has been considered to be a potential next generation non-volatile solid-state memory. Phase change material memory is a type of non-volatile memory device that stores information as the resistive state of a material that can be in different resistive states corresponding to different phases of the material. The different phases can include an amorphous state having a high resistivity and a crystalline state having a low resistivity (i.e., a resistivity lower than that of the amorphous state). The transition between the amorphous and crystalline states can be induced by controlling the cooling rate after application of an electrical pulse that renders the phase change memory material amorphous in the first part of the programming process. The second part of the programming process involves controlling the cooling rate of the phase change memory material. When a rapid quench occurs, the phase change memory material can be cooled to an amorphous high resistivity state. When a slower cooling occurs, the phase change memory material can be cooled to a crystalline low resistivity state. In this way, the state of the PCM can be controlled. Summary of the Invention

[0003] In various embodiments, a phase change memory cell and method of fabricating the same are provided. The phase change memory cell includes a phase change structure. A heater is coupled to a first side of the phase change structure. A first electrode is coupled to a second side of the phase change structure. A second electrode is coupled to the second side of the heater. A third electrode is connected to a first lateral end of the phase change structure and a fourth electrode is connected to a second lateral end of the phase change structure.

[0004] In one embodiment, the phase change structure includes a stack of alternating layers of resistive liner (RL) and phase change memory (PCM).

[0005] In one embodiment, the thickness of at least one PCM layer in a stack of alternating layers of RL and PCM is different from the other PCM layers in the stack.

[0006] In one embodiment, at least one RL layer in a stack of alternating RL and PCM layers has a different thickness than other RL layers in the stack.

[0007] In one embodiment, the phase change structure includes a homogenous phase change material (PCM) without a RL layer.

[0008] In one embodiment, the phase change structure has a trapezoidal prism shape.

[0009] In one embodiment, the phase change structure has a trapezoidal first portion and a rounded or right angled second abutting portion.

[0010] In one embodiment, the first and second electrodes are configured to program the phase change structure.

[0011] In one embodiment, the phase change structure is configured to store two or more bits.

[0012] In one embodiment, the third and fourth electrodes are configured to read the state of the phase change structure.

[0013] In one embodiment, a substrate is present below the first electrode, a first dielectric layer is present above the substrate and to the left and right of the first electrode, and a second dielectric layer is present above the phase change structure and to the left and right of the heater.

[0014] In one embodiment, the phase change structure becomes wider towards the substrate.

[0015] In one embodiment, a substrate is present below the second electrode. A first dielectric layer is present above the substrate and to the left and right of the second electrode. Silicon nitride (SiN) layers are present above the first dielectric layer and the second electrode and to the left and right of the heater.

[0016] In one embodiment, the phase change structure tapers towards the substrate.

[0017] In one embodiment, the heater has a ring shape.

[0018] In one embodiment, the heater includes multiple layers.

[0019] According to one embodiment, a method for fabricating a phase change memory cell memory is provided: a bottom electrode is provided; a phase change structure is formed over the bottom electrode; left and right electrodes are formed on the left and right sides, respectively, of the phase change structure; a heater is formed above the phase change structure; and a top electrode is provided above the heater.

[0020] In one embodiment, the bottom electrode is above a substrate and the phase change structure has a trapezoidal prism shape that widens toward the substrate.

[0021] In one embodiment, the left and right electrodes provide multiple levels of the phase change structure.

[0022] In one embodiment, forming the phase change structure includes providing a stack of alternating layers of resistive liner (RL) and phase change memory (PCM).

[0023] In one embodiment, the method further includes providing a first dielectric layer on an upper side of the substrate to the left and right of the first electrode, and a second dielectric layer is formed on an upper side of the phase change structure and to the left and right of the heater.

[0024] The techniques described herein may be implemented in many ways, example implementations are provided below with reference to the following drawings:

[0025] The drawings are of exemplary embodiments. They do not represent all embodiments. Other embodiments may be used in addition or alternatively. Details that may be obvious or unnecessary may be omitted to save space or for a more effective explanation. Some embodiments may be practiced with additional components or steps or without all components or steps shown, or both. When the same numeral appears in different drawings, it refers to the same or similar components or steps. [Brief description of the drawings]

[0026] [Figure 1A] 1 is a cross-sectional front view of a phase change memory capable of storing two or more bits according to an exemplary embodiment. [Figure 1B] 1 is a cross-sectional side view of a phase change memory capable of storing two or more bits according to an exemplary embodiment. [Figure 1C] FIG. 1 illustrates an exemplary comparison of programming curves for a rectangular cell and a trapezoidal cell, according to an exemplary embodiment. [Figure 2A] 1A-1D illustrate a semiconductor structure that has undergone several semiconductor processing steps, according to an exemplary embodiment. [Figure 2B] 1 is a cross-sectional view of a semiconductor structure having alternating stacks of phase change memory layers and resistive liner according to an illustrative embodiment. [Figure 2C] 1 is a plan view of a semiconductor structure having alternating stacks of phase change memory layers and resistive liner according to an illustrative embodiment. [Figure 3A] 2 is a cross-sectional view of a semiconductor structure having a deposition of read electrodes on the lateral left and right sides of the semiconductor structure according to an exemplary embodiment. [Figure 3B]2 is a plan view of a semiconductor structure having a deposition of read electrodes on the lateral left and right sides of the semiconductor structure according to an exemplary embodiment. FIG. [Figure 4A] 1 is a cross-sectional view of a semiconductor structure having a trapezoid according to an example embodiment. [Figure 4B] 1 is a plan view of a semiconductor structure having a trapezoid according to an example embodiment. [Figure 5A] 1 is a cross-sectional view of a semiconductor structure in which a bottom corner of a phase change structure is removed. [Figure 5B] 2 is a top view of a semiconductor structure with a bottom corner of the phase change structure removed. FIG. [Figure 6A] 4B is a cross-sectional view of a semiconductor structure for encapsulation layer deposition in the trench region of FIG. 4A according to an exemplary embodiment. [Figure 6B] 4B is a plan view of a semiconductor structure for encapsulation layer deposition in the trench region of FIG. 4A according to an illustrative embodiment. [Figure 7A] 1 is a cross-sectional view of a semiconductor structure immediately after deposition and planarization of an encapsulation layer in accordance with an illustrative embodiment. [Figure 7B] 1 is a top view of a semiconductor structure immediately after deposition and planarization of an encapsulation layer in accordance with an illustrative embodiment. [Figure 8A] 1 is a cross-sectional view of a semiconductor structure including a top electrode according to an illustrative embodiment. [Figure 8B] 1 is a plan view of a semiconductor structure including a top electrode according to an illustrative embodiment; [Figure 9A] 2 is another cross-sectional view of a semiconductor structure with a top electrode according to an illustrative embodiment. [Figure 9B] 2 is another plan view of a semiconductor structure with a top electrode according to an illustrative embodiment. [Figure 10A] 1A-1C are cross-sectional views of memory structures having stacked structures in which the resistive liner and / or phase change memory layer may be of different thicknesses, according to example embodiments. [Figure 10B] 1A-1C are cross-sectional views of memory structures having stacked structures in which the resistive liner and / or phase change memory layer may be of different thicknesses, according to example embodiments. [Figure 11] FIG. 2 is a cross-sectional view of a phase change memory cell in which the RL layer is omitted and a full PCM film is used instead, according to an exemplary embodiment. [Figure 12A] 1A-1D illustrate a semiconductor structure that has undergone several semiconductor processing steps, according to an exemplary embodiment. [Figure 12B] FIG. 2 is a cross-sectional view of a semiconductor structure having a first dielectric deposited over a SiO 2 and a bottom electrode according to an illustrative embodiment. [Figure 13A] FIG. 2 is a cross-sectional view of a semiconductor structure having an open via in a dielectric layer that extends to the top surface of a bottom electrode. [Figure 13B] 1 is a cross-sectional view of a semiconductor structure having a heater formed therein according to an exemplary embodiment. [Figure 14A] 1 is a cross-sectional view of a semiconductor structure having a phase change structure coupled to a heater according to an illustrative embodiment. [Figure 14B] 1 is a plan view of a semiconductor structure having a phase change structure coupled to a heater according to an illustrative embodiment. [Figure 15A] 2A-2C are different cross-sectional views of a semiconductor structure illustrating example shapes of alternating stacks of resistive liners and phase change memory layers according to example embodiments. [Figure 15B] 2A-2C are different plan views of a semiconductor structure illustrating example shapes of alternating stacks of resistive liners and phase change memory layers according to example embodiments. [Figure 16A] FIG. 2 is a cross-sectional view having a sealing layer according to an exemplary embodiment. [Figure 16B] FIG. 2 is a top view having an encapsulation layer according to an exemplary embodiment. [Figure 17A] 1 is a cross-sectional view of a semiconductor structure with a dielectric deposition according to an exemplary embodiment. [Figure 17B] 1 is a plan view of a semiconductor structure with a dielectric deposition according to an exemplary embodiment; [Figure 18A] 4 is another cross-sectional view of a semiconductor structure according to an example embodiment. [Figure 18B]2 is another plan view of a semiconductor structure in accordance with an example embodiment. [Figure 19] 1 provides a three-dimensional (3D) perspective view of a PCM structure, according to an exemplary embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] overview

[0028] In the following detailed description, numerous specific details are set forth by way of example in order to provide a thorough understanding of the relevant teachings. However, it will be apparent that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components or circuits, or combinations thereof, have been described at a relatively high level, without detailed description, in order to avoid unnecessarily obscuring aspects of the present teachings.

[0029] In one aspect, spatially related terms such as "front", "back", "top", "bottom", "down", "below", "lower", "upper", "side", "left", "right" and the like may be used with reference to the orientation of the figures being described. Because components of the embodiments of the present invention may be positioned in many different orientations, the directional terms are used for purposes of illustration and not limitation. Thus, it will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in a figure is flipped over, an element described as being "below" or "below" another element or feature will now be oriented "above" the other element or feature. Thus, for example, the term "below" can encompass both an orientation that is above and an orientation that is below. The device may be otherwise oriented (rotated 90 degrees or viewed or referenced in other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0030] As used herein, the terms "lateral" and "horizontal" describe an orientation parallel to a first surface of a semiconductor substrate or body. For example, the substrate can be the surface of a wafer or die.

[0031] As used herein, the term "vertical" describes an orientation that is disposed perpendicular to a first surface of a semiconductor substrate or body.

[0032] As used herein, the terms "coupled" and / or "electrically coupled" are not intended to imply that elements must be directly coupled to one another, and intervening elements may be provided between the "coupled" or "electrically coupled" elements. In contrast, when an element is said to be "directly connected" or "directly coupled" to another element, there are no intervening elements present. The term "electrically connected" refers to a low resistance electrical connection between the elements that are electrically connected to one another.

[0033] Terms such as first, second, etc. may be used herein to describe various elements, but these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element, without departing from the scope of the exemplary embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0034] Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized or simplified embodiments (and intermediate structures). As such, variations from the illustrated shapes as a result, for example, of manufacturing techniques and / or tolerances, may be expected. Accordingly, the regions illustrated in the drawings are schematic in nature and their shapes are not necessarily indicative of the proportions of actual regions or devices and are not limiting in scope.

[0035] It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined by the claims. The description of the embodiments is not intended to be limiting. In particular, elements of the embodiments described below may be combined with elements of different embodiments.

[0036] The present invention generally relates to modern architectures of phase change memory (PCM) that allow for better control of and more accurate determination of the state of memory cells. To achieve higher density phase memory devices, a prominent consideration is the ability to store many bits per unit area. In this regard, PCMs have the ability to achieve many different intermediate states, and thus the ability to hold a large number of bits in a single cell. Intermediate resistances between amorphous and crystalline can be formed by incomplete phase transitions in the material, or by the size and shape of the amorphous regions in the phase change material. Known devices and fabrication techniques do not provide a fully effective method for achieving multilevel programming and storage in phase change memory cells. Thus, provided by the teachings herein are methods and structures for forming multilevel programmable phase change memory devices. The techniques described herein can be implemented in many ways. Exemplary implementations are provided below with reference to the following drawings. Exemplary Phase Change Memory

[0037] Reference is now made to FIGS. 1A and 1B, which respectively provide a front cross-sectional view 100A and a side cross-sectional view 100B of a phase change memory capable of storing two or more bits, according to an exemplary embodiment. The PCM cell 100A / B has a PCM material 210 and a resistive liner (RL) 208 alternately stacked between a heater 104 and a top electrode 806. The resistance of each RL 208 is substantially higher than the resistance of the PCM layer 210. While each PCM layer 210 undergoes a phase change from crystalline to amorphous in a subsequent sequence during programming, the multiple resistances can be read by two read electrodes 320 connected to two lateral ends of the PCM cell segment. The more crystalline the PCM layer 210, the lower the resistance it exhibits. Each PCM layer can be seen as a parallel resistor between two read electrodes 320. By way of example only and not by way of limitation, three PCM layers 210, each separated by a RL 208, are shown in FIGS. 1A and 1B, although it will be understood that any suitable number of stacks is within the scope of the present invention.

[0038] In one embodiment, the PCM cell 100A can have trapezoidal prism-shaped segments, sometimes referred to herein as phase change structures 250, with alternating stacks of PCM 210 and RL 208, with the bottom and top surfaces of the trapezoidal segments electrically connected to the bottom electrode 206 and top electrode 806, respectively. Between the top electrode 806 and the phase change structure 250 is the heater 104. As a thermally hot spot occurs around the interface between the heater and the phase change structure 250, amorphization of the phase change material by melting / quenching (often referred to as the reset operation of the phase change memory) starts in the phase change material layer adjacent to the heater and propagates to the other phase change material layers (downward in FIG. 1A and FIG. 1B). The trapezoid provides better control of the amorphization of each phase change material layer in the phase change structure 250. In other words, when amorphization starts near the heater and propagates downward, each phase change material layer can be fully crystallized at a lower reset current compared to the rectangle. Otherwise, a higher reset current may be required to completely (e.g., almost) shut off the segment and prevent any "leakage current," sometimes referred to herein as parasitic leakage, around the portions of the PCM 210 that were not sufficiently crystallized. In addition to the benefit of reduced reset current, another benefit of the trapezoidal phase change structure 250 is shown in FIG. 1C, which provides an exemplary comparison of programming curves for the rectangular cell 170 and the trapezoidal cell 172, according to an exemplary embodiment. As shown in FIG. 1C, the trapezoidal cell 172 provides a significantly more linear conductance (i.e., inverse resistance) response than that of the rectangular cell 170.

[0039] 1A and 1B, a voltage and / or current between the programming electrodes, sometimes referred to herein as the write top electrode 806 and the bottom electrode 206, can change the phase of one or more PCM layers in a controlled manner. For example, a current provided through the heater 104 can cause the different PCM layers to become progressively amorphous. The read electrodes 320 can be provided at the two lateral ends of the trapezoidal prism. Importantly, the read electrodes 320 on the left and right sides of the structure 100B are separate from the programming electrodes 806 and 206. For example, a small voltage applied between the read electrodes 320 can determine the cumulative resistance of the stack segments of the alternating stacks of PCM and RL. Due to the construction of the exemplary structures shown in FIG. 1A and 1B, the multi-level programmable PCM cell 100A / B is provided with a resistive liner 208 that can mitigate resistance drift. Exemplary Processes for Phase Change Memory

[0040] With the above description of the structure of the exemplary phase change memory cell 100A / B, it may be beneficial to describe an exemplary process for fabricating the same. To that end, FIGS. 2-18 illustrate various steps in the fabrication of a phase change memory cell according to an exemplary embodiment. In particular, FIG. 2(A) illustrates a semiconductor structure 200A that has undergone several semiconductor processing steps. Processing begins with a substrate 202. In various embodiments, the substrate 202 may comprise any suitable material or combination of materials, such as doped or undoped silicon, glass, dielectrics, etc. For example, the substrate may comprise, for example, a semiconductor-on-insulator (SOI) structure with a buried insulator layer, or a bulk material substrate with appropriately doped regions, for example commonly referred to as wells. In another embodiment, the substrate may be silicon with a silicon oxide, nitride, or any other insulating film on top.

[0041] Other materials that may be used for the substrate include, but are not limited to, sapphire, aluminum oxide, germanium, gallium arsenide (GaAs) or any of the other III-V periodic table compounds, indium phosphide (InP), silicon carbide (SiC), alloys of silicon and germanium, etc. The substrate 202 can act as a conductor or an insulator depending on the materials and concentrations selected. Thus, as used herein, the term substrate 202 refers to a foundation upon which a PCM can be built. In some embodiments, the foundation already has pre-built devices, such as transistor devices, isolation structures, contacts, etc.

[0042] A bottom electrode 206 is surrounded by an inter-layer dielectric (ILD), such as silicon dioxide, and is formed on top of the substrate 202. In one embodiment, the bottom electrode may be used as a bitline.

[0043] 2(B) and 2(C) provide cross-sectional and plan views 200B and 200C, respectively, of a semiconductor structure having a stack of alternating PCM layers 210 and RLs 208, according to an example embodiment. There are N PCM layers 210 and N+1 RL layers 208. In the example of FIG. 2(B), the number of PCM layers N is 3, although other numbers are supported. In an embodiment, the thickness of each PCM layer 210 and RL may be different. In other words, the thickness of one or more RL layers may be different, the thickness of one or more PCM layers may be different, or any combination thereof. In yet another embodiment, the RL layer may be omitted and a complete PCM film may be used as the phase change material element. In various embodiments, the PCM layer may include, without limitation, a Ge-Sb-Te (germanium-antimony-tellurium or "GST") alloy, a Si-Sb-Te (silicon-antimony-tellurium) alloy, a Ga-Sb-Te (gallium-antimony-tellurium) alloy, a Ge-Bi-Te (germanium-bismuth-tellurium) alloy, an In-Se (indium-tellurium) alloy, an As-Sb-Te (arsenic-antimony-tellurium) alloy, an Ag-In-Sb-Te (silver-indium-antimony-tellurium) alloy, a Ge-In-Sb-Te alloy, a Ge-Sb alloy, an Sb-Te alloy, a Si-Sb alloy, and combinations thereof. In some embodiments, the phase change material may further include nitrogen, carbon, or oxygen, or combinations thereof. In some embodiments, the phase change material can be doped with a dielectric material, including but not limited to aluminum oxide, silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, cerium oxide, silicon nitride, silicon oxynitride, germanium oxide, germanium nitride, germanium oxynitride, etc. An exemplary method for forming the phase change material uses physical vapor deposition (PVD)-sputtering or magnetron-sputtering methods. Other deposition methods, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), etc., are also contemplated.With respect to the RL layer, in various embodiments, it may include, but is not limited to, aluminum nitride (AlN), boron nitride (BN), aluminum oxide (AlO), TaN, TiN, tungsten nitride (WN), cobalt tungsten (CoW), nickel tungsten (NiW), or yttrium oxide (YO), or any combination thereof. The resistance of the resistive liner is substantially greater than the resistance of the heater (e.g., 5-50 times greater, or about 20 times greater). Furthermore, the resistance of the resistive liner is substantially greater than the resistance of the phase change material in the low resistance state (e.g., 10-40 times greater, or about 20 times greater) and substantially lower than the resistance of the phase change material in the high resistance state (e.g., 5-50 times lower, or about 10 times lower). The resistivity of the resistive liner can be, for example, in the range of 0.1 ohm-micrometer (Ωμm) to 1 kiloohm-micrometer (kΩμm). The resistive liner may be deposited by any suitable technique, including but not limited to ALD, PVD, CVD, etc. In one embodiment, the metal layer is tantalum nitride (TaN) and the PCM layer is GST (germanium-antimony-tellurium), e.g., a 10 nm GST / 2 nm TaN liner. The stacked layers of PCM 210 and RL 208 are patterned into strips.

[0044] 3(A) and 3(B) provide cross-sectional and plan views 300A and 300B, respectively, of a semiconductor structure having the formation of a read electrode 320 on the lateral left and right sides of the semiconductor structure, according to an exemplary embodiment. To that end, in some embodiments, an etch mask layer may be provided, and layers not protected thereby are removed on the left and right sides of the semiconductor structure to form the read electrode 320. For example, as will be appreciated by those skilled in the art, a mask layer (not shown) may be provided on the TiN layer 230, which may be a soft mask such as photoresist or a hard mask such as amorphous carbon. The lithography process may be performed, for example, by exposing the photoresist material to a pattern of light and developing the exposed photoresist material. An etching process, such as reactive ion etching (RIE), may be used to form a pattern (e.g., an opening) by removing portions of the TiN 230 and the stack of PCM 210 and RL 208 down to the top surface of SiO 2 204. After etching, the mask layer may be removed using a conventional plasma ashing or stripping process. Thus, the pattern of the mask layer facilitates removal of the TiN230 and multiple layers of the PCM / RL stack layer in areas where the mask layer is not deposited, leaving two read electrode areas, which are then filled with a conductive material. In various embodiments, the conductive material may include tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), nickel (Ni), titanium (Ti), ruthenium (Ru), molybdenum (Mo), or any other suitable conductive material. Each electrode may further include a barrier layer. The barrier layer may be titanium nitride (TiN), tantalum nitride (TaN), hafnium nitride (HfN), niobium nitride (NbN), tungsten nitride (WN), tungsten carbonitride (WCN), or combinations thereof. In various embodiments, the barrier layer may be deposited in the trench(es) by ALD, CVD, MOCVD, PECVD, or combinations thereof. In various embodiments, the conductive material can be formed by ALD, CVD, PVC or plating or a combination thereof.

[0045] Reference is now made to FIGS. 4(A) and 4(B), which respectively provide a cross-sectional view 400A and a plan view 400B of a semiconductor structure having a trapezoidal shape, according to an exemplary embodiment. In one embodiment, a deep tapered etch based on cyclic passivation and etching is provided to form trenches 430 and 432, thereby forming a substantially trapezoidal-like PCM pattern shape. In an alternative embodiment, as shown in FIGS. 5(A) and 5(B), the bottom corners 502 of the RL / PCM 208 / 210 are removed. For example, the bottom corners 502 are removed after cyclic etching and passivation of the trenches on the left and right sides of the stacked PCM / RL structure, without passivation reduced during the final etching step. By removing the final corners 502, parasitic current leakage paths are mitigated by allowing the PCM to be more completely amorphized. For example, a trapezoidal cell with rounded (or squared) corners has a reset current (e.g., ≦250 μA, where μA stands for micro-amperes) that is less than that of a rectangular cell (e.g., >400 μA). Thus, the teachings herein may have any suitable shape, such as a rectangle, a trapezoid, or a partial trapezoid that does not have a tapered bottom as described above.

[0046] 6(A) and 6(B) provide cross-sectional and plan views 600A and 600B, respectively, of a semiconductor structure for deposition of an encapsulation layer 610 in the trench region of FIG. 4(A) according to an exemplary embodiment. More specifically, FIG. 6(B) shows the plan view 600B immediately after the encapsulation layer 610 has been deposited. In one embodiment, the encapsulation layer 610 is a dielectric and may include silicon nitride (SiN) or silicon dioxide (SiO2). Thus, the open trench is backfilled with a dielectric. Backfill may include silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), carbon doped silicon oxide (SiOC), fluorine doped silicon oxide (SiO:F), silicon-carbon-nitrogen (SiCN), boron nitride (BN), silicon boron nitride (SiBN), silico boron carbonitride (SiBCN), silicon oxycarbonitride (SiOCN), silicon oxide, boron carbonitride (BCN), hydrogen silsesquioxane polymer (HSQ), methyl silsesquioxane polymer (MSQ), methyl doped silica (SiO:(CH3)), organosilicate glass (SiCOH), porous SiCOH, and combinations thereof. Deposition methods: CVD, ALD, spin-on, etc. This dielectric is deposited and chemical mechanical planarization (CMP) is used for planarization stopping on the top surface of TiN230. In this regard, FIGS. 7(A) and 7(B) provide a cross-sectional view 700A and a top view 700B, respectively, of a semiconductor structure immediately after deposition and planarization of an encapsulation layer 610, according to an example embodiment.

[0047] 8(A) and 8(B) provide a cross-sectional view 800A and a plan view 800B, respectively, of a semiconductor structure including a top electrode 806, according to an example embodiment. In one embodiment, the bottom and top electrodes are the same material, such as tungsten (W).

[0048] 9(A) and 9(B) provide another cross-sectional view 900A and plan view 900B of a semiconductor structure with a top electrode 806 according to an exemplary embodiment. More specifically, FIG. 9(A) shows a phase change structure including a predetermined number of intermittent RL layers 208 and PCM layers 210 stacked in an alternating manner. Although only three PCM layers 210 are shown, it will be understood that many (e.g., tens or hundreds) of such alternating stacked layers are within the scope of the present teachings. The top electrode 806 and the bottom electrode 206 can be used for programming (e.g., controlling the amorphous or crystalline state) of the stacked layers. The left and right electrodes 320 can be used to read the state of the stacked layers.

[0049] As mentioned above, the thickness of the PCM layer or the RL or both can be different. In this regard, reference is made to Figures 10(A) and 10(B) which show cross-sectional views of memory structures having stacked structures in which the RL and / or PCM can be different. In other words, the thickness of one or more RL layers can be different, the thickness of one or more PCM layers can be different, or any combination thereof. In yet another embodiment, as shown in Figure 11, the RL layer can be omitted and the complete PCM film 1102 can be used as the phase change material element.

[0050] Reference is now made to Figures 12(A)-18(B), which show various steps in the fabrication of another memory semiconductor memory structure, according to an embodiment. In particular, Figure 12(A) shows a semiconductor structure 1200A that has undergone several semiconductor processing steps. Processing begins with a substrate 202 having a bottom electrode. Similar structures have been described previously and therefore will not be repeated here for brevity. As shown in Figure 12(B), a first dielectric is deposited on top of the SiO2 and bottom electrode. In one embodiment, the first dielectric is silicon nitride (SiN).

[0051] FIG. 13(A) is a cross-sectional view 1300A of a semiconductor structure having an open via in the dielectric layer 1204 that extends to the top surface of the bottom electrode 206. Appropriate patterning and etching techniques can be used. The resulting via opening is then filled with a conductive material, as shown in the semiconductor structure 1300B in FIG. 13(B). In various embodiments, titanium nitride (TiN), tungsten (W), tantalum nitride (TaN), titanium aluminide (TiAl), or the like, or any combination thereof, can be used to form the heater 1308. Although a single layer heater 1308 is shown, in various embodiments, the heater may include many layers and may be annular. The dielectric layer 1204 and the heater 1308 layers can be planarized by a CMP process.

[0052] 14(A) and 14(B) provide a cross-sectional view 1400A and a plan view 1400B, respectively, of a semiconductor structure having a stacked structure 1402 coupled to a heater 1308, according to an exemplary embodiment. The stacked structure 1402 includes alternating stacked PCM materials 1410 and RL 1408 between the heater 1308. In one embodiment, the phase change material may include germanium-antimony-tellurium (GST). Although only three PCM layers 1410 are shown, the stacked structure 1402 may include many more (e.g., tens or hundreds) of such alternating layers. In one embodiment, a TiN layer 1420 is disposed on top of the stacked structure 1402, followed by a hard mask layer 1430, sometimes referred to as an etch mask. For example, a 10 nm GST / 2 nm TaN liner.

[0053] 15(A) and 15(B) provide different cross-sectional views 1500A and plan views 1500B of a semiconductor structure showing an example shape of a stack of alternating RL and PCM layers according to an example embodiment. The upside-down trapezoid (i.e., narrowly tapering toward the substrate 202 with respect to the substrate 202) is achieved by PCM patterning (e.g., periodic passivation and etching). Thus, in contrast to the memory structure of FIG. 8(A), the heater 1308 is coupled to the bottom electrode 206. In one embodiment, as shown in the semiconductor structure 1600A of FIG. 16(A), a sealing layer is provided on the top side of the dielectric (e.g., SiN) layer 1204, the sidewalls of the RL and PCM stacks, the TiN layer 140, and the exposed surface of the hard mask layer 1430. In one embodiment, as shown in FIG. 16(B), the SiN layer 1610 is optional (i.e., not used).

[0054] 17(A) and 17(B) provide a cross-sectional view 1700A and a plan view 1700B of a semiconductor structure with deposition of a dielectric 1708 according to an example embodiment. In one embodiment, the dielectric is silicon oxide. CMP can be used to planarize the top surface of the dielectric 1708 with a stop at the top surface of the hardmask layer 1430, which also removes the encapsulation layer.

[0055] Reference is now made to Figures 18(A) and 18(B), which show another cross-sectional view 1800A and plan view 1800B of a semiconductor structure, according to an exemplary embodiment. There is a top electrode 1420 coupled to the top side of the stacked alternating RL and PCM structures. There is a hard mask 1430 on top of the top electrode 1420. Spacers 1804 are formed on each side of the hard mask 1430 and the top electrode 1420.

[0056] A heater 1308 is coupled between the bottom of the stacked alternating RL and PCM structure and the bottom electrode 206. The top and bottom electrodes 1420, 206 are used to program the stacked structure. Importantly, the read electrodes 1820 are separate from the top electrode 1420 and bottom electrode 206 and are at the lateral ends of the stacked structure.

[0057] FIG. 19 provides a three-dimensional (3D) perspective view of a PCM structure, according to an example embodiment.

[0058] The methods described above may be used in the manufacture of integrated circuit chips. The resulting integrated circuit chips may be distributed by manufacturers in raw wafer form (i.e., as a single wafer with many unpackaged chips), as bare die, or in packaged form. In the latter case, the chips may be mounted in a single-chip package (such as a plastic carrier or other higher level carrier with leads attached to a motherboard) or in a multi-chip package (such as a ceramic carrier with single- or double-sided interconnects or embedded interconnects). In either case, the chips may then be integrated with other chips, discrete circuit elements, or other signal processing devices, or combinations thereof, as part of either (a) an intermediate product such as a motherboard or (b) a final product. The final product may be any product that includes the integrated circuit chip, ranging from low-cost applications such as toys to modern computer products with displays, keyboards or other input devices, and central processing units. conclusion

[0059] The description of various embodiments of the present teachings is provided for illustrative purposes, but is not intended to be comprehensive or limited to the disclosed embodiments. Many changes and modifications will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used in this specification have been selected to best explain the principles of the embodiments, practical applications or technical improvements from the technology found in the market, or to enable other skilled in the art to understand the embodiments disclosed herein.

[0060] While the above describes what is believed to be the best mode and / or other examples, it is understood that various modifications may be made therein, that the subject matter disclosed herein may be embodied in various forms and examples, and that the teachings may be applied in many applications, only a few of which are described herein. It is intended by the following claims to claim any and all applications, modifications and variations that fall within the true scope of the present teachings.

[0061] The components, steps, features, objects, benefits and advantages discussed herein are merely illustrative. None of them or any of the discussions related thereto are intended to limit the scope of protection. Although various advantages have been discussed herein, it will be understood that not all embodiments necessarily include all advantages. Unless otherwise stated, all measurements, values, ratings, positions, dimensions, sizes and other specifications set forth in this specification, including the following claims, are approximate and not precise. They are intended to have a reasonable range consistent with the functions to which they relate and those customary in the art to which they relate.

[0062] Numerous other embodiments are contemplated, including embodiments having fewer, additional, or different or combinations of components, steps, features, objects, benefits, and advantages, including embodiments in which the components and / or steps are arranged and / or ordered differently.

[0063] While the above has been described in connection with exemplary embodiments, it is understood that the term "exemplary" means merely an example, not best or optimal. Except as stated immediately above, nothing described or illustrated is intended to, or should be construed to, result in the provision to the public of any component, step, feature, object, benefit, advantage, or equivalent, whether or not it is recited in the claims.

[0064] It will be understood that the terms and expressions used herein have ordinary meanings consistent with such terms and expressions with respect to the corresponding respective areas of investigation and study, unless a specific meaning is otherwise indicated herein. Relational terms such as first, second, etc. may be used only to distinguish one entity or act from another, without necessarily requiring or implying any actual such relationship or order between such entities or acts. The terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusions, such that a process, method, article, or apparatus that includes a list of elements does not include only those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element following "a" or "an" does not, without further constraints, preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0065] The Abstract of the Disclosure is provided to enable the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above Detailed Description, it will be appreciated that various features have been grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the claimed embodiments have more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.

Claims

1. A phase change memory cell, comprising: A phase change structure; a heater coupled to a first surface of the phase change structure; a first electrode coupled to a second surface of the phase change structure; a second electrode coupled to a second surface of the heater; a third electrode connected to a first lateral end of the phase change structure; a fourth electrode connected to a second lateral end of the phase change structure.

2. The phase change memory cell of claim 1 , wherein the phase change structure comprises a stack of alternating layers of resistive liner (RL) and phase change memory (PCM).

3. 3. The phase change memory cell of claim 2, wherein a thickness of at least one PCM layer in said stack of alternating layers of said RL and said PCM layers is different from other PCM layers in said stack.

4. 10. The phase change memory cell of claim 1, wherein a thickness of at least one RL layer in the stack of alternating RL and PCL layers is different from other RL layers in the stack.

5. The phase change memory cell of claim 1 , wherein the phase change structure comprises a homogeneous phase change material (PCM).

6. The phase change memory cell of claim 1 , wherein the phase change structure has a trapezoidal prism shape.

7. 2. The phase change memory cell of claim 1, wherein the phase change structure has a trapezoidal first portion and a rounded or right angled second abutting portion.

8. 2. The phase change memory cell of claim 1, wherein the first and second electrodes are configured to program the phase change structure.

9. The phase change memory cell of claim 1 , wherein the phase change structure is configured to store two or more bits.

10. The phase change memory cell of claim 1 , wherein the third and fourth electrodes are configured to read a state of the phase change structure.

11. a substrate beneath the first electrode; a first dielectric layer on the top side of the substrate and to the left and right of the first electrode; 10. The phase change memory cell of claim 1 further comprising a second dielectric layer above the phase change structure and to the left and right of the heater.

12. The phase change memory cell of claim 11 , wherein the phase change structure is wider toward the substrate.

13. a substrate beneath the second electrode; a first dielectric layer on the top side of the substrate and to the left and right of the second electrode; 10. The phase change memory cell of claim 1 further comprising a silicon nitride (SiN) layer over the first dielectric layer and the second electrode and on the left and right sides of the heater.

14. The phase change memory cell of claim 13 , wherein the phase change structure tapers toward the substrate.

15. The phase change memory cell of claim 1 , wherein the heater is annular.

16. The phase change memory cell of claim 1 , wherein the heater comprises multiple layers.

17. 1. A method of manufacturing a phase change memory cell, comprising the steps of: providing a bottom electrode; forming a phase change structure over the bottom electrode; forming a left electrode and a right electrode on left and right sides, respectively, of the phase change structure; forming a heater above the phase change structure; providing a top electrode above said heater.

18. 20. The method of claim 17, wherein the bottom electrode is above a substrate, and the phase change structure has a trapezoidal prism shape that widens toward the substrate.

19. 20. The method of claim 17, wherein forming the phase change structure comprises a stack of alternating layers of a resistive liner (RL) and a phase change memory (PCM).

20. providing a first dielectric layer on the upper side of the substrate to the left and right of the first electrode; 20. The method of claim 17, further comprising forming a second dielectric layer over the phase change structure to the left and right of the heater.

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