Graphics Processing Unit Traversal Engine

Abstract

The processing unit uses a hardware traversal engine to traverse an acceleration structure, such as a ray tracing structure. The hardware traversal engine includes one or more memory modules for storing state information and other data used in the structure traversal, and control logic for performing the traversal process based on the stored data and based on received information indicating a source node of the acceleration structure to be used for the traversal process. By employing the hardware traversal engine, the processing unit can perform the traversal process more quickly and efficiently, saving processing resources and improving overall processing efficiency.

Description

[Background technology]

[0001] To improve the fidelity and quality of the generated images, some software and associated hardware perform ray tracing operations, where images are generated by tracing the paths of rays associated with each image. Some of these ray tracing operations use tree structures, such as Bounding Volume Hierarchy (BVH) trees, to represent sets of geometric objects in the scene being rendered. Geometric objects (e.g., triangles or other primitives) are surrounded by bounding boxes or other bounding volumes that form leaf nodes of the tree structure, these nodes are then grouped into smaller sets, each surrounded by its own bounding volume represented by a parent node on the tree structure, these smaller sets are then combined into larger sets that are also surrounded by their own bounding volumes representing higher parent nodes on the tree structure, and so on, until there is a single bounding volume that represents the top node of the tree structure and encompasses all lower level bounding volumes.

[0002] To perform some ray tracing operations, the tree structure is used to identify potential intersections between generated rays and geometric objects in the scene by traversing the nodes of the tree, and at each node traversed, the ray of interest is compared with the bounding volume of that node to determine whether there is an intersection, and if there is an intersection, proceed to the next node in the tree, which is identified based on a traversal algorithm, and so on. However, conventional approaches to traversing a tree structure may consume a relatively large amount of system resources or require a relatively large amount of time, thus limiting the overall quality of the resulting image.

[0003] The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by referencing the accompanying drawings, in which: The use of the same reference numbers in different drawings indicates similar or identical items. [Brief description of the drawings]

[0004] [Figure 1] FIG. 1 is a block diagram of a Graphics Processing Unit (GPU) that traverses a ray tracing structure using a hardware traversal engine, according to some embodiments. [Diagram 2] 2 is a block diagram of the traversal engine of FIG. 1 looping identified nodes of a ray tracing structure to the texture hardware of a GPU in accordance with some embodiments. [Diagram 3] 2 is a block diagram of the traversal engine of FIG. 1 that provides shader commands to a scheduler of a GPU in accordance with some embodiments. [Figure 4] 2 is a block diagram of the traversal engine of FIG. 1 according to some embodiments. [Diagram 5] FIG. 2 is a flow diagram of a method for traversing a ray tracing structure using a hardware traversal engine, according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0005] 1-5 show a technique for employing a hardware traversal engine in a processing unit to traverse an acceleration structure, such as a ray tracing structure. The hardware traversal engine includes one or more memory modules for storing state information and other data used for structure traversal, and control logic for performing the traversal process based on the stored data and based on received information indicating a source node of the acceleration structure to be used for the traversal process. By employing a hardware traversal engine, the processing unit can perform the traversal process more quickly and efficiently, saving processing resources and improving overall processing efficiency.

[0006] To illustrate, a conventional GPU employs software shaders that execute in a shader processor to control ray tracing operations. To perform BVH traversal (i.e., traversal of the BVH tree) for ray tracing, the GPU employs a loop in which the shader provides ray addresses and BVH node addresses to the GPU's texture addressing hardware, which provides corresponding rays and BVH nodes to an intersection engine to identify any intersections between the rays and the BVH nodes, and the intersection results are returned to the shader to determine the next node of the BVH tree to be processed. Thus, the shader initiates each iteration of the tree traversal process, thereby adding overhead for each iteration.

[0007] In contrast to conventional approaches, using the techniques described herein, the GPU can employ a hardware traversal engine to initiate at least some of the iterations of the tree traversal process, thereby reducing the overall overhead associated with the tree traversal. For example, in some embodiments, the traversal engine is configured to receive intersection information from the intersection engine and, based on the intersection information, identify a next step in the traversal process, possibly including continuing the tree traversal by sending the next ray / node intersection to the texture addressing hardware. Thus, for these iterations of the tree traversal, the shader is removed from the traversal process, reducing the overhead associated with the traversal process. In other cases, the traversal engine returns the ray / node intersection information to the shader to perform the specified operation (e.g., any hit shader). Once the operation is completed, the shader instructs the traversal engine to resume the tree traversal process using traversal state information stored in the traversal engine itself. Thus, using the techniques described herein, the control flow of the tree traversal process is offloaded from the shader to the traversal engine hardware, improving overall processing efficiency.

[0008] In some embodiments, the traversal engine includes multiple memory modules for storing data used in the traversal process. Thus, the traversal engine can perform operations quickly and further reduce the impact of the traversal process on memory access traffic in the processing unit, such as by reducing the number of accesses to the cache or local data store of the processing unit. In some embodiments, examples of these memory modules include an initial data store configured to store data extracted from an initial ray tracing call, a TLAS data store configured to store data of rays in a Top Level Acceleration Structure (TLAS) coordinate space, a BLAS data store configured to store data of rays in a Bottom Level Acceleration Structure (BLAS) coordinate space, a traversal state memory configured to store temporary data associated with the current iteration of the traversal process, a nearest hit memory configured to store nearest hit values ​​of rays in a tree structure, and a traversal stack configured to store a stack of node addresses for the current ray that the ray will next intersect.

[0009] For purposes of explanation, Figures 1-5 are described with respect to an example in which the traversal engine is implemented in a GPU and performs a traversal process to traverse a BVH tree, however, it will be understood that in other embodiments, the techniques described herein may be implemented in different types of processing units, implemented to traverse different types of acceleration structures, or any combination thereof.

[0010] 1 illustrates a block diagram of a GPU 100 generally configured to perform ray tracing and other graphical operations on behalf of a processing system, according to some embodiments. A processing system is generally configured to execute a set of instructions (e.g., a computer program) to perform a specified task on behalf of an electronic device. Thus, in different embodiments, the GPU 100 may be incorporated into any of a number of electronic devices, such as, for example, a desktop computer, a laptop computer, a server, a smartphone, a tablet, a gaming console, etc.

[0011] The GPU 100 is configured to receive commands (e.g., drawing commands) from another processing unit (not shown) of a processing system, generate one or more commands based on the received commands, and execute the generated commands by performing one or more graphical operations. At least some of these generated commands require texture operations, including ray tracing operations. To facilitate the execution of texture operations, the GPU 100 includes a scheduler 102, a shader processor 104, a local data store 106, a Texture Addressing (TA) module 108, a Texture Data (TD) module 110, and a cache 112.

[0012] Scheduler 102 is generally configured to schedule or order commands (e.g., commands 103) for execution in various modules of GPU 100, including TA module 108, shader processor 104, and LDS 106. In at least some embodiments, scheduler 102 is configured to receive commands for scheduling from one or more of these same modules, or from another module of GPU 100, such as a command processor (not shown).

[0013] Shader processor 104 includes one or more processing elements collectively configured to perform shading operations based on commands received from scheduler 102. Examples of these shading operations include execution of material shaders, tessellation shaders, hull shaders, vertex shaders, ray tracing shaders, etc. In the course of performing these shading operations, at least in some cases, the shader processor generates data to provide to other modules of GPU 100 and commands to provide to scheduler 102.

[0014] LDS 106 is generally a memory configured to store data shared between operations executing on GPU 100. For example, in some embodiments, LDS 106 stores data shared between thread groups executing on GPU 100.

[0015] Cache 112 is a memory configured to store cache data used for operations in GPU 100, including ray tracing and other texture operations. In the illustrated embodiment, cache 112 stores BVH tree 107 (hereinafter BVH 107) used by GPU 100 to perform ray tracing operations. BVH 107 includes multiple nodes organized as a tree with bounding boxes or other bounding volumes forming leaf nodes of the tree structure, which are then grouped into smaller sets, each enclosed within its own bounding volume representing a parent node on the tree structure, which are then combined into larger sets that are also enclosed within their own bounding volumes representing higher parent nodes on the tree structure, and so on, until there is a single bounding volume representing the top node of BVH 107 and encompassing all lower level bounding volumes.

[0016] The TA module 108 is generally configured to perform addressing tasks associated with texture operations, including ray tracing operations, based on commands received from the scheduler 102. For example, in some embodiments, the TA module 108 receives a ray tracing command indicating specific data to be used for ray tracing, such as ray data and BVH node data. The TA module 108 identifies memory addresses associated with the data and provides the memory addresses to the cache 112 for retrieval of the ray tracing data. The TA module 108 then provides the ray tracing data to the TD module 110.

[0017] The TD module 110 includes one or more circuits collectively configured to perform ray tracing and other texture operations based on data received from the TA module 108. In particular, the TD module 110 is configured to perform intersection operations to identify whether a given ray intersects with a given BVH node, and traversal operations to traverse the BVH 107 based on the intersection operations. To facilitate these operations, the TD 110 includes an intersection engine 114 and a traversal engine (TE) 115.

[0018] Intersection engine 114 is configured to receive ray data, which identifies particular rays to be used for ray tracing, and node data, which indicates nodes of BVH tree 107. Intersection engine 114 performs a node intersection process to identify whether a ray intersects a node (called a intersection hit) or does not intersect a node (called a intersection miss). Intersection engine 114 provides the intersection miss data and intersection hit data to TE 115 along with the ray data and BVH node data.

[0019] The TE 115 is a hardware engine that includes one or more circuits collectively configured to perform tree traversal operations. In particular, the TE 115 is configured to receive intersection information (hit data, miss data, ray data, and BVH node data) from the intersection engine 114. The TE 115 performs a traversal process based on the intersection information. For example, in some embodiments, the TE implements a stack-based depth-first BVH traversal process, where a traversal stack is used to store the address of the next node that the ray intersects. The tree nodes are visited in depth-first order, and for each intersected internal node, the intersected child nodes are sorted based on their distance to the ray origin. The farthest node is pushed onto the stack, and the closest node is used as the next intersection for the next iteration of the traversal loop. In some embodiments, the traversal loop is implemented using a state machine, such that the TE 115 can process a different ray every sequential clock cycle. In other embodiments, the TE implements a stackless traversal process, a while-while traversal process, or the like. In some embodiments, following the traversal process, the TE 115 identifies one of three possible outcomes: 1) the next node in the BVH 107 to be tested for intersection with the ray, 2) a shader to be executed (e.g., any-hit shader), or 3) the end of the tree traversal process for the current ray.

[0020] In response to identifying the next node of the BVH 107 to be tested, the TE 115 provides address information for the next node to the TA 108. An example according to some embodiments is shown in FIG. 2. In the illustrated example, the TA receives a command 103 to begin traversal of the BVH 107. In response, the TA 108 provides ray and node address information to the intersection engine 114, which retrieves corresponding ray and node data from the cache 112. Using the ray and node data, the intersection engine 114 determines intersection information for the ray and node and provides the intersection information to the TE 115. Based on the intersection information and in accordance with the tree traversal process, the TE 115 determines a next node 220 that represents the next node of the BVH 107 to be tested for intersection with the ray.

[0021] The TE 115 provides address information for the next node 220 directly to the TA block 108, and also provides any metadata required for traversal, such as a ray identifier. In response, the TA 108 sends a request for node data for the next node 220 to the cache 112 and sends the next node address and other parameters to the intersection engine 114, which determines intersection information based on the next node 220 and the ray data provided by the cache 112. Thus, in the example of FIG. 2, the TE loops the next node 220 directly to the TA 108, triggering the next iteration of the traversal process, bypassing both the scheduler 102 and the shader processor 104. This reduces the overhead associated with the next iteration of the traversal process and improves the overall efficiency of the traversal process.

[0022] Returning to FIG. 1, possibly for some iterations of the traversal process, the TE 115 identifies a shader to be executed for the current node and current ray of the BVH 107. Examples of shaders to be executed include any hit shader, procedural shader, etc. In response, the TE 115 provides a command to the scheduler 102 that triggers the execution of the identified shader. In some embodiments, the TE 115 provides the shader type to the shader processor 104, which determines the address of the shader function to call. An example according to some embodiments is shown in FIG. 3.

[0023] In the example of FIG. 3, the TA receives a command 103 to begin traversal of the BVH 107. Similar to the example of FIG. 2, in response to the command 103, the TA 108 provides ray and node address information to the intersection engine 114, which retrieves corresponding ray and node data from the cache 112. Using the ray and node data, the intersection engine 114 determines intersection information for the ray and node, and provides the intersection information to the TE 115. Based on the intersection information and in accordance with the tree traversal process, the TE 115 determines a return command 322 representing a command to execute a particular shader. The TE 115 provides the return command 322 to the scheduler 102, which schedules the command for execution in the shader processor 104.

[0024] In some embodiments, in conjunction with issuing the return command 322, the TE 115 saves state information in a local data store indicating the current state of the traversal process. Upon completion of the shader indicated by the return command 322, the shader processor 104 issues a command to the TE 115, via the scheduler 102, to resume the traversal process. In response to the resume command, the TE 115 loads the stored state data and resumes traversal of the BVH 107.

[0025] Returning to Figure 1, at a certain point in the traversal process, the TE 115 determines that traversal of the BVH 107 is complete. In response, the TE 115 returns data such as hit data (which nodes were hit (if any)), distance from the ray origin, BVH node addresses, data flags, bookkeeping data (e.g., memory data), and any BVH information required by the shader processor 104, such as by storing the BVH information in the LDS 106. The shader processor 104 uses this information to initiate further ray tracing operations, such as, for example, initiating a traversal of the BVH 107 based on another ray.

[0026] 4 is a block diagram of the TE 115, according to some embodiments. In the illustrated example, the TE 115 includes a traversal decode module 430 and multiple memory structures including a traversal stack 434, a closest hit memory 436, a traversal state memory 438, and a per ray storage memory 440. The TE 115 also includes a next node matching module 432.

[0027] The traversal decoding module 430 is a set of circuits collectively configured to implement in hardware a traversal process for a BVH (e.g., BVH 107). In some embodiments, the traversal decoding module 430 is configured as a state machine that implements the traversal process, including an initial state and one or more result states (states that cause the traversal decoding module 430 to generate a result that is provided to the TA module 108, the scheduler 102, or other modules). The intersection engine 114 provides intersection results to the traversal decoding module 430, where each intersection result includes intersection data for a particular ray and a particular BVH node. In response to receiving intersection data, the traversal engine 115 sets the traversal state of the corresponding intersection result to the initial state. Based on the intersection data and the nodes of the BVH tree 107, the traversal decoding engine 430 modifies the state of the intersection result until the result reaches one or more specified final states, such as a result state. As the intersection result progresses through the different states of the state machine, the traversal decode engine 430 generates and provides any output information indicated by the state of the intersection result, including generating the next node 220, a return command 322, etc. In some embodiments, the traversal decode module 430 is clocked by a designated clock signal, and the state of the intersection result is set by the traversal decode module 430 on every cycle of the clock signal. Furthermore, in some embodiments, the traversal decode module 430 is configured as a pipeline, and the traversal decode module 430 processes multiple intersection results simultaneously for different rays, different BVH nodes, or both.

[0028] The next node matching module 432 is configured to receive BVH node information from the traversal decoding module 430. Based on the received BVH node information, the next node matching module 432 improves cache utilization when fetching BVH node data for subsequent rays that are intended to intersect for the same BVH node. In some embodiments, the next node matching module 432 groups rays provided by the traversal decoding module 430 based on their next node address. The next node matching module 432 reorders the rays sent for the next traversal iteration (intersection) based on the next node request. For example, for a ray at the end of a traversal decoding block, if the ray needs a node address that the TE 115 just sent to the TA 108, the TE 115 sends the ray id in a loop without enqueuing a memory fetch for the cache 112. This allows the cache 112 to be used by non-traversals during this cycle. If a ray requires a different node address, the TE 115 adds it to a queue (not shown) corresponding to that node address and sends a different ray for the intersection that matches the node address requested in the previous cycle. If that queue is empty, the TE selects another queue to request the intersection.

[0029] The traversal stack 434 includes a traversal stack for each ray being processed by the traversal decoding module 430. In at least some embodiments, the number of entries assigned to a given ray in the traversal stack 434 is a programmable value. Depending on the state of the ray intersection data in the traversal decoding module 430, the traversal decoding module writes elements to or reads elements from the ray's stack. Thus, the traversal stack 434 enables the traversal decoding module 430 to perform a recursive traversal process using an iterative process.

[0030] The nearest hit memory 436 stores a nearest hit value for each ray being processed by the traversal decoding module 430. The nearest hit memory 436 is initialized to a specified maximum distance value, and as the traversal decoding module 430 processes the intersection data for a given ray and finds a new intersection or hit with a node of the BVH tree 107, the traversal decoding module 430 updates the nearest hit memory 436 to reflect the ray's minimum ray hit distance to the node in the BVH 107. In some embodiments, the minimum ray hit distance for a ray is returned to the shader processor 108 in response to the ray completing traversal of the BVH 107.

[0031] The traversal state memory 438 is configured to store temporary data associated with the traversal process. The temporary data is used by the traversal decoding module 430 to determine the current traversal state for each ray and therefore the next state of the ray based on the intersection information provided by the intersection engine 114. Examples of temporary information include the current node of the BVH tree 107 associated with the ray, the previous node of the BVH tree 107 associated with the ray, pointer information for the traversal stack 434, TLAS and BLAS information indicating the level of the BVH tree 107 being used for the traversal, etc.

[0032] Per-ray storage 440 stores ray definition data for rays being processed by the traversal decode engine 430. In some embodiments, per-ray storage 440 stores BLAS definitions for rays, and a separate data store (not shown) in the TD module 110 stores BLAS definition data for use by the intersection engine 114.

[0033] 5 illustrates a method 500 of using a hardware traversal engine to traverse an acceleration structure according to some embodiments. Although method 500 is described with respect to an exemplary embodiment in GPU 100 of FIG. 1, it will be understood that in other embodiments, techniques reflected by method 500 are implemented in other types of processing units or in processing units having different configurations.

[0034] In block 502, the TA 108 receives a trace ray command from the scheduler 102 indicating a ray to traverse the BVH 107. In response, the TA 108 generates address information for the ray and an initial node of the BVH 107. Based on the address information, the cache 112 provides the ray data and the BVH node data to the intersection engine 114. In response, the intersection engine 114 generates intersection data based on the ray data and the node data. Based on the intersection data, the TE 115 identifies a next node 220 in the BVH 107. In block 503, the TE 115 provides the next node 220 to the TA module 108, which generates address information for the next node. Based on the address information, the cache 112 provides data for the next node 220 to the intersection engine 114, which generates intersection data for the next node and the current ray. Thus, the traversal engine 115 bypasses the scheduler 102 and shader processor 104 and loops the next node 220 directly to the TA module 108, thereby improving the speed and efficiency of the BVH traversal process.

[0035] Once the TE 115 has traversed the BVH 107, it returns a command to the scheduler 102 in block 504. In response, the scheduler 102 schedules the command for execution in the shader processor 104. The particular command returned by the TE 115 depends on the current node of the BVH 107 being processed and, if different, is an Any Hit Shader (AHS) command (block 506), a Procedural Shader (PS) command (block 512), a traversal abort command (block 516), and a traversal complete command (block 518). Each of these commands is described below.

[0036] At block 506, the TE 115 returns an AHS command. In response, at block 508, the shader processor 104 executes the AHS indicated by the AHS command. At block 510, the shader processor 104 post-processes the BVH hit data generated by the TE 115. The shader processor 104 then generates a BVH traversal continue command, and in response, method flow returns to block 503 and the TE 115 continues traversing the BVH 107. In some embodiments, the continue command terminates the traversal, such as when the AHS has accepted the hit and determined that the traversal should stop.

[0037] At block 512, the TE 115 returns a PS command. In response, at block 514, the shader processor 104 executes the PS indicated by the PS command. At block 510, the shader processor 104 post-processes the BVH hit data generated by the TE 115. The shader processor 104 then generates a BVH traversal continue command, in response, method flow returns to block 503 and the TE 115 continues traversing the BVH 107. In some embodiments, the continue command terminates the traversal.

[0038] At block 516, the TE 115 returns a traversal abort command to indicate that traversal of the BVH 107 has been aborted. In response, the shader processor 104 generates a BVH traversal continue command, and in response, the method flow returns to block 503 and the TE 115 continues traversing the BVH 107.

[0039] At block 518, the TE 115 returns a traversal complete command indicating that traversal of the BVH 107 for the given ray is complete. The TE 115, via the traversal complete command, indicates either the closest hit node of the BVH 107 (stored in the closest hit memory 436) or an indication that the ray missed a node in the BVH 107. In response, the shader processor 104 determines whether another ray should be traced, and if so, the method flow returns to block 502 where the shader processor 104 issues a new ray trace command for the new ray. If not, the method flow moves to block 522 where the shader processor 104 returns the hit data (i.e., data indicating the node in the BVH 107 that the ray intersected) and other data, such as the hit distance from the ray origin, centroid information, etc., to the thread or process that requested the ray tracing.

[0040] It will be appreciated that method 500 is just one example of using the TE 115 to assist in ray tracing, and that in other embodiments, the TE 115 is used in other ways. For example, in some embodiments, hits in the BVH 107 are processed within the shader itself (i.e., in the shader processor 104) without returning hit data to the callee. In these embodiments, the TE does not return a traversal abort command, but instead traverses all rays associated with a given wavefront until a BVH hit is found or traversal of the BVH 107 is complete.

[0041] As disclosed herein, in some embodiments, a processing unit comprises a scheduler that schedules commands for execution in modules of the processing unit, and a hardware traversal engine configured to traverse a ray tracing structure in response to a first command from the scheduler, the hardware traversal engine bypassing the scheduler in response to identifying a first node of the ray tracing structure. In one aspect, the processing unit includes a shader processor for performing shading operations, the hardware traversal engine bypassing the shader processor in response to identifying a first node of the ray tracing structure. In another aspect, the processing unit comprises a texture addressing module configured to identify address information for the ray tracing structure in response to the first command. In yet another aspect, the hardware traversal engine bypasses the scheduler in response to the first command by providing information associated with the first node to the texture addressing module. In yet another aspect, the hardware traversal engine returns a command to the scheduler in response to identifying a second node of the ray tracing structure.

[0042] In one aspect, the command includes a command to execute a specified shader in a shader processor of the processing unit. In another aspect, the specified shader is an arbitrary hit shader. In yet another aspect, the ray tracing structure includes a bounding volume hierarchy (BVH).

[0043] In some embodiments, the system comprises a scheduler that provides ray tracing commands; a memory that stores ray tracing data of a ray tracing structure; and a hardware traversal engine for traversing the ray tracing structure in response to the ray tracing commands, where traversing the ray tracing structure includes bypassing the scheduler for at least one node of the ray tracing structure. In one aspect, the hardware traversal engine comprises a traversal stack memory for storing node addresses of the ray tracing structure. In another aspect, the hardware traversal engine comprises a nearest hit memory for storing information indicative of a nearest node of the ray tracing structure for a ray associated with the ray tracing command. In yet another aspect, the hardware traversal engine comprises a traversal state memory for storing state information for a ray associated with the ray tracing command. In one aspect, the system comprises a shader processor, and traversing the ray tracing structure includes bypassing the shader processor for at least one node of the ray tracing structure.

[0044] In some embodiments, the method includes scheduling, at a scheduler of the processing unit, commands for execution at a module of the processing unit, and traversing, at a hardware traversal engine of the processing unit, a ray tracing structure in response to a first command from the scheduler, the hardware traversal engine bypassing the scheduler in response to identifying a first node of the ray tracing structure. In one aspect, the method includes bypassing a shader processor of the processing unit in response to the hardware traversal engine identifying the first node of the ray tracing structure. In another aspect, the method includes identifying, at a texture addressing module of the processing unit, address information of the ray tracing structure in response to the first command.

[0045] In one aspect, the hardware traversal engine bypasses the scheduler in response to the first command by providing information associated with the first node to the texture addressing module. In another aspect, the method includes returning a command from the hardware traversal engine to the scheduler in response to identifying a second node of the ray tracing structure. In yet another aspect, the command includes a command to execute a specified shader in a shader processor of the processing unit. In yet another aspect, the ray tracing structure includes a bounding volume hierarchy (BVH).

[0046] In some embodiments, certain aspects of the techniques described above are implemented by one or more processors of a processing system executing software. The software includes one or more sets of executable instructions stored or otherwise tangibly embodied in a non-transitory computer-readable storage medium. The software may include instructions and specific data that, when executed by the one or more processors, operate the one or more processors to perform one or more aspects of the techniques described above. The non-transitory computer-readable storage medium may include, for example, a magnetic or optical disk storage device, a solid-state storage device such as a flash memory, a cache, a random access memory (RAM), or other non-volatile memory device(s), etc. The executable instructions stored in the non-transitory computer-readable storage medium may be implemented as source code, assembly language code, object code, or other form of instructions that can be interpreted or otherwise executed by one or more processors.

[0047] In addition to the above, it should be noted that not all activities or elements described in the summary description are required, some of the specific activities or devices may not be required, one or more additional activities may be performed, and one or more additional elements may be included. Furthermore, the order in which the activities are listed is not necessarily the order in which they are performed. Also, the concepts have been described with reference to specific embodiments. However, those skilled in the art will appreciate that various changes and modifications can be made without departing from the scope of the invention as set forth in the claims. Thus, the specification and drawings should be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the invention.

[0048] Benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, the benefits, advantages, solutions to problems, and features by which any benefit, advantage, or solution may occur or be manifested are not to be construed as critical, essential, or essential features of any or all claims. Moreover, the specific embodiments described above are illustrative only, as the disclosed invention may be modified and practiced in different but similar manners apparent to those skilled in the art having the benefit of the teachings herein. No limitations are intended to the details of construction or design herein shown, other than as set forth in the appended claims. It is therefore apparent that the specific embodiments described above may be altered or modified, and all such variations are considered to be within the scope of the disclosed invention. Accordingly, the protection sought herein is set forth in the appended claims.

Claims

1. A processing unit comprising: a scheduler for scheduling commands for execution in modules of said processing units; a hardware traversal engine configured to traverse a ray tracing structure in response to a first command from the scheduler, the hardware traversal engine bypassing the scheduler in response to identifying a first node of the ray tracing structure. Processing unit.

2. a shader processor for performing shading operations; the hardware traversal engine bypasses the shader processor in response to identifying the first node of the ray tracing structure. The processing unit of claim 1.

3. a texture addressing module configured to identify address information for the ray tracing structure in response to the first command; A processing unit according to claim 1 or 2.

4. the hardware traversal engine bypasses the scheduler in response to the first command by providing information associated with the first node to the texture addressing module; The processing unit of claim 3.

5. the hardware traversal engine returns a command to the scheduler in response to identifying a second node of the ray tracing structure. The processing unit of claim 1.

6. the commands include a command to execute a specified shader in a shader processor of the processing unit; The processing unit of claim 5.

7. The specified shader is any hit shader. The processing unit of claim 6.

8. The ray tracing structure includes a Bounding Volume Hierarchy (BVH); The processing unit of claim 1.

9. 1. A system comprising: a scheduler that serves ray tracing commands; A memory for storing ray tracing data of the ray tracing structure; a hardware traversal engine for traversing the ray tracing structure in response to the ray tracing command, wherein traversing the ray tracing structure includes bypassing the scheduler for at least one node of the ray tracing structure. system.

10. the hardware traversal engine comprises a traversal stack memory for storing node addresses of the ray tracing structure; The system of claim 9.

11. the hardware traversal engine comprising a closest hit memory for storing information indicative of a closest node of the ray tracing structure to a ray associated with the ray tracing command; 11. The system of claim 9 or 10.

12. the hardware traversal engine comprises a traversal state memory for storing state information about rays associated with the ray tracing command. The system of claim 9.

13. A shader processor is provided, traversing the ray tracing structure includes bypassing the shader processor for the at least one node of the ray tracing structure. The system of claim 9.

14. scheduling, in a scheduler of a processing unit, commands for execution in modules of said processing unit; traversing a ray tracing structure in a hardware traversal engine of the processing unit in response to a first command from the scheduler; the hardware traversal engine bypasses the scheduler in response to identifying a first node of the ray tracing structure. method.

15. in response to the hardware traversal engine identifying the first node of the ray tracing structure, bypassing a shader processor of the processing unit.

15. The method of claim 14.

16. identifying, in a texture addressing module of the processing unit, address information for the ray tracing structure in response to the first command; 16. The method of claim 14 or 15.

17. the hardware traversal engine bypasses the scheduler in response to the first command by providing information associated with the first node to the texture addressing module; 17. The method of claim 16.

18. returning a command from the hardware traversal engine to the scheduler in response to identifying a second node of the ray tracing structure.

15. The method of claim 14.

19. the commands include a command to execute a specified shader in a shader processor of the processing unit; 20. The method of claim 18.

20. The ray tracing structure includes a Bounding Volume Hierarchy (BVH); 15. The method of claim 14.

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