Server and its server management system

Abstract

This application discloses a server and its server management system, which belongs to the server field and is used for managing the server. The server management system can support the startup of two CPUs, receive PCIe signals sent from the two CPUs to display an operating system interface, and send the received keyboard and mouse commands to the CPU whose gating switch (3) is currently on via the USB controller (2), thereby realizing the application of a keyboard and mouse. When the USB controller (2) converts between USB signals and PCIe signals, the first USB interface (4) can realize communication with the CPU whose gating switch (3) is currently on. Obviously, this system can be applied to a future solution in which the CPU is partitioned and the USB interface is removed, and has a simple structure and strong stability.

Description

[Technical field]

[0001] TECHNICAL FIELD This application relates to the field of servers, and in particular to server management systems and servers.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to a Chinese patent application filed with the China Patent Office on April 29, 2022, bearing application number 202210466930.0 and entitled "Server and Server Management System Thereof," the entire contents of which are incorporated herein by reference. [Background technology]

[0003] Traditionally, the server management unit is included in the server motherboard, and the advantages of modularizing the server management unit and separating it from the server motherboard are obvious. As server CPU technology is updated repeatedly, server applications are constantly innovating, and in the future, the south bridge of the CPU (Central Processing Unit) and the CPU will be integrated, and low-speed interfaces such as USB (Universal Serial Bus) will be eliminated. With the application of CPU partitioning, the two-way CPU can run the operating system independently. For such new CPU designs, the conventional technology lacks a mature server management system. Summary of the Invention [Problem to be solved by the invention]

[0004] The object of the present application is to provide a server management system, which can be applied to future solutions in which the CPU is partitioned and the USB interface is removed, and has a simple structure and strong stability. Another object of the present application is to provide a server including the server management system, which can be applied to future solutions in which the CPU is partitioned and the USB interface is removed, and has a simple structure and strong stability. [Means for solving the problem]

[0005] In order to solve the above technical problems, the present application provides a server management system, which includes: a board management control device for receiving a PCIe (Peripheral Component Interconnect express, a high-speed serial computer expansion bus standard) signal transmitted from the CPU by the gating switch, and transmitting a keyboard / mouse command received via the first USB interface to the CPU whose gating switch is currently on, thereby supporting the startup of the CPU whose gating switch is currently on; A USB controller connected to the board management control device, the USB controller converting between a USB signal and a PCIe signal so as to realize communication between a CPU whose gating switch is currently on and a first USB interface; A gating switch is connected to two CPUs, a board management control device, and a USB controller of the server, respectively, for turning on one set of PCIe signals in a designated CPU of the two CPUs to the board management control device and turning on the other set of PCIe signals to the USB controller; a first USB interface connected to the board management control device and the USB controller, respectively.

[0006] In some embodiments, the substrate management controller comprises: A BMC (Baseboard Management Controller) connected to an ESPI (Enhanced Serial Peripheral Interface) interface of one of the CPUs receives a PCIe signal sent from the CPU by a gating switch, sends a keyboard / mouse command received via a first USB interface to the CPU whose gating switch is currently on, and receives boot information sent from the one of the CPUs via its own ESPI interface; a control module connected to the BMC, the ESPI interface of the other CPU, and the gating switch, for processing the boot information sent by the other CPU via the ESPI interface using a preset program, and for controlling the state of the gating switch; The system further includes a root of trust security management device connected to the two CPUs and the BMC, the root of trust security management device providing an authenticated boot program to the CPUs and the BMC at the power-on stage of the server.

[0007] In some embodiments, the control module is further connected to a Low Voltage Differential Signaling (LVDS) interface of the motherboard; The control module is further for decoupling an LVDS signal obtained by combining a plurality of specified types of low-speed signals transmitted from the motherboard, and then transmitting the decoupling signal to the BMC, and for combining a plurality of specified types of low-speed signals transmitted from the BMC as an LVDS signal, and then transmitting the decoupling signal to the motherboard.

[0008] In some embodiments, the server management system comprises: A protocol conversion device connected to a UART (Universal Asynchronous Receiver / Transmitter) interface of the BMC for converting between a USB protocol and a UART protocol; a second USB interface connected to the protocol conversion device; The BMC is further for outputting UART signals received from the control module from the UART interface, and for transmitting UART signals transmitted from the protocol converter to the control module.

[0009] In some embodiments, the control module is further connected to an I3C (Improved Inter Integrated Circuit) interface of the CPU; The control module further comprises: This is to turn on the CPU's I3C signal to the BMC so that the BMC can debug the CPU using the I3C signal.

[0010] In some embodiments, the gating switch comprises: a first alternative PCIe switch, the first end of which is connected to the first PCIe signal channels of the two CPUs respectively and the second end of which is connected to the USB controller, the first alternative PCIe switch being for turning on the first PCIe signal of one way of the first alternative PCIe switch to the USB controller under the control of the control module; a second alternative PCIe switch, the first end of which is connected to the second PCIe signal channels of the two CPUs respectively and the second end of which is connected to the BMC, for turning on one of the second PCIe signals to the BMC under the control of the control module; a two-way logic switch having a first end connected to the clock signals of the two CPUs, respectively, and a second end connected to the USB controller and the BMC, for transmitting the clock signals of the two CPUs to the USB controller and the BMC, respectively.

[0011] In some embodiments, the server management system further includes a third USB interface connected to the USB controller; The USB controller is for converting between USB signals and PCIe signals so as to realize communication between the CPU whose gating switch is currently on and the first USB interface and the third USB interface, respectively.

[0012] In some embodiments, the control module is a Field Programmable Gate Array (FPGA).

[0013] In some embodiments, the root of trust security manager comprises: A Cerberus root of trust security management module connected to two CPUs and a BMC, respectively, for providing an authenticated boot program to the CPUs and the BMCs at a power-on stage of the server; A first CPU Flash for storing a boot program of one of the CPUs; A second CPU Flash for storing a boot program of the other CPU; and BMC Flash for storing the BMC boot program.

[0014] In order to solve the above technical problems, the present application further provides a server including the above server management system.

[0015] The present application provides a server management system, in which the server management system can support the startup of two CPUs, receive PCIe signals sent from the two CPUs to display an operating system interface, and send the received keyboard and mouse commands to the CPU whose gating switch is currently on by a USB controller, thereby realizing the application of a keyboard and mouse; and when the USB controller converts between USB signals and PCIe signals, the first USB interface can realize communication with the CPU whose gating switch is currently on. It is apparent that the present application is applicable to a future solution in which the CPU is partitioned and the USB interface is removed, and has a simple structure and strong stability.

[0016] The present application further provides a server having the same beneficial effects as the above server management system. [Brief description of the drawings]

[0017] In order to more clearly describe the technical solutions of the embodiments of the present application, the drawings necessary for use in the prior art and embodiments are briefly described. Of course, the drawings in the following description are some embodiments of the present application, and those skilled in the art can further obtain other drawings based on these drawings without creative labor. [Figure 1] FIG. 2 is a structural diagram of a server management system according to some embodiments of the present application; [Diagram 2] FIG. 1 is a structural schematic diagram of a conventional server management system. [Diagram 3] FIG. 2 is a structural schematic diagram of another server management system according to some embodiments of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] The core of the present application is to provide a server management system, which can be applied to a future solution in which the CPU is partitioned and the USB interface is removed, and has a simple structure and strong stability. Another core of the present application is to provide a server including the server management system, which can be applied to a future solution in which the CPU is partitioned and the USB interface is removed, and has a simple structure and strong stability.

[0019] In order to make the objectives, technical solutions and advantages of some embodiments of the present application clearer, the technical solutions in some embodiments of the present application will be described clearly and completely below with reference to the drawings, and it is obvious that the described embodiments are not all the embodiments, but only some of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work belong to the protection scope of the present invention.

[0020] Referring to FIG. 1, FIG. 1 is a structural diagram of a server management system according to some embodiments of the present application, and the server management system includes: a board management control device 1 for receiving a PCIe signal transmitted from a CPU by a gating switch 3, transmitting a keyboard / mouse command received via a first USB interface 4 to the CPU for which the gating switch 3 is currently on, and supporting the startup of the CPU for which the gating switch 3 is currently on; A USB controller 2 connected to the board management control device 1, the USB controller 2 converting between a USB signal and a PCIe signal so as to realize communication between a CPU whose gating switch 3 is currently on and a first USB interface 4; a gating switch 3 connected to two CPUs of the server, the board management control device 1, and the USB controller 2, respectively, for turning on one set of PCIe signals in a designated CPU of the two CPUs to the board management control device 1, and turning on the other set of PCIe signals to the USB controller 2; and a first USB interface 4 connected to the board management control device 1 and the USB controller 2, respectively.

[0021] Referring to FIG. 2, FIG. 2 is a structural schematic diagram of a conventional server management system. A conventional two-way general-purpose server motherboard includes two CPUs, CPU0 and CPU1, CPU0 boots independently and only needs to run the operating system, while CPU1 is mostly used to extend calculation and PCIe resources, and does not need to run the operating system, and CPU1 is induced by CPU0 to complete the boot process. The BMC chip participates in the CPU0 boot process, the PCIe bus of CPU0 is connected to the PCIe controller of the BMC chip and used for output display of the operating system interface, the ESPI bus of the CPU0 south bridge is connected to the BMC chip to transmit the CPU0 serial interface information, and the CPU0 south bridge USB bus is connected to the BMC chip to realize keyboard mouse application, etc. The UART interface of the BMC is externally connected to a serial interface COM connector to output serial interface information. The BMC is connected to the FPGA through the SGPIO (Serial General Purpose Input / Output) bus, and the FPGA in this module is interconnected with the SGPIO bus of the motherboard to realize the IO (Input / Output) interface expansion function. PFR (Platform Firmware Resilience) is a currently widely used safe boot technology, which is mainly realized by FPGA. In the initial power-on stage, the PFR FPGA checks the storage units such as CPU FLASH and BMC FLASH to determine whether the system is ready to boot. In the traditional method, CPU0, CPU1, and BMC chips all need to be connected to FLASH, so a large number of binary 1-out (2-in 1-out) logic switches are required to perform gating. In the current PFR solution, the introduction of multiple logic switches greatly increases the link branching, bringing about risks to signal integrity, and the PFR inspection logic program is redundant and difficult to develop, and the time of production burst cutting is long, which greatly reduces production efficiency.

[0022] Current CPU products are rapidly updated, and in the future, the CPU south bridge and CPU will be integrated, which will eliminate low-speed interfaces such as USB, and the traditional USB scheme cannot fit the next generation CPU. With the low-energy consumption application of data centers, the demand for reliable operation is constantly increasing, and the concept of CPU partitioning application is proposed, but the traditional server management solution does not support CPU partitioning application. CPU partitioning application can make two-way CPUs run the system independently, and has the following features: 1. Meet the multi-system needs of users. 2. Realize 1+1 backup of operating system. When one system fails, the system can quickly switch to the other system. 3. Improve resource utilization. If the user's single system is not highly configured, the original two-way server will run a single system, and CPU1 will be wasted.

[0023] PFR technology is mainly based on logic, which is redundant and has a high risk of signal integrity in PFR circuits. These characteristics greatly increase the difficulty of development, production and maintenance. Traditional servers can only remotely debug the CPU through a COM (cluster communication port) or BMC.

[0024] Considering the technical problems in the background art as described above, in order to accommodate new CPU designs (the integration of the CPU south bridge and the CPU eliminates low-speed interfaces such as USB, and the CPU partitioning application allows the two-way CPU to operate the operating system independently), the next-generation CPU will no longer have a USB interface, and the two CPUs (CPU0, CPU1) of the server will each have a two-way PCIe bus connected to a new server management system, and the gating switch 3 will collectively control the channels of the two-way CPUs, totaling four PCIe buses, and the gating switch 3 can respectively turn on the two-way PCIe bus of the currently operating CPU to the board management control device 1 and the USB controller, for example: When the CPU0 is operating, the gating switch 3 can turn on and control the two-way PCIe bus of the CPU0 to the board management control device 1 and the USB, where the CPU can transmit PCIe signals via the PCIe bus connected to the board management control device 1, for example, transmitting correlation data of the operating system interface so that the board management control device 1 performs display control of the operating system interface, and the USB controller 2 to which the first USB interface 4 is connected can perform mutual conversion between USB signals and PCIe signals, so that the first USB interface 4 can realize USB communication with the CPU for which the gating switch 3 is currently turned on, via the USB controller 2.

[0025] Here, in order to realize the keyboard mouse function of the server, the signal of the keyboard mouse device can be sent to the board management control device 1 via the first USB interface 4, and the board management control device 1 can process the keyboard mouse command and then send it to the CPU whose gating switch 3 is currently on via the USB controller 2 and the gating switch 3, so as to realize the application of the keyboard mouse.

[0026] In some embodiments, the substrate management control device 1 can also assist in the startup of a CPU whose gating switch 3 is currently on, including providing an authenticated startup program to the CPU during a server startup phase and receiving startup information sent from the CPU.

[0027] Due to the presence of the gating switch 3, the server management system in some embodiments of the present application can also support conventional CPUs, and has high compatibility and versatility.

[0028] In some embodiments of the present application, a server management system is provided, which can support the startup of two CPUs, receive PCIe signals sent from the two CPUs to display an operating system interface, and send the received keyboard and mouse commands to the CPU whose gating switch is currently on via a USB controller, thereby realizing the application of a keyboard and mouse. When the USB controller converts between USB signals and PCIe signals, the first USB interface can realize communication with the CPU whose gating switch is currently on, which can be applied to a future solution in which the CPU is partitioned and the USB interface is removed, and has a simple structure and strong stability.

[0029] To better explain the embodiments of the present application, please refer to FIG. 3. FIG. 3 is a structural schematic diagram of another server management system according to some embodiments of the present application. In addition to the above embodiments, In some embodiments, the substrate management controller 1 includes: a board management controller BMC connected to an ESPI interface of one of the CPUs, the board management controller BMC receiving a PCIe signal transmitted from the CPU via a gating switch 3, transmitting a keyboard / mouse command received via a first USB interface 4 to the CPU whose gating switch 3 is currently on, and receiving boot information transmitted from the one of the CPUs via its own ESPI interface; a control module connected to the BMC, the ESPI interface of the other CPU, and the gating switch 3, for processing the boot information sent by the other CPU via the ESPI interface using a preset program, and for controlling the state of the gating switch 3; The system further includes a root of trust security management device connected to the two CPUs and the BMC, the root of trust security management device providing an authenticated boot program to the CPUs and the BMC at the power-on stage of the server.

[0030] The configuration of the BMC, the control module and the root of trust security management module has the advantages of simple structure, low cost, high stability, etc.

[0031] Of course, in addition to the above configuration, the board management control device 1 may have other configurations.

[0032] Considering the traditional two-way server, CPU0 transmits UART information to BMC through ESPI bus and outputs through BMC COM interface, ESPI bus is high speed and UART bus is low speed, ESPI transmits UART information to greatly reduce the utilization rate of ESPI bus, after the new server management system is improved and supports CPU partitioning application, ESPI mainly executes CPU boot information and improves CPU boot efficiency. Since BMC chip only supports one ESPI interface, in this application, the ESPI of one CPU (CPU0) can be connected to the ESPI interface of BMC to participate in CPU0 boot, and the ESPI of CPU1 can be connected to the control module to participate in the independent boot of CPU1 through the control module.

[0033] The control module can also control the state of the gating switch 3, and can control the state of the gating switch 3 according to instructions sent from the BMC.

[0034] In some embodiments, the control module is further connected to an LVDS interface of the motherboard; The control module is further for decoupling an LVDS (Low-Voltage Differential Signaling) signal obtained by combining a plurality of specified types of low-speed signals transmitted from the motherboard, and then transmitting the LVDS signal to the BMC, and for combining a plurality of specified types of low-speed signals transmitted from the BMC as an LVDS signal, and then transmitting the LVDS signal to the motherboard.

[0035] The introduction of the PCIe bus and ESPI bus of the CPU inevitably puts strain on the interface between the BMC and the motherboard. Some low-speed signals interconnected between the BMC and the motherboard, such as I2C, UART, and GPIO signals, are logically coupled to the LVDS bus for transmission, and can be further decoupled by the control module at the motherboard end. The LVDS bus completes the information interaction between the BMC module and the motherboard, which can increase the signal transmission speed and reduce the number of BMC-motherboard interface signals.

[0036] In some embodiments, the server management system comprises: a protocol conversion device connected to a UART interface of the BMC for converting between a USB protocol and a UART protocol; a second USB interface connected to the protocol conversion device; The BMC is further for outputting UART signals received from the control module from the UART interface, and for transmitting UART signals transmitted from the protocol converter to the control module.

[0037] In the server management system of some embodiments of the present application, the UART signal logically decoupled from the control module is output through the UART interface of the BMC and connected to a second USB interface through a protocol conversion device (UART-USB chip, USB UART BRIDGE in FIG. 3), so as to realize communication with the UART signal on the motherboard through the second USB interface.

[0038] In some embodiments, the control module is further connected to an I3C interface of the CPU; The control module further comprises: This is to turn on the CPU's I3C signal to the BMC so that the BMC can debug the CPU using the I3C signal.

[0039] In order to enable the BMC to debug the CPU through the I3C signal, the control module is further connected to the I3C interface of the CPU, and the control module turns on the I3C signal of the CPU to the BMC so that the BMC can debug the CPU through the I3C signal.

[0040] In addition, the I3C signal of the CPU can also be directly connected to the second USB interface (in this case, the second USB interface can be a TYPEC connector), and the serial interface information can be debugged via the TYPEC interface, and the CPU can also be debugged via I3C, improving test efficiency.

[0041] In some embodiments, the gating switch 3 is a first binary PCIe switch, the first ends of which are respectively connected to the first PCIe signal channels of the two CPUs and the second ends of which are connected to the USB controller 2, for turning on the first PCIe signal of one way of the first binary PCIe switch to the USB controller 2 under the control of the control module; a second alternative PCIe switch, the first end of which is connected to the second PCIe signal channels of the two CPUs respectively and the second end of which is connected to the BMC, for turning on one of the second PCIe signals to the BMC under the control of the control module; a two-way logic switch having a first end connected to the clock signals of the two CPUs, respectively, and a second end connected to the USB controller 2 and the BMC, respectively, for transmitting the clock signals of the two CPUs to the USB controller 2 and the BMC, respectively.

[0042] The gating switch 3 in some embodiments of the present application includes two one-way PCIe switches and one one-way logic switch, and has a simple structure and low cost.

[0043] Of course, the gating switch 3 may have other structures.

[0044] In some embodiments, the server management system further includes a third USB interface connected to the USB controller 2; The USB controller 2 is for converting between USB signals and PCIe signals so as to realize communication between the CPU whose gating switch 3 is currently on and the first USB interface 4 and the third USB interface, respectively.

[0045] In consideration of the connection needs of more USB devices, in addition to the keyboard and mouse, the server can provide multiple USB interfaces, where the first USB interface 4 can be a USB 2.0 protocol interface, and the third USB interface can be a USB 3.0 or higher version protocol interface, so as to improve user experience.

[0046] In some embodiments, the control module is an FPGA.

[0047] FPGAs have the advantages of small volume, high performance, and low cost.

[0048] Of course, in addition to an FPGA, the control module may be of other types.

[0049] In some embodiments, the root of trust security manager comprises: A Cerberus root of trust security management module connected to two CPUs and a BMC, respectively, for providing an authenticated boot program to the CPUs and the BMCs at a power-on stage of the server; A first CPU Flash for storing a boot program of one of the CPUs; A second CPU Flash for storing a boot program of the other CPU; and BMC Flash for storing the BMC boot program.

[0050] Cerberus is a root of trust security management module based on ARM processing, which provides multiple SPI interfaces to the outside and can complete chip testing and recovery of CPU, BMC, etc. while the server is powered on. The Cerberus solution avoids the stuck logic switch in the PFR solution, reducing the difficulty of PCB design, as well as greatly reducing the difficulty of logic development and improving production efficiency.

[0051] Of course, in addition to the above structures, the root of trust security management device may be of other types.

[0052] Some embodiments of the present application further provide a server including the server management system of the above embodiments.

[0053] For a description of the server according to some embodiments of the present application, please refer to the above embodiments of the server management system.

[0054] Each embodiment in this specification is described in a progressive manner, and each embodiment is described with emphasis on the differences from other embodiments, and the same and similar parts between each embodiment may be referred to. In this specification, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is such an actual relationship or order between these entities or operations. And, "comprises", "includes" or other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device that includes a set of elements not only includes those elements, but also includes other elements not expressly listed, or includes elements inherent to this process, method, article, or device. In the absence of further limitations, an element defined by the phrase "including a ..." does not exclude the presence of other identical elements in the process, method, article, or device that includes the element.

[0055] The above description of the disclosed embodiments enables one skilled in the art to realize or use the present application. Various modifications of these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Thus, the present application is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. a board management control device for receiving a high-speed serial computer expansion bus standard PCIe signal transmitted from a central processor CPU by a gating switch, and transmitting a keyboard / mouse command received via a first USB interface to the CPU whose gating switch is currently on, and supporting the startup of the CPU whose gating switch is currently on; a universal serial bus (USB) controller connected to the board management control device, the universal serial bus (USB) controller performing mutual conversion between a USB signal and a PCIe signal so as to realize communication between a CPU in which the gating switch is currently on and a first USB interface; the gating switch being connected to two CPUs of the server, the board management control device, and the USB controller, respectively, for turning on one set of PCIe signals in a designated CPU of the two CPUs to the board management control device, and turning on the other set of PCIe signals to the USB controller; the first USB interface connected to the board management control device and the USB controller, respectively.

2. The substrate management control device includes: a board management controller BMC connected to an extended serial peripheral interface (ESP) interface of one of the CPUs, the board management controller BMC receiving a PCIe signal transmitted from the CPU by a gating switch, transmitting a keyboard / mouse command received via a first USB interface to the CPU whose gating switch is currently on, and receiving startup information transmitted from the one of the CPUs via its own ESPI interface; a control module connected to the BMC, the ESPI interface of the other CPU, and the gating switch, the control module processing startup information sent by the other CPU via the ESPI interface using a preset program, and further controlling a state of the gating switch; 2. The server management system according to claim 1, further comprising: a root of trust security management device connected to the two CPUs and the BMC, the root of trust security management device providing an authenticated boot program to the CPU and the BMC at a power-on stage of the server.

3. The control module is further connected to a low voltage differential signal LVDS interface of a motherboard; 3. The server management system of claim 2, wherein the control module is further configured to decouple an LVDS signal formed by combining a plurality of specified types of low-speed signals transmitted from a motherboard, and then transmit the decoupled LVDS signal to the BMC, and to combine a plurality of specified types of low-speed signals transmitted from the BMC as an LVDS signal, and then transmit the LVDS signal to the motherboard.

4. a protocol conversion device connected to a universal asynchronous receiver-transmitter (UART) interface of the BMC, the protocol conversion device being for converting between a USB protocol and a UART protocol; a second USB interface connected to the protocol conversion device; 4. The server management system according to claim 3, wherein the BMC is further configured to output a UART signal received from the control module from the UART interface and to transmit a UART signal transmitted from the protocol conversion device to the control module.

5. The control module is further connected to an I3C interface of the CPU; The control module further comprises:

5. The server management system according to claim 4, wherein the improved internal integrated circuit I3C signal of the CPU is turned on to the BMC, so that the BMC debugs the CPU through the I3C signal.

6. The gating switch is a first alternative PCIe switch, the first end of which is connected to the first PCIe signal channels of the two CPUs respectively and the second end of which is connected to the USB controller, the first alternative PCIe switch being for turning on a first PCIe signal of one way among the first alternative PCIe switches to the USB controller under the control of the control module; a second alternative PCIe switch, the first end of which is connected to the second PCIe signal channels of the two CPUs respectively and the second end of which is connected to the BMC, the second alternative PCIe switch for turning on one-way second PCIe signals of the second alternative PCIe switch to the BMC under the control of the control module; 3. The server management system according to claim 2, further comprising: a two-way logic switch having a first end connected to the clock signals of two CPUs, respectively, and a second end connected to the USB controller and the BMC, respectively, for transmitting the clock signals of the two CPUs to the USB controller and the BMC, respectively.

7. a third USB interface connected to the USB controller; 3. The server management system according to claim 2, wherein the USB controller is for converting between USB signals and PCIe signals so as to realize communications between a CPU on which the gating switch is currently on and a first USB interface and a third USB interface, respectively.

8. 4. The server management system according to claim 3, wherein the control module is a field programmable gate array FPGA.

9. The trust root safety management device is A Cerberus security management module of a root of trust connected to two CPUs and the BMC, respectively, for providing an authenticated boot program to the CPUs and the BMC during a power-on phase of a server; A first CPU Flash for storing a boot program of one of the CPUs; A second CPU Flash for storing a boot program of the other CPU; 9. The server management system according to claim 2, further comprising a BMC Flash for storing a boot program for the BMC.

10. 2. The server management system according to claim 1, wherein the gating switch is for turning on a two-way PCIe bus of a currently operating CPU to the board management control device and the USB controller, respectively.

11. The server management system of claim 1 , wherein the board management control device provides an authenticated startup program to a CPU in a server startup step.

12. The server management system according to claim 2 , wherein the control module is for controlling a state of a gating switch according to an instruction sent from a BMC.

13. 6. The server management system of claim 5, wherein the control module is further for directly connecting an I3C signal of a CPU to the second USB interface, and the second USB interface is a TYPEC connector.

14. 2. The server management system according to claim 1, wherein the first USB interface is a USB 2.0 protocol interface.

15. 2. The server management system according to claim 1, wherein the third USB interface is USB 3.

0.

16. A server comprising the server management system according to any one of claims 1 to 15.

17. 17. The server according to claim 16, wherein each of the two CPUs of the server is connected to the server management system via a two-way PCIe bus.

18. 17. The server according to claim 16, wherein the channels of the four-way PCIe bus of the two CPUs of the server are collectively controlled by a gating switch in the server management system.

19. 17. The server according to claim 16, wherein a CPU in the server transmits a PCIe signal via a PCIe bus connected to a board management control device in the server management system.

20. 20. The server of claim 19, wherein the PCIe signal includes operating system interface correlation data, and the operating system interface correlation data is used by the board management control device to perform display control of the operating system interface.

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