Peak Current Limit Management for High Frequency Buck Converters

Abstract

A controller for a voltage converter, such as a buck converter (104), includes a switching regulator circuit (112) having high-side and low-side switches (210, 222), a comparator (212, 214, 216, 218) configured to compare a voltage of an output circuit (114) to a reference voltage, and a control circuit (110) coupled to the comparator and configured to receive an output from the comparator, the control circuit configured to generate control signals to alternately switch the high-side switch and the low-side switch such that when the high-side switch is on the low-side switch is off and when the low-side switch is on the high-side switch is off, the control circuit including a latch circuit configured to latch a signal corresponding to at least one of the outputs from the comparator. A method of operating a buck converter in conjunction with a fixed high frequency automotive radar system with robust overcurrent detection is also described.

Description

[Background technology]

[0001] A voltage converter steps up or down an input voltage to generate an output voltage suitable for an electronic device. One type of voltage converter is a switching converter, in which one or more transistors are turned on and off at a target duty cycle to generate the output voltage. A buck converter is an example of a switching voltage converter. The output voltage of a buck converter is typically a lower voltage than the input voltage. An example of a buck converter is described in U.S. Patent Application No. 16 / 945,666, filed July 31, 2020, entitled "Current Limiting Technique for Buck Converters." The entire disclosure of U.S. Patent Application No. 16 / 945,666 is incorporated herein by reference. [Patent Document 1] U.S. Patent Application No. 16 / 945,666 Summary of the Invention

[0002] According to one aspect of the present description, a controller for a voltage converter includes a switching regulator circuit having a high-side switch and a low-side switch coupled between an input and an output, a current comparison circuit having a comparator configured to compare a voltage of the output circuit to a reference voltage, and a switching regulator control circuit coupled to the current comparison circuit and configured to receive an output from the comparator. The switching regulator control circuit is configured to generate control signals for alternately switching the high-side switch and the low-side switch such that the low-side switch is off when the high-side switch is on and the high-side switch is off when the low-side switch is on. The switching regulator control circuit includes a latch circuit configured to latch a signal corresponding to at least one of the outputs from the comparator.

[0003] According to another aspect of the present description, a controller for a step-down converter is configured to convert an input voltage to an output voltage, the output voltage being lower than the input voltage. The controller includes a switching regulator circuit having an input, an output, and a high-side switch and a low-side switch coupled in series with each other between the input and the output, a current comparison circuit having an input coupled to the output of the switching regulator circuit and adapted to be coupled to the input of the output circuit and a comparator configured to compare a voltage of the output circuit with a reference voltage, and a switching regulator control circuit coupled to the current comparison circuit and configured to receive an output from the comparator. The switching regulator control circuit is configured to generate control signals for alternately switching the high-side switch and the low-side switch such that the low-side switch is off when the high-side switch is on and the high-side switch is off when the low-side switch is on, and the switching regulator control circuit includes a latch circuit configured to latch a signal corresponding to at least one of the outputs from the comparator so that a current in the output circuit is reliably detected.

[0004] According to another aspect of the present description, an input voltage is converted to an output voltage, the output voltage being lower than the input voltage, the method of conversion including: providing a high-side switch and a low-side switch; coupling the input voltage to the high-side switch, coupling the low-side switch to ground, and alternatingly coupling the high-side switch and the low-side switch to an inductor; comparing a voltage representative of a current in the inductor to a reference voltage; using a switching regulator control circuit to generate control signals for alternately switching the high-side switch and the low-side switch off and on, such that when the high-side switch is on, the low-side switch is off, and when the low-side switch is on, the high-side switch is off; and applying the output from the comparator to the switching regulator control circuit, using a latch circuit to latch a signal corresponding to at least one of the outputs from the comparator, such that an overcurrent condition in the inductor is reliably detected, even when switching is performed at high frequencies. [Brief description of the drawings]

[0005] [Figure 1] FIG. 1 is a block diagram of an example of a system including a power supply, a voltage converter, and a load.

[0006] [Diagram 2] FIG. 2 is a circuit diagram of the voltage converter of FIG. 1.

[0007] [Diagram 3] FIG. 2 is a circuit diagram of a control circuit for the voltage converter of FIG. 1.

[0008] [Figure 4] 4 is a flow chart of a method of operating the control circuit of FIG. 3.

[0009] [Diagram 5] 2 is a timing diagram for a method of operating the voltage converter of FIG. 1.

[0010] [Figure 6] 2 is another timing diagram of a method of operating the voltage converter of FIG. 1. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] As mentioned above, a switching voltage converter includes one or more transistors operated as switches to regulate the converter's output voltage. For example, a step-down converter includes two switching transistors, a high-side transistor coupled to a low-side transistor at a switching node. The transistors consume very little power when fully on or fully off. However, the transistors consume power while being turned on or off, referred to as "switching losses." The transistors may also be susceptible to high ringing voltages or voltage spikes due to an output circuit coupled between the transistors and a load. The output circuit may include, for example, an inductor that begins to store energy in response to a first transistor (e.g., a high-side transistor) having an on state and a second transistor (e.g., a low-side transistor) having an off state. In response to the transistors switching states, the energy stored in the inductor may begin to dissipate to maintain the current to the load, and thus a voltage spike may occur at the switching node where the transistors and the output circuit are coupled. The voltage spikes may cause transistor or other component failures or may cause corresponding spikes in current to the load and may damage or interfere with the operation of the load.

[0012] In one example, the voltage converter includes a current comparison circuit to help manage voltage spikes by responding to measurements only when the measurement information is likely to be reliable, such as when no spike noise is occurring. The current comparison circuit may include a comparator to compare a voltage associated with the current of the output circuit to a reference voltage associated with a current limit level. The voltage associated with the current of the output circuit may be measured at a switching node, which may be referred to as a sense voltage. As the current of the output circuit increases, the sense voltage decreases. To determine whether the current of the output circuit is above the current limit level, the current comparison circuit may determine whether the sense voltage is lower than the reference voltage. The current limit level may be set to a value slightly higher than the current required to supply a load adapted to be coupled to the voltage converter.

[0013] The current comparison circuit may also include a second comparator for comparing the sense voltage to a second reference voltage associated with a second current limit level. When the current in the output circuit decreases, the sense voltage increases. To determine whether the current in the output circuit is below the current limit level, the current comparison circuit may determine whether the sense voltage is greater than the second reference voltage. The second current limit level may be set to a value slightly lower than the current selected according to any suitable criteria for a particular system or device.

[0014] The voltage converter described as an example herein limits the current of the output circuit so that the current of the output circuit remains between an upper current limit level and a lower current limit level. The current limit levels may include, for example, a first set of current limit levels and a second set of current limit levels. The first set of current limit levels may define an upper current limit range in which the current of the output circuit operates, and the second set of current limit levels may define a lower current limit range in which the current of the output circuit operates. Each current limit range includes an upper current limit level and a lower current limit level. For example, the upper current limit range may include an upper current limit level of 5 amperes (A) and a lower current limit level of 4A, and the lower current limit range may include a lower current limit level of -2A and an upper current limit level of -1A. However, these are examples. The description is not limited to the numerical values ​​stated for illustrative purposes.

[0015] FIG. 1 is a block diagram of an example of a system 100 having a voltage converter 104. The voltage converter 104 may be, for example, a fixed high frequency step-down converter for powering an automotive radar device. In one example, the switching frequency of the voltage converter is greater than 15 MHz or greater than 20 MHz. In a particular example, the switching frequency is 21.12 MHz. However, again, the description is not limited to the numerical values ​​set forth herein. The scope of the claimed subject matter is defined according to the appended claims. The system 100 may represent any system or device that includes a voltage converter, particularly any system or device that includes a high frequency step-down converter (e.g., a buck converter). Thus, the system 100 may benefit from limiting the output current so that the output current is within an acceptable range for compliance with applicable safety and other standards.

[0016] The system 100 illustrated in FIG. 1 includes a power source 102, a voltage converter 104, and a load 116. In the illustrated configuration, the power source 102 is coupled to the voltage converter 104. The power source 102 may be any device capable of providing a DC voltage to the voltage converter 104. For example, the power source 102 may be a power storage component (e.g., a battery) or an AC-DC converter. As an AC-DC converter, the power source may include a rectifier circuit (e.g., an alternator) configured to convert an AC voltage to a DC voltage. The voltage converter 104 receives an input voltage VIN from the power source 102 and provides a regulated output voltage VOUT to the load 116. In the example of FIG. 1, the voltage converter 104 includes a current comparator circuit 108, a switching regulator control circuit 110, a switching regulator circuit 112, and an output circuit 114. The current comparator circuit 108, the switching regulator control circuit 110, and the switching regulator circuit 112 are elements of a controller for the voltage converter 104. The load 116 may be any suitable component, circuit, or device adapted to receive and be powered by the output voltage V from the voltage converter 104. For example, the load 116 may be, or a component of, an automotive radar system.

[0017] In operation, the power supply 102 outputs an input voltage VIN to the voltage converter 104 for processing by the voltage converter 104. The voltage converter 104 processes the input voltage VIN and outputs an output voltage VOUT to the load 116. The current comparison circuit 108 enables the voltage converter 104 to switch on a transistor in response to an indication that the current in the output circuit 114 exceeds a current limit level. The switching regulator control circuit 110 drives the switching regulator circuit 112 in response to one or more signals from the current comparison circuit 108. In response to the output signal of the switching regulator control circuit 110, the switching regulator circuit 112 switches the state of the transistor in an alternating manner. The output circuit 114 regulates and filters the voltage of the switching regulator circuit 112 to generate an output voltage VOUT having a current within the current limit level. The load 116 operates, at least in part, according to the output voltage VOUT. In an example where the voltage converter 104 is a step-down converter, such as a buck converter, the output voltage VOUT is lower than the input voltage VIN.

[0018] 2 is an example circuit diagram of the voltage converter 104. As described above with respect to FIG 1, the voltage converter 104 includes a current comparison circuit 108, a switching regulator control circuit 110, a switching regulator circuit 112, and an output circuit 114. The voltage converter 104 may also include a loop comparator 200.

[0019] In operation, the current comparison circuit 108 receives a number of reference voltages and is coupled to the switching regulator control circuit 110, the switching regulator circuit 112, and the output circuit 114. Each reference voltage is associated with a respective current limit level. The different current limit levels are application specific and may be determined using any suitable criteria. For example, the first and second current limit levels may determine an upper current limit range for the output current of the voltage converter 104, and the third and fourth current limit levels may determine a lower current limit range for the output current of the voltage converter 104. The reference voltages may be provided by any suitable component, circuit, or device configured to provide such voltages.

[0020] The illustrated current comparison circuit 108 includes a first comparator 212, a second comparator 214, a third comparator 216, and a fourth comparator 218. A non-inverting terminal of the first comparator 212 receives a reference voltage 5A_ref_voltage. The reference voltage 5A_ref_voltage may be associated with a current limit level of 5A, for example. An inverting terminal of the first comparator 212 is coupled to a switching node 220, a source of a high-side (HS) transistor (an example of an HS switch) 210, a drain of a low-side (LS) transistor (an example of an LS switch) 222, and a first end of an inductor 224. An output terminal of the first comparator 212 is applied to an input of a first AND gate 213. A high-side gate signal HS_gate is applied to another terminal of the first AND gate 213. An output terminal of the first AND gate 213 is coupled to an input HS_pos_comp of the switching regulator control circuit 110. In the illustrated example, when the current sensed at switching node 220 is greater than 5 A and the high side gate signal HS_gate is high, the input HS_pos_comp of switching regulator control circuit 110 is high. Otherwise, the input HS_pos_comp is low.

[0021] A non-inverting terminal of the second comparator 214 receives a second reference voltage 4A_ref_voltage. The second reference voltage 4A_ref_voltage may be associated with a current limit level of, for example, 4A. An inverting terminal of the second comparator 214 is coupled to a switching node 220. An output terminal of the second comparator 214 is applied to an input of a second AND gate 215. A low-side gate signal LS_gate is applied to another input terminal of the second AND gate 215. An output terminal of the second AND gate 215 is coupled to a second input LS_pos_comp of the switching regulator control circuit 110. In the illustrated example, when the current sensed at the switching node 220 is greater than 4A and the low-side gate signal LS_gate is high, the second input LS_pos_comp of the switching regulator control circuit 110 is high. Otherwise, the second input LS_pos_comp is low.

[0022] An inverting terminal of the third comparator 216 receives a third reference voltage -1A_ref_voltage. The third reference voltage -1A_ref_voltage may be associated with a current limit level of -1A, for example. A non-inverting terminal of the third comparator 216 is coupled to a switching node 220. An output terminal of the third comparator 216 is applied to an input of a third AND gate 217. A high-side gating signal HS_gate is applied to another input terminal of the third AND gate 217. An output terminal of the third AND gate 217 is coupled to a third input HS_neg_comp of the switching regulator control circuit 110. In the illustrated example, when the current sensed at the switching node 220 is lower than -1A and the high-side gating signal HS_gate is high, the third input HS_neg_comp of the switching regulator control circuit 110 is high. Otherwise, the third input HS_neg_comp is low.

[0023] An inverting terminal of the fourth comparator 218 receives a fourth reference voltage −2A_ref_voltage. The fourth reference voltage −2A_ref_voltage may be associated with a current limit level of −2A, for example. A non-inverting terminal of the fourth comparator 218 is coupled to a switching node 220, and an output terminal of the fourth comparator 218 is applied to an input of a fourth AND gate 219. A low-side gating signal LS_gate is applied to another input terminal of the fourth AND gate 213. An output terminal of the fourth AND gate 213 is coupled to a fourth input LS_neg_comp of the switching regulator control circuit 110. In the illustrated example, when the current sensed at the switching node 220 is lower than −2A and the low-side gating signal LS_gate is high, the fourth input LS_neg_comp of the switching regulator control circuit 110 is high. Otherwise, the fourth input LS_neg_comp is low.

[0024] The switching regulator control circuit 110 is coupled to the current comparison circuit 108 and to the switching regulator circuit 112. The switching regulator control circuit 110 also includes a loop input Loop_comp that is coupled to the output of the loop comparator 200. The switching regulator control circuit 110 therefore includes a number of inputs and an output 227 that is coupled to a driver circuit 226 of the switching regulator circuit 112. A PWM signal Buck_PWM is provided at the output 227 of the switching regulator control circuit 110 and applied to the driver circuit 226.

[0025] The switching regulator circuit 112 receives an input voltage VIN and is coupled to the switching regulator control circuit 110, the output circuit 114, and the current comparison circuit 108. In the illustrated configuration, the switching regulator circuit 112 includes a driver circuit 226, a high-side (HS) transistor 210, and a low-side (LS) transistor 222. In the illustrated example, the transistors 210, 222 are field effect transistors (FETs), preferably high voltage n-channel FETs (NFETs). The driver circuit 226 is coupled to an output 227 of the switching regulator control circuit 110 and to a gate terminal of the HS transistor 210 and a gate terminal of the LS transistor 222. The driver circuit 226 applies gate signals HS_gate, LS_gate to the gate terminals of the HS and LS transistors 210, 222. The drive circuit 226 may be any suitable circuit configured to alternately switch the transistors 210, 222 such that when the HS transistor 210 is on, the LS transistor is off, and when the HS transistor 210 is off, the LS transistor 222 is on.

[0026] A drain terminal of the HS transistor 210 receives the input voltage VIN. A source terminal of the HS transistor 210 is coupled to a drain terminal of the LS transistor 222, a switching node 220, a first end of an inductor 224, inverting terminals of the first and second comparators 212, 214, and non-inverting terminals of the third and fourth comparators 216, 218. A source terminal of the LS transistor 222 is coupled to the ground terminal.

[0027] The output circuit 114 is adapted to be coupled to the load 116 (FIG. 1) and is coupled to the current comparator circuit 108 (FIG. 2) and the switching regulator circuit 112. In the illustrated configuration, the output circuit 114 includes a switching node 220, an inductor 224, an output node 211, and a capacitor 228. A first end of the inductor 224 is coupled to the switching node 220, the inverting terminals of the first and second comparators 212, 214, the non-inverting terminals of the third and fourth comparators 216, 218, the source terminal of the HS transistor 210, and the drain terminal of the LS transistor 222. A second end of the inductor 224 is adapted to be coupled to the load 116 (FIG. 1) and is coupled to a first end of the capacitor 228, the output node 211, and the appropriate compensator 201. A second terminal of the capacitor 228 is coupled to a ground terminal. An output voltage VOUT is provided at the output node 211.

[0028] The loop comparator 200 is coupled to the switching regulator control circuit 110 and the compensator 201. In operation, a reference voltage V_ref is applied to a non-inverting terminal of the loop comparator 200. The reference voltage V_ref may be provided by the compensator 201. In the illustrated configuration, the compensator 201 is an element of a controller for the voltage converter 104. The reference voltage V_ref may be referred to as a feedback voltage threshold. In the illustrated configuration, the inverting terminal of the loop comparator 200 is coupled to a feedback voltage V_fb from the compensator 201. The feedback voltage V_fb corresponds to a voltage at an output node 211, and the output terminal of the comparator 200 is coupled to a corresponding input Loop_comp of the switching regulator control circuit 110. The loop input Loop_comp is high when the feedback voltage V_fb, which represents the output voltage VOUT, is lower than the reference voltage V_ref. Otherwise, the loop input Loop_comp is low.

[0029] The operation of the current comparison circuit 108 will now be described in more detail with respect to a specific example. The first reference voltage 5A_ref_voltage may be associated with a target inductor current of, for example, 5A. The inductor current is the current of the inductor 224 and may be referred to as the current of the output circuit 114. In the illustrated configuration, the first reference voltage 5A_ref_voltage is associated with a current limit level corresponding to a current slightly greater than the current level required to operate the system or device. For example, the reference voltage 5A_ref_voltage may be associated with a current limit level that is 0.5A greater than the current required to operate the system or device. In the illustrated configuration, the desired maximum inductor current is 4.5A, which is midway between the two current limit levels (4A and 5A) of the upper current limit range. However, the description is not limited to the specific numerical values ​​described herein for illustrative purposes. In some examples, the reference voltage 5A_ref_voltage is application specific and may be selected according to appropriate criteria for a particular system or device.

[0030] The first comparator 212 compares the reference voltage 5A_ref_voltage to the sense voltage provided at the switching node 220. As described above, the sense voltage is related to the current of the output circuit 114. Because the current of the output circuit 114 is measured at the switching node 220 (transistors 210, 222 are coupled to the output circuit 114), the current of the output circuit 114 can be referred to as the input current of the output circuit 114. Based on the comparison, the first comparator 212 generates an output signal indicating whether the reference voltage 5A_ref_voltage is greater or less than the sense voltage. When the high side gate signal HS_gate is high, the output signal of the first comparator 212 is provided to a first input HS_pos_comp of the switching regulator control circuit 110.

[0031] The second reference voltage 4A_ref_voltage may be associated with a target inductor current of, for example, 4 A. In some examples, the second reference voltage 4A_ref_voltage is associated with a current limit level that is just slightly lower than the current required to ensure that reliable current sense information is available to prevent the sense voltage from falling below the first reference voltage 5A_ref_voltage in response to the HS transistor 210 switching on. For example, the second reference voltage 4A_ref_voltage may be associated with a current limit level that is 0.2 A lower than the current required to ensure that reliable current sense information is available to prevent the sense voltage from falling below the first reference voltage 5A_ref_voltage in response to the HS transistor 210 switching on.

[0032] In some examples, the second reference voltage 4A_ref_voltage is application specific and selected according to appropriate criteria for a particular system or device. In some examples, the first reference voltage 5A_ref_voltage and the second reference voltage 4A_ref_voltage correspond to an upper current limit level and a lower current limit level, respectively, of an upper current limit range in which the inductor current operates. The second comparator 214 compares the second reference voltage 4A_ref_voltage with the sense voltage. Based on the comparison, the second comparator 214 generates an output signal indicating whether the second reference voltage 4A_ref_voltage is greater than or less than the sense voltage. When the low-side gate signal LS_gate is high, the output signal of the second comparator 214 is provided to a second input LS_pos_comp of the switching regulator control circuit 110.

[0033] In the illustrated configuration, the third reference voltage -1A_ref_voltage provided to the inverting terminal of the third comparator 216 is associated with a target inductor current of, for example, -1A. In some examples, the third reference voltage -1A_ref_voltage is associated with a current limit level that is slightly higher than the current required to ensure that reliable current sense information is available to prevent the sense voltage from having a value greater than the fourth reference voltage -2A_ref_voltage in response to the LS transistor 222 switching on. For example, the third reference voltage -1A_ref_voltage is associated with a current limit level that is 0.2A higher than the current required to ensure that reliable current sense information is available to prevent the sense voltage from exceeding the fourth reference voltage -2A_ref_voltage in response to the LS transistor 222 switching on. In some examples, the third reference voltage -1A_ref_voltage is application specific and selected according to appropriate criteria for a particular system or device. The third comparator 216 compares a third reference voltage, −1A_ref_voltage, to the sense voltage. Based on the comparison, the third comparator 216 generates an output signal indicating whether the reference voltage, −1A_ref_voltage, is greater than or less than the sense voltage. When the high side gate signal, HS_gate, is high, the output signal of the third comparator 216 is provided to a third input, HS_neg_comp, of the switching regulator control circuit 110.

[0034] The fourth reference voltage -2A_ref_voltage may be associated with a current limit level of -2A, for example. In some examples, the fourth reference voltage -2A_ref_voltage is associated with a current limit level that is slightly lower than the minimum current required for the system or device to operate. For example, the fourth reference voltage -2A_ref_voltage may be associated with a current limit level that is 0.5A lower than the current required to operate the system or device. The reference voltage -2A_ref_voltage may be selected according to appropriate criteria for a particular system or device. The third reference voltage -1A_ref_voltage and the fourth reference voltage -2A_ref_voltage may be, for example, upper and lower current limit limit levels of a lower current limit range within which the inductor current operates. The fourth comparator 218 compares the fourth reference voltage -2_ref_voltage with the sensed voltage. Based on the comparison, the fourth comparator 218 generates an output signal indicative of whether the fourth reference voltage -2A_ref_voltage is greater than or less than the sensed voltage. When the low side gate signal LS_gate is high, the output signal generated by the fourth comparator 218 is provided to a fourth input LS_neg_comp of the switching regulator control circuit 110 .

[0035] The specific operation of switching regulator circuit 112 and output circuit 114 will now be described. Drive circuit 226 receives as an input a PWM signal Buck_PWM from switching regulator control circuit 110. In response to PWM signal Buck_PWM indicating that high-side (HS) transistor 210 should be enabled, drive circuit 226 drives the gate terminal of HS transistor 210 high and the gate terminal of low-side (LS) transistor 222 low. In response to the gate terminal of HS transistor 210 being high, HS transistor 210 allows current to propagate from the drain terminal of HS transistor 210 to the source terminal of HS transistor 210, or a negative inductor current is allowed to propagate from the source terminal of HS transistor 210 to the drain terminal of HS transistor 210, and HS transistor 210 is described as being on.

[0036] In response to the gate terminal of the LS transistor 222 being low, the LS transistor 222 prevents current from propagating from the drain terminal of the LS transistor 222 to the source terminal of the LS transistor 222, and the LS transistor 222 is described as off. In operation, in response to the HS transistor 210 being on and the LS transistor 222 being off, current propagates through the HS transistor 210 to the switching node 220 through the inductor 224. As the current propagates through the inductor 224 to the capacitor 228, energy is stored in the inductor 224, the capacitor 228 stores a charge, and an output voltage VOUT is provided at the output node 211. An input current of the output circuit 114 is provided at the switching node 220, and a corresponding sense voltage may be measured at the switching node 220.

[0037] In response to the PWM signal Buck_PWM indicating that the HS transistor 210 should be disabled, the drive circuit 226 drives the gate terminal of the HS transistor 210 low and the gate terminal of the LS transistor 222 high. In response to the gate terminal of the HS transistor 210 being low, no current propagates through the HS transistor 210. In response to the gate terminal of the LS transistor 222 being high, current is allowed to propagate through the LS transistor 222. Thus, in response to the LS transistor 222 switching on, the stored energy in the inductor 224 begins to dissipate and the inductor current decreases. The decreasing inductor current is provided at the switching node 220, and a corresponding sense voltage may be measured at the switching node 220.

[0038] The operation of the loop comparator 200 will now be described. The loop comparator 200 compares the reference voltage V_ref with the feedback voltage V_fb. (The reference voltage V_ref and the feedback voltage V_fb are generated by the compensator 201.) Based on the comparison, the comparator 200 generates an output signal indicative of whether the feedback voltage V_fb is greater than or less than the reference voltage V_ref. The output signal of the comparator 200 is provided to a corresponding input Loop_comp of the switching regulator control circuit 110. Therefore, the loop input Loop_comp triggers when the feedback voltage V_fb falls below the reference voltage V_ref, and defines the inductor current peak value.

[0039] 3, the switching regulator control circuit 110 may include a first OR gate 302, a second OR gate 304, a third OR gate 306, a first AND gate 308, and a second AND gate 310 (examples of suitable logic gates). A first input HS_pos_comp and a second input LS_pos_comp (from the current comparison circuit 108) are applied to inputs of the first OR gate 302. Blanking signals HS_blank and LS_blank are applied to inputs of the second OR gate 304. A third input HS_neg_comp and a fourth input LS_neg_comp (from the current comparison circuit 108) are applied to inputs of the third OR gate 306.

[0040] Therefore, if the current sensed at the switching node 220 (FIG. 2) is greater than either of the currents associated with the first reference voltage 5A_ref_voltage and the second reference voltage 4A_ref_voltage, the output of the first OR gate 302 (FIG. 3) is high during the corresponding high side or low side operation. Otherwise, the output of the first OR gate 302 is low. When either or both of the blanking signals HS_blank, LS_blank are high, the output of the second OR gate 304 is high. Otherwise, the output of the second OR gate 304 is low. If the current sensed at the switching node 220 (FIG. 2) is less than either of the currents associated with the third reference voltage -1A_ref_voltage and the fourth reference voltage -2A_ref_voltage, the output of the third OR gate 306 is high during the corresponding high side or low side operation. Otherwise, the output of the third OR gate 306 is low.

[0041] The output of the first OR gate 302 is applied to a first input of a first AND gate 308, and the output OCP_blank of the second OR gate 304 is applied to an inverting input of the first AND gate 308. The output of the third OR gate 306 is applied to a first input of a second AND gate 310, and the output OCP_blank of the second OR gate 304 is applied to an inverting input of the second AND gate 310. As a result, when the output OCP_blank of the second OR gate 304 is high (because at least one of the blanking signals HS_blank, LS_blank is high), the outputs Pos_ocp_blanked of the first AND gate 308 and Neg_ocp_blanked of the second AND gate 310 are both low.

[0042] (1) the current sensed at the switching node 220 (FIG. 2) is greater than at least one of the currents associated with the first reference voltage 5A_ref_voltage and the second reference voltage 4A_ref_voltage during the corresponding high side or low side operation, and (2) when neither of the blanking signals HS_blank, LS_blank is high, the output of the first OR gate 302 is high and the output OCP_blank of the second OR gate 304 is low, thereby causing the output Pos_ocp_blanked of the first AND gate 308 to be high. Similarly, when (1) the current sensed at the switching node 220 (FIG. 2) is lower than at least one of the currents associated with the third reference voltages −1A_ref_voltage and the fourth reference voltages −2A_ref_voltage during corresponding high side or low side operation, and (2) neither blanking signal HS_blank, LS_blank is high, the output of the third OR gate 306 is high and the output OCP_blank of the second OR gate 304 is low, thereby causing the output Neg_ocp_blanked of the second AND gate 310 to be high. The outputs Pos_ocp_blanked and Neg_ocp_blanked of the AND gates 308 and 310 are applied to a switch control logic circuit 312 (described in more detail below).

[0043] The switching regulator control circuit 110 also includes a first circuit 314 and a second circuit 316 for enabling the control logic to monitor the comparators after changing the PWM signal Buck_PWM as long as the corresponding transistors 210, 222 are conducting to provide sufficiently long HS and LS periods to reliably sense the inductor current. The first such circuit 314 (an example of a latch circuit) includes a first AND gate 318, a second AND gate 320, and a third AND gate 322, a NOR gate 324, a set-reset latch 326, and an OR gate 328 (an example of a digital logic element). The second input LS_pos_comp is applied to a first input of the first AND gate 318, and the second blanking signal LS_blank is applied to an inverting input of the first AND gate 318. The output LS_pos_ocp_blanked of the first AND gate 318 is high when (1) the current sensed at the switching node 220 is greater than the current associated with the second reference voltage 4A_ref_voltage, (2) the low side gate signal LS_gate (applied to the second comparator associated AND gate 215) is high, and (3) the second blanking signal LS_blank is low. Otherwise, the output LS_pos_ocp_blanked of the first AND gate 318 is low.

[0044] The output LS_pos_ocp_blanked of the first AND gate 318 is applied to a first input of a NOR gate 324, and the PWM signal Buck_PWM is applied to another input of the NOR gate 324. In operation, when the output LS_pos_ocp_blanked of the first AND gate 318 is low and the PWM signal Buck_PWM is also low, the output of the NOR gate 324 is high. Otherwise, the output of the NOR gate 324 is low.

[0045] The output of the first AND gate 318, LS_pos_ocp_blanked, is also applied to a set terminal S of a latch 326. The output of the NOR gate 324 is applied to a reset terminal R of the latch 326. The latch 326 generates an output, Pos_ocp_ls_late_latch, that is applied to a first input of a third AND gate 322. A low side minimum time signal, LS_min_on (described further below), is applied to a second input of the third AND gate 322.

[0046] The first input HS_pos_comp is applied to a first input of a second AND gate 320, and the first blanking signal HS_blank is applied to an inverting input of the second AND gate 320. When the first input HS_pos_comp is high and the first blanking signal HS_blank is low, the output HS_pos_ocp_blanked of the second AND gate 320 is high. Otherwise, the output HP_pos_ocp_blanked of the second AND gate 320 is low. The outputs of the third AND gate 322 and the second AND gate 320 and a signal from an additional AND gate 329 are applied to the inputs of an OR gate 328. When the output Pos_ocp_blanked from the first AND gate 308 is high and the PWM signal Buck_PWM is high, the output of the additional AND gate 329 is high. When the output of the third AND gate 322 is high, the output HS_pos_ocp_blank of the second AND gate 320 is high, and / or the output of the additional AND gate 329 is high, the output POS_ocp_set of the OR gate 328 is high.

[0047] The second enabling circuit 316 (another example of a latch circuit) includes first, second, and third AND gates 330, 332, 334, a fourth AND gate 336, a latch 338, and an OR gate 340 (an example of a digital logic circuit). The third input HS_neg_comp is applied to a first input of the second AND gate 332, and the first blanking signal HS_blank is applied to an inverting input of the second AND gate 332. The output HS_neg_ocp_blanked of the second AND gate 332 is high when (1) the current sensed at the switching node 220 is lower than the current associated with the third reference voltage −1A_ref_voltage, (2) the HS gate signal HS_gate (applied to the third comparator associated AND gate 217) is high, and (3) the first blanking signal HS_blank is low. Otherwise, the output of the second AND gate 332, HS_neg_ocp_blanked, is low.

[0048] The output HS_neg_ocp_blanked of the second AND gate 332 is applied to an inverting input of a fourth AND gate 336, and the PWM signal Buck_PWM is applied to a non-inverting input of the AND gate 336. When the output HS_neg_ocp_blanked of the second AND gate 332 is low and the PWM signal Buck_PWM is high, the output of the fourth AND gate 336 is high. Otherwise, the output of the fourth AND gate 336 is low.

[0049] The output of the second AND gate 332, HS_neg_ocp_blanked, is applied to a set terminal S of a latch 338. The output of the fourth AND gate 336 is applied to a reset terminal R of the latch 338. The latch 338 produces an output, Neg_ocp_hs_late_latch, that is applied to a first input of a third AND gate 334. A high side minimum time signal, HS_min_on (described in more detail below), is applied to a second input of the third AND gate 334.

[0050] At the same time, the fourth input LS_neg_comp is applied to the first input of the first AND gate 330, and the second blanking signal LS_blank is applied to the inverting input of the first AND gate 330. When the fourth input LS_neg_comp is high and the second blanking signal LS_blank is low, the output LS_neg_ocp_blanked of the first AND gate 330 is high. Otherwise, the output LS_neg_ocp_blanked of the first AND gate 330 is low. The output of the third AND gate 334, the output LS_neg_ocp_blanked of the first AND gate 330, and the signal from the additional AND gate 335 are applied to the inputs of the OR gate 340. When the output Neg_ocp_blanked of the second AND gate 310 is high and the PWM signal Buck_PWM is low, the output of the additional AND gate 335 is high. When the output of the third AND gate 334 is high, the output LS_neg_ocp_blanked of the first AND gate 330 is high, and / or the output of the additional AND gate 335 is high, the output Neg_ocp_set of the OR gate 340 is high. Otherwise, the output Neg_ocp_set of the OR gate 340 is low.

[0051] Late latching (326) is applied in the first enable circuit 314 to signals associated with the second input LS_pos_comp, but not to signals associated with the first input HS_pos_comp. The current level limit associated with the first input HS_pos_comp is greater than the current level limit associated with the second input LS_pos_comp. Similarly, late latching (338) is applied in the second enable circuit 316 to signals associated with the third input HS_neg_comp, but not to signals associated with the fourth input LS_neg_comp. The current level limit associated with the fourth input LS_neg_comp is less than the current level limit associated with the third input HS_neg_comp.

[0052] The outputs Pos_ocp_set, Neg_ocp_set of the OR gates 328, 340 of the first and second enable circuits 314, 316 are applied to set terminals S of respective additional latches 360, 362. The HS trigger signal HS_trigger and the LS trigger signal LS_trigger (described in more detail below) are applied to respective reset terminals R of the additional latches 360, 362. The latched outputs Pos_ocp_latched, Neg_ocp_latched of the additional latches 360, 362 are applied to the switch control logic circuit 312, as well as the clock timing signal Clk_sw and the input Loop_comp from the loop comparator 200 (FIG. 2).

[0053] The latched outputs Pos_ocp_latched and Neg_ocp_latched of the first and second additional latches 360, 362 are reset by the HS trigger signal HS_trigger and the LS trigger signal LS_trigger, respectively. When the HS trigger signal HS_trigger is high (thus, when the buck converter 104 switches to the on state of the high-side switch 210), the latched output Pos_ocp_latched of the first additional latch 360 is low. When the LS trigger signal LS_trigger is high (thus, when the buck converter 104 switches to the on state of the low-side switch 222), the latched output Neg_ocp_latched of the second additional latch 362 is low.

[0054] As described further below in connection with FIG. 4, the switch control logic 312 (FIG. 3) drives the inductor current (at the switching node 220) to a safe level based on at least four inputs Pos_ocp_latched, Pos_ocp_blanked, Neg_ocp_blanked, Neg_ocp_latched. HS trigger signals HS_trigger and LS trigger signals LS_trigger that are applied to reset terminals R of additional latches 360, 362 are generated as outputs of the switch control logic 312. The trigger signals HS_trigger, LS_trigger are also applied to a HS single-shot block 364 and a LS single-shot block 366, respectively.

[0055] In operation, a rising edge of the HS trigger signal HS_trigger causes the HS single shot block 364 to generate a first blanking signal HS_blank and a high side minimum time signal HS_min_on, both of which are high for a predetermined period of time. In each case, the time period from the rising edge to the falling edge of the first blanking signal HS_blank and the high side minimum time signal HS_min_on is a predetermined period of time. A rising edge of the LS trigger signal LS_trigger causes the LS single shot block 366 to generate a second blanking signal LS_blank and a low side minimum time signal LS_min_on, both of which are high for a predetermined period of time. In each case, the time period from the rising edge to the falling edge of the second blanking signal LS_blank and the low side minimum time signal LS_min_on is a predetermined period of time.

[0056] As mentioned above, the first blanking signal HS_blank is applied to the inverting inputs of the HS related AND gates 320, 332 of the first and second enabling circuits 314, 316 and to an input of the second OR gate 304. The second blanking signal LS_blank is applied to the inverting inputs of the LS related AND gates 318, 330 of the enabling circuits 314, 316 and to another input of the second OR gate 304. The high side minimum time signal HS_min_on and the low side minimum time signal LS_min_on enable the recognition of the late latching signals Neg_ocp_hs_late_latch, Pos_ocp_ls_late_latch in the second enabling circuit 316 and the first enabling circuit 316, 314 via AND gates 334, 322, respectively.

[0057] The high side minimum time signal HS_min_on and the low side minimum time signal LS_min_on are also applied to the set terminal S and the reset terminal R, respectively, of a fifth latch 368 to generate the PWM signal Buck_PWM. When the high side minimum time signal HS_min_on is high (and thus from the rising edge of the HS trigger signal HS_trigger until the end of the subsequent predetermined time period), the PWM signal Buck_PWM is set (latched) high. When the high side minimum time signal HS_min_on is low and the fifth latch 368 is reset by the low side minimum time signal LS_min_on, the PWM signal Buck_PWM is low. The low side minimum time signal LS_min_on is high from the rising edge of the LS trigger signal LS_trigger until the end of the subsequent predetermined time period.

[0058] According to one aspect of the present description, the control logic operation for positive current limit rate detection may be as follows: The first input HS_pos_comp may be detected when the buck converter 104 is in a high side operating condition, the inductor current (at the switching node 220) is greater than the HS positive current limit level (5A in this example) and the first blanking signal HS_blank is low. If the first input HS_pos_comp is detected after the control logic has already decided to switch to a low side operating state, the output Pos_ocp_latched of the first additional latch 360 is set high and the switch control logic keeps the buck converter 104 in a low side operating state (with the LS switch 222 in an on state) until the inductor current drops below the LS positive current limit level (4A in this example).

[0059] When the converter 104 is in a low side operating condition, the second input LS_pos_comp is detected when the current at the switching node 220 is greater than the LS positive current limit level (4A in this example) and the second blanking signal LS_blank is low. If the second input LS_pos_comp is detected after the control logic decides to switch to a high side operating condition, the late latch signal Pos_ocp_ls_late_latch is set and the output Pos_ocp_latched from the first additional latch 360 is set the next time the buck converter 104 goes into a low side operating condition and the switch control logic keeps the buck converter 104 in a low side operating condition until the inductor current drops below the LS positive current limit level (4A in this example).

[0060] And the control logic operation for negative current limit rate detection may be as follows: When the buck converter 104 is in a low side operating condition, the fourth input LS_neg_comp is detected when the current at the switching node 220 is lower than the LS negative current limit level (-2A in this example) and the second blanking signal LS_blank is low. If the fourth input LS_neg_comp is detected after the control logic decides to switch to a high side operating state, the output Neg_ocp_latched of the second additional latch 362 is set high and the switch control logic keeps the buck converter 104 in a high side operating state until the inductor current increases higher than the HS negative current limit level (-1A in this example).

[0061] The third input HS_neg_comp is detected when the converter 104 is in a high side operating condition, the current at the switching node 220 is lower than the HS negative current limit level (-1A in this example) and the first blanking signal HS_blank is low. If the third input HS_neg_comp is detected after the control logic decides to switch to a low side operating condition, the corresponding late latch signal Neg_ocp_hs_late_latch is set and the output signal Neg_ocp_latched of the second additional latch 362 is set high the next time the buck converter 104 goes into a high side operating condition and the switch control logic keeps the buck converter 104 in a high side operating condition until the inductor current (at the switching node 220) increases above the HS negative current limit level (-1A in this example).

[0062] Therefore, according to one aspect of the present description, even after the control logic decides to change the state of the power FETs 210, 222, the overcurrent protection comparators 212, 214, 216, 218 may be monitored until the gate voltages of the FETs 210, 222 start to change. The HS comparators 212, 216 for late detection are blanked only with the first blanking signal HS_blank, and the LS comparators 214, 218 for late detection are blanked only with the second blanking signal LS_blank. The late overcurrent detection logic may be used to capture if the inductor current was too high (or too low) during the previous switching cycle. If a late overcurrent is detected, the switch control logic is used to drive the inductor current within the desired level.

[0063] The switch control logic 312 (FIG. 3) may be configured to operate the switching regulator control circuit 110 as shown in FIG. 4. After the LS trigger signal LS_trigger is generated (after step 800), the switch control logic waits until the low side minimum time signal LS_min_on goes low (step 802). (The low side minimum time signal LS_min_on enables the detection of the late latch signal Pos_ocp_ls_late_latch in the first enable circuit 314.) The switch control logic then determines whether the output Pos_ocp_latched of the first additional latch 360 is set (step 804). If the output Pos_ocp_latched of the first additional latch 360 is not set (step 804, "No"), then the switch control logic waits to receive the clock switching signal Clk_sw or one of the outputs Neg_ocp_blanked, Pos_ocp_blanked generated outside the enable circuits 314, 316. When one of these three signals Clk_sw, Neg_ocp_blanked, Pos_ocp_blanked is high, then the switch control logic determines whether the output Pos_ocp_blanked of the first AND gate 308 is high (step 808). When the output Pos_ocp_blanked of the first AND gate 308 is low (step 808: No), then the HS trigger signal HS_trigger is generated to switch the buck converter 104 to a high side operating condition (step 818).

[0064] If the output Pos_ocp_latched of the first additional latch 360 is set when the low-side minimum time signal goes low (step 804, "yes"), the switch control logic waits for the LS blanking signal to go low (at the end of the LS blanking time) (step 812). The second input LS_pos_comp (and thus the gated output (215) of the second comparator 214 during low-side operation) rises during that blanking time when the inductor current at the switching node 220 is greater than the lower current limit level of the upper current limit range (4A in the illustrated example). Low-side operation then continues until the inductor current falls below the lower current limit level of the upper current limit range and the output Pos_ocp_blanked of the first AND gate 308 goes low (step 814). In response to determining in step 808 that the output Pos_ocp_blanked of the first AND gate 308 is high, low side operation continues ("Yes" in step 808 follows step 814) until the inductor current falls below the lower current limit level of the upper current limit range (step 814).

[0065] In either event, once the inductor current falls below the lower current limit level of the upper current limit range (at the conclusion of step 814), a determination is made whether the clock switching signal Clk_sw rises during low-side operation (step 816). If low-side operation has occurred long enough for the clock switching signal Clk_sw to rise (step 816, "yes"), then the switch control logic generates an HS trigger signal HS_trigger to switch the converter 104 to a high-side operating condition (step 818). If low-side operation has not occurred long enough for the clock switching signal Clk_sw to rise (step 816, "no"), then the switch control logic waits until either the clock switching signal Clk_sw or one of the outputs Neg_ocp_blank of the second AND gate 310 rises (step 810), and then the switch control logic generates the HS trigger signal HS_trigger.

[0066] After the HS trigger signal HS_trigger is generated (after step 818), the switch control logic waits until the high side minimum time signal HS_min_on goes low (step 820). (The high side minimum time signal HS_min_on enables the detection of the late latch signal Neg_ocp_hs_late_latch in the second enable circuit 316.) The switch control logic then determines whether the output Neg_ocp_latched of the second additional latch 362 is set (step 822). If the output Neg_ocp_latched of the second additional latch 362 is not set (step 822: No), the switch control logic waits to receive the loop signal Loop_comp (and thus the output of the loop comparator 200) or one of the outputs Neg_ocp_blanked, Pos_ocp_blanked generated outside the enable circuits 314, 316. When one of these three signals Loop_comp, Neg_ocp_blanked, Pos_ocp_blanked is high, the switch control logic determines whether the output Neg_ocp_blanked of the second AND gate 310 is high (step 826). If the output Neg_ocp_blanked is low (step 826: No), the LS trigger signal LS_trigger is generated again (step 800).

[0067] If the output Neg_ocp_latched of the second additional latch 362 is set when the high side minimum time signal HS_min_on goes low ("YES" at step 822), the switch control logic waits for the HS blanking signal HS_blank to go low (at the end of the HS blanking time) (step 830). The third input HS_neg_comp (and thus the gated output (217) of the third comparator 216 during high side operation) rises during the blanking time when the inductor current at the switching node 220 is less than the upper current limit level of the lower current limit range (-1A in the illustrated example). High side operation then continues (step 832) until the inductor current exceeds the upper current limit level of the lower current limit range, such that the output Neg_ocp_blanked of the second AND gate 310 goes low (indicating that the inductor current is greater than the upper current limit level of the lower current limit range (-1A in the illustrated example). Thereafter, after the loop signal Loop_comp or the output Pos_ocp_blanked of the first AND gate 308 goes high (thus at the conclusion of step 828), the switch control logic generates the LS trigger signal LS_trigger (step 800) to switch the converter 104 back to a low side operating state. In response to determining in step 826 that the output Neg_ocp_blanked of the second AND gate 310 is high, high side operation continues ("Yes" in step 826 follows step 832) until the inductor current rises above the upper current limit level of the lower current limit range.

[0068] In relation to the above, the voltage at the switch node 220 is a function of the current through the inductor 224 and the resistance of the transistors 210, 222 through which the same current is conducted. During high side operation, V_sw=VIN-1×R_HS_on, where V_sw is the sense voltage applied to the comparators 212, 214, 216, 218, VIN is the input voltage from the power supply 102, I is the current through the high side switch 210, R_HS_on is the resistance of the high side switch 210, and I×R_HS_on is the voltage drop across the high side switch 210. During low-side operation, V_sw=GND-l×R_LS_on, where V_sw is the sense voltage applied to the comparators 212, 214, 216, 218, GND is the voltage at the ground terminal, I is the current through the low-side switch 222, R_LS_on is the resistance of the low-side switch 222, and I×R_LS_on is the voltage drop across the low-side switch 222. In each case, as the current I increases, the sense voltage V_sw decreases and vice versa.

[0069] However, in operation, the switch resistances R_HS_on, R_LS_on may depend on a variety of factors, including the manufacturing process, temperature, and the respective gate-source voltages vgs. Therefore, the desired voltage sensing or reference voltage generation may be performed using replica switches (not shown in the drawings) having resistances that match the actual resistances of the power FETs 210, 222. The current sense circuits 220, 108 may also be configured with appropriate level shifting circuitry (not shown in the drawings) to level shift the sense and reference voltages applied to the comparators 212, 214, 216, 218 so that the applied voltages do not exceed VIN (HS_neg_ocp) or fall below GND (LS_pos_ocp).

[0070] FIG. 5 is a timing diagram of a method of operating the voltage converter 104 shown in FIGS. 1 and 2 (including the switching regulator control circuit 110 shown in FIGS. 2-4). In operation, an HS gate signal HS_gate is applied to the gate terminal of the HS transistor 210 and goes high and low in response to the PWM signal Buck_PWM going high and low, respectively, with a time delay 502 between the rising and falling edges of the PWM signal Buck_PWM and the respective rising and falling edges of the HS gate signal HS_gate. Similarly, an LS gate signal LS_gate applied to the gate terminal of the LS transistor 222 goes high and low in response to the PWM signal Buck_PWM going high and low, respectively, with the same time delay 502 between the rising and falling edges of the PWM signal Buck_PWM and the respective rising and falling edges of the LS gate signal LS_gate. In each case, the delay 502 may be caused by the propagation delays of the switch control logic and the FET drivers.

[0071] The HS blanking signal HS_blank and the PWM signal Buck_PWM are established by the HS single shot block 264 operating through the set terminal S of the third latch. Thus, the HS blanking signal HS_blank and the PWM signal Buck_PWM both go high and remain high for a fixed period of time each time the HS blanking signal HS_blank goes high, but the HS blanking signal HS_blank and the PWM signal Buck_PWM do not necessarily both go low.

[0072] The LS blanking signal LS_blank and the PWM signal Buck_PWM, operating via the reset terminal R of the third latch 368, go both high and low, respectively, and remain high for a fixed period of time each time the LS blanking signal LS_blank goes high. The LS blanking signal LS_blank and the PWM signal Buck_PWM do not necessarily go both low and high, respectively. Importantly, when the frequency of the PWM signal Buck_PWM is high, the HS and LS blanking signals HS_blank, LS_blank may overlap each other in time, for example within the dotted oval 504, as shown.

[0073] The combined blanking signal OCP_blank produced by the second OR gate 304 is high whenever at least one of the HS and LS blanking signals HS_blank, LS_blank is high. The combined blanking signal OCP_blank is low only when both the HS and LS blanking signals HS_blank, LS_blank are low, such as at times 506, 508.

[0074] The first input HS_pos_comp (associated with the upper current limit) goes high when (1) the inductor current is greater than the HS_pos_comp level (5A in the illustrated example) and (2) the inductor current is increasing (hence, during high side operation when the HS transistor 210 is on), e.g., at times 510, 512. The first input HS_pos_comp goes low when the PWM signal Buck_PWM causes the transistors 210, 222 to switch states such that the inductor current begins to fall, e.g., at times 514, 516.

[0075] The second input LS_pos_comp goes high only when (1) the inductor current is greater than the LS_pos_comp level (4A in the illustrated example) and (2) the inductor current is falling (hence, during low side operation when the LS transistor 222 is on) but after a delay 518. In the situation shown in FIG. 5, the delay 518 is evident for the second input LS_pos_comp, but there is no such delay for the first input HS_pos_comp. This is because the inductor current during low side operation starts at an already high current level, while the inductor current during high side operation starts at a lower level and increases to give the first comparator 212 time to provide a reliable comparison before the inductor current exceeds the HS_pos_comp level.

[0076] The late latching of the second input LS_pos_comp is implemented by the latches 326, 360. The output Pos_ocp_ls_late_latch is set high when the second input LS_pos_comp is high and the second blanking signal LS_blank is low, for example at time 520, 521. At time 520, the low-side positive overcurrent protection (LS OCP) is latched after the LS blanking signal LS_blank falls, even though the PWM signal Buck_PWM has already switched to high-side operation. This latching allows current limiting operation at high switching frequencies. The output Pos_ocp_ls_late_latch of the latch 326 is reset low when the PWM signal Buck_PWM goes low, for example at time 522, or when the second input LS_pos_comp goes low, for example at time 523.

[0077] The output Pos_ocp_latched of the latch 360 is set at the beginning of the next LS period of the PWM signal Buck_PWM (e.g., at time 522). The output Pos_ocp_latched may be used to bring the inductor current below the LS_pos_comp level. The inductor current continues to fall after reaching the LS_pos_comp level and after the PWM signal Buck_PWM switches due to the delay 502 between the Buck_PWM signal and the HS and LS gate signals HS_gate, LS_gate. As a result, there is enough time in the subsequent HS period to reliably detect the inductor current exceeding the higher HS_pos_comp level.

[0078] 5 illustrates what can happen when the switching of the PWM signal Buck_PWM occurs at a high frequency: the late LS overcurrent detection is latched after the PWM signal Buck_PWM has already switched to HS, but the LS gate 222 is still high due to the propagation delay of the control logic and the FET drivers.

[0079] FIG. 6 illustrates what can happen when a late high-side overcurrent detection is latched after the PWM signal Buck_PWM has already gone to low-side operation, but while the HS gate 210 is still on due to the propagation delay of the control logic and FET driver. As illustrated in relation to oval 724, the HS positive overcurrent protection is latched after the first blanking signal HS_blank falls even though the PWM signal Buck_PWM has already switched to high-side operation. The HS OCP comparator data is available until the HS gate signal HS_gate falls. This is important because it allows current limiting operation at high switching frequencies. Also, as was the case in FIG. 5, Pos_ocp_latched may be used to bring the inductor current below the LS_pos_comp level at time 726, when there is a delay 502 between the time the second input LS_pos_comp falls (and the PWM signal Buck_PWM switches to HS) and the time the HS transistor 210 actually turns on.

[0080] The load 116 may be a component of an automotive radar application requiring high switching frequency and accurate peak current limit operation, if desired. When switching at high frequency, depending on the duty ratio, one or more of the HS and LS periods may be shorter than the current limit detection time. The system described in U.S. Patent Application No. 16 / 945,666 uses two comparators for the HS and LS periods with different reference levels to accurately limit the positive peak inductor current of the buck converter. Similarly, the negative peak inductor current is limited using two comparators. The system described herein has advantages over the system described in U.S. Patent Application No. 16 / 945,666, particularly in relation to high frequency operation.

[0081] Advantages can be obtained by continuing to monitor the HS OSP comparators 212, 216 after the switch control logic has decided to go to LS as long as the HS FET 210 is conducting. This is because the current sense information is reliable until the time when the HS FET gate voltage starts to change again after the HS blanking signal goes low. Similarly, the LS OSP comparators 212, 216 may be monitored as long as the LS FET 222 is conducting after the switch control logic has decided to go to HS. If an overcurrent is detected after the switch control logic switches, a late detection is latched and the inductor current is forced to be lower than the LS positive current limit level (4A in the illustrated example) or higher than the HS negative current limit level (-1A in the illustrated example). As a result, sufficient current sensing time may be available to reliably detect an overcurrent condition.

[0082] Implementing the converter circuit as described above eliminates the occurrence of voltage spikes in cases where the converter circuit operates at high frequencies. Due to the ability of the output circuit to limit current for applications operating at high frequencies, the voltage converter described above can be used in fixed high frequency automotive radar systems.

[0083] If desired, multiple portions of the voltage converter 104, such as the current comparator circuit 108, the switching regulator control circuit 110, the switching regulator circuit 112, and the compensator 201 (collectively, the controllers 108, 110, 112, 201 for the voltage converter 104) may be integrated into an integrated circuit (IC) and / or formed on or above a single semiconductor die 113 (FIGS. 1 and 2) according to various semiconductor and / or other processes. The conductive lines of the IC may be metal structures formed in or between insulating layers above the semiconductor die 113, doped regions (which may be silicided) formed within the semiconductor die 113, or doped semiconductor structures (which may be silicided) formed above the semiconductor die 113. The transistors used to implement the circuit structure of this example may be bipolar junction transistors (BJTs) or metal oxide semiconductor field effect transistors (MOSFETs), and may be n-type or p-type. The integrated devices and elements may also include resistors, capacitors, logic gates, and other suitable electronic devices not shown in the drawings for clarity. The description is not limited to the details and specific features of the examples shown in the drawings and otherwise described herein.

[0084] Also, note that in this description, the term "couple" may encompass a connection, communication, or signal path that allows for a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, (a) in a first example, device A is coupled to device B by a direct connection, or (b) in a second example, device A is coupled to device B via an intervening component C such that device B is controlled by device A via a control signal generated by device A, where intervening component C does not change the functional relationship between device A and device B. Also, in this description, a value that is "associated with" or "corresponding to" another value may describe a relationship between that value and the other value. The relationship may be determined, for example, using a calculation, a table, or any other suitable manner. For example, a voltage associated with a current may describe a relationship between the voltage and the current such that if the voltage is known, the current can be inferred, and vice versa. Also, in this description, a device that is "configured to" perform a certain task or function may be configured (e.g., programmed and / or hardwired) at the time of manufacture by a manufacturer to perform that function and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be through firmware and / or software programming of the device, through the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof. Also, as used herein, a circuit or device that includes certain components may alternatively be adapted to be combined with those components to form the described circuit or device.For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (voltage and / or current sources) may instead include only the semiconductor elements (e.g., a semiconductor die and / or integrated circuit (IC) package) in a single physical device and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure, either during or after manufacture, by an end user and / or a third party, etc.

[0085] Although certain components may be described herein as being of a particular process technology, these components may be interchanged for components of other process technologies. Circuits described herein are reconfigurable to include replaced components to provide functionality at least partially similar to that available prior to the replacement of the components. Components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the resistor shown, unless otherwise stated. For example, a resistor or capacitor shown and described as a single component may instead be multiple resistors or capacitors, respectively, coupled in series or parallel between the same two nodes as a single resistor or capacitor. Additionally, use of the phrase "ground voltage potential" in this description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or appropriate to the teachings of this description. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means ±10 percent of the stated value.

[0086] Variations in the described embodiments are possible and other embodiments are possible within the scope of the claims.

Claims

1. 1. A controller for a voltage converter, comprising: a switching regulator circuit having a regulator input and a regulator output, the switching regulator circuit including a high-side switch coupled between the regulator input and a switching terminal, and the low-side switch coupled between the switching terminal and a ground terminal; a current comparison circuit including at least four comparators, each of the comparators having a first comparator input coupled to the switching terminal, a second comparator input coupled to a respective reference voltage source, and a comparator output; a switching regulator control circuit coupled to the current comparison circuit, the switching regulator control circuit including a latch circuit configured to latch a signal corresponding to the at least one comparator output; receiving a respective comparator output from each of said comparators; generating a control signal for alternately turning the high-side switch and the low-side switch off and on such that the low-side switch is off when the high-side switch is on and the high-side switch is off when the low-side switch is on; the switching regulator control circuit configured as follows: Including, a controller, wherein two of the comparators are configured to compare the sensed current at the switching terminals to a first set of current limit levels that define an upper current limit range, and wherein two of the comparators are configured to compare the sensed current at the switching terminals to a second set of current limit levels that define a lower current limit range.

2. 2. The controller of claim 1, The high-side switch and the low-side switch include transistors.

3. 3. The controller of claim 2, a controller, wherein a voltage at the regulator input is applied to a first end of an inductor when the high-side switch is on, and wherein the first end of the inductor is connected to the ground terminal when the low-side switch is on.

4. 2. The controller of claim 1, the regulator output is adapted to be coupled to a load; The controller, wherein the voltage converter includes an inductor coupled between the switching terminal and the regulator output, and a capacitor coupled to the inductor.

5. 2. The controller of claim 1, The controller, wherein the latch circuit includes a latch configured to latch a signal associated with a lower current limit level of the first set of current limit levels.

6. 6. The controller of claim 5, The controller, wherein the switching regulator control circuit further includes a second latch circuit configured to latch a signal corresponding to one of the comparator outputs.

7. 7. The controller of claim 6, The controller, wherein the second latch circuit includes a latch configured to latch a signal associated with an upper current limit level of the second set of current limit levels.

8. 2. The controller of claim 1, The controller, wherein the latch circuit includes a latch configured to latch a signal associated with an upper current limit level of the second set of current limit levels.

9. 9. The controller of claim 8, The controller, wherein the switching regulator control circuit further includes a second latch circuit configured to latch a signal corresponding to one of the comparator outputs.

10. 10. The controller of claim 9, The controller, wherein the second latch circuit includes a latch configured to latch a signal associated with a lower current limit level of the first set of current limit levels.

11. 1. A controller for a buck converter, comprising: a switching regulator circuit having a regulator input and a regulator output, the switching regulator circuit including a high-side switch connected to a switching terminal, and a low-side switch connected to the switching terminal and coupled in series with the high-side switch; a current comparison circuit including at least four comparators, each of the comparators having a first comparator input coupled to the switching terminal, a second comparator input coupled to a respective reference voltage source, and a comparator output; a switching regulator control circuit coupled to the current comparison circuit, the switching regulator control circuit including a latch circuit configured to latch a signal corresponding to the at least one comparator output; receiving a respective comparator output from each of said comparators; generating a control signal for alternately turning the high-side switch and the low-side switch off and on such that the low-side switch is off when the high-side switch is on and the high-side switch is off when the low-side switch is on; the switching regulator control circuit configured as follows: Including, The controller, wherein the comparator is configured to compare the voltage at the switching terminal to a first set of current limit levels defining an upper current limit range and a second set of current limit levels defining a lower current limit range.

12. 12. The controller of claim 11, the high-side switch and the low-side switch include transistors; the switching regulator circuit is further configured such that when the high-side switch is on, a voltage at the regulator input is provided to a first end of an inductor, and when the low-side switch is on, the first end of the inductor is connected to ground.

13. 13. The controller of claim 12, The controller, wherein the latch circuit includes a latch configured to latch a signal associated with a lower current limit level of the first set of current limit levels.

14. 14. The controller of claim 13, The controller, wherein the switching regulator control circuit further includes a second latch circuit configured to latch a signal corresponding to one of the comparator outputs.

15. 15. The controller of claim 14, The controller, wherein the second latch circuit includes a latch configured to latch a signal associated with an upper current limit level of the second set of current limit levels.

16. 12. The controller of claim 11, The controller, wherein the latch circuit includes a latch configured to latch a signal associated with an upper current limit level of the second set of current limit levels.

17. 17. The controller of claim 16, The controller, wherein the switching regulator control circuit further includes a second latch circuit configured to latch a signal corresponding to one of the comparator outputs.

18. 18. The controller of claim 17, The controller, wherein the second latch circuit includes a latch configured to latch a signal associated with a lower current limit level of the second set of current limit levels.

19. 1. A method for converting an input voltage into an output voltage, comprising: coupling a switching node to the input voltage via a high-side switch and to ground via a low-side switch, and alternately providing the input voltage and the ground to an inductor coupled to the switching node; comparing, with a comparator, a voltage representative of the current in the inductor to a reference voltage; applying an output from the comparator to a switching regulator control circuit, generating a control signal by the switching regulator control circuit to alternately turn off and on the high-side switch and the low-side switch so that the low-side switch is off when the high-side switch is on and the high-side switch is off when the low-side switch is on, and latching a signal corresponding to at least one of the outputs from the comparator by a latch circuit; comparing, by at least four comparators, the sensed current in the inductor to a first set of current limit levels defining an upper current limit range and a second set of current limit levels defining a lower current limit range; A method comprising:

20. 20. The method of claim 19, the high-side switch and the low-side switch include transistors; the transistor is operated such that when the high-side switch is on, the input voltage is applied to a first end of the inductor, and when the low-side switch is on, the first end of the inductor is connected to ground.

21. 20. The method of claim 19, The method, wherein latching the signal includes latching a signal associated with a current limit level of the first set of current limit levels.

22. 20. The method of claim 19, The method further includes applying the output voltage to a component of a high frequency automotive radar system.

Images