Direct bonding and peeling of elements

Abstract

A bonding method is disclosed. The bonding method can include providing a first element having a device portion and a first non-conductive bonding material disposed on the device portion. The bonding method can include providing a second element including a carrier. The second element has a substrate and a second non-conductive bonding material disposed on the substrate. The bonding method can include depositing a release layer between the device portion of the first element and the first non-conductive bonding material or between the substrate of the second element and the second non-conductive bonding material. The bonding method can include directly bonding the first non-conductive bonding material of the first element to the second non-conductive bonding material of the second element without an intervening adhesive. The bonding method can include detaching the second element from the first element by transferring thermal energy to the release layer, thereby inducing diffusion of a gas comprising a volatile species from the release layer.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Patent Application No. 63 / 265,761, "Direct Bonding and Debonding of Elements," filed on December 20, 2021, the entire disclosure of which is incorporated herein by reference.

[0002] (Technical field) The field of the invention relates to direct bonding of a semiconductor device to a carrier, removal of the carrier from the semiconductor device after direct bonding, and structures therefor. [Background technology]

[0003] In some applications, semiconductor devices (such as wafers and dies) are temporarily bonded to carriers for intermediate processing. However, processing (e.g., thinning or backside processing) can be difficult using conventional temporary bonding materials (adhesives). Thus, there remains a need for improved methods and structures for temporary bonding. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Pat. No. 9,564,414 [Patent Document 2] U.S. Patent No. 9,391,143 [Patent Document 3] U.S. Pat. No. 1,043,4749 [Patent Document 4] U.S. Patent No. 9,716,033 [Patent Document 5] U.S. Patent No. 9,852,988 [Patent Document 6] U.S. Pat. No. 1,195,748

[0005] Specific implementations will now be described with reference to the following drawings, which are presented by way of example and not by way of limitation: [Brief description of the drawings]

[0006] [Figure 1A] FIG. 2 is a schematic cross-sectional side view of two elements prior to direct hybrid bonding. [Figure 1B] FIG. 1B is a schematic cross-sectional side view of the two elements shown in FIG. 1A after direct hybrid bonding. [Figures 2A-2E] Figure 2A is a schematic cross-sectional side view of a carrier, Figure 2B is a schematic cross-sectional side view of the carrier after preparation for direct bonding, Figure 2C is a schematic cross-sectional side view of a semiconductor element having a bonding layer, Figure 2D is a schematic cross-sectional side view of a semiconductor element having a bonding layer after preparation for direct bonding, and Figure 2E is a schematic cross-sectional side view of the bonding structure. [Fig. 2F-2I] Figure 2F is a schematic cross-sectional side view of the bonding structure of Figure 2E reproduced for explanatory purposes, Figure 2G is a schematic cross-sectional side view of the carrier and semiconductor element after peeling, Figure 2H is a schematic cross-sectional side view of the carrier and semiconductor element on the peeling tape, and Figure 2I is a schematic cross-sectional side view of the carrier and semiconductor element after peeling. [Diagram 3] 1 is a schematic cross-sectional side view of a joint structure according to one embodiment. [Figure 4] 1 is a schematic cross-sectional side view of a joint structure according to another embodiment. [Figure 5A-5B] FIG. 5A is a schematic cross-sectional side view of a joint structure according to another embodiment, and FIG. 5B is an enlarged view of a portion of the joint structure shown in FIG. 5A. [Figures 6A-6E] FIG. 6A is a schematic cross-sectional side view of a semiconductor element having a bonding layer, FIG. 6B is a schematic cross-sectional side view of a semiconductor element having a bonding layer after preparation for direct bonding, FIG. 6C is a schematic cross-sectional side view of a carrier, FIG. 6D is a schematic cross-sectional side view of the carrier after preparation for direct bonding, and FIG. 6E is a schematic cross-sectional side view of a bonding structure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] The embodiments described herein can combine direct bonding or hybrid direct bonding techniques with temporary bonding layers configured to release or peel the directly bonded elements.

[0008] Various embodiments disclosed herein relate to a direct bond structure in which two or more elements can be directly bonded to each other without the use of adhesive. FIGS. 1A and 1B show a schematic process of forming a direct hybrid bonded structure without the use of adhesive according to some embodiments. In FIGS. 1A and 1B, the bonded structure 100 comprises two elements 102 and 104 that can be directly bonded to each other at a bonding interface 118 without the use of adhesive. Two or more microelectronic elements 102 and 104 (e.g., integrated device dies, wafers, semiconductor elements including passive devices, individual active devices such as power switches, etc.) can be stacked or bonded to each other to form the bonded structure 100. A conductive feature 106a (e.g., a contact pad, an exposed end of a via (e.g., TSV), or a through-substrate electrode) of the first element 102 can be electrically connected to a corresponding conductive feature 106b of the second element 104. Any suitable number of elements can be stacked in the bonded structure 100. For example, a third element (not shown) can be stacked on top of the second element 104, a fourth element (not shown) can be stacked on top of the third element, and so on. Additionally or alternatively, one or more additional elements (not shown) can be stacked laterally adjacent to one another along the first element 102. In some embodiments, the laterally stacked additional elements can be smaller than the second element. In some embodiments, the laterally stacked additional elements can be half the size of the second element.

[0009] In some embodiments, the elements 102 and 104 are directly bonded to each other without adhesive. In various embodiments, a non-conductive field region comprising a non-conductive or dielectric material can serve as the first bonding layer 108a of the first element 102, which can be directly bonded without adhesive to a corresponding non-conductive field region comprising a non-conductive or dielectric material that serves as the second bonding layer 108b of the second element 104. The non-conductive bonding layers 108a and 108b can be disposed on the front surfaces 114a and 114b of device portions 110a and 110b, such as semiconductor (e.g., silicon) portions of the elements 102, 103, respectively. Active devices and / or circuits can be patterned and / or otherwise disposed in or on the device portions 110a and 110b. Active devices and / or circuits may be located on or near the front surfaces 114a and 114b of the device portions 110a and 110b and / or on or near the opposite back surfaces 116a and 116b of the device portions 110a and 110b. An adhesive layer may be provided on the front and / or back surfaces of the elements. A non-conductive material may be referred to as a non-conductive adhesive region or adhesive layer 108a of the first element 102. In some embodiments, the non-conductive adhesive layer 108a of the first element 102 may be directly bonded to a corresponding non-conductive adhesive layer 108b of the second element 104 using a dielectric-dielectric bonding technique. For example, a dielectric-dielectric bond may be formed without adhesive using direct bonding techniques as disclosed in at least U.S. Pat. Nos. 9,564,414, 9,391,143, and 10,434,749, the entire disclosures of each of which are incorporated herein by reference for all purposes. It should be appreciated that in various embodiments, bonding layers 108a and / or 108b can include a non-conductive material, such as, for example, a dielectric material, such as silicon oxide, or an undoped semiconductor material, such as undoped silicon.Suitable dielectric bonding surfaces or materials for direct bonding include inorganic dielectrics such as, but not limited to, silicon oxide, silicon nitride, or silicon oxynitride, or may contain carbon, such as silicon carbide, silicon oxycarbonitride, low-K dielectric materials, SiCOH dielectrics, silicon carbonitride, or diamond-like carbon, or materials with a diamond surface. Such carbon-containing ceramic materials may be considered inorganic, even though they contain carbon. In some embodiments, the dielectric material does not include polymeric materials such as epoxies, resins, or molding compounds.

[0010] In some embodiments, the device portions 110a and 110b can have significantly different coefficients of thermal expansion (CTE), defining a heterostructure. The difference in CTE between the device portions 110a and 110b, and in particular between the bulk semiconductor, typically single crystal portions of the device portions 110a, 110b, can be greater than 5 ppm or greater than 10 ppm. For example, the difference in CTE between the device portions 110a and 110b can be in the range of 5 ppm to 100 ppm, 5 ppm to 40 ppm, 10 ppm to 100 ppm, or 10 ppm to 40 ppm. In some embodiments, one of the device portions 110a and 110b can comprise an optoelectronic single crystal material, including perovskite materials useful for optoelectronic or pyroelectric applications, and the other of the device portions 110a, 110b comprises a more conventional substrate material. For example, one of the device portions 110a, 110b may include lithium tantalate (LiTaO3) or lithium niobate (LiNbO3), and the other of the device portions 110a, 110b may include silicon (Si), quartz, fused silica glass, sapphire, or glass. In another embodiment, one of the device portions 110a and 110b may include a single III-V semiconductor material, such as gallium arsenide (GaAs) or gallium nitride (GaN), and the other of the device portions 110a and 110b may include a non-III-V semiconductor material, such as silicon (Si), or another material with a similar CTE, such as quartz, fused silica glass, sapphire, or glass.

[0011] In various embodiments, a direct hybrid bond can be formed without the use of an adhesive. For example, the non-conductive bonding surfaces 112a and 112b can be polished to a high degree of smoothness. The bonding surfaces 112a and 112b can be cleaned and exposed to a plasma and / or an etchant to activate the bonding surfaces 112a and 112b. In some embodiments, the bonding surfaces 112a and 112b can be terminated with chemical species after or during activation (e.g., during a plasma and / or etch process). Without being limited by theory, in some embodiments, an activation process can be performed to break the chemical bonds of the bonding surfaces 112a and 112b, and a termination process can provide additional chemical species to the bonding surfaces that improve the bond energy during direct bonding. In some embodiments, activation and termination are provided in the same step, such as, for example, applying a plasma to activate and terminate the bonding surfaces 112a and 112b. In other embodiments, the bonding surfaces 112a and 112b can be terminated in a separate process to provide additional chemical species for direct bonding. In various embodiments, the termination species can include nitrogen. For example, in some embodiments, the bonding surface(s) 112a, 112b can be exposed to a nitrogen-containing plasma. Additionally, in some embodiments, the bonding surfaces 112a and 112b can be exposed to fluorine. For example, one or more fluorine peaks can be present at or near the bonding interface 118 of the first element 102 and the second element 104. Thus, in the direct bond structure 100, the bonding interface 118 between the two non-conductive materials (e.g., bonding layers 108a and 108b) can have a very smooth interface with high nitrogen content and / or fluorine peaks at the bonding interface 118. Further examples of activation and / or termination treatments can be found throughout U.S. Pat. Nos. 9,564,414, 9,391,143, and 10,434,749, the entire disclosures of which are incorporated herein by reference for all purposes.

[0012] In various embodiments, the conductive feature 106a of the first element 102 can also be directly bonded to the corresponding conductive feature 106b of the second element 104. For example, direct hybrid bonding techniques can be used to provide a direct conductor-conductor bond along a bonding interface 118 that includes covalently directly bonded non-conductive-non-conductive (e.g., dielectric-dielectric) surfaces prepared as described above. In various embodiments, direct conductor-conductor (e.g., conductive feature 106a-conductive feature 106b) bonds and hybrid dielectric-dielectric bonds can be formed using direct bonding techniques disclosed in at least U.S. Pat. Nos. 9,716,033 and 9,852,988, the entire disclosures of which are incorporated herein by reference for all purposes. In the direct hybrid bonding embodiments described herein, the conductive feature is provided in a non-conductive bonding layer, and both the conductive feature and the non-conductive feature are prepared for direct bonding, such as by planarization, activation, and / or termination processes described above. Thus, the bonding surfaces prepared for direct bonding include both conductive and non-conductive features.

[0013] For example, non-conductive (e.g., dielectric) bonding surfaces 112a, 112b (e.g., inorganic dielectric surfaces) can be prepared and bonded directly to one another without an adhesive as described above. Also, conductive contact features (e.g., conductive features 106a and 106b that can be at least partially surrounded by a non-conductive dielectric field region in bonding layers 108a, 108b) can be bonded directly to one another without an adhesive. In various embodiments, conductive features 106a, 106b can comprise individual pads or traces at least partially embedded in a non-conductive field region. In some embodiments, the conductive contact features can comprise exposed contact surfaces of through-substrate vias (e.g., through silicon vias (TSVs)). In some embodiments, the respective conductive features 106a and 106b can be recessed below the dielectric field region or the outer (e.g., upper) surface of the non-conductive bonding layers 108a and 108b (non-conductive bonding surfaces 112a and 112b), e.g., by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, e.g., in the range of 2 nm to 20 nm, or in the range of 4 nm to 10 nm. In various embodiments, prior to direct bonding, the recesses of the opposing elements can be sized such that the total gap between the opposing contact pads is less than 15 nm, or less than 10 nm. In some embodiments of the bonding tool described herein, the non-conductive bonding layers 108a and 108b can be directly bonded to each other without adhesive, in some embodiments, at room temperature, after which the bonded structure 100 can be annealed. Upon annealing, the conductive features 106a and 106b can expand and contact each other to form a metal-metal direct bond. Advantageously, Direct Bond Interconnect, or DBI (registered trademark) technology available from Adeia, Inc., San Jose, California, USA, allows for a high density of conductive features 106a and 106b to be connected across the direct bond interface 118 (e.g., small or fine pitch for a regular array).In some embodiments, the pitch of the conductive features 106a and 106b, such as the conductive traces embedded in one of the bonding surfaces of the bonding element, can be less than 100 microns, or less than 10 microns, or even less than 2 microns. In some applications, the ratio of the pitch of the conductive features 106a and 106b to one of the dimensions of the bonding pad (e.g., diameter) is less than 20, or less than 10, or less than 5, or less than 3, and in some cases desirably less than 2. In other applications, the width of the conductive traces embedded in one of the bonding surfaces of the bonding element can be in the range of 0.3 to 20 microns, such as in the range of 0.3 to 3 microns. In various embodiments, the conductive features 106a and 106b and / or the traces can include copper or a copper alloy, although other metals may also be suitable. For example, the conductive features disclosed herein, such as the conductive features 106a and 106b, can include a fine-grain metal (e.g., fine-grain copper).

[0014] Thus, in a direct bonding process, the first element 102 may be directly bonded to the second element 104 without the aid of an adhesive. In some configurations, the first element 102 may comprise a singulated element, such as a singulated integrated device die. In another configuration, the first element 102 may comprise a carrier or substrate (e.g., a wafer) comprising a plurality (e.g., tens, hundreds, or more) of device regions that, when singulated, form a plurality of integrated device dies. Similarly, the second element 104 may comprise a singulated element, such as a singulated integrated device die. In another configuration, the second element 104 may comprise a carrier or substrate (e.g., a wafer). Thus, the embodiments disclosed herein may be applied to wafer-to-wafer (W2W), die-to-die (D2D), or die-to-wafer (D2W) bonding processes. In a wafer-to-wafer (W2W) process, two or more wafers may be directly bonded (e.g., direct hybrid bonded) to one another and singulated using a suitable singulation process. After singulation, the side edges of the singulated structures (e.g., the side edges of the two joining elements) can be substantially flush and can include a pattern indicative of a common singulation process for the joining structures (e.g., a saw mark if a saw singulation process is used).

[0015] As described herein, the first element 102 and the second element 104 can be directly bonded to each other without an adhesive, which is different from a deposition process and results in a structurally different interface compared to deposition. In one application, the width of the first element 102 of the bonded structure is similar to the width of the second element 104. In some other embodiments, the width of the first element 102 of the bonded structure 100 is different from the width of the second element 104. Similarly, the width or area of ​​the larger element of the bonded structure may be at least 10% larger than the width or area of ​​the smaller element. Thus, the first element 102 and the second element 104 can comprise non-deposited elements. Additionally, the direct bonded structure 100 can include defect regions in which nanoscale voids (nanovoids) exist along the bonded interface 118. The nanovoids can be formed due to activation (e.g., exposure to plasma) of the bonded surfaces 112a and 112b. As described above, the bonded interface 118 can include a concentration of material resulting from the activation process and / or the final chemical treatment process. For example, in embodiments utilizing nitrogen plasma for activation, nitrogen peaks may form at the bonding interface 118. The nitrogen peaks may be detected using secondary ion mass spectrometry (SIMS) techniques. In various embodiments, for example, nitrogen termination (e.g., exposing the bonding surface to a nitrogen-containing plasma) may replace OH groups of a hydrolyzed (OH-terminated) surface with NH2 molecules to generate a nitrogen-terminated surface. In embodiments utilizing oxygen plasma for activation, oxygen peaks may form at the bonding interface 118. In some embodiments, the bonding interface 118 may include silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As described herein, direct bonding may include covalent bonds that are stronger than van der Waals bonds. The bonding layers 108a and 108b may also include polished surfaces that are planarized to a high degree of smoothness.

[0016] In various embodiments, the metal-metal bond between the conductive features 106a and 106b can be bonded such that the metal grains grow toward each other across the bond interface 118. In some embodiments, the metal is or includes copper, and the copper can have grains oriented along (111) crystal planes to enhance diffusion of the copper across the bond interface 118. In some embodiments, the conductive features 106a and 106b can include a nanotwinned copper grain structure, which can aid in fusing the conductive features during annealing. The bond interface 118 can extend substantially completely to at least a portion of the bonded conductive features 106a and 106b, such that there are substantially no gaps between the non-conductive bonding layers 108a and 108b at or near the bonded conductive features 106a and 106b. In some embodiments, a barrier layer can be provided under and / or laterally surrounding the conductive features 106a and 106b (which can include copper, for example). However, in other embodiments, there may be no barrier layer underneath the conductive features 106a and 106b, as described, for example, in U.S. Pat. No. 1,195,748, the entire disclosure of which is incorporated herein by reference for all purposes.

[0017] Advantageously, the use of the hybrid bonding techniques described herein allows for extremely fine pitches between adjacent conductive features 106a and 106b and / or small pad sizes. For example, in various embodiments, the pitch p between adjacent conductive features 106a (or 106b) (i.e., edge-to-edge or center-to-center distance as shown in FIG. 1A) can be in the range of 0.5 microns to 50 microns, 0.75 microns to 25 microns, 1 micron to 25 microns, 1 micron to 10 microns, or 1 micron to 5 microns. Additionally, the major lateral dimensions (e.g., pad diameter) can also be small, e.g., in the range of 0.25 microns to 30 microns, 0.25 microns to 5 microns, or 0.5 microns to 5 microns.

[0018] As described above, the non-conductive bonding layers 108a and 108b can be bonded directly to one another without an adhesive, and then the bonded structure 100 can be annealed. Upon annealing, the conductive features 106a, 106b expand and contact one another, forming a direct metal-metal bond. In some embodiments, the materials of the conductive features 106a, 106b can interdiffuse during the annealing process.

[0019] In some applications, it may be desirable to utilize thinned semiconductor elements in a multi-element device stack, such as a memory device. For example, a semiconductor element (such as a semiconductor device wafer) can be temporarily bonded to a carrier (e.g., a glass or silicon carrier wafer) via an adhesive (e.g., a thin polymeric film or an organic adhesive), such as a thermally or UV-curable adhesive. The backside of the semiconductor element can be thinned, for example, by grinding and / or chemical mechanical polishing (CMP). Additionally, additional backside processing can be performed on the backside of the semiconductor element while it is attached to the carrier. For example, a metallization layer or back-end interconnect (BEOL) layer can be deposited or otherwise provided on the thinned semiconductor element.

[0020] However, the use of adhesives for temporary bonding can be challenging in many ways. For example, when the device wafer is thinned, any thermal treatments together with residual stresses from the BEOL thin films may cause a lateral expansion of the die size because the organic adhesives cannot provide sufficient bond strength to suppress the lateral expansion of the device wafer. Furthermore, the mechanical stability of the adhesive bond between the device wafer and the carrier wafer during the thinning process (e.g., grinding process) may be reduced or unreliable due to the forces applied during thinning. The adhesive may have thickness non-uniformity or uneven thickness along the bonding surface. In some cases, the thinning process may cause the device wafer to have a significant thickness variation, exceeding the desired total thickness variation (TTV). For example, the temporary adhesive interposed between the device wafer and the carrier wafer may have non-uniformity that results in excessive thickness variation upon thinning. Furthermore, the temporary adhesive bond may not have sufficient thermal and / or chemical stability when exposed to various processes. For example, the temporary adhesive may degrade when exposed to chemicals used in wafer cleaning, electrochemical deposition (ECD), and / or CMP. Alternatively or additionally, the temporary adhesive may decompose during the deposition and / or etching process (e.g., chemical vapor deposition (CVD), plasma enhanced CVD, physical vapor deposition, etc.). As another example, organic adhesives may have relatively low thermal conductivity. Furthermore, when the carrier and adhesive are removed from the device wafer, the device wafer may contain adhesive residues, which may lead to the use of extra cleaning steps. Thus, there remains a need for improved methods and structures for temporarily bonding devices and processing (e.g., thinning) the devices.

[0021] 2A-2E illustrate a bonding method, and FIG. 2F-2I illustrate a peeling or delaminating method according to various embodiments. The bonding and delaminating methods can be performed in sequence to form a processed (e.g., thinned) element. FIG. 2A is a schematic cross-sectional side view of a first element (e.g., carrier 10). Carrier 10 can include an intermediate layer 14 (which can be an inorganic layer such as silicon oxide) on substrate 12, a release layer 16 on intermediate layer 14, and a bonding layer 18 (which can also be a dielectric layer such as silicon oxide) on release layer 16. In the illustrated embodiment, release layer 16 is provided together with carrier 10. However, in some other embodiments, release layer 16 can be provided together with semiconductor element 20 on device portion 22 of FIG. 2C (see FIG. 6A-6I). In some embodiments, substrate 12 can include a wafer. Substrate 12 can include any suitable material, such as, for example, glass, low-doped silicon, etc. In some embodiments, substrate 12 can include a bulk carrier portion. Each of the intermediate layer 14 and the bonding layer 18 may comprise a non-conductive material, such as those materials mentioned above as suitable for direct bonding, including, but not limited to, silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, and the like. The intermediate layer 14 may be thin. For example, the intermediate layer 14 may range between 50 nm and 500 nm, or between 100 nm and 200 nm. The intermediate layer 14 may perform an adhesive function between the release layer 16 and the substrate 12. When neither a barrier function nor an adhesive function is required, for example, in the case of a sacrificial or inactive carrier such as a glass substrate, the intermediate layer 14 may be omitted.

[0022] The release layer 16 can include a material configured to release a gas in response to application of thermal energy. In some embodiments, the release layer 16 can release a gas in response to heating or irradiation. For example, the release layer 16 can be configured to release a gas in response to irradiative heating, laser rastering, rapid thermal annealing, thermal annealing, or microwave heating. In some embodiments, the release layer 16 can include a carbon-containing layer, such as a carbon-based layer. The release layer 16 can include amorphous carbon with a contaminant. The contaminant can include a chemical species that becomes volatile upon absorption of energy and is released as a gas. In some embodiments, the volatile chemical species includes hydrogen. In some embodiments, the volatile chemical species includes a halogen, such as chlorine or fluorine. The contaminant can also include chemical species that do not release a gas in addition to the volatile chemical species.

[0023] In some embodiments, the release layer 16 can include amorphous carbon containing hydrogen and fluorine. The release layer 16 can include sufficient volatilizable components to allow mechanical release upon absorption of energy, yet have a mechanically robust composition to aid in subsequent processing as described herein. In some embodiments, the hydrogen and fluorine can comprise between about 10 wt% and 85 wt%, more particularly between about 30 wt% and 65 wt% of the release layer 16.

[0024] The release layer 16 can be deposited on the intermediate layer 14. For example, the release layer 16 can be deposited by chemical vapor deposition (CVD), more particularly by plasma enhanced CVD (PECVD), or by physical vapor deposition (PVD). The release layer 16 can have a thickness in the range of, for example, 10 nm to 3 μm, 10 nm to 500 nm, more particularly, for example, in the range of, for example, 200 nm to 500 nm. In another embodiment, the release layer can have a thickness of about 500 nm to 1 μm. In general, this thickness can be selected to produce sufficient outgassing to allow physical separation, and can be easily deposited using available equipment. Since one of the functions of the release layer 16 is to absorb thermal energy in order to outgas, it may be desirable to make the layer thicker, provided that thickness uniformity can be maintained. The thickness of the release layer 16 can have a thickness uniformity of, for example, less than 3%, or, for example, less than 1.5%.

[0025] Applying the release layer 16 by PECVD advantageously allows deposition at low temperatures and allows the deposition parameters to be adjusted to control the outgas(es) content of the release layer 16. For example, PECVD of an α-C:H,F layer can use hydrocarbon and / or hydrofluorocarbon precursors (e.g., CHF3, CH4, CF4, C2H6, C3F6, C4F8, C6F6, C6H5F, HFPO, SF6, NF3, H2, N2, He, Ar, CH4, C2H2, C6H6, etc.) and inert gases. Other alkanes that are partially or fully fluorinated and can be easily delivered in the gas phase into the vacuum chamber can also be used. Additionally, alkene analog materials can be used. The deposition temperature, plasma power and pressure, among other parameters, can be adjusted to control the hydrogen and / or fluorine content. Its content is desirably sufficient to volatilize between 10% and 95% of the film thickness upon heating, more specifically between 50% and 90% of the film thickness, as described below. At the same time, α-C:H,F (originally developed for low-k applications in semiconductor interconnect layers) is robust enough to withstand the desired processing of the temporary bond structure and can provide a uniform thickness sufficient to apply a planar bonding layer 18 thereover. Of course, the detailed settings will depend on the tool employed for deposition. A non-limiting example is the use of an ECR plasma at 2 mTorr and an applied plasma generation power of 600 W. The deposition temperature can be, for example, between 50° C. and 300° C., desirably below 200° C. The deposition temperature for applying the release layer 16 is lower than the release temperature for releasing the release layer 16. Advantageously, no post-deposition anneal is performed to avoid loss of hydrogen and fluorine content.

[0026] In FIG. 2B, after the bonding layer 18 is deposited on the release layer, the bonding layer 18 can be prepared for direct bonding. The bonding surface of the bonding layer 18 can be polished to a high degree of smoothness. For example, the bonding surface can be polished to a root mean square (rms) surface roughness of less than 2 nm, e.g., less than 1 nm, less than 0.5 nm, etc. The bonding surface can be cleaned and exposed to a plasma and / or an etchant to activate the bonding surface, thereby at least partially defining the prepared surface 18a. In some embodiments, the bonding surface can be terminated with a chemical species after or during activation (e.g., during the plasma and / or etch process).

[0027] FIG. 2C is a schematic cross-sectional side view of a second element, in this case a semiconductor element 20, with a bonding layer 24. Similar to the bonding layer 18 of the carrier 10, the bonding layer 24 of the second element can include an inorganic non-conductive material, such as silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, and the like. The semiconductor element 20 can include semiconductor device elements in wafer form or as singulated integrated device dies. The semiconductor element 20 can include a device portion 22 having active circuits and / or devices therein. As mentioned above, in some other embodiments, the release layer 16 can be prepared together with the semiconductor element 20, rather than preparing the release layer 16 together with the carrier 10.

[0028] In FIG. 2D, the bonding dielectric layer 24 can be prepared for direct bonding. The bonding surfaces of the bonding dielectric layer 24 can be polished to a high degree of smoothness. For example, the bonding surfaces can be polished to a root mean square (rms) surface roughness of less than 2 nm, e.g., less than 1 nm, less than 0.5 nm, etc. The bonding surfaces can be cleaned and exposed to a plasma and / or an etchant to activate the bonding surfaces, thereby at least partially defining the prepared surface 24a. In some embodiments, the bonding surfaces can be terminated with a chemical species after or during activation (e.g., during the plasma and / or etch process).

[0029] 2E, semiconductor device 20 can be bonded to carrier 10. Prepared surface 24a of semiconductor device 20 and prepared surface 18a of carrier 10 can be directly bonded to one another without an intervening adhesive along bond interface 26. As discussed above, direct bonding can be performed at room temperature, without the application of external pressure (e.g., other than light touch to initiate bond surface propagation), with or without subsequent annealing to strengthen the direct bond.

[0030] 2F is a schematic cross-sectional side view of the bonding structure 30 formed in FIG. 2E. The bonding structure 30 includes a semiconductor device 20 directly bonded to a carrier 10. The device portion 22 of the semiconductor device 20 may be processed. In some embodiments, the device portion 22 of the semiconductor device 20 may be thinned or otherwise processed (e.g., by adding BEOL layers) while in the bonding structure 30. For example, the backside 22a of the device portion 22 may be thinned by grinding and / or chemical mechanical polishing (CMP). Other processing at this stage may include robotic transfer and bonding the backside of the semiconductor device 20 to a third device (not shown).

[0031] In FIG. 2G, after any processing, the carrier 10 of the bonded structure 30 can be detached from the semiconductor device 20 by transferring thermal energy to the release layer 16, thereby inducing gas diffusion from the release layer 16. In some embodiments, the release layer 16 can outgas hydrogen and / or fluorine. Thermal energy can be transferred to the release layer 16 by, for example, irradiation, laser rastering, thermal annealing, rapid thermal annealing, microwave heating, and the like. When thermal energy is transferred to the release layer 16 using irradiation heat or laser rastering, the substrate 12 can include a material transparent to light. The laser or irradiation heating light can be irradiated to the release layer 16 through the substrate 12, thereby heating the release layer 16 and causing outgassing. In some embodiments, the release layer 16 can be heated locally. In some other embodiments, the entire bonded structure 30 can be heated. In some embodiments, the thermal energy can heat the release layer 16 to a temperature of about 100° C. to 400° C., particularly about 200° C. to 250° C. In some embodiments, the temperature to which release layer 16 is heated may be at least 50° C. higher than the deposition temperature used to deposit release layer 16.

[0032] The amount of gas released from the release layer 16 can be controlled. In some embodiments, the temperature applied to the release layer 16 can be controlled to vary the amount of gas released from the release layer 16. In some embodiments, the deposition process of the release layer 16 can be controlled to adjust the amount of gaseous elements incorporated into the release layer 16 and vary the amount of gas released from the release layer 16 upon heating. For example, the amount of volatile gas in the release layer 16 can be adjusted by adjusting the fluorine and / or hydrogen content in the release layer 16, such as by controlling the plasma power, substrate bias, precursor flow rate, pressure and / or substrate temperature in the release layer deposition process.

[0033] 2H, a release tape 32 or other device can be applied to the substrate 12 before removing the carrier 10 from the semiconductor device 20. In some embodiments, the release tape 32 can include a dicing tape.

[0034] In FIG. 2I, the carrier 10 of the bonding structure 30 can be detached from the semiconductor device 20 by transferring thermal energy to the release layer 16, thereby inducing gas diffusion from the release layer 16.

[0035] In some embodiments, the surface of the semiconductor element 20 may be ashed after the carrier 10 is removed from the semiconductor element 20 to remove any residue of the release layer 16. In the illustrated embodiment, the release layer 16 is provided together with the carrier 10, but in various embodiments, the release layer 16 may be provided together with the semiconductor element 20 (see FIGS. 6A-6E). Also, in various embodiments, the carrier 10 may include a semiconductor element, and the two semiconductor elements may be directly bonded and peeled off.

[0036] After processing the semiconductor element 20, the semiconductor element 20 can be bonded to another element (not shown). In some embodiments, the semiconductor element 20 can be bonded directly to another element without an intervening adhesive. For example, the semiconductor element 20 and the other element can be bonded directly to one another in the manner described with respect to Figures 1A and 1B. For example, the semiconductor element 20 can include the first element 102 of Figures 1A and 1B, and the other element can include the second element 104.

[0037] FIG. 3 is a schematic cross-sectional side view of a bonding structure 34 according to one embodiment. Unless otherwise stated, the components of FIG. 3 can be similar or the same as the similar components of FIGS. 1A-2I. The release layer 16 can have a footprint smaller than the footprint of the substrate 12 or the intervening layer 14 of the carrier 10. The footprint of the release layer 16 can be sized to provide sufficient bonding strength to process (thin) the semiconductor device 20 and to release the device upon outgassing. In some embodiments, the side edges of the release layer 16 can be covered with the material of the intervening layer 14 or the bonding layer 18. The intervening layer 14 or the bonding layer 18 can protect the side edges of the release layer 16 from chemicals used in intervening process steps before the release layer 16 is released.

[0038] FIG. 4 is a schematic cross-sectional side view of a bonding structure 36 according to one embodiment. Unless otherwise indicated, the components of FIG. 4 can be similar or the same as the similar components of FIGS. 1A-3. The bonding structure 36 can include two release layers (first release layer 16 and second release layer 16'). In some embodiments, the first release layer 16 can be prepared together with the carrier 10, and the second release layer 16' can be prepared together with the semiconductor device 20. For example, the semiconductor device 20 can include a device portion 22, an intermediate layer 38 on the device portion 22, a second release layer 16' on the intermediate layer 38, and an adhesive layer 24 on the second release layer 16', and the carrier 10 can include a substrate 12, an intermediate layer 14 on the substrate 12, a first release layer 16 on the intermediate layer 14, and an adhesive layer 18 on the intermediate layer 14. The adhesive layers 18, 24 can be bonded along an adhesive interface 26, as shown in FIG. 4.

[0039] In some embodiments, the first release layer 16 and the second release layer 16' can include the same material or different materials. For example, the first release layer 16 and the second release layer 16' can include different ratios of fluorine and / or hydrogen. By providing different release layers for the first and second release layers 16, 16', the temperature at which the first and second release layers 16, 16' outgas can be controlled.

[0040] FIG. 5A is a schematic cross-sectional side view of a bonding structure 40 according to one embodiment. FIG. 5B is an enlarged view of a portion of the bonding structure 40 shown in FIG. 5A. Unless otherwise noted, the components of FIG. 5A and FIG. 5B can be similar or the same as the similar components of FIG. 1A-FIG. 4. The bonding structure 40 can include a reflective layer 42 and a dielectric layer 44 disposed between the reflective layer 42 and the substrate 12. The reflective layer 42 can be advantageous when irradiating energy (e.g., laser rastering) is used to induce gas diffusion from the release layer 16. For example, laser light can pass through the substrate 12 to the release layer 16, and a portion of the laser light can pass through the release layer 16. The reflective layer 42 can reflect the laser light that passes through the release layer 16 back to the release layer 16, thereby enhancing or maximizing the energy transfer from the laser light source to the release layer 16. In some embodiments, the reflective layer 42 can include a reflective metal that is reflective to the wavelength of the irradiating energy. Thus, the reflective layer 42 can reflect the laser light back into the release layer 16 to facilitate its decomposition. In some embodiments, the reflective layer 42 can be partially transparent.

[0041] In Figures 2A and 2B, the release layer 16 is provided together with the carrier 10. However, as described herein, in some other embodiments, the release layer 16 can be provided on the device portion 22 together with the semiconductor element 20. Figures 6A-6E show bonding methods according to various embodiments in which the release layer 16 is provided together with the semiconductor element 20. Figures 6A-6E can be generally the same as Figures 2A-2E. Unless otherwise stated, the components in Figures 6A-6E can be similar or the same as similar components in other figures disclosed herein.

[0042] In one aspect, a bonding method is disclosed. The bonding method can include preparing a first element having a device portion and a first non-conductive bonding material disposed on the device portion. The bonding method can include preparing a second element including a carrier. The second element has a substrate and a second non-conductive bonding material disposed on the substrate. The bonding method can include depositing a release layer between the device portion of the first element and the first non-conductive bonding material or between the substrate of the second element and the second non-conductive bonding material. The bonding method can include directly bonding the first non-conductive bonding material of the first element to the second non-conductive bonding material of the second element without an intervening adhesive. The bonding method can include detaching the second element from the first element by transferring thermal energy to the release layer, thereby inducing diffusion of a gas containing a volatile chemical species from the release layer.

[0043] In one embodiment, the volatile species comprises hydrogen.

[0044] In one embodiment, the volatile species comprises a halogen.

[0045] In one embodiment, the volatile species include hydrogen and fluorine.

[0046] In one embodiment, the release layer is deposited by plasma enhanced vapor deposition (PECVD).

[0047] In one embodiment, the release layer has a thickness in the range between 10 nm and 3 μm.

[0048] In one embodiment, the release layer comprises carbon. The release layer can comprise amorphous carbon. The amorphous carbon can comprise hydrogen. The amorphous carbon can comprise fluorine.

[0049] In one embodiment, the step of transferring thermal energy includes heating the directly joined second element and the first element.

[0050] In one embodiment, the step of transferring thermal energy includes irradiating the release layer through a substrate of the second element. The irradiating step can include laser rastering. The substrate can be transparent to the laser light used in the laser rastering.

[0051] In one embodiment, the step of transferring thermal energy includes rapid thermal annealing, thermal annealing, or microwave heating.

[0052] In one embodiment, the step of transferring thermal energy causes the release layer to outgas a volatile species, thereby weakening the bond between the first element and the second element and enabling removal of the second element from the first element. The volatile species can include hydrogen. The volatile species can include halogen. The volatile species can include hydrogen and fluorine.

[0053] In one embodiment, the direct bonding step includes contacting a first element and a second element and heating the contacted first element and second element at a first temperature that is lower than a second temperature used to heat and detach the directly bonded second element and first element. The second temperature can be in the range of 100°C to 400°C. The second temperature can be in the range of 200°C to 250°C.

[0054] In one embodiment, the bonding method further includes activating at least one of a surface of the first non-conductive bonding material and a surface of the second non-conductive bonding material prior to the direct bonding step.

[0055] In one embodiment, the first non-conductive bonding material comprises an inorganic dielectric material.

[0056] In one embodiment, the second non-conductive bonding material comprises an inorganic dielectric material.

[0057] In one embodiment, the step of depositing the release layer is performed on an intervening layer, such that the intervening layer is positioned between the substrate of the second element and the release layer. The intervening layer can be configured to perform an adhesive function between the release layer and the substrate.

[0058] In one embodiment, the bonding method further includes processing the first element after the direct bonding step. Processing the first element can include thinning a back surface of the first element. The back surface is opposite the first non-conductive bonding material. Processing the first element can include forming interconnects on the back surface of the first element. The bonding method can further include bonding a release tape to the thinned back surface of the first element. The detaching step can occur after bonding the release tape to the first element. The bonding method can further include directly bonding a second first element to the first element. The detaching step can occur after directly bonding the second first element to the first element.

[0059] In one embodiment, the bonding method further comprises, after the detaching step, ashing a surface of the first element that has been detached from the second element.

[0060] In one embodiment, the bonding method further comprises, after the detaching step, singulating the first element into a plurality of singulated first elements.

[0061] In one embodiment, the bonding method further comprises singulating the second element and the first element into a plurality of bonded structures prior to the detaching step.

[0062] In one embodiment, the step of depositing a release layer is performed on an intervening layer on the device portion of the first element, such that the intervening layer is positioned between the device portion of the first element and the release layer.

[0063] In one embodiment, the step of depositing a release layer is performed on the second element before forming the second non-conductive bonding material. The footprint of the release layer can be smaller than the footprint of the second non-conductive bonding material, and the ends of the release layer can be interleaved with the ends of the second non-conductive bonding material. The ends of the release layer can be covered with the second non-conductive bonding material. The bonding method can further include depositing a release layer between the device portion of the first element and the first non-conductive bonding material. The second release layer can be configured to outgas at a temperature higher than the temperature at which the release layer outgases.

[0064] In one embodiment, the bonding method further includes adjusting a deposition process for depositing the release layer to adjust the amount of volatile gas in the release layer. Adjusting the amount of volatile gas can include adjusting a fluorine-hydrogen ratio. Adjusting the amount of volatile gas can include adjusting a substrate bias or a flow rate of deposition precursors in a plasma enhanced chemical vapor deposition process.

[0065] In one embodiment, the bonding method further comprises providing a reflective layer between the release layer and the first element.

[0066] In one aspect, a bonding method is disclosed. The bonding method can include providing a first element having a device portion and a first non-conductive bonding material disposed on the device portion. The bonding method can include providing a second element having a substrate, an intervening layer disposed on the substrate, an amorphous carbon layer including a volatile gaseous species disposed on the intervening layer, and a second non-conductive bonding material disposed on the amorphous carbon layer. The bonding method can include directly bonding the first non-conductive bonding material of the first element to the second non-conductive bonding material of the second element without an intervening adhesive.

[0067] In one embodiment, the volatile gaseous species include fluorine and hydrogen.

[0068] In one embodiment, the method further includes detaching the second element from the first element by transferring thermal energy to the amorphous carbon layer to induce gas diffusion from the amorphous carbon layer.

[0069] In one embodiment, providing the second element includes depositing an amorphous carbon layer by plasma enhanced chemical vapor deposition (PECVD).

[0070] In one embodiment, the step of transferring thermal energy includes heating the directly joined second element and the first element.

[0071] In one embodiment, the step of transferring thermal energy includes irradiating the amorphous carbon layer through a substrate of the second element, The step of irradiating can include laser rastering, and the substrate is transparent to laser light used in the laser rastering.

[0072] In one embodiment, the step of transferring thermal energy includes rapid thermal annealing, thermal annealing, or microwave heating.

[0073] In one embodiment, the step of transferring thermal energy causes the amorphous carbon layer to outgas hydrogen and fluorine, thereby weakening the amorphous carbon layer and enabling detachment of the second element from the first element.

[0074] In one embodiment, the step of directly bonding includes contacting a first element and a second element and heating the contacted first element and second element at a first temperature that is lower than a second temperature used to heat and detach the directly bonded second element and first element.

[0075] In one embodiment, the bonding method further comprises activating at least one of a surface of the first non-conductive bonding material and a surface of the second non-conductive bonding material prior to the direct bonding step.

[0076] In one embodiment, the first non-conductive bonding material comprises a dielectric material.

[0077] In one embodiment, the second non-conductive bonding material comprises a dielectric material.

[0078] In one embodiment, the bonding method further comprises, after the direct bonding step, thinning a back surface of the first element, the back surface being opposite the non-conductive bonding material. The bonding method may further comprise bonding a release tape to the thinned back surface of the first element. The detaching step may occur after bonding the release tape to the first element. The bonding method may further comprise directly bonding a second first element to the first element. The detaching step may occur after directly bonding the second first element to the first element.

[0079] In one embodiment, the bonding method further comprises, after the detaching step, ashing a surface of the first element that has been detached from the second element.

[0080] In one embodiment, the bonding method further comprises, after the detaching step, singulating the first element into a plurality of singulated first elements.

[0081] In one embodiment, the bonding method further comprises singulating the second element and the first element into a plurality of bonded structures prior to the detaching step.

[0082] In one embodiment, the amorphous carbon layer has a footprint smaller than the footprint of the second non-conductive bonding material.

[0083] In one embodiment, the bonding method further comprises depositing an amorphous carbon layer between the device portion and the first non-conductive bonding material. The amorphous carbon layer can be disposed between the substrate and the second non-conductive bonding material.

[0084] In one embodiment, the bonding method further includes adjusting the amount of volatile gas in the amorphous carbon layer by adjusting deposition conditions of the amorphous carbon layer. Adjusting the amount of volatile gas can include adjusting a fluorine-hydrogen ratio.

[0085] In one embodiment, the bonding method further comprises providing a reflective layer between the amorphous carbon layer and the first element.

[0086] In one aspect, a carrier is disclosed that can include a substrate, an intervening layer on the substrate, a deposited carbon layer configured to release a gas when heated, and a non-conductive bonding layer on the deposited carbon layer, the non-conductive bonding layer configured to be directly bonded to a semiconductor device.

[0087] In one embodiment, the deposited carbon layer comprises amorphous carbon. The amorphous carbon may comprise fluorine and hydrogen. The deposited carbon layer may have a thickness uniformity within 3%. The fluorine and hydrogen may comprise between 10 wt% and 85 wt% of the deposited carbon layer.

[0088] In one embodiment, the non-conductive bonding layer is prepared for direct bonding. The surface of the non-conductive bonding layer can have a root mean square (rms) surface roughness of less than 2 nm and is configured for direct bonding.

[0089] In one aspect, a semiconductor device is disclosed. The semiconductor device can include a device portion, an intervening layer on the device portion, a deposited release layer configured to outgas hydrogen and fluorine when heated, and a non-conductive bonding layer on the deposited release layer. The non-conductive bonding layer is configured to be bonded directly to the device.

[0090] In one embodiment, the deposited release layer is an amorphous carbon layer containing hydrogen and fluorine. The fluorine and hydrogen can comprise between 10 wt % and 85 wt % of the deposited carbon layer.

[0091] In one embodiment, the deposited release layer has a thickness uniformity within 3%.

[0092] In one embodiment, the non-conductive bonding layer is prepared for direct bonding. The surface of the non-conductive bonding layer has a root mean square (rms) surface roughness of less than 2 nm.

[0093] In one aspect, a temporary bonding method is disclosed. The bonding method can include preparing a first element having a device portion and a first non-conductive bonding material disposed on the device portion. The bonding method can include preparing a second element having a substrate and a second non-conductive bonding material disposed on the substrate. The bonding method can include depositing a release layer by plasma enhanced chemical vapor deposition (PECVD) between the device portion and the first non-conductive bonding material of the first element or between the substrate and the second non-conductive bonding material of the second element. The bonding method can include directly bonding the first non-conductive bonding material of the first element to the second non-conductive bonding material of the second element without an intervening adhesive.

[0094] In one embodiment, the step of transferring thermal energy induces diffusion of hydrogen and fluorine.

[0095] In one embodiment, the bonding method further includes detaching the second element from the first element by transferring thermal energy to the release layer, thereby inducing gas diffusion from the release layer. The release layer can include an amorphous carbon layer containing hydrogen and fluorine. The detaching can include outgassing the hydrogen and fluorine.

[0096] In one aspect, a bonding method is disclosed. The bonding method can include providing a first element having a device portion and a first non-conductive material disposed on the device portion. The bonding method can include providing a second element having a substrate and a second non-conductive material disposed on the substrate. The bonding method can include depositing a release layer by plasma enhanced chemical vapor deposition (PECVD) on the first non-conductive material of the first element or the second non-conductive material of the second element. The bonding method can include providing a third non-conductive material on the release layer and directly bonding the first non-conductive material or the second non-conductive material to the third non-conductive material without an intervening adhesive.

[0097] In one embodiment, the bonding method further comprises detaching the second element from the first element by transferring thermal energy to the release layer, thereby inducing gas diffusion from the release layer.

[0098] In one embodiment, the first, second and third non-conductive materials comprise inorganic dielectric materials.

[0099] In one embodiment, the release layer comprises an amorphous carbon layer comprising hydrogen and fluorine capable of releasing a gas in response to heating.

[0100] Unless the context clearly indicates otherwise, the words "comprises," "comprising," "including," "including," and the like throughout this specification and claims are to be construed in an inclusive sense, i.e., "including but not limited to," as opposed to a restrictive or inclusive sense. As used generally herein, the word "coupled" refers to two or more elements that are either directly connected or connected through one or more intermediate elements. Similarly, as used generally herein, the word "connected" refers to two or more elements that are either directly connected or connected through one or more intermediate elements. In addition, the words "herein," "above," "below," and words of similar import, when used in this application, refer to this application as a whole and not to any particular portion of this application. Furthermore, as used herein, when a first element is described as being "on" or "over" a second element, the first element can be directly on or over the second element, such that the first and second elements are in direct contact, or the first element can be indirectly on or over the second element, such that there are one or more intervening elements between the first and second elements. Where the context permits, words using the singular or plural in the above detailed description can also include the plural or singular, respectively. The word "or" in connection with a list of two or more items covers all of the following interpretations for that word: any of the items in the list, all of the items in the list, and any and all combinations of the items in the list.

[0101] Additionally, conditional language used herein, such as, among others, "may," "could," "could be," "may," "for example," "for example," and "such as," is generally intended to convey that certain embodiments include particular features, elements, and / or conditions, while other embodiments do not, unless specifically stated otherwise or understood otherwise within the context in which it is used. Thus, such conditional language is generally not intended to imply that a feature, element, and / or condition is in any way required for one or more embodiments.

[0102] Although certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in different other forms, and various omissions, substitutions, and modifications may be made to the forms of the methods and systems described herein without departing from the spirit of the present disclosure. For example, although blocks are presented in a given arrangement, alternative embodiments may perform similar functions using different components and / or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of the elements and operations of the various embodiments described above may provide further embodiments. The claims and their equivalents are intended to cover such forms or modifications as fall within the scope and spirit of the present disclosure. [Explanation of symbols]

[0103] 12 Substrate 18 Bonding layer 22 Device part 24 Bonding layer 26 Joint interface

Claims

1. A joining method comprising: providing a first element having a device portion and a first non-conductive bonding material disposed on the device portion; providing a second element comprising a carrier, the second element having a substrate and a second non-conductive bonding material disposed on the substrate; depositing a release layer between the device portion of the first element and the first non-conductive bonding material or between the substrate of the second element and the second non-conductive bonding material; directly bonding the first non-conductive bonding material of the first element to the second non-conductive bonding material of the second element without an intervening adhesive; detaching the second element from the first element by transferring thermal energy to the release layer, thereby inducing diffusion of a gas containing a volatile species from the release layer; and A bonding method comprising:

2. The bonding method of claim 1 , wherein the volatile species comprises hydrogen, a halogen, or fluorine.

3. The bonding method of claim 1 , wherein the release layer is deposited by plasma-enhanced chemical vapor deposition (PECVD).

4. The bonding method of claim 1 , wherein the release layer has a thickness in the range between 10 nm and 3 μm, and the release layer comprises carbon or amorphous carbon.

5. 2. The bonding method of claim 1, wherein the transferring of thermal energy includes irradiating the release layer through the substrate of the second element, the irradiating including laser raster processing, and the substrate is transparent to laser light used in the laser raster processing.

6. 2. The bonding method of claim 1, wherein the direct bonding comprises contacting the first element and the second element and heating the contacted first element and second element at a first temperature that is lower than a second temperature used to heat and detach the directly bonded second element and first element, and the second temperature is in a range of 100°C to 400°C.

7. 2. The bonding method of claim 1, wherein depositing the release layer is performed on an intervening layer, the intervening layer being arranged between the substrate of the second element and the release layer, and the intervening layer being configured to perform an adhesive function between the release layer and the substrate.

8. 2. The bonding method of claim 1, further comprising processing the first element after the direct bonding, wherein processing the first element comprises thinning a back surface of the first element, the back surface being opposite the first non-conductive bonding material.

9. 2. The bonding method of claim 1, wherein depositing the release layer is performed on an intervening layer on the device portion of the first element, such that the intervening layer is disposed between the device portion of the first element and the release layer.

10. The bonding method of claim 1 , wherein depositing the release layer is performed on the second element before forming the second non-conductive bonding material.

11. 11. The bonding method according to claim 10, wherein an area occupied by the release layer is smaller than an area occupied by the second non-conductive bonding material, and an end of the release layer is inserted into an end of the second non-conductive bonding material.

12. 10. The bonding method of claim 1, further comprising adjusting a deposition process for depositing the release layer to adjust an amount of volatile gas in the release layer, wherein adjusting the amount of volatile gas comprises adjusting a fluorine-hydrogen ratio, and wherein adjusting the amount of volatile gas comprises adjusting a substrate bias or a deposition precursor flow rate of a plasma-enhanced chemical vapor deposition process.

13. The bonding method of claim 1 further comprising providing a reflective layer between the release layer and the first element.

14. 10. The bonding method of claim 1, further comprising directly bonding the first element to a third element, such that non-conductive field regions of the first element are directly bonded to non-conductive field regions of the third element and conductive features of the first element are directly bonded to conductive features of the third element.

15. A joining method comprising: providing a first element having a device portion and a first non-conductive bonding material disposed on the device portion; providing a second element having a substrate, an intervening layer disposed on the substrate, an amorphous carbon layer containing volatile gaseous species disposed on the intervening layer, and a second non-conductive bonding material disposed on the amorphous carbon layer; directly bonding the first non-conductive bonding material of the first element to the second non-conductive bonding material of the second element without an intervening adhesive; A bonding method comprising:

16. The bonding method of claim 15 , wherein the volatile gaseous species include fluorine and hydrogen.

17. 16. The bonding method of claim 15, wherein preparing the second element comprises depositing the amorphous carbon layer by plasma-enhanced chemical vapor deposition (PECVD).

18. 16. The bonding method of claim 15, further comprising detaching the second element from the first element by transferring thermal energy to the amorphous carbon layer to induce gas diffusion from the amorphous carbon layer.

19. 20. The method of claim 18, wherein the transferring of thermal energy comprises heating the directly bonded second element and first element.

20. 20. The bonding method of claim 18, wherein the transferring of thermal energy includes irradiating the amorphous carbon layer through the substrate of the second element.

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