Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing resistance variations of a field plate.SOLUTION: A semiconductor device includes: a semiconductor substrate; a semiconductor layer located on the semiconductor substrate and including a drain region, a source region, a drift region, and a channel region; an insulating film located on the semiconductor layer; a field plate located on the insulating film, overlapping the drift region, and electrically connected to the drain region; and a trench filled in a groove provided in the semiconductor layer. The field plate includes an active region located between the drain region and the source region, and a termination region located outside the active region in a plan view. The insulating film is defined into a first region in which the active region is provided and a second region in which the termination region is provided. The groove and the trench are located at a portion of the semiconductor layer overlapping the second region.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor layer, a first electrode, a second electrode, a lateral element, and a LOCOS oxide resistive field plate. The first electrode is formed on the surface of the semiconductor layer. The second electrode is formed on the surface of the semiconductor layer at a distance from the first electrode. The lateral element is formed in a region between the first electrode and the second electrode in a surface layer portion of the surface of the semiconductor layer, and is electrically connected to the first electrode and the second electrode. The LOCOS oxide separates each part constituting the lateral element on the surface of the semiconductor layer. The resistive field plate is formed on the LOCOS oxide. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2013 / 0075877

[0004] [overview] An object according to one aspect of the present disclosure is to provide a semiconductor device that can be miniaturized while ensuring a withstand voltage.

[0005] A semiconductor device according to one aspect of the present disclosure includes a semiconductor substrate, a semiconductor layer located on the semiconductor substrate and having a drain region, a source region, a drift region, and a channel region, an insulating film located on the semiconductor layer, a field plate located on the insulating film, overlapping the drift region, and electrically connected to the drain region, and a trench filled in a groove provided in the semiconductor layer, the field plate has an operating region located between the drain region and the source region, and a termination region located outside the operating region in a plan view, the insulating film defines a first region in which the operating region is provided, and a second region in which the termination region is provided, and the groove and the trench are located in a portion of the semiconductor layer that overlaps the second region. This semiconductor device can be miniaturized while ensuring a breakdown voltage. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view showing a chip of a semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is an enlarged view of region II shown in FIG. [Diagram 3] FIG. 3 is a perspective cross-sectional view of a region III shown in FIG. [Figure 4] FIG. 4 is a cross-sectional view of region III shown in FIG. [Diagram 5] FIG. 5 is a cross-sectional view taken along line VV in FIG. [Figure 6] FIG. 6 is an enlarged view showing the area below the insulating film in region II shown in FIG. [Figure 7] FIG. 7 is an enlarged cross-sectional view of a main part of a semiconductor device according to a first modified example of the embodiment. [Figure 8] FIG. 8 is an enlarged cross-sectional view of a main part of a semiconductor device according to a second modification of the embodiment. [Figure 9A] FIG. 9A is a schematic cross-sectional view for illustrating a part of a method for manufacturing a semiconductor device in the second modification. [Figure 9B] FIG. 9B is a schematic cross-sectional view for illustrating a part of the method for manufacturing the semiconductor device in the second modification. [Figure 9C] FIG. 9C is a schematic cross-sectional view for illustrating a part of the method for manufacturing the semiconductor device in the second modification. [Figure 9D] FIG. 9D is a schematic cross-sectional view for illustrating a part of the method for manufacturing the semiconductor device in the second modification. [Figure 9E] FIG. 9E is a schematic cross-sectional view for illustrating a part of the method for manufacturing the semiconductor device in the second modification. [Figure 9F] FIG. 9F is a schematic cross-sectional view for illustrating a part of the method for manufacturing the semiconductor device in the second modification. [Figure 9G] FIG. 9G is a schematic cross-sectional view for illustrating a part of the method for manufacturing the semiconductor device in the second modification. [Figure 10] FIG. 10 is an enlarged cross-sectional view of a main part of a semiconductor device according to a third modification of the embodiment. [Figure 11A] FIG. 11A is a schematic cross-sectional view for illustrating a part of a method for manufacturing a semiconductor device in the third modification. [Figure 11B] FIG. 11B is a schematic cross-sectional view for illustrating a part of the method for manufacturing the semiconductor device in the third modification. [Figure 11C] FIG. 11C is a schematic cross-sectional view for illustrating a part of the method for manufacturing the semiconductor device in the third modification. [Figure 11D] FIG. 11D is a schematic cross-sectional view for illustrating a part of the method for manufacturing the semiconductor device in the third modification. [Figure 11E] FIG. 11E is a schematic cross-sectional view for illustrating a part of the method for manufacturing the semiconductor device in the third modification.

[0007] [Detailed Description] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, the same elements or elements having the same functions will be designated by the same reference numerals, and duplicated descriptions will be omitted. In this specification, the term "same" and similar words are not limited to "completely same". In addition, since the drawings are intended to conceptually explain the embodiments, the dimensions and ratios of each component shown may differ from the actual ones.

[0008] FIG. 1 is a plan view showing a chip of a semiconductor device according to this embodiment. FIG. 2 is an enlarged view of region II shown in FIG. 1. FIG. 3 is a partially cutaway perspective cross-sectional view of region III shown in FIG. 2. FIG. 4 is a cross-sectional view of region III shown in FIG. 2. As shown in FIG. 1, semiconductor device 1A includes a silicon chip 2 (semiconductor chip) having a rectangular parallelepiped shape. Chip 2 is one of multiple devices formed on a silicon wafer having a diameter of, for example, 300 mm (about 12 inches).

[0009] The chip 2 has a pair of main surfaces, a first main surface 3 and a second main surface 4, and a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D that connect the first main surface 3 and the second main surface 4. In the following, the extension direction of the first side surface 5A and the second side surface 5B in a plan view is defined as a first direction X, the extension direction of the third side surface 5C and the fourth side surface 5D in a plan view is defined as a second direction Y, and the normal direction of the first main surface 3 and the second main surface 4 is defined as a third direction Z. The second direction Y is a direction that intersects with the first direction X in a plan view, and the third direction Z corresponds to the thickness direction of the chip 2.

[0010] The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed from the third direction Z, but are not limited to this. In this embodiment, the first main surface 3 is the top surface, and the second main surface 4 is the bottom surface. For this reason, a configuration located near the first main surface 3 in the third direction Z corresponds to a configuration located on the top surface side (upper side) of the semiconductor device 1A, and a configuration located near the second main surface 4 in the third direction Z corresponds to a configuration located on the bottom surface side (lower side) of the semiconductor device 1A.

[0011] The semiconductor device 1A includes a first semiconductor region 6 located in an upper region in the chip 2. The first semiconductor region 6 is a region having a first conductivity type and has a layer shape extending along the first main surface 3. For this reason, the first semiconductor region 6 is sometimes also called a semiconductor layer. The first semiconductor region 6 is at least a part of an epitaxial semiconductor layer. The first semiconductor region 6 is exposed from the first main surface 3 and the first side surface 5A, the second side surface 5B, the third side surface 5C, and the fourth side surface 5D. The thickness of the first semiconductor region 6 is, for example, 5 μm or more and 20 μm or less. In this embodiment, the first conductivity type is n-type.

[0012] The semiconductor device 1A includes a second semiconductor region 7 located in a lower region within the chip 2. The second semiconductor region 7 is a region having a second conductivity type and fixed to a predetermined potential, and has a layer shape extending along the second main surface 4. The second semiconductor region 7 is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the second semiconductor region 7 is fixed to a back gate potential. The back gate potential may be a reference potential that serves as a reference for circuit operation, or may be a ground potential. In this embodiment, the second conductivity type is p-type.

[0013] The second semiconductor region 7 is connected to the first semiconductor region 6. The thickness of the second semiconductor region 7 may be 50 μm or more and 400 μm or less. The second semiconductor region 7 is at least a part of a p-type semiconductor substrate. That is, the chip 2 has the first semiconductor region 6 included in an epitaxial semiconductor layer, and the second semiconductor region 7 included in a semiconductor substrate. In other words, the chip 2 has a layered structure including a semiconductor substrate and an epitaxial semiconductor layer located on the semiconductor substrate.

[0014] The semiconductor device 1A includes a plurality of device regions 8 defined on the first main surface 3. In the semiconductor device 1A, the number and arrangement of the plurality of device regions 8 are determined appropriately. Each of the plurality of device regions 8 includes a functional device formed by utilizing regions inside and outside the chip 2. The functional device includes, for example, at least one of a semiconductor switching device, a semiconductor rectifying device, and a passive device. The functional device may include a circuit network in which at least two of the semiconductor switching device, the semiconductor rectifying device, and the passive device are combined.

[0015] The semiconductor switching device may include at least one of a metal insulator semiconductor field effect transistor (MISFET), a bipolar junction transistor (BJT), an insulated gate bipolar junction transistor (IGBT), and a JFET. The semiconductor rectifying device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The passive device may include at least one of a resistor, a capacitor, an inductor, and a fuse.

[0016] The multiple device regions 8 include at least one transistor region 9. The transistor region 9 includes a FET structure. In this embodiment, the FET structure has a so-called LDMISFET (Lateral Double Diffused MISFET) structure. The FET structure is, for example, a high-voltage device to which a drain voltage of 800 V or more can be applied in an off state. The structure of the transistor region 9 will be described below.

[0017] The transistor region 9 is a region partitioned by an isolation region (not shown), and includes an n-type impurity region 10 located in the first semiconductor region 6, a first potential region 11, a second potential region 12, and a drift region 13. In this embodiment, the impurity region 10 is a part of the portion of the first semiconductor region 6 partitioned by the isolation region. The n-type impurity concentration of the impurity region 10 is equal to the n-type impurity concentration of the first semiconductor region 6, for example. The impurity region 10 has an oval shape in a plan view, but is not limited to this. The impurity region 10 may have a circular shape, an elliptical shape, a polygonal shape (for example, a rectangular shape), or the like.

[0018] The first potential region 11 is a region to which a first potential is applied, and is located in the center of the impurity region 10. The second potential region 12 is a region to which a second potential different from the first potential is applied, and is spaced apart from the first potential region 11 in a cross-sectional view and located above the first semiconductor region 6. The second potential region 12 is located within the above-mentioned separation region in a plan view and surrounds the first potential region 11. For example, the first potential region 11 is a high potential region to which a high potential (first potential) is applied, and the second potential region 12 is a low potential region to which a low potential (second potential) less than the high potential is applied. The drift region 13 is located between the first potential region 11 and the second potential region 12 in the impurity region 10.

[0019] The first potential region 11 includes a well region 14 and a drain region 15. The well region 14 and the drain region 15 are each provided above the first semiconductor region 6. The well region 14 surrounds the drain region 15 in a plan view and is in contact with the drain region 15. Therefore, the potential of the well region 14 and the potential of the drain region 15 are fixed to an equal potential (drain potential). In a plan view, the drain region 15 is spaced apart from the periphery of the well region 14. In other words, in a plan view, the drain region 15 is located inside the periphery of the well region 14. The drain region 15 constitutes a part of the first main surface 3. The n-type impurity concentration of the well region 14 is higher than the n-type impurity concentration of the impurity region 10. In addition, the n-type impurity concentration of the drain region 15 is higher than the n-type impurity concentration of the well region 14. The n-type impurity concentration of the well region 14 is, for example, 1.0×10 15 cm -3 Above 1.0×10 18 cm -3 The n-type impurity concentration of the drain region 15 is, for example, 1.0×10 18 cm -3 Above 1.0×10 21 cm -3 The following is the result.

[0020] In this embodiment, the well region 14 has an elliptical shape extending along the impurity region 10 in a planar view, but is not limited to this. The well region 14 may have a circular, elliptical, or polygonal shape (e.g., a rectangular shape) in a planar view. In this embodiment, the drain region 15 has an elliptical shape similar to the well region 14 in a planar view, but is not limited to this. The drain region 15 may have a circular, elliptical, or polygonal shape (e.g., a rectangular shape) in a planar view.

[0021] The second potential region 12 includes a p-type body region 16 located between the isolation region and the well region 14 in a plan view. The body region 16 extends, for example, along the periphery of the impurity region 10. Specifically, the body region 16 has an oval ring shape surrounding the impurity region 10 in a plan view. The body region 16 extends in the third direction Z from the first main surface 3 to the boundary between the first semiconductor region 6 and the second semiconductor region 7. For this reason, the body region 16 is electrically connected to the second semiconductor region 7 and is fixed to the potential of the second semiconductor region 7 (for example, the back gate potential). The body region 16 may be provided in both the first semiconductor region 6 and the second semiconductor region 7. The p-type impurity concentration of the body region 16 is, for example, 1.0×10 15 cm -3 Above 1.0×10 18 cm -3 The following is the result.

[0022] 2, in a plan view, the body region 16 is divided into a first region 16A, a second region 16B, a third region 16C, and a fourth region 16D. Each of the first region 16A and the second region 16B is a strip-shaped portion extending along the second direction Y in a plan view, and extends parallel to each other. In a plan view, the first region 16A and the second region 16B are provided such that the drain region 15 is located between the first region 16A and the second region 16B in the first direction X. In the second direction Y, each of the length of the first region 16A and the length of the second region 16B may be equal to or shorter than the length of the drain region 15.

[0023] The third region 16C is a band-shaped portion connecting one end of the first region 16A in the second direction Y and one end of the second region 16B in the second direction Y. In the present embodiment, the third region 16C extends in an arc-shaped band shape between one end of the first region 16A and one end of the second region 16B in a plan view, but is not limited to this. The third region 16C may extend along the first direction X.

[0024] The fourth region 16D is a band-shaped portion connecting the other end of the first region 16A in the second direction Y and the other end of the second region 16B in the second direction Y. In the present embodiment, the fourth region 16D extends in an arc band shape between the other end of the first region 16A and the other end of the second region 16B in a plan view, but is not limited to this. The fourth region 16D may extend along the first direction X.

[0025] The semiconductor device 1A includes a source region 17 provided in the body region 16. In this embodiment, the semiconductor device 1A includes a plurality of source regions 17, but is not limited thereto. Each of the plurality of source regions 17 is an n-type region and is fixed to a source potential. Specifically, a source potential is applied to each of the plurality of source regions 17 from outside the chip 2. In the impurity region 10, a p-type channel region 18 in the above FET structure is formed between the source region 17 and the drift region 13 in the first direction X. Therefore, a current path extending in the first direction X is formed in the drift region 13 between the source region 17 and the drift region 13 in the first direction X. The source potential corresponds to the second potential. The n-type impurity concentration of the source region 17 is higher than the n-type impurity concentration of the well region 14. The n-type impurity concentration of the source region 17 may be equal to the n-type impurity concentration of the drain region 15. The n-type impurity concentration of the source region 17 is, for example, 1.0×10 18 cm -3 Above 1.0×10 21 cm -3 The channel region 18 controls whether the current path between the drain region 15 and the source region 17 is conductive or non-conductive.

[0026] Each of the source regions 17 has a band shape in a plan view and is located inside the body region 16 relative to the outer periphery of the body region 16. Each of the source regions 17 constitutes a part of the first main surface 3, that is, a part of the surface layer of the body region 16. A part of the source regions 17 is located in the first region 16A. Each end of the part in the second direction Y is located inside the each end of the first region 16A in the second direction Y, but is not limited to this. The other part of the source regions 17 is located in the second region 16B. Each end of the part in the second direction Y is located inside the each end of the second region 16B in the second direction Y, but is not limited to this. None of the source regions 17 is located in the third region 16C or the fourth region 16D. In the second direction Y, the length of each source region 17 is, for example, equal to or less than the length of the drain region 15. For example, when one source region 17 is located in the body region 16, the source region 17 is located in at least one of the first region 16A and the second region 16B of the body region 16.

[0027] The second potential region 12 includes a contact region 19 provided in the body region 16. In this embodiment, the semiconductor device 1A includes a plurality of contact regions 19, but is not limited to this. Each of the plurality of contact regions 19 is a p-type region. The p-type impurity concentration of each contact region 19 may be higher than the p-type impurity concentration of the body region 16. For example, the p-type impurity concentration of the contact region 19 is, for example, 1.0×10 18 cm -3 Above 1.0×10 21 cm -3 The following is the result.

[0028] Each contact region 19 has a band shape in a plan view and is located in the body region 16 and on the inside of the outer periphery of the body region 16. Each contact region 19 is located closer to the outer periphery of the body region 16 than the source region 17. Each contact region 19 constitutes a part of the first main surface 3, that is, a part of the surface layer of the body region 16. Each contact region 19 is in contact with the outer periphery of the body region 16, but is not limited to this. A part of the multiple contact regions 19 is located in the first region 16A. Each end of the part in the second direction Y is located on the inside of each end of the first region 16A in the second direction Y, but is not limited to this. The other parts of the multiple contact regions 19 are located in the second region 16B. Each end of the other parts in the second direction Y is located on the inside of each end of the second region 16B in the second direction Y, but is not limited to this. In the present embodiment, none of the contact regions 19 is located in the third region 16C or the fourth region 16D, but this is not limited to the above. In the second direction Y, the length of each contact region 19 is, for example, equal to or less than the length of the drain region 15.

[0029] Each of the contact regions 19 is located between the corresponding source region 17 and the outer periphery of the body region 16 in a plan view. Each of the contact regions 19 is adjacent to the corresponding source region 17 in a plan view. Therefore, in the surface layer portion of the body region 16, the source region 17 fixed to the source potential and the contact region 19 fixed to a potential different from the source potential coexist.

[0030] The semiconductor device 1A includes an n-type drift region 13 located between the drain region 15 and the source region 17 and in a surface layer portion of the impurity region 10. The drift region 13 has, for example, an oval ring shape surrounding the drain region 15 in a plan view. In this embodiment, the drift region 13 has a first portion (straight portion) extending in the second direction Y so as to be parallel to the first region 16A and the second region 16B, and a second portion (arc portion) extending in an arc shape so as to be parallel to the third region 16C and the fourth region 16D. The drift region 13 forms a current path in a portion along the first region 16A and the second region 16B, but does not form a current path in a portion along the third region 16C and the fourth region 16D.

[0031] The width of drift region 13 is, for example, 50 μm or more and 200 μm or less. The width of drift region 13 corresponds to the distance between first potential region 11 and second potential region 12, and is, for example, approximately constant along the elliptical ring shape. The width of the arc portion of drift region 13 may increase from the straight portion toward the center of the arc. On the other hand, the width of the straight portion of drift region 13 may be approximately constant.

[0032] The semiconductor device 1A includes insulating films 22, 23 that selectively cover the first main surface 3 in the transistor region 9. Each of the insulating films 22, 23 includes silicon oxide. Each of the insulating films 22, 23 includes a LOCOS film (Local oxidation of silicon film) formed by selective oxidation of the first main surface 3, a buried oxide film (STI: Shallow Trench Isolation) that fills shallow trenches provided in the first main surface 3, and the like. The insulating films 22, 23 may have a single-layer structure or a multilayer structure.

[0033] The insulating film 22 is located on the first semiconductor region 6 and covers the region between the drain region 15 and the source region 17 on the first main surface 3. The insulating film 22 is located, for example, on the drift region 21 in the impurity region 10, has an oval ring shape surrounding the drain region 15 in a plan view, and includes an inner edge portion 22a and an outer edge portion 22b. In FIG. 2, the outer edge portion 22b is indicated by a dashed line. The inner edge portion 22a of the insulating film 22 is located outside the drain region 15. The outer edge portion 22b is located inside the inner edge of the body region 16 in a plan view. Note that the body region 16, the source region 17, the contact region 19, and a part of the drift region 13 are exposed from the insulating film 22. In the insulating film 22, a first region 22c (see FIGS. 3, 4, and FIG. 5 described later) in which an operating region OR of a field electrode 25 described later is provided, and a second region 22d (see FIG. 5 described later) in which a termination region TR of the field electrode 25 is provided are defined. Although not shown, in this embodiment, a pair of first regions 22c and a pair of second regions 22d are defined in the insulating film 22.

[0034] The insulating film 23 covers the region outside the transistor region 9. The thickness of the insulating film 23 may be equal to that of the insulating film 22, and the material of the insulating film 23 may be the same as that of the insulating film 22. The insulating film 23 covers the outer periphery of the body region 16.

[0035] As shown in FIG. 2 to FIG. 4, the semiconductor device 1A includes a field electrode 25 (field plate) located on the insulating film 22 in the transistor region 9. The field electrode 25 has a function of suppressing disturbance of the electric field in the first semiconductor region 6 and the like, a function of suppressing local electric field concentration, a function of monitoring a high-voltage drain-gate voltage Vdg, and the like, and is a high-resistance film connected to the first potential region 11 and the second potential region 12. The field electrode 25 overlaps a portion located in the drift region 13 in the third direction Z. In this embodiment, the field electrode 25 does not overlap the channel region 18 in the third direction Z. The field electrode 25 includes, for example, polysilicon. The field electrode 25 is electrically connected to at least the drain region 15. In this embodiment, the field electrode 25 forms a potential gradient that gradually changes from the first potential region 11 toward the second potential region 12. By providing such a field electrode 25, bias in the electric field distribution in the drift region 13 is suppressed. The thickness of the field electrode 25 is, for example, 50 nm or more and 100 nm or less.

[0036] As shown in FIG. 2, the field electrode 25 has an operating region OR located between the drain region 15 and the source region 17, and a termination region TR located outside the operating region OR in a planar view. In this embodiment, the operating region OR of the field electrode 25 is located between a pair of termination regions TR in the second direction Y. Also, each termination region TR is located outside the operating region OR in the second direction Y. In other words, each termination region TR is located outside the operating region OR in a direction intersecting or perpendicular to the current path. Alternatively, one of the termination regions TR can be said to be located between the drain region 15 and the third region 16C of the body region 16 in a planar view, and the other of the termination regions TR can be said to be located between the drain region 15 and the fourth region 16D of the body region 16 in a planar view.

[0037] The operating region OR is a region including a portion of the field electrode 25 that overlaps with the current path. In a plan view, one end of the operating region OR in the second direction Y is located between one end 17a of the source region 17 and one end 15a of the drain region 15 in the second direction Y, but is not limited thereto. For example, as shown in FIG. 2, in a plan view, one end of the operating region OR in the second direction Y may be aligned with one end 17a of the source region 17 in the second direction Y, may be aligned with one end 15a of the drain region 15 in the second direction Y, or may be aligned with one end of a linear portion of the drain region 15 in the second direction Y. In addition, in a plan view, the other end of the operating region OR in the second direction Y is located between the other end 17b of the source region 17 and the other end 15b of the drain region 15 in the second direction Y, but is not limited thereto. For example, in a plan view, the other end of the operating region OR in the second direction Y may be aligned with the other end 17b of the source region 17 in the second direction Y, may be aligned with the other end 15b of the drain region 15 in the second direction Y, or may be aligned with the other end of the straight portion of the drain region 15 in the second direction Y. The one end of the operating region OR corresponds to the boundary between the operating region OR and one of the termination regions TR, and overlaps with the boundary between each of the first regions 22c of the insulating film 22 and one of the second regions 22d in the second direction Y. The other end of the operating region OR corresponds to the boundary between the operating region OR and the other termination region TR, and overlaps with the boundary between each of the first regions 22c of the insulating film 22 and the other of the second regions 22d in the second direction Y. Therefore, each of the one end and the other end of the operating region OR can be regarded as the boundary.

[0038] The operating region OR has a plurality of first line portions 25a. Each of the plurality of first line portions 25a is a portion extending linearly along the second direction Y and is spaced apart from one another in the first direction X. Each of the first line portions 25a overlaps a linear portion of the drift region 13 in the third direction Z via a corresponding first region 22c of the insulating film 22. Note that an end of the first line portion 25a in the second direction Y may overlap an arc portion of the drift region 13. In this case, the end may extend in an arc shape.

[0039] The entirety or most of each termination region TR is a region including a portion of the field electrode 25 that does not overlap the current path. Each termination region TR has a plurality of second line portions 25b. Each of the plurality of second line portions 25b is a portion extending in an arc shape in the first direction X and is spaced apart from each other in the second direction Y. Each of the second line portions 25b overlaps with an arc portion of the drift region 13 in the third direction Z via a corresponding second region 22d (see FIG. 5 described later) of the insulating film 22. Note that an end of the second line portion 25b in the first direction X may overlap with a straight portion of the drift region 13. In this case, the end may extend in a straight line. Each of the plurality of second line portions 25b is connected to a corresponding first line portion 25a. As a result, the field electrode 25 is routed in a line shape on the insulating film 22.

[0040] For example, the field electrode 25 concentrically surrounds the first potential region 11 including the drain region 15 multiple times in a plan view. In this embodiment, the field electrode 25 has a spiral shape surrounding the first potential region 11 in a plan view.

[0041] The field electrode 25 has a first end 26 located near the drain region 15, a second end 27 located near the body region 16, and a spiral portion 28 extending between the first end 26 and the second end 27. The location of the first end 26 and the second end 27 is arbitrary.

[0042] The first end 26 is a connection portion electrically connected to the drain region 15, and is the portion (innermost periphery) located on the innermost side of the field electrode 25. The first end 26 corresponds to the first line portion 25a located on the innermost side of the multiple first line portions 25a in a plan view, for example. The potential applied to the first end 26 is the first potential or a potential in the vicinity thereof. The first end 26 may overlap the well region 14 in the third direction Z.

[0043] The second end 27 is the portion (outermost periphery) located on the outermost side of the field electrode 25. The first end 26 corresponds to the first line portion 25a located on the outermost side of the plurality of first line portions 25a in a plan view, for example. The potential applied to the second end 27 is the second potential or a potential in the vicinity thereof. The second end 27 may overlap the drift region 13 in the third direction Z. The spiral portion 28 is a portion (connection portion) that connects the first end 26 and the second end 27, and is wound in an elliptical spiral shape from the first end 26 to the second end 27 so as to surround the drain region 15 in a plan view. The spiral portion 28 overlaps the drift region 13 in the third direction Z. A part of the spiral portion 28 may overlap the well region 14.

[0044] Field electrode 25 forms a potential gradient in the spiral direction from first end 26 to second end 27. Field electrode 25 also forms a potential gradient in a direction perpendicular to the spiral direction that gradually decreases according to the winding pitch of spiral portion 28 from first potential region 11 to second potential region 12. Field electrode 25 thins out the electric field in drift region 13, suppressing bias in the electric field distribution in drift region 13.

[0045] The field electrode 25 may have a line width of 0.5 μm or more and 5 μm or less. The line width is defined by the width in a direction perpendicular to the extension direction (i.e., the spiral direction) of the field electrode 25. The field electrode 25 may have a resistance value of 10 MΩ or more and 100 MΩ or less. The line width of the first line portion 25a and the line width of the second line portion 25b may each be approximately constant. When the width of the drift region 13 gradually increases toward the center of the arc, the line width of the second line portion 25b may gradually increase toward the center of the arc.

[0046] The pitch of the field electrode 25 may be 1 μm or more and 10 μm or less. The pitch of the field electrode 25 is defined by the distance between adjacent line portions (i.e., the winding pitch of the spiral portion 28). The number of turns of the field electrode 25 is, for example, 5 to 100. The number of turns may be 75 or less, or 50 or less.

[0047] The semiconductor device 1A includes an inner field electrode 29 located on the insulating film 22 and connected to the field electrode 25. The inner field electrode 29 is located closer to the drain region 15 than the field electrode 25 in a plan view. In this embodiment, the inner field electrode 29 is located in a region surrounded by the field electrode 25 in a plan view. The potential of the inner field electrode 29 is fixed to a first potential. The inner field electrode 29 may be a part of the field electrode 25. In this case, the inner field electrode 29 functions as the innermost part of the field electrode 25. The inner field electrode 29 includes the same material as the field electrode 25, such as conductive polysilicon described later.

[0048] The inner field electrode 29 is disposed at a position spaced apart from the drain region 15 in a plan view. In this embodiment, the inner field electrode 29 has an oval ring shape surrounding the drain region 15. The inner field electrode 29 may overlap the well region 14 in the third direction Z. The inner field electrode 29 includes an inner edge portion 29a and an outer edge portion 29b. The inner edge portion 29a is provided, for example, at a position spaced apart from the drain region 15 in a plan view. The outer edge portion 29b is provided, for example, at a position spaced apart from the spiral portion 28 of the field electrode 25. The distance between the inner field electrode 29 and the spiral portion 28 is, for example, equal to the pitch of the field electrode 25.

[0049] In this embodiment, the width of the innerfield electrode 29 is non-uniform along the circumferential direction. The innerfield electrode 29 has a protruding portion 30 at the outer edge portion 29b. The protruding portion 30 protrudes toward the field electrode 25 so as to contact the first end 26 of the field electrode 25. From the viewpoint of suppressing the bias of the electric field caused by the first end 26 of the field electrode 25, the protruding portion 30 keeps the distance between the innerfield electrode 29 and the field electrode 25 approximately constant. The protruding portion 30 is connected to the first end 26, but is not limited thereto. In other words, the innerfield electrode 29 does not need to be connected to the first end 26 as long as it is fixed to the same potential as the first end 26. Therefore, the protruding portion 30 may face the tip of the first end 26 in the above-mentioned spiral direction. The presence or absence of the innerfield electrode 29 is optional. Therefore, the innerfield electrode 29 may not be provided as necessary.

[0050] The width of the inner field electrode 29 is, for example, 1 μm or more and 15 μm or less. The inner field electrode 29 may be formed wider than the field electrode 25. In this case, the width of the inner field electrode 29 is, for example, 1.5 times or more and 5 times or less the width of the field electrode 25. The width of the inner field electrode 29 may be equal to or less than the line width of the field electrode 25.

[0051] The semiconductor device 1A includes a gate insulating film 31 that is in contact with the first semiconductor region 6 and located on the channel region 18. A portion of the gate insulating film 31 overlaps the insulating film 22. The thickness of the gate insulating film 31 is less than the thickness of the insulating film 22, and is, for example, 10 nm or more and 200 nm or less. The gate insulating film 31 has a single-layer structure or a multilayer structure, and includes, for example, a silicon oxide film. In this embodiment, the gate insulating film 31 has an oval ring shape surrounding the insulating film 22 in a plan view. The gate insulating film 31 covers a portion of the drift region 13 and a portion of the body region 16.

[0052] The semiconductor device 1A includes a gate electrode 32 located on a gate insulating film 31. The gate electrode 32 includes, for example, a metal film, an alloy film, conductive polysilicon, etc. When the gate electrode 32 includes conductive polysilicon, the conductive polysilicon includes at least one of an n-type region and a p-type region. The gate electrode 32 overlaps not only the channel region 18 but also the drift region 13 in the third direction Z. The gate electrode 32 has an oval ring shape extending along the channel region 18 in a plan view, but is not limited to this. The gate electrode 32 has an extraction portion 33 that is extracted from the gate insulating film 31 onto the insulating film 22. The extraction portion 33 has an oval ring shape surrounding a field electrode 25 described later in a plan view, and is located on the drift region 13. In addition, the entire gate electrode 32 is located outside the field electrode 25 in a plan view.

[0053] The gate electrode 32 includes an inner edge portion 32a and an outer edge portion 32b. The inner edge portion 32a is formed by an extension portion 33. The outer edge portion 32b is located in a region overlapping the body region 16 in a plan view. In this embodiment, the width of the gate electrode 32 is non-uniform along the circumferential direction, but is not limited to this. Specifically, as shown in FIG. 2, the gate electrode 32 has a gate extension portion 34 that extends toward the drain region 15 at the outer edge portion 32b (extension portion 33). The gate extension portion 34 is a portion that is provided according to the shape of the field electrode 25 described later. By providing the gate extension portion 34, the distance between the gate electrode 32 and the field electrode 25 is maintained approximately constant in a plan view.

[0054] The semiconductor device 1A includes an insulating layer 40 covering a plurality of device regions 8 on the first main surface 3. The insulating layer 40 has a laminated structure including a plurality of interlayer insulating films 41 stacked on top of each other. The number of stacked interlayer insulating films 41 is arbitrary and is not limited to a specific number. The insulating layer 40 may include three or more interlayer insulating films 41. In FIG. 3, a first interlayer insulating film 41A and a second interlayer insulating film 41B of the plurality of interlayer insulating films 41 are shown.

[0055] The first interlayer insulating film 41A and the second interlayer insulating film 41B are laminated in order in the third direction Z. The first interlayer insulating film 41A covers at least the first main surface 3, the insulating film 22, the gate insulating film 31, and the gate electrode 32. The second interlayer insulating film 41B covers the first interlayer insulating film 41A. The thickness of the first interlayer insulating film 41A and the thickness of the second interlayer insulating film 41B are determined according to, for example, the function required for the field electrode 25, the thickness of the insulating film 22, and the like. Each of the first interlayer insulating film 41A and the second interlayer insulating film 41B includes at least one of a silicon oxide film and a silicon nitride film. Therefore, each of the first interlayer insulating film 41A and the second interlayer insulating film 41B may have a single-layer structure or a laminated structure.

[0056] A plurality of wiring films 42 are provided in the insulating layer 40. In this embodiment, a plurality of interlayer insulating films 41 and a plurality of wiring films 42 are alternately stacked, and therefore a multilayer wiring structure is provided on the first semiconductor region 6. The number of stacked wiring films 42 is arbitrary and is not limited to a specific value. In FIG. 3, among the plurality of wiring films 42, a first wiring film 42A located on the first interlayer insulating film 41A and a second wiring film 42B located on the second interlayer insulating film 41B are shown. Each wiring film 42 includes, for example, at least one of an Al film, a Cu film, an AlSiCu alloy film, an AlSi alloy film, and an Alcu alloy film. Therefore, each of the first wiring film 42A and the second wiring film 42B may have a single-layer structure or a stacked structure.

[0057] A plurality of first vias 43 and a plurality of second vias 49 are provided in the insulating layer 40. Each of the plurality of first vias 43 is a conductive part that electrically connects conductive parts such as the first potential region 11, the second potential region 12, and the field electrode 25 located under the first interlayer insulating film 41A to the first wiring film 42A, and penetrates the first interlayer insulating film 41A. Each of the plurality of second vias 49 is a conductive part that electrically connects conductive parts such as the first wiring film 42A located under the second interlayer insulating film 41B to the second wiring film 42B, for example, and penetrates the second interlayer insulating film 41B. Each of the plurality of first vias 43 and the plurality of second vias 49 is, for example, a tungsten plug.

[0058] The first wiring film 42A includes, for example, a first drain wiring 44, a first source wiring 45, a first gate wiring 46, a field wiring 47, and a field wiring 48. The first drain wiring 44 is electrically connected to the drain region 15 through one or more first vias 43. The first source wiring 45 is electrically connected to the source region 17 through one or more first vias 43. The first gate wiring 46 is electrically connected to the gate electrode 32 through one or more first vias 43. The field wiring 47 is electrically connected to the first end 26 of the field electrode 25 through one or more first vias 43. The field wiring 47 is electrically connected to the inner field electrode 29 through, for example, one or more first vias 43. The field wiring 47 may be a part of the first drain wiring 44. The field wiring 48 is electrically connected to the second end 27 of the field electrode 25 through one or more first vias 43. The field wiring 48 may be a part of the first source wiring 45.

[0059] The second wiring films 42B include, for example, a second drain wiring 50, a second source wiring 51, and a second gate wiring (not shown). The second drain wiring 50 is electrically connected to the first drain wiring 44 and the field wiring 47 through a plurality of second vias 49. The second drain wiring 50 overlaps the drain region 15 and the field wiring 47. The second drain wiring 50 may overlap the entire drain region 15 and the entire field wiring 47. The second drain wiring 50 may overlap the inner field electrode 29. The second source wiring 51 is electrically connected to the first source wiring 45 and the field wiring 48 through a plurality of second vias 49. The second source wiring 51 has a ring shape extending along the body region 16 in a plan view. The second source wiring 51 may overlap the gate electrode 32 and the field wiring 48. The second source wiring 51 may overlap the entire body region 16, the entire gate electrode 32, and the entire field wiring 48.

[0060] Fig. 5 is a cross-sectional view taken along line VV in Fig. 2. Fig. 6 is an enlarged view showing the area below the insulating film in region II shown in Fig. 1. Unlike Fig. 2, field electrode 25 (see Fig. 2, etc.) is not shown in Fig. 6, but the operating region OR and termination region TR of field electrode 25 are shown for explanation.

[0061] As shown in FIG. 5 and FIG. 6, a groove G is provided in the first semiconductor region 6, and a trench T is filled in the groove G. The groove G and the trench T are portions that contribute to improving the breakdown voltage of the transistor region 9. The groove G is a recessed portion provided by patterning at least the first semiconductor region 6, and has an arc shape in a plan view. By having the groove G have an arc shape in a plan view in this manner, the trench T filled in the groove G also has an arc shape in a plan view. This makes it difficult for a corner to be formed in the trench T, so that the occurrence of electric field concentration at the corner can be suppressed. The groove G may be provided by patterning not only the first semiconductor region 6 but also the second semiconductor region 7. In this embodiment, the bottom of the groove G is defined by the second semiconductor region 7, but is not limited to this. For example, the bottom may be defined by the first semiconductor region 6. The depth of the groove G may be half or more of the thickness of the first semiconductor region 6.

[0062] As shown in FIG. 5, the groove G is provided in a portion of the first semiconductor region 6 that overlaps with the second region 22d of the insulating film 22 (hereinafter referred to as portion 6a). Therefore, the trench T is also provided in the portion 6a of the first semiconductor region 6. Here, the portion 6a corresponds to a portion located between the drain region 15 and the third region 16C of the body region 16, and a portion located between the drain region 15 and the fourth region 16D of the body region 16. That is, it can be said that the portion 6a has a portion along the third region 16C in the drift region 13, and a portion along the fourth region 16D in the drift region 13. Alternatively, it can be said that the portion 6a is a portion in the first semiconductor region 6 that does not form a current path, or a portion that does not substantially form a current path.

[0063] In this embodiment, a plurality of grooves G are provided in the portion 6a of the first semiconductor region 6, and a trench T is filled in each of the plurality of grooves G. This allows the potential applied to the portion 6a of the first semiconductor region 6 from the first potential region 11 to the second potential region 12 to be changed stepwise in combination with the field electrode 25. In order to suppress electric field concentration at a specific point in the portion 6a of the first semiconductor region 6, each of the plurality of grooves G is provided on a concentric circle. In a plan view, the plurality of grooves G have an arc shape centered on a specific point in the first potential region 11. The width of each groove G, the depth of each groove G, the number of grooves G, and the pitch between two adjacent grooves G are appropriately adjusted according to the shape of the transistor region 9, the characteristics required of the transistor region 9, and the like. For example, the depth of each of the plurality of grooves G is the same in FIG. 5, but is not limited thereto.

[0064] As shown in FIG. 6, some of the grooves G may be located in a portion of the first semiconductor region 6 that overlaps one of the termination regions TR. The other portions of the grooves G are located in a portion of the first semiconductor region 6 that overlaps the other of the termination regions TR. The positions of the ends of the grooves G in a planar view are located, for example, at the boundary between the first region 22c and the second region 22d of the insulating film 22. In other words, as shown in FIG. 6, the positions of the ends of the grooves G in a planar view are located at one end or the other end of the operating region OR in the second direction Y. In this embodiment, the ends of the grooves G that overlap one of the termination regions TR are aligned at one end of the operating region OR in the second direction Y, and the ends of the grooves G that overlap the other of the termination regions TR are aligned at the other end of the operating region OR in the second direction Y, but this is not limited to this. For example, the ends of some of the grooves G may be located within the operating region OR. In this case, the ends of some of the grooves G may have a strip shape that extends linearly along the second direction Y in a planar view. In other words, most of some of the grooves G may have an arc shape in a plan view.

[0065] 5, in the direction from the first potential region 11 to the second potential region 12, the multiple second line portions 25b and the multiple grooves G included in the field electrode 25 are alternately arranged in a plan view. Also, the second line portions 25b do not overlap with the grooves G in the third direction Z, but this is not limited thereto. At least a portion of the groove G (i.e., the trench T) may overlap with the second line portion 25b included in the field electrode 25. For example, the overlap rate of the groove G with the second line portion 25b may be 50% or less.

[0066] The trenches T are portions that are filled into the grooves G and are insulating with respect to the first semiconductor region 6. The trenches T are, for example, insulating oxides, nitrides, etc. The trenches T are filled into each groove G without gaps, so that electric field relaxation can occur in the portion 6a of the first semiconductor region 6. In this embodiment, the entire trenches T are insulating, but this is not limited thereto. The trenches T only need to be non-conductive with respect to at least the first semiconductor region 6. This can prevent leakage current and the like from occurring through the trenches T. The width, depth, and number of the trenches T, as well as the pitch between two adjacent trenches T, are appropriately adjusted in the same manner as the grooves G.

[0067] The grooves G and the trenches T are formed, for example, before the formation of the insulating film 22. For example, a plurality of grooves G are formed in the first semiconductor region 6 by anisotropic etching using a mask formed on the first semiconductor region 6. Then, the trenches T are formed to fill each groove G. The trenches T have, for example, a natural oxide film provided on the side surface of the grooves G and a deposited insulator provided on the natural oxide film.

[0068] According to the semiconductor device 1A of the present embodiment described above, the field electrode 25 has an operating region OR located between the drain region 15 and the source region 17, and a termination region TR located outside the operating region OR in a plan view. In addition, in the semiconductor device 1A, a trench T filled in the groove G is provided in the first semiconductor region 6, and the groove G and the trench T are located in a portion 6a of the first semiconductor region 6 that overlaps with the second region 22d of the insulating film 22. As a result, in a portion of the first semiconductor region 6 that does not form a current path, the field electrode 25 and the trench T relieve electric field concentration. As a result, even if the area of ​​the portion 6a in a plan view is reduced by shortening the distance between the drain region 15 and the third region 16C and the distance between the drain region 15 and the fourth region 16D, for example, the breakdown voltage of the semiconductor device 1A can be ensured. Therefore, according to this embodiment, it is possible to achieve miniaturization while ensuring the breakdown voltage.

[0069] In one example, the groove G and the trench T have an arc shape in a plan view. This makes it possible to effectively suppress electric field concentration at a specific point of the trench T.

[0070] In one example, at least a portion of the trench T may overlap the second line portion 25b included in the termination region TR in the field electrode 25. In this case, it becomes possible to achieve further miniaturization of the semiconductor device 1A.

[0071] In one example, a plurality of grooves G are provided in the portion 6a of the first semiconductor region 6, and each of the plurality of grooves G is filled with a trench T. This allows the potential in the portion 6a to change stepwise more satisfactorily. This makes it possible to realize both a compact semiconductor device 1A and a high breakdown voltage.

[0072] In one example, the multiple second line portions 25b of the field electrode 25 included in the termination region TR and the multiple grooves G may be provided alternately in a plan view.

[0073] In one example, the positions of the ends of the plurality of grooves G in a plan view may be located at the boundary between the first region 22c and the second region 22d of the insulating film 22.

[0074] In the following, modified examples of the above-described embodiment will be described. In the description of the modified examples, descriptions that overlap with the above-described embodiment will be omitted, and differences will be described. In other words, to the extent technically possible, the description of the above-described embodiment may be used appropriately in the modified examples.

[0075] 7 is an enlarged cross-sectional view of a main part of a semiconductor device according to a first modified example of the above embodiment. As shown in FIG. 7, in the semiconductor device 1B according to the first modified example, the pitch P1 between two adjacent grooves G becomes narrower as it approaches the drain region 15. In other words, the pitch P1 becomes wider as it approaches the source region 17. Therefore, the grooves G (i.e., trenches T) are formed more densely as it approaches the drain region 15, and the grooves G (i.e., trenches T) are formed more sparsely as it approaches the source region 17. For example, the maximum value of the pitch P1 is about three times the minimum value of the pitch P1.

[0076] The first modified example described above also provides the same effects as those of the above embodiment. The curvature of the trench T increases as it approaches the first potential region 11. Therefore, the closer the trench T is to the first potential region 11, the more likely electric field concentration is to occur. By applying the first modified example to this, the occurrence of electric field concentration in the vicinity of the first potential region 11 can be effectively suppressed.

[0077] 8 is an enlarged cross-sectional view of a main part of a semiconductor device according to a second modification of the embodiment. As shown in FIG. 8, in the semiconductor device 1C according to the second modification, the trench T1 has an insulating portion 61 that covers at least the side surface of the trench G, and a conductive portion 62 that is surrounded by the insulating portion 61 in a plan view. The insulating portion 61 is an insulating film deposited on the side surface of the trench G, a natural oxide film of the first semiconductor region 6 that forms the side surface of the trench G, or the like. When the insulating portion 61 is the natural oxide film, for example, the insulating portion 61 is formed by selectively etching the natural oxide film formed on the bottom of the trench G. From the viewpoint of preventing conduction between the first semiconductor region 6 and the conductive portion 62, the insulating portion 61 covers the entire side surface of the trench G.

[0078] The conductive portion 62 is a portion electrically connected to the second semiconductor region 7 at the bottom of the groove G. Therefore, the lower end of the conductive portion 62 is in contact with the second semiconductor region 7, and the potential of the conductive portion 62 is the same as the potential of the second semiconductor region 7. The conductive portion 62 includes, for example, conductive polysilicon. When the conductive portion 62 includes conductive polysilicon, the conductive polysilicon includes at least one of an n-type region and a p-type region. From the viewpoint of electric field relaxation in the surface layer of the first semiconductor region 6, the upper end of the conductive portion 62 may be in contact with the insulating film 22, but is not limited to this. For example, the upper end of the conductive portion 62 may be covered with the insulating portion 61. From the viewpoint of electric field relaxation by the conductive portion 62 and prevention of conduction between the conductive portion 62 and the first semiconductor region 6, the diameter of the conductive portion 62 is, for example, 20% to 40% of the diameter of the groove G.

[0079] Next, an example of a method for manufacturing the trench T1 in the second modified example will be described with reference to Figures 9A to 9G. Each of Figures 9A to 9G is a schematic cross-sectional view for explaining a part of the method for manufacturing the semiconductor device in the second modified example of the above embodiment.

[0080] First, as shown in FIG. 9A, a first layer 71, a second layer 72, and a third layer 73 are formed in this order on the first semiconductor region 6. The first layer 71 is a pad oxide film (silicon oxide film) located on the first semiconductor region 6. The first layer 71 may be included in a part of the insulating films 22, 23 later. The second layer 72 is an insulating film located on the first layer 71, and is, for example, a silicon nitride film formed by a CVD method or the like. The third layer 73 is an insulating film located on the second layer 72, and is, for example, a silicon oxide film made from TEOS (Si(OC2H5)4). The thicknesses of the first layer 71, the second layer 72, and the third layer 73 are adjusted as appropriate.

[0081] 9B, the first layer 71 to the third layer 73 are patterned to form an opening OP. For example, the opening OP is formed in the first layer 71 to the third layer 73 by anisotropic etching using a hard mask.

[0082] Next, as shown in FIG. 9C, the first semiconductor region 6 is patterned to form a groove G. For example, a portion of the first semiconductor region 6 overlapping with the opening OP is removed by anisotropic etching using the first layer 71 to the third layer 73. This forms the groove G in the first semiconductor region 6. In FIG. 9C, the bottom of the groove G coincides with the surface of the second semiconductor region 7, but this is not limited thereto. For example, in forming the groove G, not only the first semiconductor region 6 but also a part of the second semiconductor region 7 may be etched.

[0083] 9D, an insulating portion 61 is formed on the side surface of the groove G. For example, after the surface of the groove G is oxidized to form an oxide film, the insulating portion 61 is formed by selecting a part of the oxide film. The insulating portion 61 may be connected to the first layer 71. Note that, at the bottom of the groove G, wet etching is performed so that the second semiconductor region 7 is exposed.

[0084] 9E, a conductor C is formed to fill the groove G. The conductor C is, for example, polysilicon formed using a CVD method. The portion of the conductor C that fills the groove G is in contact with the second semiconductor region 7.

[0085] Next, as shown in FIG. 9F, a part of the conductor C is removed, and the second layer 72 and the third layer 73 are also removed. As a result, the conductive portion 62 buried in the groove G is formed, and the trench T1 including the insulating portion 61 and the conductive portion 62 is formed. The part of the conductor C and the third layer 73 are each removed by isotropic etching such as wet etching. The second layer 72 is removed from the first layer 71 by peeling, for example. Then, as shown in FIG. 9G, for example, an insulating film 22 is formed on the trench T1 by forming a LOCOS insulating film 74 covering the trench T1 and forming a further insulating film (not shown). In this manner, the trench T1 buried in the first semiconductor region 6 is manufactured.

[0086] The second modified example described above also provides the same advantageous effects as the above-described embodiment. Moreover, by forming the conductive portion 62 in contact with the second semiconductor region 7 in the trench T1, the potential of the conductive portion 62 becomes the same as the potential of the second semiconductor region 7. This makes it possible to effectively alleviate electric field concentration in the vicinity of the trench T1.

[0087] FIG. 10 is an enlarged cross-sectional view of a main part of a semiconductor device according to a third modified example of the embodiment. As shown in FIG. 10, in the semiconductor device 1D according to the third modified example, a plurality of trenches T2 are formed. The conductive portion 62A of the trenches T2 is exposed from the insulating film 22. Therefore, the side surface of the trench T2 is formed by the insulating portion 61 and a part of the insulating film 22. The conductive portion 62A included in at least a part of the plurality of trenches T2 is electrically connected to the field electrode 25A. Specifically, the conductive portion 62A is in contact with the corresponding second line portion 25b. As a result, the potential of at least a part of the conductive portion 62A is matched to the potential of the field electrode 25A.

[0088] Next, an example of a method for manufacturing the trench T2 and the field electrode 25A in the third modified example will be described with reference to Figures 11A to 11E. Each of Figures 11A to 11E is a schematic cross-sectional view for explaining a part of the method for manufacturing the semiconductor device in the third modified example of the present embodiment.

[0089] First, as shown in FIG. 11A, an insulating portion 61 is formed on the side surface of the groove G in the same manner as in the second modified example. In the third modified example, the laminate of the first layer 71, the second layer 72, and the third layer 73 functions as the insulating films 22, 23. Next, as shown in FIG. 11B, a conductor C is formed to fill the groove G. Next, as shown in FIG. 11C, a part of the conductor C is removed. In the third modified example, a part of the conductor C located on the third layer 73 is selectively removed by using, for example, CMP (Chemical Mechanical Polishing). This forms the conductive portion 62A while leaving the third layer 73. In the third modified example, the conductive portion 62A fills not only the groove G but also the opening OP. In addition, when performing CMP, the surface of the third layer 73 may be planarized together with the removal of the conductor C.

[0090] Next, as shown in FIG. 11D, a conductor C1 is formed on the third layer 73 and the conductive portion 62A. The conductor C1 is, for example, polysilicon using a CVD method. As a result, the conductive portion 62A and the conductor C1 come into contact with each other. Next, as shown in FIG. 11E, the conductor C1 is patterned to form a field electrode 25A. At this time, the contact state between the field electrode 25A and the conductive portion 62A is maintained. As a result, the electrical connection between the field electrode 25A and the conductive portion 62 is maintained.

[0091] The above-described third modified example also provides the same advantageous effects as those of the second modified example of the present embodiment.

[0092] Although the embodiment and the modified examples of the present disclosure have been described above, the present disclosure can be implemented in other forms. The above embodiment and each of the modified examples may be appropriately combined with each other. For example, the first modified example may be combined with the second modified example or the third modified example.

[0093] In the above embodiment and modified examples, the conductivity types of the various semiconductor regions may be inverted, that is, p-type parts may be made n-type and n-type parts may be made p-type.

[0094] In the above embodiment and the above modification, a MISFET is formed in the transistor region, but this is not limited to this. For example, a JFET having a field plate and a trench as shown in the above embodiment may be formed in the transistor region. Even in this case, the same effects as those of the above embodiment can be achieved.

[0095] In the above embodiment and the above modified example, the semiconductor device can be applied to a power module used in an inverter circuit that drives an electric motor used as a power source for, for example, automobiles (including electric automobiles), trains, industrial robots, air conditioners, air compressors, electric fans, vacuum cleaners, dryers, refrigerators, etc. The semiconductor device can also be applied to a power module used in an inverter circuit for solar cells, wind power generators, and other power generation devices, etc. Alternatively, the semiconductor device can be applied to a circuit module that constitutes an analog control power supply, a digital control power supply, etc.

[0096] Although the embodiments and variants relating to one aspect of the present disclosure have been described in detail above, these are merely specific examples used to clarify the technical content of the present disclosure, and the present disclosure should not be interpreted as being limited to these specific examples, and the scope of the present disclosure is limited only by the appended claims.

[0097] Below, examples of features extracted from the description of this specification and the drawings are presented.

[0098] [A1] A semiconductor substrate; a semiconductor layer located on the semiconductor substrate and having a drain region, a source region, a drift region and a channel region; an insulating film located on the semiconductor layer; a field plate located on the insulating film, overlapping the drift region, and electrically connected to the drain region; A trench filled in a groove provided in the semiconductor layer; Equipped with the field plate has an active region located between the drain region and the source region, and a termination region located outside the active region in a plan view; the insulating film is defined into a first region in which the operating region is provided and a second region in which the termination region is provided; the groove and the trench are located in a portion of the semiconductor layer that overlaps the second region; Semiconductor device.

[0099] [A2] The semiconductor device according to [A1], wherein the groove and the trench have an arc shape in a plan view.

[0100] [A3] The semiconductor device according to [A1] or [A2], wherein at least a portion of the trench overlaps a line portion of the field plate that is included in the termination region.

[0101] [A4] The semiconductor device according to any one of [A1] to [A3], wherein a bottom of the groove is defined by the semiconductor substrate.

[0102] [A5] a plurality of the grooves are provided in the portion of the semiconductor layer that overlaps with the second region, The semiconductor device according to any one of [A1] to [A4], wherein each of the plurality of grooves is filled with the trench.

[0103] [A6] The semiconductor device according to [A5], wherein the pitch of the multiple trenches is shorter as they are closer to the drain region.

[0104] [A7] The semiconductor device according to [A5], wherein a plurality of line portions of the field plate included in the termination region and a plurality of the grooves are alternately arranged in a planar view.

[0105] [A8] The semiconductor device according to any one of [A1] to [A7], wherein each end position of the plurality of grooves in a plan view is located at a boundary between the first region and the second region.

[0106] [A9] the trench has an insulating portion covering at least a side surface of the groove and a conductive portion surrounded by the insulating portion in a plan view, The semiconductor device according to any one of [A1] to [A8], wherein the conductive portion is electrically connected to the semiconductor substrate.

[0107] [A10] The semiconductor device according to [A9], wherein the conductive portion is electrically connected to the field plate.

[0108] [A11] The semiconductor device according to [A9] or [A10], wherein the conductive portion includes polysilicon. [Explanation of symbols]

[0109] Reference Signs List 1A to 1D... semiconductor device, 2... chip (semiconductor chip), 6... first semiconductor region (semiconductor layer), 6a... portion, 7... second semiconductor region (semiconductor substrate), 9... transistor region, 10... impurity region, 11... first potential region, 12... second potential region, 13... drift region, 15... drain region, 15a, 17a... one end, 15b, 17b... other end, 16... body region, 17... source region, 18... channel region, 19... contact region, 22, 23... insulating film, 22c... first region, 22d... second region, 25, 25A... field electrode (field plate), 25a... first line portion, 25b... second line portion (line portion), 26... first end, 27... second end, 28... spiral portion, 29... inner field electrode, 30... tension extension portion, 31...gate insulating film, 32...gate electrode, 32b...outer edge portion, 33...drawing portion, 34...gate extension portion, 40...insulating layer, 41...interlayer insulating film, 41A...first interlayer insulating film, 41B...second interlayer insulating film, 42...wiring film, 42A...first wiring film, 42B...second wiring film, 43...first via, 44...first drain wiring, 45...first source wiring, 46...first gate wiring, 47, 48...field wiring, 49...second via, 50...second drain wiring, 51...second source wiring, 61...insulating portion, 62, 62A...conductive portion, 71...first layer, 72...second layer, 73...third layer, 74...LOCOS insulating film, C, C1...conductor, G...groove, OP...opening, OR...operating region, P1...pitch, T, T1, T2...trench, TR...termination region.

Claims

1. A semiconductor substrate; a semiconductor layer located on the semiconductor substrate and having a drain region, a source region, a drift region and a channel region; an insulating film located on the semiconductor layer; a field plate located on the insulating film, overlapping the drift region, and electrically connected to the drain region; A trench that is filled in a groove provided in the semiconductor layer; Equipped with the field plate has an active region located between the drain region and the source region, and a termination region located outside the active region in a plan view; a first region in which the operating region is provided and a second region in which the termination region is provided are defined in the insulating film; the groove and the trench are located in a portion of the semiconductor layer that overlaps the second region; Semiconductor device.

2. The semiconductor device according to claim 1 , wherein the groove and the trench are arc-shaped in a plan view.

3. The semiconductor device according to claim 1 , wherein at least a portion of said trench overlaps a line portion of said field plate that is included in said termination region.

4. The semiconductor device according to claim 1 , wherein a bottom of the groove is defined by the semiconductor substrate.

5. a plurality of the grooves are provided in the portion of the semiconductor layer that overlaps with the second region, 3. The semiconductor device according to claim 1, wherein each of the plurality of grooves is filled with the trench.

6. The semiconductor device according to claim 5 , wherein a pitch between the plurality of trenches is shorter the closer to the drain region.

7. 6. The semiconductor device according to claim 5, wherein a plurality of line portions of said field plate and a plurality of said grooves included in said termination region are provided alternately in a plan view.

8. The semiconductor device according to claim 1 , wherein each end of the plurality of grooves is positioned at a boundary between the first region and the second region in a plan view.

9. the trench has an insulating portion covering at least a side surface of the groove and a conductive portion surrounded by the insulating portion in a plan view, The semiconductor device according to claim 1 , wherein the conductive portion is electrically connected to the semiconductor substrate.

10. The semiconductor device according to claim 9 , wherein the conductive portion is electrically connected to the field plate.

11. The semiconductor device according to claim 9 , wherein the conductive portion includes polysilicon.

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