Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device capable of suppressing diffusion of atoms between different layers in wiring, and a method of manufacturing the same.SOLUTION: According to one embodiment, a semiconductor device includes a first insulating film. The device further includes first wiring including a first layer that is provided on a side surface and an upper surface of the first insulating film in the first insulating film and contains a first element which is a metallic element, a second element that is provided on a side surface and an upper surface of the first layer in the first insulating film and is a metallic element different from the first element, and a second layer that includes a third element different from the first element and the second element. The second layer includes a first portion, an intermediate region, and a second portion that are provided on the side surface of the first layer in order. A concentration of the third element in the intermediate region is higher than a concentration of the third element in the first portion, and is higher than a concentration of the third element in the second portion.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same. [Background technology]

[0002] When forming wiring that includes multiple layers, it can be a problem that atoms in one layer diffuse into another layer, for example, metal atoms in a barrier metal layer diffuse into a wiring material layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 11-016912 [Patent Document 2] JP 2000-150647 A Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of suppressing diffusion of atoms between different layers in wiring and a method for manufacturing the same. [Means for solving the problem]

[0005] According to one embodiment, a semiconductor device includes a first insulating film. The device further includes a first wiring including a first layer provided in the first insulating film on a side surface and an upper surface of the first insulating film and including a first element that is a metal element, and a second layer provided in the first insulating film on a side surface and an upper surface of the first layer and including a second element that is a metal element different from the first element and a third element different from the first element and the second element. The second layer includes a first portion, an intermediate region, and a second portion provided in this order on a side surface of the first layer. The concentration of the third element in the intermediate region is higher than the concentration of the third element in the first portion and is higher than the concentration of the third element in the second portion. [Brief description of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment. [Diagram 2] 1 is an enlarged cross-sectional view showing a structure of a semiconductor device according to a first embodiment. [Diagram 3] 4 is a cross-sectional view (1 / 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] 4 is a cross-sectional view (2 / 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Diagram 5] 1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment. [Figure 6] 4 is a cross-sectional view (1 / 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 4 is a cross-sectional view (2 / 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 5A to 5C are cross-sectional views showing a method for manufacturing a semiconductor device according to a comparative example of the first embodiment. [Figure 9] 4 is a graph showing characteristics of the semiconductor device according to the first embodiment. [Figure 10] 6 is another graph showing characteristics of the semiconductor device according to the first embodiment. [Figure 11] 6 is another graph showing characteristics of the semiconductor device according to the first embodiment. [Figure 12] 6 is another graph showing characteristics of the semiconductor device according to the first embodiment. [Figure 13] FIG. 11 is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment. [Figure 14] 11 is a cross-sectional view (1 / 2) showing a method for manufacturing a semiconductor device according to a second embodiment. [Figure 15] 11 is a cross-sectional view (2 / 2) illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 16] 11A to 11C are cross-sectional views for illustrating characteristics of the semiconductor device according to the second embodiment and a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In Fig. 1 to Fig. 16, the same components are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0008] (First embodiment) FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment.

[0009] The semiconductor device of this embodiment includes, for example, a three-dimensional semiconductor memory. The semiconductor device of this embodiment is manufactured by bonding an array wafer including an array chip 1 and a circuit wafer including a circuit chip 2 together, as described later.

[0010] The array chip 1 includes a memory cell array 11 including a plurality of memory cells, an insulating film 12 on the memory cell array 11, and an interlayer insulating film 13 below the memory cell array 11. The insulating film 12 is, for example, a SiO2 film (silicon oxide film). The interlayer insulating film 13 is, for example, a stacked film including a SiO2 film and another insulating film.

[0011] The circuit chip 2 is provided under the array chip 1. The reference character S indicates the bonding surface between the array chip 1 and the circuit chip 2. The circuit chip 2 includes an interlayer insulating film 14 under the interlayer insulating film 13, and a substrate 15 under the interlayer insulating film 14. The interlayer insulating film 14 is, for example, a laminated film including a SiO2 film and other insulating films. The substrate 15 is, for example, a semiconductor substrate such as a Si (silicon) substrate.

[0012] 1 shows an X direction and a Y direction parallel to the surface of the substrate 15 and perpendicular to each other, and a Z direction perpendicular to the surface of the substrate 15. The X direction, the Y direction, and the Z direction intersect with each other. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may or may not coincide with the direction of gravity.

[0013] The array chip 1 includes a plurality of word lines WL as a plurality of electrode layers in a memory cell array 11. FIG. 1 shows a staircase structure 21 in the memory cell array 11 and a plurality of beam portions 22 provided in the staircase structure 21. Each word line WL is electrically connected to a word wiring layer 24 via a contact plug 23. Each columnar portion CL penetrating these word lines WL is electrically connected to a bit line BL via a via plug 25, and is also electrically connected to a source line SL. The bit line BL is provided below these word lines WL, and the source line SL is provided above these word lines WL.

[0014] The circuit chip 2 includes a plurality of transistors 31. Each transistor 31 includes a gate insulating film 31a and a gate electrode 31b provided in order on the substrate 15, and a source diffusion layer and a drain diffusion layer (not shown) provided in the substrate 15. The circuit chip 2 also includes a plurality of contact plugs 32 provided on the gate electrodes 31b, the source diffusion layer, or the drain diffusion layer of these transistors 31. The circuit chip 2 also includes a wiring layer 33, a wiring layer 34, and a wiring layer 35. The wiring layer 33 includes a plurality of wirings and is provided on these contact plugs 32. The wiring layer 34 includes a plurality of wirings and is provided on the wiring layer 33. The wiring layer 35 includes a plurality of wirings and is provided on the wiring layer 34.

[0015] The circuit chip 2 further includes a plurality of via plugs 36 provided on the wiring layer 35, and a plurality of metal pads 37 provided on these via plugs 36. The metal pads 37 are, for example, a metal layer including a Cu (copper) layer. The circuit chip 2 functions as a control circuit (logic circuit) that controls the operation of the array chip 1. This control circuit is composed of transistors 31 and the like, and is electrically connected to the metal pads 37.

[0016] The array chip 1 includes a plurality of metal pads 41 provided on these metal pads 37, and a plurality of via plugs 42 provided on these metal pads 41. The metal pads 41 are, for example, a metal layer including a Cu layer. The array chip 1 also includes a wiring layer 43 and a wiring layer 44. The wiring layer 43 includes a plurality of wirings and is provided on these via plugs 42. The wiring layer 44 includes a plurality of wirings and is provided on the wiring layer 43. The bit lines BL are included in the wiring layer 44. The control circuit is electrically connected to the memory cell array 11 via the metal pads 41, 37, etc., and controls the operation of the memory cell array 11 via the metal pads 41, 37, etc.

[0017] The array chip 1 further includes a plurality of via plugs 45 provided on the wiring layer 44, and metal pads 46 provided on the via plugs 45 and on the insulating film 12. The array chip 1 also includes a passivation insulating film 47 provided on the metal pads 46 and on the insulating film 12. The metal pads 46 are, for example, a metal layer including a Cu layer, and function as external connection pads (bonding pads) of the semiconductor device of this embodiment. The passivation insulating film 47 is, for example, a laminated film including a SiO2 film and a SiN film (silicon nitride film), and has an opening P that exposes the upper surface of the metal pads 46. The metal pads 46 can be electrically connected to a mounting board or other devices through the opening P by a bonding wire, a solder ball, a metal bump, or the like.

[0018] FIG. 2 is an enlarged cross-sectional view showing the structure of the semiconductor device of the first embodiment.

[0019] 2 shows the memory cell array 11 shown in FIG. The memory cell array 11 includes a laminated film 51 including a plurality of electrode layers 51a and a plurality of insulating films 51b alternately laminated in the Z direction. These electrode layers 51a function as the above-mentioned word lines WL, for example. Each electrode layer 51a is, for example, a metal layer including a W (tungsten) layer. Each insulating film 51b is, for example, a SiO2 film.

[0020] FIG. 2 further illustrates one of the multiple columnar portions CL illustrated in FIG. 1. Each columnar portion CL includes a memory insulating film 52, a channel semiconductor layer 53, and a core insulating film 54, which are provided in this order on the side surface of the laminated film 51. The memory insulating film 52 includes a block insulating film 52a, a charge storage layer 52b, and a tunnel insulating film 52c, which are provided in this order on the side surface of the laminated film 51. The block insulating film 52a is, for example, a SiO2 film. The charge storage layer 52b is, for example, an insulating film such as a SiN film. The charge storage layer 52b may be a semiconductor layer such as a polysilicon layer. The tunnel insulating film 52c is, for example, a SiO2 film. The channel semiconductor layer 53 is, for example, a polysilicon layer. The core insulating film 54 is, for example, a SiO2 film.

[0021] 3 and 4 are cross-sectional views showing the method for manufacturing the semiconductor device of the first embodiment.

[0022] Fig. 3 shows an array wafer W1 including a plurality of array chips 1 and a circuit wafer W2 including a plurality of circuit chips 2. The orientation of the array wafer W1 in Fig. 3 is opposite to that of the array chip 1 in Fig. 1. In this embodiment, a semiconductor device is manufactured by bonding the array wafer W1 and the circuit wafer W2 together. Fig. 3 shows the array wafer W1 before its orientation is reversed for bonding, and Fig. 1 shows the array chip 1 after its orientation is reversed for bonding, bonding, and dicing.

[0023] 3, reference symbol S1 indicates the upper surface of the array wafer W1, and reference symbol S2 indicates the upper surface of the circuit wafer W2. The array wafer W1 includes a substrate 16 provided under an insulating film 12. The substrate 16 is, for example, a semiconductor substrate such as a Si substrate.

[0024] In this embodiment, first, as shown in FIG. 3, the memory cell array 11, the insulating film 12, the interlayer insulating film 13, the metal pad 41, etc. are formed on the substrate 16 of the array wafer W1, and the interlayer insulating film 14, the transistor 31, the metal pad 37, etc. are formed on the substrate 15 of the circuit wafer W2. Next, as shown in FIG. 4, the array wafer W1 and the circuit wafer W2 are bonded together by mechanical pressure so that the surface S1 and the surface S2 face each other. This causes the interlayer insulating film 13 and the interlayer insulating film 14 to be bonded together. Next, the array wafer W1 and the circuit wafer W2 are annealed. This causes the metal pad 41 and the metal pad 37 to be bonded together. In this manner, the substrate 16 and the substrate 15 are bonded together via the interlayer insulating films 13 and 14.

[0025] Thereafter, the substrate 16 is removed by CMP (Chemical Mechanical Polishing), the substrate 15 is thinned by CMP, and the array wafer W1 and the circuit wafer W2 are cut into a plurality of chips (dicing). In this manner, the semiconductor device shown in Fig. 1 is manufactured. Note that the metal pads 46 and the passivation insulating film 47 are formed on the insulating film 12 after the substrate 16 is removed and the substrate 15 is thinned.

[0026] 1 shows the boundary surface between the interlayer insulating film 13 and the interlayer insulating film 14 and the boundary surface between the metal pad 41 and the metal pad 37, but these boundaries generally cannot be observed after the above-mentioned annealing. However, the positions of these boundaries can be estimated by detecting, for example, the inclination of the side surface of the metal pad 41 or the side surface of the metal pad 37, or the positional deviation between the side surface of the metal pad 41 and the side surface of the metal pad 37.

[0027] FIG. 5 is a cross-sectional view showing the structure of the semiconductor device of the first embodiment.

[0028] As shown in Fig. 5, the semiconductor device of this embodiment includes a substrate 101, an interlayer insulating film 102 formed on the substrate 101, and a wiring 103 formed in the interlayer insulating film 102. The wiring 103 is, for example, a damascene wiring formed in the interlayer insulating film 102 by single damascene or dual damascene. In Fig. 5, the lower surface of the wiring 103 is the bottom surface of the wiring 103, and the wiring 103 faces upward. The interlayer insulating film 102 is an example of a first insulating film. The wiring 103 is an example of a first wiring.

[0029] 1, the interlayer insulating film 102 is the interlayer insulating film 14 in FIG. 1, and the wiring 103 is the wiring in the wiring layer 33, the wiring layer 34, or the wiring layer 35 in FIG. 1. In this case, the semiconductor device of this embodiment includes an interlayer insulating film 13 on the interlayer insulating film 102 (=14), a metal pad 37 in the interlayer insulating film 102 (=14), and a metal pad 41 on the metal pad 37 in the interlayer insulating film 13. In this case, the interlayer insulating film 14, the interlayer insulating film 13, the metal pad 37, and the metal pad 41 are examples of the first insulating film, the second insulating film, the first pad, and the second pad, respectively.

[0030] On the other hand, the substrate 101, the interlayer insulating film 102, and the wiring 103 may be the substrate 15, the interlayer insulating film 13, and the wiring layer 43 or the wiring in the wiring layer 44 in FIG. 1, respectively. In this case, the wiring layers 43 and 44 in FIG. 1 face downward, whereas the wiring 103 in FIG. 5 faces upward, so that the orientation of the semiconductor device in FIG. 5 is opposite to that of the semiconductor device in FIG. 1. Therefore, the substrate 101 (=15) in this case is not located below the interlayer insulating film 102 (=13) as shown in FIG. 5, but is located above the interlayer insulating film 102 (=13). In this case, the interlayer insulating film 13, the interlayer insulating film 14, the metal pad 41, and the metal pad 37 are examples of the first insulating film, the second insulating film, the first pad, and the second pad, respectively.

[0031] With continued reference to FIG. 5, further details of wiring 103 will now be described.

[0032] The wiring 103 includes a barrier metal layer 103a and a wiring layer 103b. The barrier metal layer 103a is an example of a first layer. The wiring layer 103b is an example of a second layer. The wiring layer 103b also includes a seed layer 111, a plating layer 112, and a plating layer 113, and further includes a region R located between the plating layers 112 and 113. The plating layer 112 is an example of a first portion. The plating layer 113 is an example of a second portion. Region R is an example of an intermediate region.

[0033] The barrier metal layer 103a is formed in the interlayer insulating film 102 on the side and upper surface of the interlayer insulating film 102. The barrier metal layer 103a is, for example, a metal layer containing Ti (titanium) as a metal element. The barrier metal layer 103a in this embodiment is a Ti layer. The Ti element is an example of the first element.

[0034] The wiring layer 103b is formed on the side and top surfaces of the barrier metal layer 103a in the interlayer insulating film 102. The wiring layer 103b is, for example, a metal layer containing Cu as a metal element. The wiring layer 103b of this embodiment is a Cu layer. The wiring layer 103b is, for example, a metal layer containing an impurity element. The impurity element is, for example, a non-metal element such as C (carbon), N (nitrogen), O (oxygen), S (sulfur), or Cl (chlorine). The Cu element is an example of the second element. The impurity element is an example of the third element.

[0035] The seed layer 111, the plating layer 112, the region R, and the plating layer 113 are formed in this order on the side and upper surface of the barrier metal layer 103a. The plating layers 112 and 113 are formed, for example, by a plating process using the seed layer 111. In this embodiment, the plating layers 112 and 113 are formed by ECD (Electro Chemical Deposition).

[0036] As described above, wiring layer 103b of the present embodiment contains Cu and impurity elements. For example, when plating layers 112 and 113 are formed by plating, the impurity elements are imparted to wiring layer 103b by C, N, O, S, or Cl elements in a plating solution for plating that enters wiring layer 103b. Wiring layer 103b of the present embodiment contains a high concentration of impurity elements in region R. Thus, the concentration of impurity elements in region R of the present embodiment is higher than the concentration of impurity elements in plating layer 112 and is also higher than the concentration of impurity elements in plating layer 113. For example, the concentration of impurity elements in region R is 5 times or more the concentration of impurity elements in plating layer 112 and / or the concentration of impurity elements in plating layer 113.

[0037] The region R is interposed between the plating layer 112 and the plating layer 113. The thickness of the region R may be set to be so thin that the region R cannot be called a layer, or may be set to be so thick that the region R can be called a layer. In the former case, the region R may extend between the side and upper surface of the plating layer 112 and the side and lower surface of the plating layer 113 in a shape with a thickness close to zero, that is, a shape close to a surface. On the other hand, in the latter case, the region R may be interposed between the plating layer 112 and the plating layer 113 in a state where the thickness is not clear, specifically, in a state where the boundary between the plating layer 112 and the region R is not clear, or in a state where the boundary between the plating layer 113 and the region R is not clear. In this case, a part of the plating layer 112 or a part of the plating layer 113 may be the region R. In this case, the part of the plating layer 112 other than the region R is an example of the first part, and the part of the plating layer 113 other than the region R is an example of the second part. Further details of region R will be described later.

[0038] 6 and 7 are cross-sectional views showing the method for manufacturing the semiconductor device of the first embodiment.

[0039] First, an interlayer insulating film 102 is formed on a substrate 101 (FIG. 6(a)). Next, a recess H is formed in the interlayer insulating film 102 by photolithography and RIE (Reactive Ion Etching) (FIG. 6(b)). The recess H is, for example, a wiring trench for burying a wiring 103.

[0040] Next, a barrier metal layer 103a, a seed layer 111, and a plating layer 112 are formed in this order on the entire surface of the substrate 101 (FIG. 6(c)). Specifically, the barrier metal layer 103a is formed on the side and upper surface of the interlayer insulating film 102 in the recess H, and is formed on the upper surface of the interlayer insulating film 102 outside the recess H. Furthermore, the seed layer 111 is formed on the side and upper surface of the barrier metal layer 103a in the recess H, and is formed on the upper surface of the barrier metal layer 103a outside the recess H. Furthermore, the plating layer 112 is formed on the side and upper surface of the seed layer 111 in the recess H, and is formed on the upper surface of the seed layer 111 outside the recess H. The plating layer 112 is formed, for example, by a plating process using the seed layer 111.

[0041] In the plating process of this embodiment, when forming the plating layers 112, 113 using an electric current, the value of the electric current is set to zero for a certain period of time. As a result, a predetermined element Q in the plating solution adheres to the surface of the plating layer 112, and thus a region R containing the element Q at a high concentration is formed on the surface of the plating layer 112 (FIG. 7(a)). In FIG. 7(a), atoms of the element Q are typically shown as black squares. The region R is, for example, a Cu region containing the element Q at a high concentration as an impurity element. In this embodiment, the region R is formed on the surface of the plating layer 112 inside and outside the recesses H.

[0042] The element Q is, for example, a component element contained in an additive to the plating solution. Examples of the element Q are C, N, O, S, and Cl. In this embodiment, when the value of the current for plating is temporarily set to zero, the element Q in the plating solution is adsorbed onto the surface of the plating layer 112. As a result, a region R is formed on the surface of the plating layer 112. The plating solution is, for example, an aqueous solution of copper sulfate.

[0043] The plating process of this embodiment is performed so as to include, in order, a current-carrying period in which the current value is not zero, a non-current-carrying period in which the current value is zero, and a current-carrying period in which the current value is not zero. The former current-carrying period, non-current-carrying period, and the latter current-carrying period are examples of the first, second, and third periods, respectively. Moreover, the current values ​​in the former current-carrying period, non-current-carrying period, and the latter current-carrying period are examples of the first, second, and third values, respectively. The plating layer 112 is formed during the former current-carrying period (FIG. 6(c)). The region R is formed over the non-current-carrying period and the latter current-carrying period (FIG. 7(a)). The plating layer 113 is formed during the latter current-carrying period (FIG. 7(b)).

[0044] In FIG. 7(b), plating layer 113 is formed inside and outside recess H, and recess H is filled with plating layer 113. In this manner, wiring layer 103b is formed, which includes seed layer 111, plating layer 112, region R, and plating layer 113 in that order. In this embodiment, wiring layer 103b is formed such that the concentration of element Q in region R is higher than the concentration of element Q in plating layer 112 and higher than the concentration of element Q in plating layer 113. When element Q includes multiple types of elements, such a concentration relationship may hold for each type of element Q, or may hold for the total concentration of all types of element Q.

[0045] In addition, the plating layer 113 of this embodiment is formed by a plating process including a first half period in which the current value is set to be small and a second half period in which the current value is set to be large. Generally, the plating layer 113 inside the recess H is formed in the first half period, and the plating layer 113 outside the recess H is formed in the second half period. The first half period is an example of the third period described above, and the second half period is an example of the fourth period. Furthermore, the current value in the first half period is an example of the third value described above, and the current value in the second half period is an example of the fourth value. Further details of these periods and current values ​​will be described later.

[0046] Next, the surface of the wiring layer 103b is polished by CMP (FIG. 7(c)). As a result, the wiring layer 103b and the barrier metal layer 103a outside the recess H are removed, and the wiring 103 is formed inside the recess H.

[0047] After that, the subsequent steps for manufacturing the semiconductor device of this embodiment are performed. For example, the array wafer W1 and the circuit wafer W2 are bonded together as described with reference to Figures 3 and 4. In this manner, the semiconductor device of this embodiment having the structure shown in Figures 1 and 5 is manufactured.

[0048] 8A to 8C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a comparative example of the first embodiment.

[0049] First, an interlayer insulating film 102 is formed on a substrate 101, and a recess H is formed in the interlayer insulating film 102 (FIG. 8(a)). Next, a barrier metal layer 103a, a seed layer 111, and a plating layer 114 are formed in this order on the entire surface of the substrate 101 (FIG. 8(a)). Specifically, a wiring material layer 103b including the seed layer 111 and the plating layer 114 in this order is formed.

[0050] The plating process in the first embodiment is performed so as to include a current-carrying period, a non-current-carrying period, and a current-carrying period in that order. On the other hand, the plating process in this comparative example is performed so as to include only a current-carrying period. As a result, the wiring layer 103b in this comparative example is formed so as not to include the region R.

[0051] In this case, when the barrier metal layer 103a or the wiring layer 103b is annealed at high temperature, Ti atoms in the barrier metal layer 103a may diffuse into the wiring layer 103b (FIG. 8(b)). In FIG. 8(b), Ti atoms diffused into the wiring layer 103b (plating layer 114) are shown as black squares. In this case, the electrical resistance of the wiring 103 increases (FIG. 8(c)). In addition, when the array wafer W1 and the circuit wafer W2 are bonded together to manufacture a semiconductor device, the annealing for bonding the metal pad 37 and the metal pad 41 may cause Ti atoms in the barrier metal layer 103a to diffuse into the wiring layer 103b.

[0052] On the other hand, when the barrier metal layer 103a and the wiring layer 103b of this embodiment are annealed at high temperatures, the region R has the effect of suppressing the diffusion of Ti atoms. Therefore, according to this embodiment, it is possible to suppress the diffusion of Ti atoms in the barrier metal layer 103a into the wiring layer 103b. This makes it possible to keep the electrical resistance of the wiring 103 low.

[0053] In this embodiment, region R contains a high concentration of element Q (impurity element). As a result, the grain size of the crystal grains in region R is smaller than the grain size of the crystal grains in plating layer 112, and also smaller than the grain size of the crystal grains in plating layer 113. This makes it difficult for Ti atoms to pass through region R, and region R can suppress the diffusion of Ti atoms. The grain size of these crystal grains can be measured, for example, by observing wiring layer 103b with a SEM (Scanning Electron Microscope).

[0054] FIG. 9 is a graph showing characteristics of the semiconductor device of the first embodiment.

[0055] The horizontal axis of Fig. 9 indicates the annealing temperature when annealing the barrier metal layer 103a and the wiring material layer 103b as described above. The vertical axis of Fig. 9 indicates the resistivity of the wiring 103 after annealing in au. Fig. 9 shows the resistivity of the wiring 103 when the barrier metal layer 103a is a Ti layer and when the barrier metal layer 103a is a Ta (tantalum) layer.

[0056] 9, when the barrier metal layer 103a is a Ti layer, high-temperature annealing increases the resistivity of the wiring 103. This is believed to be because Ti atoms easily diffuse into a Cu layer, whereas Ta atoms do not easily diffuse into a Cu layer.

[0057] FIG. 10 is another graph showing the characteristics of the semiconductor device of the first embodiment.

[0058] FIG. 10 shows the change over time of the current used in the above-described plating process. The plating process of the present embodiment is performed so as to sequentially include an energization period in which the current value is set to M1, a non-energization period in which the current value is set to zero, an energization period in which the current value is set to M2, and an energization period in which the current value is set to M3. Hereinafter, the energization periods in which the current values are set to M1, M2, and M3 are referred to as the M1 period, the M2 period, and the M3 period, respectively. The M1 period, the non-energization period, the M2 period, and the M3 period are examples of the first, second, third, and fourth periods, respectively. Also, the current value (M1) during the M1 period, the current value (0) during the non-energization period, the current value (M2) during the M2 period, and the current value (M3) during the M3 period are examples of the first, second, third, and fourth values, respectively. In the present embodiment, the relationship 0 < M2 < M1 < M3 holds among M1, M2, and M3.

[0059] In the present embodiment, the plating layer 112 is formed during the M1 period. Also, the region R is formed over the non-energization period and the M2 period. Also, the plating layer 113 is formed over the M2 period and the M3 period. Generally, when the value of the current in the plating process is increased, the formation rate of the plating layer increases, but the quality of the plating layer may deteriorate. According to the present embodiment, by forming the plating layer 113 inside the recess H with a small current, it is possible to improve the quality of the plating layer 113 that becomes part of the wiring 103. Also, according to the present embodiment, by forming the plating layer 113 outside the recess H with a large current, it is possible to form the plating layer 113 to be removed by CMP in a short time.

[0060] The length of the non-energization period can be arbitrarily set. However, if the non-energization time is too short, there is a risk that a sufficient amount of element Q cannot be imparted to the region R. On the other hand, if the non-energization time is too long, there is a risk that the plating layer will dissolve due to the influence of the non-energization time. Therefore, the non-energization period of the present embodiment is set, for example, within the range of 10 milliseconds to 100 milliseconds. Note that the non-energization period of the present embodiment is set shorter than the M1 period, the M2 period, and the M3 period.

[0061] The non-energized period may be replaced with an energized period in which the value of the current is set to a minute value M. The value of M is, for example, 1 / 10 or less, 1 / 100 or less, or 1 / 1000 or less of the value of M2. According to this embodiment, by performing plating processing including such an energized period, it is possible to obtain the same effect as in the case of performing plating processing including a non-energized period.

[0062] FIG. 11 is another graph showing the characteristics of the semiconductor device of the first embodiment.

[0063] The horizontal axis of Fig. 11 indicates the height (Z coordinate) of each point in the wiring 103. The vertical axis of Fig. 11 indicates the concentration of element Q (impurity element) at each point in the wiring 103 on a logarithmic scale. Fig. 11 shows the concentration profiles of impurity elements in the wiring 103 for C element, O element, S element, and Cl element. Note that the height of each point in the wiring 103 is an example. Also, the concentration of element Q (impurity element) at each point in the wiring 103 is an example.

[0064] 11 shows concentration profiles in the barrier metal layer 103a, the seed layer 111, the plating layer 112, and the plating layer 113. As shown in FIG. 11, the plating process of this embodiment is performed so as to include a no-current period after the formation of the plating layer 112. As a result, the impurity concentration in the portion of the plating layer 113 near the plating layer 112 becomes high, as indicated by the open arrow. In this case, this portion becomes the region R of this embodiment.

[0065] In Fig. 11, the concentration of C element is high in region R, and the concentrations of S element and Cl element are much higher in region R. Therefore, in the case of Fig. 11, it is desirable for region R to contain C element, and it is further desirable for region R to contain S element and Cl element.

[0066] FIG. 12 is another graph showing the characteristics of the semiconductor device of the first embodiment.

[0067] The horizontal axis of FIG. 12 indicates the height (Z coordinate) of each point in the wiring 103. The vertical axis of FIG. 12 indicates the Ti concentration at each point in the wiring 103 on a logarithmic scale. FIG. 12 shows the Ti concentration profile for the wiring 103 of the first embodiment and the wiring 103 of the comparative example. Note that "plating layer 112" and "plating layer 113" shown in FIG. 12 are replaced with "plating layer 114" in the comparative example. Also, the height of each point in the wiring 103 is an example. Also, the Ti concentration at each point in the wiring 103 is an example.

[0068] 12, it can be seen that the Ti concentration in plating layer 113 formed during M2 period in this embodiment, i.e., plating layer 113 formed in recess H, is lower than that in the comparative example. This shows that this embodiment can suppress the diffusion of Ti atoms from barrier metal layer 103a to wiring material layer 103b.

[0069] As described above, wiring 103 of the present embodiment is formed to include region R between plating layer 112 and plating layer 113. Therefore, according to the present embodiment, it is possible to suppress diffusion of Ti atoms in barrier metal layer 103a into wiring material layer 103b.

[0070] The wiring 103 of this embodiment may be other than the wiring in the wiring layers 33, 34, 35, 43, and 44, and may be, for example, a contact plug (contact wiring), a via plug (via wiring), or a metal pad (pad wiring). For example, the wiring 103 of this embodiment may be any of the contact plug 32, the via plugs 36 and 42, and the metal pads 37 and 41.

[0071] The barrier metal layer 103a of this embodiment may contain a metal element other than Ti. The wiring layer 103b of this embodiment may contain a metal element other than Cu. The region R of this embodiment may contain an impurity element other than C, N, O, S, and Cl. The semiconductor device of this embodiment may be manufactured without bonding wafers together.

[0072] Second embodiment FIG. 13 is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment.

[0073] The semiconductor device of this embodiment (FIG. 13) has a structure similar to that of the semiconductor device of the first embodiment (FIG. 5). However, the region R of this embodiment is formed on the side of the plating layer 112 and is removed from the upper part of the plating layer 112. As a result, the plating layer 113 of this embodiment includes a portion facing the plating layer 112 via the region R and a portion facing the plating layer 112 without the region R, as shown in FIG.

[0074] 14 and 15 are cross-sectional views showing a method for manufacturing the semiconductor device according to the second embodiment.

[0075] First, an interlayer insulating film 102 is formed on a substrate 101, and a recess H is formed in the interlayer insulating film 102 (FIG. 14(a)). Next, a barrier metal layer 103a, a seed layer 111, and a plating layer 112 are formed in this order on the entire surface of the substrate 101, and a region R is formed on the surface of the plating layer 112 (FIG. 14(a)). The process of FIG. 14(a) is performed in the same manner as the processes of FIGS. 6(a) to 7(a).

[0076] Next, the region R is removed by RIE from other than the side of the recess H (FIG. 14(b)). As a result, the upper surface of the plating layer 112 is exposed at the bottom of the recess H. At this time, the plating layer 112 may also be removed from other than the side of the recess H, exposing the upper surface of the seed layer 111 at the bottom of the recess H.

[0077] Next, plating layer 113 is formed over the entire surface of substrate 101 (FIG. 15(a)). In this manner, wiring layer 103b is formed, which includes seed layer 111, plating layer 112, region R, and plating layer 113, in that order. Wiring layer 103b in this embodiment is also formed so that the concentration of element Q in region R is higher than the concentration of element Q in plating layer 112, and is also higher than the concentration of element Q in plating layer 113.

[0078] Next, the surface of the wiring layer 103b is polished by CMP (FIG. 15(b)). As a result, the wiring layer 103b and the barrier metal layer 103a outside the recess H are removed, and the wiring 103 is formed inside the recess H.

[0079] After that, the subsequent steps for manufacturing the semiconductor device of this embodiment are performed. For example, the array wafer W1 and the circuit wafer W2 are bonded together as described with reference to Figures 3 and 4. In this manner, the semiconductor device of this embodiment having the structure shown in Figures 1 and 13 is manufactured.

[0080] FIG. 16 is a cross-sectional view for illustrating characteristics of the semiconductor device according to the second embodiment and a comparative example.

[0081] Fig. 16(a) shows a semiconductor device of a comparative example of this embodiment. The structure of the semiconductor device of the comparative example of this embodiment is similar to the structure of the semiconductor device of the comparative example of the first embodiment (see Fig. 8(c)). Fig. 16(a) shows crystal grains, grain boundaries, voids, Ti atoms, etc. in the plating layer 114.

[0082] Fig. 16(b) shows the semiconductor device of this embodiment. Like Fig. 16(a), Fig. 16(b) shows a schematic diagram of crystal grains, grain boundaries, voids, Ti atoms, and the like in plating layers 112 and 113. Fig. 16(b) further shows region R between plating layers 112 and 113, and atoms of element Q.

[0083] The wiring 103 of the comparative example does not include the region R. Therefore, the Ti atoms in the barrier metal layer 103a of the comparative example are not only likely to diffuse from the barrier metal layer 103a near the bottom surface of the wiring 103 to the plating layer 114, but also likely to diffuse from the barrier metal layer 103a near the side surface of the wiring 103 to the plating layer 114. On the other hand, the aggregation of voids in the plating layer 114 can be suppressed by the Ti atoms. This is because when the Ti atoms penetrate into the plating layer 114, voids are less likely to be formed in the plating layer 114, and the number of voids in the plating layer 114 is reduced. As a result, defects in the wiring 103 caused by voids are reduced.

[0084] On the other hand, the wiring 103 of this embodiment includes a region R between the plating layer 112 and the plating layer 113 near the side surface of the wiring 103. Therefore, the Ti atoms in the barrier metal layer 103a of this embodiment are likely to diffuse from the barrier metal layer 103a near the bottom surface of the wiring 103 to the plating layer 113, but are unlikely to diffuse from the barrier metal layer 103a near the side surface of the wiring 103 to the plating layer 113. This makes it possible to keep the electrical resistance of the wiring 103 low. Also, according to this embodiment, the Ti atoms diffused in a small amount into the plating layer 113 can suppress the aggregation of voids in the plating layer 114. This makes it possible to reduce defects in the wiring 103 caused by voids.

[0085] As described above, wiring 103 of the present embodiment is formed to include region R between plating layer 112 and plating layer 113. Therefore, according to the present embodiment, it is possible to suppress diffusion of Ti atoms in barrier metal layer 103a into wiring material layer 103b.

[0086] Moreover, the region R in this embodiment is formed near the side surface of the wiring 103, and is removed from near the bottom surface of the wiring 103. Therefore, according to this embodiment, it is possible to diffuse a small amount of Ti atoms in the barrier metal layer 103a into the wiring material layer 103b. This makes it possible to enjoy the advantages of Ti atoms (suppression of the void problem) while suppressing the disadvantages of Ti atoms (increased resistance).

[0087] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel device and method described in this specification can be implemented in various other forms. In addition, various omissions, substitutions, and modifications can be made to the forms of the device and method described in this specification without departing from the spirit of the invention. The appended claims and their equivalents are intended to include such forms and modifications that fall within the scope and spirit of the invention. [Explanation of symbols]

[0088] 1: array chip, 2: circuit chip, 11: memory cell array, 12: insulating film, 13: interlayer insulating film, 14: interlayer insulating film, 15: substrate, 16: substrate, 21: staircase structure portion, 22: beam portion, 23: contact plug, 24: word wiring layer, 25: via plug, 31: transistor; 31a: gate insulating film; 31b: gate electrode; 32: contact plug; 33: wiring layer; 34: wiring layer; 35: wiring layer, 36: via plug, 37: metal pad, 41: metal pad, 42: via plug, 43: wiring layer, 44: wiring layer, 45: via plug, 46: metal pad, 47: passivation insulating film, 51: laminated film, 51a: electrode layer, 51b: insulating film, 52: memory insulating film, 52a: block insulating film, 52b: charge storage layer, 52c: tunnel insulating film, 53: channel semiconductor layer, 54: core insulating film, 101: substrate, 102: interlayer insulating film, 103: wiring, 103a: barrier metal layer, 103b: wiring material layer, 111: seed layer, 112: plating layer, 113: plating layer, 114: plating layer

Claims

1. A first insulating film; a first wiring including: a first layer provided within the first insulating film on a side surface and an upper surface of the first insulating film, the first layer including a first element which is a metal element; and a second layer provided within the first insulating film on a side surface and an upper surface of the first layer, the second layer including a second element which is a metal element different from the first element, and a third element which is different from the first element and the second element; the second layer includes a first portion, an intermediate region, and a second portion provided in that order on a side surface of the first layer; a concentration of the third element in the intermediate region is higher than a concentration of the third element in the first portion and is higher than a concentration of the third element in the second portion; Semiconductor device.

2. The semiconductor device according to claim 1 , wherein the first portion, the intermediate region, and the second portion are provided in that order on a side surface and an upper surface of the first layer.

3. 2 . The semiconductor device according to claim 1 , wherein said second portion includes a portion facing said first portion with said intermediate region interposed therebetween, and a portion facing said first portion without said intermediate region interposed therebetween.

4. 2. The semiconductor device according to claim 1, wherein the first layer is a barrier metal layer in the first wiring, and the second layer is a wiring material layer in the first wiring.

5. 2. The semiconductor device according to claim 1, wherein said first element is Ti (titanium).

6. The semiconductor device according to claim 1 , wherein the second element is Cu (copper).

7. 2. The semiconductor device according to claim 1, wherein the third element is C (carbon), N (nitrogen), O (oxygen), S (sulfur), or Cl (chlorine).

8. The semiconductor device according to claim 1 , wherein the third element is a nonmetallic element.

9. 2. The semiconductor device according to claim 1, wherein the second layer is a metal layer containing the third element as an impurity element.

10. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a concentration of the third element in the intermediate region is five times or more than a concentration of the third element in the first portion and / or a concentration of the third element in the second portion.

11. a first pad provided in the first insulating film; A second insulating film provided on the first insulating film; a second pad provided on the first pad within the second insulating film; The semiconductor device according to claim 1 , further comprising:

12. forming a first insulating film; forming a first wiring including a first layer provided in the first insulating film on a side surface and an upper surface of the first insulating film and including a first element which is a metal element; and a second layer provided in the first insulating film on a side surface and an upper surface of the first layer and including a second element which is a metal element different from the first element and a third element which is different from the first element and the second element; Including, the second layer is formed to include a first portion, an intermediate region, and a second portion provided in that order on a side surface of the first layer; a concentration of the third element in the intermediate region is set to be higher than a concentration of the third element in the first portion and higher than a concentration of the third element in the second portion; A method for manufacturing a semiconductor device.

13. the second layer is formed by a plating process using an electric current; the plating process is performed to include a first period during which the current is set to a first value, a second period during which the current is set to a second value smaller than the first value after the first period, and a third period during which the current is set to a third value larger than the second value after the second period. The method for manufacturing a semiconductor device according to claim 12 .

14. The method for manufacturing a semiconductor device according to claim 13 , wherein the third value is smaller than the first value.

15. The method for manufacturing a semiconductor device according to claim 13 , wherein the second value is zero.

16. The first portion is formed within the first period of time; the intermediate region is formed within the second period and the third period; The second portion is formed during the third period. The method for manufacturing a semiconductor device according to claim 13.

17. The method for manufacturing a semiconductor device according to claim 13 , wherein the intermediate region is formed by the third element in a plating solution for the plating process being attached to a surface of the first portion.

18. 18. The method for manufacturing a semiconductor device according to claim 17, wherein the plating solution is an aqueous solution of copper sulfate.

19. 14. The method of claim 13, wherein the plating process is performed so as to further include a fourth period after the third period, during which the current is set to a fourth value greater than the third value.

20. forming a first pad in the first insulating film; forming a second insulating film; forming a second pad in the second insulating film; bonding the first insulating film and the second insulating film together so that the first pad and the second pad are bonded together; The method for manufacturing a semiconductor device according to claim 12, further comprising:

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