Bimetallic liner layer
Patent Information
- Application Number
- JP2024154031
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2020-06-23
- Filing Date
- 2024-09-06
- Publication Date
- 2026-02-16
- Estimated Expiration
- 2041-05-05
AI Technical Summary
The challenge in microelectronic devices is to improve metal/dielectric-to-metal adhesion and reduce copper wire susceptibility to electromigration failures as feature sizes shrink, particularly at the 5 nm node, where current barrier and liner thicknesses are limited by inherent properties and thickness, affecting reliability and adhesion.
A two-metal liner film is introduced between the metal barrier layer and the gap fill metal, comprising two metals in a single film or alternating layers, formed using methods like ALD/CVD/PE-ALD, thermal treatment, and plasma treatment, with specific metal combinations such as Co and Mn, Ru and Ta, to enhance adhesion and mobility.
The two-metal liner film provides a better interface, improving adhesion and reducing electromigration failures while allowing for thinner layers that enhance gap filling and capping, enabling advanced node technologies.
Smart Images

Figure 00000000_0000_ABST
Abstract
Description
[Technical field]
[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to bimetallic liner layers and methods of treating and / or doping bimetallic liner layers. More particularly, embodiments of the present disclosure relate to bimetallic liner layers that include two metals. [Background technology]
[0002] Microelectronic devices such as semiconductors or integrated circuits can contain millions of electronic circuit devices such as transistors, capacitors, etc. To further increase the density of devices found on an integrated circuit, smaller feature sizes are desired. To achieve these smaller feature sizes, the size of conductive lines, vias, and interconnects, gates, etc. must be reduced. Reliable formation of multi-level interconnect structures is also necessary to increase circuit density and quality. Advances in manufacturing technology have made it possible to use copper for conductive lines, interconnects, vias, and other structures.
[0003] Specifically, for the 5 nm node and below, the thickness of barriers and liners for copper interconnects becomes increasingly critical with respect to device reliability and adhesion of the barrier layer to the dielectric layer. Shrinking feature sizes also leads to higher resistance as well as higher susceptibility of copper lines to electromigration (EM) failure. A high-quality bond at the interface between copper and the dielectric barrier layer can reduce or prevent EM failure. Typical thicknesses of barrier layers and liners at the 5 nm node are on the order of about 45 Å. Thicker barrier / liner layers tend to provide less space for metal gap-filling, which increases resistivity. The current approach to improve metal / dielectric-to-metal adhesion and mobility of the fill metal during gap-filling is to increase the film thickness of a single material, which is limited by the intrinsic properties and thickness of the single material. Summary of the Invention [Problem to be solved by the invention]
[0004] Therefore, there is a need for a material layer that improves the adhesion between metal / dielectric and metal, and a method for depositing such a material layer. [Means for solving the problem]
[0005]
[0005] Embodiments of the present disclosure provide a two-metal liner film between a metal barrier layer and a gap-fill metal. In one or more embodiments, the two-metal liner film includes two metals in a single film or in a first liner film and a second liner film.
[0006] In one or more embodiments, a method of forming a liner film includes forming a barrier layer on a substrate, forming a two-metal liner film on the barrier layer, and forming a gap-fill metal on the two-metal liner film. Another method embodiment relates to forming a microelectronic device, the method includes forming a dielectric layer on a substrate including at least one feature that defines a gap, forming a barrier layer on the dielectric layer, forming the two-metal liner film on the barrier layer, and forming a gap-fill metal on the two-metal liner film.
[0007] A further embodiment of the present disclosure is directed to a non-transitory computer readable medium including instructions that, when executed by a controller of a processing system, cause the processing system to perform operations of forming a two-metal liner film, including forming a barrier layer on a substrate, forming a liner two-metal liner film on the barrier layer, and forming a gap-fill metal on the two-metal liner film.
[0008] So that the above-mentioned features of the invention may be understood in detail, a more particular description of the invention briefly summarized above can be made by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical embodiments of the invention and therefore should not be considered as limiting the scope of the invention, which may admit of other equally effective embodiments. [Brief description of the drawings]
[0009] [Figure 1] FIG. 1 is a process flow diagram according to one or more embodiments of the present disclosure. [Diagram 2] 1 is a cross-sectional view of an electronic device according to one or more embodiments of the present disclosure. [Figure 3A] 1 is a cross-sectional view of an electronic device according to one or more embodiments of the present disclosure. [Figure 3B] 1 is a cross-sectional view of an electronic device according to one or more embodiments of the present disclosure. [Figure 3C] 1 is a cross-sectional view of an electronic device according to one or more embodiments of the present disclosure. [Figure 4] 1 is a cross-sectional view of an electronic device according to one or more embodiments of the present disclosure. [Diagram 5] FIG. 1 is a cross-sectional view of a cluster tool according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0010] Before describing certain example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description as being capable of other embodiments and of being practiced and carried out in various ways.
[0011] As used herein and in the appended claims, the terms "substrate" and "wafer" are used interchangeably and both refer to a surface or a portion of a surface on which a process acts. Those skilled in the art will also understand that a reference to a substrate can also refer to only a portion of the substrate, unless the context clearly indicates otherwise. In addition, a reference to depositing on a substrate can refer to both a bare substrate and a substrate on which one or more films or features have been deposited or formed.
[0012] "Substrate" as used herein refers to any substrate or surface of material formed on a substrate on which a film treatment is performed during a manufacturing process. For example, substrate surfaces on which treatment can be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, as well as any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate (or otherwise generate or graft targeted chemical moieties to impart chemical functionality), anneal, and / or bake the substrate surface. In addition to performing film treatments directly on the surface of the substrate itself, the present disclosure also allows any of the disclosed film treatment steps to be performed on an underlayer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlayers as the context indicates. Thus, for example, if a film / layer or partial film / layer is deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface. What a given substrate surface comprises depends on which film is to be deposited as well as the particular chemistry used.
[0013] As used herein and in the appended claims, the terms "reactive gas," "precursor," "reactant," and the like are used interchangeably to mean a gas that contains a species that is reactive with the substrate surface. For example, a first "reactive gas" may simply adsorb onto the surface of the substrate and be available for further chemical reaction with a second reactive gas.
[0014] As used herein, "atomic layer deposition" or "cyclic deposition" refers to the sequential exposure of two or more reactive compounds to deposit layers of material on a substrate surface. The substrate or a portion of the substrate is separately exposed to two or more reactive compounds introduced into a reaction zone of a processing chamber. In a time-domain ALD process, the exposure to each reactive compound is separated by a time delay to allow each compound to deposit and / or react on the substrate surface and then be purged from the processing chamber. These reactive compounds are said to be sequentially exposed to the substrate. In a spatial ALD process, different portions of the substrate surface or materials on the substrate surface are exposed to two or more reactive compounds simultaneously, such that any given point on the substrate is not substantially exposed to two or more reactive compounds simultaneously. As used herein and in the appended claims, the term "substantially" as used in this respect means that it is possible that a small portion of the substrate may be exposed to multiple reactive gases simultaneously due to diffusion, as would be understood by one skilled in the art, and simultaneous exposure is not intended.
[0015] In one aspect of a time-domain ALD process, a first reactive gas (i.e., a first precursor or compound A) is pulsed into the reaction zone, followed by a first time delay. Then, a second precursor or compound B is pulsed into the reaction zone, followed by a second delay. During each time delay, a purge gas, such as argon, is introduced into the process chamber to purge the reaction zone or otherwise remove any residual reactive compounds or reaction by-products from the reaction zone. Alternatively, the purge gas may flow continuously throughout the deposition process, such that only the purge gas flows during the time delay between pulses of reactive compounds. The reactive compounds are pulsed alternately until a desired film or film thickness is formed on the substrate surface. In either scenario, the ALD process of pulsing compound A, purge gas, compound B, and purge gas is a cycle. The cycle can start with either compound A or compound B, and continue with each turn of the cycle until a film having a predetermined thickness is achieved.
[0016] In one embodiment of a spatial ALD process, a first reactive gas and a second reactive gas (e.g., nitrogen gas) are simultaneously supplied to a reaction zone but separated by an inert gas curtain and / or a vacuum curtain. The substrate is moved relative to the gas supply such that any given point on the substrate is exposed to the first reactive gas and the second reactive gas.
[0017] It has been found that the adhesion of the barrier layer can be advantageously improved by depositing a liner film that includes two metals. In some embodiments, the two-metal liner film includes an alloy of two metals in a single layer. In some embodiments, the two-metal liner film includes alternating layers of two metals M1 and M2, or a first metal liner film and a second metal liner film. In one or more embodiments, the two metals include two metals selected from the group consisting of: (M1) cobalt (Co) and (M2) manganese (Mn); (M1) Co and (M2) tantalum (Ta); (M1) Co and (M2) tungsten (W); (M1) Co and (M2) molybdenum (Mo); (M1) ruthenium (Ru) and (M2) Mn; (M1) Ru and (M2) Ta; (M1) Ru and (M2) W; (M1) Ru and (M2) Mo; (M1) Ta and (M2) Mn; and (M1) Ta and (M2) W. In one or more embodiments, the two metal liner film has a thickness of less than 20 angstroms.
[0018] According to one or more embodiments, the two-metal liner film can be formed by a variety of deposition methods, including alternating and / or co-flow precursors by ALD / CVD / PE-ALD, precursors with multi-metal ligands, dopant implantation, and / or thermal diffusion. The two-metal liner film can be formed in a single processing chamber or in multiple processing chambers. In one or more embodiments, the two-metal liner film can be treated by a variety of methods, including thermal, plasma, and / or chemical treatments.
[0019] Advantageously, the ultra-thin (e.g., having a thickness of 20 angstroms or less) bimetallic liner films according to one or more embodiments provide better interfacial adhesion and mobility between two metals, such as a barrier layer and a gap-filling metal. The bimetallic liner films and methods described according to one or more embodiments can be used in metal contact, interconnect, and capping applications. The bimetallic liner films according to one or more embodiments are thinner than current liners, which are typically greater than 20 angstroms up to 30 angstroms. In some embodiments, the bimetallic liner film has a thickness in the range of 10 Å to 20 Å, 10 Å to 19 Å, 10 Å to 18 Å, 10 Å to 17 Å, 10 Å to 16 Å, 10 Å to 15 Å, 10 Å to 14 Å, 10 Å to 13 Å, or 10 Å to 12 Å. The bimetallic liner film described herein can extend metal filling and capping to advance nodes, such as enabling Cu reflow at 3nm / 2nm nodes, low resistivity in middle of the line (MOL) and back end of line (BEOL), and memory. The methods described herein can also simplify current complex integrated systems to one-chamber or multi-chamber processes including CVD / ALD / PVD / PEALD / ion implantation.
[0020] In one or more embodiments, the barrier layer and / or metal film can be deposited via ALD. In a typical ALD process, a film can be deposited using alternating pulses or flows of "A" and "B" precursors. Alternating exposure of the surface to reactants "A" and "B" continues until a film of the desired thickness is reached. However, instead of pulsing the reactants, gases can be simultaneously flowed from one or more gas delivery heads or nozzles, and the substrate and / or gas delivery head can be moved such that the substrate is sequentially exposed to each of the reactive gases. Of course, the aforementioned ALD cycles are merely illustrative of the wide variety of ALD process cycles in which a deposition layer is formed by alternating layers of precursors and co-reactants.
[0021] In one or more embodiments, the co-reactant is in the form of a vapor or gas. The reactants may be delivered with a carrier gas. The carrier gas, purge gas, deposition gas, or other process gas may include nitrogen, hydrogen, argon, neon, helium, or combinations thereof. The various plasmas described herein, such as nitrogen plasma or inert gas plasma, may be ignited from and / or may include a plasma co-reactant gas.
[0022] In one or more embodiments, the various gases for the process may be pulsed from various holes or outlets, through the gas channels, into the inlet, and into the central channel. In one or more embodiments, the deposition gases may be pulsed sequentially into and through the showerhead. Alternatively, as described above, the gases may flow simultaneously through the gas delivery nozzles or heads, and the substrate and / or gas delivery head may be moved so that the substrate is sequentially exposed to the gases.
[0023] In one or more embodiments, the barrier layer material and the liner film are deposited using a multi-chamber process with the barrier layer material (e.g., tantalum nitride (TaN)) and the two-metal liner film being separately deposited. In other embodiments, a single-chamber approach is used where all processes are performed in one chamber and the different layers / films are separated in the process by gas purging.
[0024] Some embodiments of the present invention are directed to barrier applications, such as copper barrier applications. A barrier layer formed by one or more embodiments may be used as a copper barrier. Barrier layers suitable for copper barrier applications include, but are not limited to, TaN and MnN. For copper barrier applications, suitable dopants include, but are not limited to, Ru, Cu, Co, Mn, Al, Ta, Mo, Nb, V, or combinations thereof. Plasma treatments can be used after doping to promote intermetallic compound formation between the matrix and the dopant, remove film impurities, and improve the density of the barrier layer. In other embodiments, post-treatments can include, but are not limited to, physical vapor deposition (PVD) treatments, thermal annealing, chemical strengthening, and the like. For some copper barrier applications, high frequency plasma (defined as greater than about 14 MHz or greater than about 40 MHz) is used with neon (Ne), hydrogen (H 2 ), and argon (Ar) gas. In one or more embodiments, a higher plasma frequency (above 13.56 MHz) can be used to prevent low dielectric constant damage. In some embodiments, the barrier layer is a copper barrier and includes TaN doped with Ru.
[0025] Suitable precursors for depositing the liner layer include metal-containing precursors, such as carbonyl-containing precursors and cyclopentadiene-containing precursors. In a non-limiting example, when the liner layer is RuCo, the Ru-containing precursor is triruthenium dodecacarbonyl Ru 3 (CO) 12and the Co-containing precursor may be dicobalt hexacarbonyl tertiary butyl acetylene (CCTBA). When the liner layer is TaRu, the Ta-containing precursor may be pentakis(dimethylamino)tantalum (PDMAT). Other suitable precursors are known to those skilled in the art. The organic species in the organic-containing precursor for the liner layer may be partially incorporated into the underlayer (such as a barrier layer or a dielectric layer), which can improve adhesion at the liner layer-underlayer interface.
[0026] As used herein, "chemical vapor deposition" refers to a process in which a substrate surface is exposed to precursors and / or co-reagents simultaneously or substantially simultaneously. As used herein, "substantially simultaneously" refers to either co-flow or where there is overlap for the majority of the exposure of the precursors.
[0027] The bimetallic liner film can be formed by depositing alternating layers of the two metals or by co-reacting two metal precursors by CVD, PVD or ALD. Depending on the liner metal used, a co-reactant or co-precursor can be used to deposit the bimetallic liner film. In one or more embodiments, ion implantation may be used to incorporate the second metal into the liner film of the first metal. In other embodiments, physical vapor deposition (PVD) co-processing can be used to add the second metal to the doped liner film formed on the barrier layer. In further embodiments, the bimetallic liner film can be annealed in an atmosphere containing the second metal to thermally diffuse the second metal into the bimetallic liner film of the first metal to form the bimetallic liner film on the barrier layer.
[0028] In one or more embodiments, a PVD process by sputtering can be used as a method to incorporate a second metal into a liner film that includes a first metal. For example, a PVD process using cobalt (Co) can infuse a ruthenium film with Co to form a liner film that includes ruthenium and cobalt.
[0029] In some embodiments, instead of or in addition to using a co-reactant, a plasma post-treatment step may be used after exposing the bimetallic liner film containing the first metal to the second metal precursor. According to one or more embodiments, the plasma comprises any suitable inert gas known to those of skill in the art. In one or more embodiments, the plasma may comprise any suitable inert gas such as helium (He), argon (Ar), ammonia (NH 3 ), hydrogen (H 2 ), and nitrogen (N 2 In some embodiments, the plasma comprises one or more of Ar:H in the range of 1:1 to 1:10. 2 Mixtures having molar ratios of Ar and H, etc. 2 The plasma power may range from about 200 to about 1000 Watts. The plasma frequency may range from 350 kHz to 40 MHz. The plasma treatment time may vary from 5 seconds to 60 seconds, such as from 10 seconds to 30 seconds. In some embodiments, the pressure during plasma treatment may range from 0.5 to 50 Torr, such as from 1 to 10 Torr. In some embodiments, the wafer spacing may range from 100 mil to 600 mil.
[0030] In one or more embodiments, a two-metal liner film comprising a first metal may be exposed to a second metal precursor during deposition, i.e., the second metal precursors can be used sequentially in an ALD cycle to provide a liner film comprising two metals on a barrier layer.
[0031] In various embodiments, the duration of exposure to the second metal-containing precursor can range from 1 to 60 seconds, such as from 3 to 30 seconds or from 5 to 10 seconds. Longer exposure to the second metal precursor increases the amount of the second metal in the two-metal liner film.
[0032] FIG. 1 illustrates a process flow diagram of a method according to one or more embodiments. FIGS. 2-4 illustrate a cross-sectional view of a microelectronic device 200 according to one or more embodiments of the present disclosure. With reference to FIG. 2, a dielectric layer 204 is formed on a substrate 202. In one or more embodiments, the dielectric layer 204 may include at least one feature 206. While the figure shows a substrate with a single feature for purposes of illustration, one of ordinary skill in the art will understand that there may be two or more features. The shape of the feature 206 may be any suitable shape, including, but not limited to, trenches and cylindrical vias. In some embodiments, the feature 206 defines a gap in the dielectric layer 204. When used in this context, the term "feature" refers to any intentional surface irregularity. Suitable examples of a feature include, but are not limited to, a trench having a top, two sidewalls and a bottom, a peak having a top and two sidewalls. The feature may have any suitable aspect ratio (the ratio of the depth of the feature to the width of the feature). In some embodiments, the aspect ratio is about 5:1, 10:1, 15:1, 20:1, 25:1, 30:1, 35:1 or 40:1 or greater.
[0033] In one or more embodiments, the at least one feature 206 includes a bottom 212, a first sidewall 208, and a second sidewall 210. In one or more embodiments, the dielectric layer 204 is a low-k dielectric layer. In certain embodiments, the dielectric layer 204 is a silicon oxide (SiO x Further embodiments include those in which the dielectric layer 204 is porous or carbon-doped SiO x In some embodiments, the dielectric layer 204 is a porous or carbon-doped SiO 2 layer having a dielectric constant value of less than about 5. x In other embodiments, the dielectric layer 204 is a multi-layer structure. For example, in one or more embodiments, the dielectric layer 204 includes a multi-layer structure having one or more of a dielectric layer, an etch stop layer, and a hard mask layer.
[0034] 1-3A, in operation 104, a barrier layer 214 is deposited on a dielectric layer 204 on a substrate 202. In some embodiments, the barrier layer 214 is formed by a conformal deposition process. In some embodiments, the barrier layer 214 is formed by one or more of atomic layer deposition or chemical vapor deposition.
[0035] In one or more embodiments, the deposition of the barrier layer 214 is substantially conformal. In one or more embodiments, the barrier layer 214 is formed on the first sidewall 208, the second sidewall 210, and the bottom 212 of at least one feature. As used herein, a "substantially conformal" layer refers to a layer that has about the same thickness throughout (e.g., at the top, middle, and bottom of the sidewalls and at the bottom of the opening 206). A substantially conformal layer varies in thickness by no more than about 5%, 2%, 1%, or 0.5%.
[0036] 3A illustrates the microelectronic device 200 after deposition of a barrier layer 214 covering at least a portion of the first sidewall 208, the second sidewall 210, and the bottom 212 of the at least one feature 206. As illustrated in FIG. 3B, the barrier layer 214 can cover the entirety of the first sidewall 208, the second sidewall 210, and the bottom 212 of the at least one feature 206. In one or more embodiments, the barrier layer 214 can include one or more of tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), niobium (Nb), niobium nitride (NbN), manganese (Mn), manganese nitride (MnN), titanium (Ti), titanium nitride (TiN), molybdenum (Mo), molybdenum nitride (MoN), and the like.
[0037] In one or more embodiments, the barrier layer 214 is deposited by atomic layer deposition (ALD) and has a thickness in the range of about 2 Å to about 10 Å. In some embodiments, the barrier layer 214 is deposited in a single ALD cycle. In other embodiments, the barrier layer 214 is deposited in 1 to 15 ALD cycles.
[0038] 1 and 3B, in operation 106, a first liner film is deposited by chemical vapor deposition, atomic layer deposition, or PVD of a first liner film 216. In one or more embodiments, the first liner film may include a first metal (M1) and a second metal (M2). In one or more embodiments, the two metals comprise two metals selected from the group consisting of: (M1) cobalt (Co) and (M2) manganese (Mn); (M1) Co and (M2) tantalum (Ta); (M1) Co and (M2) tungsten (W); (M1) Co and (M2) molybdenum (Mo); (M1) ruthenium (Ru) and (M2) Mn; (M1) Ru and (M2) Ta; (M1) Ru and (M2) W; (M1) Ru and (M2) Mo; (M1) Ta and (M2) Mn; and (M1) Ta and (M2) W.
[0039] In one or more embodiments, the second metal M2 is diffused into the first liner film 216 of the first metal M1.
[0040] In one or more embodiments, the first liner film 216 comprises in the range of about 0.01 to about 50 weight percent of the second metal, based on the total weight of the first liner film. In certain embodiments, the first liner film 216 comprises in the range of about 5% to about 70% of the second metal, such as in the range of about 10 to about 30 weight percent of the second metal, such as in the range of about 8 to about 25 weight percent of the second metal, or in the range of about 10 to about 20 weight percent of the second metal.
[0041] 1 and 3C, in operation 108, in some embodiments, a second liner film 218 is deposited on the first liner film 218 to provide a two-metal liner film 220 consisting of a first liner film made of a first metal M1 and a second liner film 218 made of a second metal M2. In one or more embodiments, the two metals comprise two metals selected from the group consisting of: (M1) cobalt (Co) and (M2) manganese (Mn); (M1) Co and (M2) tantalum (Ta); (M1) Co and (M2) tungsten (W); (M1) Co and (M2) molybdenum (Mo); (M1) ruthenium (Ru) and (M2) Mn; (M1) Ru and (M2) Ta; (M1) Ru and (M2) W; (M1) Ru and (M2) Mo; (M1) Ta and (M2) Mn; and (M1) Ta and (M2) W.
[0042] In one or more embodiments, the second liner film is deposited by atomic layer deposition (ALD), CVD, or PVD. In some embodiments, the second liner film 218 is deposited in 1-15 ALD cycles.
[0043] In one or more embodiments, the two metal liner film 220, including the first liner film and the second liner film 218, has a total thickness in a range of about 5 Å to about 15 Å, or about 8 Å to about 10 Å. In further embodiments, the total thickness is less than about 20 Å. In some embodiments, the two metal liner film 220 has a thickness in a range of 10 Å to 20 Å, 10 Å to 19 Å, 10 Å to 18 Å, 10 Å to 17 Å, 10 Å to 16 Å, 10 Å to 15 Å, 10 Å to 14 Å, 10 Å to 13 Å, or 10 Å to 12 Å.
[0044] In operation 110, the device is optionally post-treated. The optional post-treatment operation 110 can be, for example, a process to modify the film properties (e.g., annealing) or a further film deposition process to grow additional films (e.g., additional ALD or CVD processes). In some embodiments, the optional post-treatment operation 110 can be a process to modify the properties of the deposited film. In some embodiments, the optional post-treatment operation 110 includes annealing the as-deposited film. In some embodiments, the annealing is performed at a temperature in the range of about 300° C., 400° C., 500° C., 600° C., 700° C., 800° C., 900° C., or 1000° C. The annealing environment in some embodiments is an inert gas (e.g., molecular nitrogen (N 2 ), argon (Ar), or a reducing gas (e.g., molecular hydrogen (H 2 ) or ammonia (NH 3 )), or, but not limited to, oxygen (O 2 ), ozone (O 3 The annealing may include one or more of an oxidizing agent, such as a fluorine atom, an iodine atom, or a peroxide. The annealing may be performed for any suitable length of time. In some embodiments, the film is annealed for a predetermined time ranging from about 15 seconds to about 90 minutes, or from about 1 minute to about 60 minutes. In some embodiments, annealing the as-deposited film increases the density, decreases the resistivity, and / or increases the purity of the bimetal film 220.
[0045] 4, a conductive fill metal 222 fills at least a portion of the trench 206 lined with the barrier layer 214, the doped barrier layer 216, and the second barrier layer 218. According to one or more embodiments, the conductive fill metal 222 includes copper (Cu) or a copper alloy. In further embodiments, the conductive fill metal 222 also includes manganese (Mn). In other embodiments, the conductive fill metal 222 further includes aluminum (Al). In some embodiments, the conductive fill metal 222 includes tungsten (W).
[0046] In an embodiment, a seed layer (not shown) may be deposited over the two-metal liner film 220. According to one or more embodiments, the seed layer may include an alloy of copper, such as a Cu-Mn alloy.
[0047] In some embodiments, the substrate is transferred from the first chamber to a separate subsequent chamber for further processing. The substrate can be transferred directly from the first chamber to a separate processing chamber, or the substrate can be transferred from the first chamber to one or more transfer chambers and then to a separate processing chamber. In some embodiments, deposition of the barrier layer and the dopant film can be performed in a single chamber, followed by post-processing in separate chambers. Thus, the processing equipment can include multiple chambers in communication with the transfer station. This type of equipment can be referred to as a "cluster tool" or a "clustered system", or the like.
[0048] In general, a cluster tool is a modular system with multiple chambers that perform various functions including center detection and orientation, degassing, annealing, deposition and / or etching of the substrate. According to one or more embodiments, the cluster tool includes at least a first chamber and a central transfer chamber. The central transfer chamber can house a robot that can shuttle the substrate between the processing chambers and the load lock chamber. The transfer chamber is typically maintained under vacuum and provides an intermediate stage for shuttle transfer of the substrate from one chamber to another and / or to the load lock chamber located at the front end of the cluster tool. Two well-known cluster tools that can be adapted for the present disclosure are the Centura® and Endura®, both available from Applied Materials, Inc., Santa Clara, Calif. However, the exact arrangement and combination of chambers may be altered for the purpose of performing the specific steps of the processes described herein. Other processing chambers that can be used include, but are not limited to, cyclic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etching, precleaning, chemical cleaning, plasma nitridation, degassing, orientation, hydroxylation, and other substrate processes. By performing processes in chambers on a cluster tool, surface contamination of the substrate with atmospheric impurities can be avoided without oxidation prior to depositing a subsequent film.
[0049] According to one or more embodiments, the substrate is constantly under vacuum or "load-lock" conditions and is not exposed to ambient air when moving from one chamber to the next. The transfer chamber is therefore under vacuum and is "pumped down" under vacuum pressure. An inert gas may be present in the processing or transfer chamber. In some embodiments, an inert gas is used as a purge gas to remove some or all of the reactants (e.g., reactants). According to one or more embodiments, a purge gas is injected at the outlet of the deposition chamber to prevent the reactants (e.g., reactants) from moving from the deposition chamber to the transfer chamber and / or additional processing chambers. Thus, the flow of the inert gas forms a curtain at the outlet of the chamber.
[0050] Substrates may be processed in a single substrate deposition chamber, where a single substrate is loaded, processed, and unloaded before another substrate is processed. As with a conveyor system, substrates may also be processed continuously, where multiple substrates are individually loaded into a first portion of the chamber, moved through the chamber, and unloaded from a second portion of the chamber. The geometry of the chamber and associated conveyor system may form a linear or curvilinear path. Additionally, the processing chamber may be a carousel, where multiple substrates move around a central axis and are exposed to processes such as deposition, etching, annealing, cleaning, etc. throughout the carousel path.
[0051] During processing, the substrate can be heated or cooled. Such heating or cooling can be accomplished by any suitable means, including but not limited to changing the temperature of the substrate support and flowing a heated or cooled gas over the substrate surface. In some embodiments, the substrate support includes a heater / cooler that can be controlled to conductively change the substrate temperature. In one or more embodiments, the gas used (either reactive or inert gas) is heated or cooled to locally change the substrate temperature. In some embodiments, a heater / cooler is located in the chamber adjacent to the substrate surface to convectively change the substrate temperature.
[0052] The substrate may be stationary or may rotate during processing. A rotating substrate may be rotated (about the substrate axis) continuously or in discrete steps. For example, the substrate may be rotated throughout the entire process, or the substrate may be rotated only a small amount between exposures to different reactive or purge gases. Rotating the substrate (continuously or in steps) during processing may help to provide a more uniform deposition or etching, for example, by minimizing the effects of local variations in the geometry of the gas flow.
[0053] A further embodiment of the present disclosure is directed to a processing tool 900 for forming the described devices and practicing the methods, as shown in Figure 5. The cluster tool 900 includes at least one central transfer station 921, 931 having multiple sides. Robots 925, 935 are disposed within the central transfer station 921, 931 and configured to move a robot blade and a wafer to each of the multiple sides.
[0054] The cluster tool 900 includes multiple processing chambers, also referred to as process stations, 902, 904, 906, 908, 910, 912, 914, 916, and 918, connected to a central transfer station. The various processing chambers provide separate processing regions isolated from adjacent process stations. The processing chambers can be any suitable chambers, including, without limitation, atomic layer deposition chambers, chemical vapor deposition chambers, annealing chambers, and the like. The particular arrangement of process chambers and components can vary depending on the cluster tool and should not be construed as limiting the scope of the present disclosure.
[0055] 5, a factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a loading chamber 954 and an unloading chamber 956 at the front 951 of the factory interface 950. Although the loading chamber 954 is shown on the left and the unloading chamber 956 is shown on the right, one of ordinary skill in the art will appreciate that this is merely representative of one possible configuration.
[0056] The size and shape of the loading chamber 954 and the unloading chamber 956 can vary depending on, for example, the substrate being processed in the cluster tool 900. In the illustrated embodiment, the loading chamber 954 and the unloading chamber 956 are sized to hold a wafer cassette with multiple wafers disposed therein.
[0057] The robot 952 is in the factory interface 950 and can move between a loading chamber 954 and an unloading chamber 956. The robot 952 can transfer wafers from a cassette in the loading chamber 954 to a load lock chamber 960 through the factory interface 950. The robot 952 can also transfer wafers from a load lock chamber 962 to a cassette in the unloading chamber 956 through the factory interface 950. As will be appreciated by those skilled in the art, the factory interface 950 can have more than one robot 952. For example, the factory interface 950 can have a first robot that transfers wafers between the loading chamber 954 and the load lock chamber 960 and a second robot that transfers wafers between the load lock 962 and the unloading chamber 956.
[0058] The illustrated cluster tool 900 has a first section 920 and a second section 930. The first section 920 is connected to a factory interface 950 via load lock chambers 960, 962. The first section 920 includes a first transfer chamber 921 with at least one robot 925 disposed therein. The robot 925 is also referred to as a robotic wafer transport mechanism. The first transfer chamber 921 is centrally located with respect to the load lock chambers 960, 962, the process chambers 902, 904, 916, 918, and the buffer chambers 922, 924. The robot 925 of some embodiments is a multi-arm robot capable of independently moving two or more wafers at a time. In some embodiments, the first transfer chamber 921 includes two or more robotic wafer transfer mechanisms. The robot 925 in the first transfer chamber 921 is configured to move wafers between chambers around the first transfer chamber 921. Individual wafers are supported on a wafer transport blade located at the distal end of the first robotic mechanism.
[0059] After processing the wafer in the first section 920, the wafer may be passed through a pass-through chamber to the second section 930. For example, the chambers 922, 924 may be one-way or two-way pass-through chambers. The pass-through chambers 922, 924 may be used, for example, to cryogenically cool the wafer before processing in the second section 930 or to allow for cooling or post-processing of the wafer before returning to the first section 920.
[0060] A system controller 990 communicates with the first robot 925, the second robot 935, the first plurality of processing chambers 902, 904, 916, 918, and the second plurality of processing chambers 906, 908, 910, 912, 914. The system controller 990 can be any suitable component capable of controlling the processing chambers and robots. For example, the system controller 990 can be a computer including a central processing unit (CPU) 992, memory 994, input / output (I / O) 996, and support circuits 998. The controller 990 may directly control the processing tool 900 or may control it via computers (or controllers) associated with particular process chambers and / or support system components.
[0061] In one or more embodiments, the controller 990 may be one of any form of general-purpose computer processor that can be used in an industrial environment to control various chambers and sub-processors. The memory 994 or computer readable medium of the controller 990 may be one or more of readily available memory such as non-transitory memory (e.g., random access memory (RAM)), read-only memory (ROM), floppy disk, hard disk, optical storage medium (e.g., compact disk or digital video disk), flash drive, or any other form of digital storage, local or remote. The memory 994 may hold a set of instructions operable by the processor (CPU 992) to control parameters and components of the processing tool 900.
[0062] The support circuits 998 are coupled to the CPU 992 for supporting the processor in a conventional manner. These circuits include cache, power supplies, clock circuits, input / output circuits and subsystems, etc. One or more processes may be stored in the memory 994 as software routines that, when executed or invoked by the processor, cause the processor to control the operation of the processing tool 900 or individual processing units in the manner described herein. The software routines may also be stored and / or executed by a second CPU (not shown) located remotely from the hardware controlled by the CPU 992.
[0063] Some or all of the processes and methods of the present disclosure may be performed in hardware. Thus, the processes may be implemented in software and may be performed using a computer system in hardware, for example as an application specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. The software routines, when executed by a processor, transform a general-purpose computer into a special-purpose computer (controller) that controls the operation of the chamber to perform the processes.
[0064] In some embodiments, the controller 990 has one or more configurations for performing individual processes or sub-processes to perform a method. The controller 990 can be connected to and configured to operate intermediate components to perform the functions of a method. For example, the controller 990 can be connected to and configured to control a physical vapor deposition chamber.
[0065] The processes may generally be stored in the memory 994 of the system controller 990 as software routines that, when executed by a processor, cause the process chamber to perform the processes of the present disclosure. The software routines may also be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Some or all of the methods of the present disclosure may be performed in hardware. Thus, the processes may be implemented in software and may be performed in hardware using a computer system, for example, as an application specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. The software routines, when executed by a processor, transform a general-purpose computer into a special-purpose computer (controller) that controls the operation of the chamber so that the processes are performed.
[0066] In some embodiments, the system controller 990 is configured to control an atomic layer deposition, chemical vapor deposition, or physical vapor deposition chamber to deposit a two-metal liner layer on a substrate.
[0067] In one or more embodiments, the processing tool includes a central transfer station including a robot configured to move the wafer; a plurality of process stations, each process station connected to the central transfer station and providing a processing area isolated from the processing areas of adjacent process stations, the plurality of process stations including a deposition chamber, a plasma processing chamber, a remote plasma source, and an annealing chamber; and a controller connected to the central transfer station and the plurality of process stations, the controller configured to operate the robot to move the wafer between the process stations and to control the process performed at each of the process stations.
[0068] Another aspect of the present disclosure relates to a non-transitory computer readable medium comprising instructions that, when executed by a controller of a processing system, cause the processing system to perform the operations of the method described herein. In one embodiment, the non-transitory computer readable medium comprises instructions that, when executed by a controller of the processing system, cause the processing system to perform the operations of forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap, forming a barrier layer on the dielectric layer, forming a two-metal liner film on the barrier layer, and forming a gap-filling metal on the two-metal liner film. The non-transitory computer readable medium may further comprise instructions that, when executed by a controller of the processing system, cause the processing system to perform the operations of depositing a two-metal liner film comprising a first metal liner film and a second metal liner film.
[0069] The two-metal liner films described herein provide hybrid metal liner films that can provide tailored properties to improve adhesion, improve gap-fill metal reflow, and reduce electromigration failures. For example, the Ru liner has a wide Cu reflow window for void-free gap-filling with the gap-filling metal, while the Co liner has good adhesion to copper for improved reliability. A composite metal liner made of two metals, such as Co and Ru, can exploit the beneficial properties of each metal in a single liner made of two metals. For example, a two-metal liner film made of Ru and Co shows less ISO narrow line Cu voids after annealing. The two-metal liner fill shows better gap-filling and longer electromigration times during testing, which indicates devices with less electromigration failures.
[0070] Throughout this specification, references to "one embodiment," "a particular embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of phrases such as "in one or more embodiments," "in a particular embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment of the disclosure. Furthermore, particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.
[0071] Although the disclosure of the present specification has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure is intended to cover modifications and variations that come within the scope of the appended claims and their equivalents.
Claims
1. a dielectric layer on a substrate, the dielectric layer including at least one feature defining a gap; a barrier layer on the dielectric layer selected from the group consisting of TaN, doped TaN, MnN, and doped MnN; a two-metal liner film on the barrier layer, comprising alternating layers of a first liner film of a first metal M1 on the barrier layer and a second liner film of a second metal M2 on the first liner film, the first liner film and the second liner film being formed separately from each other, the first liner film having a thickness in the range of 1 angstrom to 10 angstroms, the second liner film on the first liner film having a thickness in the range of 1 angstrom to 10 angstroms, and the first metal M1 and the second metal M2 are selected from the group consisting of M1 Co and M2 tantalum (Ta); M1 Co and M2 tungsten (W); M1 cobalt (Co) and M2 molybdenum (Mo); M1 ruthenium (Ru) and M2 tungsten (W); M1 ruthenium (Ru) and M2 molybdenum (Mo); M1 tantalum (Ta) and M2 manganese (Mn); and M1 tantalum (Ta) and M2 tungsten (W); a two-metal liner film selected from the group consisting of: a gap-fill metal on the bimetallic liner film, the bimetallic liner film providing interfacial adhesion between the barrier layer and the gap-fill metal; Equipped with The microelectronic device wherein the two-metal liner film has a thickness in the range of 5 Angstroms to 20 Angstroms.
2. The microelectronic device of claim 1 , wherein the two-metal liner film has a thickness in the range of 5 Angstroms to 15 Angstroms.
3. The microelectronic device of claim 1 , wherein the first liner film has a thickness in the range of 1 Angstrom to 5 Angstroms.
4. 1. A method of forming a microelectronic device, comprising: forming a dielectric layer on a substrate, the dielectric layer including at least one feature that defines a gap; forming a barrier layer on the dielectric layer selected from the group consisting of TaN, doped TaN, MnN, and doped MnN; forming a two-metal liner film on the barrier layer, separately forming alternating layers of a first liner film made of a first metal M1 on the barrier layer and a second liner film made of a second metal M2 on the first liner film on the barrier layer, the first liner film having a thickness in the range of 1 angstrom to 10 angstroms and made of the first metal M1, and the second liner film on the first liner film having a thickness in the range of 1 angstrom to 10 angstroms and made of the second metal M2; wherein the first metal M1 and the second metal M2 are selected from the group consisting of M1, Co, and M2, tantalum (Ta); M1, Co, and M2, tungsten (W); M1, Co, and M2, tungsten (Mo); M1, Ruthenium (Ru), and M2, tungsten (W); M1, Ruthenium (Ru), and M2, molybdenum (Mo); M1, Tantalum (Ta), and M2, manganese (Mn); and M1, Tantalum (Ta), and M2, tungsten (W); and forming a gap-fill metal on the bimetallic liner film, the bimetallic liner film providing interfacial adhesion between the barrier layer and the gap-fill metal; Including, The method wherein the two metal liner film has a thickness in the range of 5 Angstroms to 20 Angstroms.
5. The method of claim 4, wherein the two-metal liner film has a thickness in the range of 5 Angstroms to 15 Angstroms.
6. The method of claim 4, wherein the first liner film has a thickness in the range of 1 Angstrom to 5 Angstroms.
7. a dielectric layer on a substrate, the dielectric layer including at least one feature defining a gap; a barrier layer on the dielectric layer selected from the group consisting of TaN, doped TaN, MnN, and doped MnN; a single layer liner film on the barrier layer, the single layer liner film having a thickness in the range of 10 angstroms to 20 angstroms and comprising an alloy of two metals, the two metals being selected from the group consisting of a first metal M1 and a second metal M2, where M1 is ruthenium (Ru) and M2 is tungsten (W); and M1 is ruthenium (Ru) and M2 is molybdenum (Mo); a gap-filling metal on the single layer liner film, the single layer liner film providing interfacial adhesion between the barrier layer and the gap-filling metal; A microelectronic device comprising:
8. The microelectronic device of claim 7, wherein the single layer liner film has a thickness in the range of 10 Angstroms to 19 Angstroms.
9. The microelectronic device of claim 7, wherein the single layer liner film has a thickness in the range of 10 Angstroms to 15 Angstroms.