3-d dram structures and methods of manufacture

Abstract

To provide methods of forming a dynamic random access memory, which includes bridged word lines and / or an etch stop layer, and stacked memory devices.SOLUTION: Memory devices 100 incorporating bridged word lines 160 include a plurality of active regions 115 spaced along a first direction 20, a second direction 30 and a third direction 40. A plurality of conductive layers 120 is arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction. A conductive bridge 130 extends along the second direction to connect each of the conductive layers to one or more adjacent conductive layer. Some embodiments include an integrated etch stop layer.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE

[0001] Embodiments of the present disclosure relate to the field of electronic devices and electronic device manufacturing. In particular, embodiments of the present disclosure provide a dynamic random access memory having bridged wordlines and / or etch stop layers. [Background technology]

[0002]

[0002] Electronic devices such as personal computers, workstations, computer servers, mainframes, and other computer-related equipment such as printers, scanners, and hard disk drives use memory devices that provide significant data storage capacity while consuming low power. There are two main types of random access memory cells suitable for use in electronic devices: dynamic and static. Dynamic random access memories (DRAMs) can be programmed to store a voltage that represents one of two binary values, but may require periodic reprogramming or "refreshing" to maintain this voltage for more than a very short period of time. Static random access memories (SRAMs) are so named because they do not require periodic refreshing.

[0003]

[0003] DRAM memory circuits are manufactured by replicating millions of identical circuit elements, known as DRAM cells, on a single semiconductor wafer. Each DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components: a field effect transistor (FET) and a capacitor.

[0004]

[0004] The manufacture of a DRAM cell involves the fabrication of a transistor, a capacitor, and three contacts: one for the bit line, the word line, and the reference voltage. The manufacture of DRAM is a competitive business. There is a constant drive to reduce the size of individual cells and increase memory cell density, especially to densities above 256 megabits, to allow for more memory to be packed onto a single memory chip. The limitations to the reduction of cell size are the passage of both active and passive word lines through the cell, the size of the cell capacitor, and the compatibility of array devices with non-array devices.

[0005]

[0005] In a 3D memory device, the word lines of a unit cell layer should be connected. However, the active layer of the unit cell should not be connected. Furthermore, the length of the capacitor needs to be controlled without the influence of variations during the selective removal process interfering. The length of the capacitor is longer than the gate length of the cell transistor. A longer selective removal length will cause a larger length variation due to variable removal rate. Therefore, there is a need in the art for a memory device and a method of forming a memory device that includes one or more of connected word lines, isolated active areas, or etching control. Summary of the Invention

[0006]

[0006] One or more embodiments of the present disclosure are directed to a memory device including a plurality of active areas spaced apart along a first direction, a second direction, and a third direction. A plurality of conductive layers are arranged such that at least one conductive layer is adjacent at least one side of each of the active areas along the third direction. A conductive bridge extends along the second direction and connects each conductive layer to one or more adjacent conductive layers.

[0007]

[0007] Further embodiments of the present disclosure are directed to a memory device comprising a plurality of pairs of active areas spaced apart along a first direction, a second direction, and a third direction. A plurality of bit lines extend along a third direction between pairs of the active areas spaced apart in the first direction. A plurality of conductive layers are arranged such that at least one conductive layer is adjacent to at least one side of each of the active areas. The at least one side is positioned along the third direction relative to the active areas. A conductive bridge extends along the second direction and connects each conductive layer to one or more adjacent conductive layers.

[0008]

[0008] Further embodiments of the present disclosure are directed to a method of forming a memory device. A stack of films including a sacrificial layer and a channel layer is patterned to form a pair of prebridge stacks separated along a first direction and an isolation film stack extending along the first direction. The prebridge stacks are formed on either side of the isolation film stack along a second direction to create an opening between the prebridge stacks and an opening outside the prebridge stack along the first direction and to create a gap between the isolation film stack and an adjacent film stack along the second direction. The channel layer is removed from the prebridge stack through the opening and recessed into the isolation film stack to form a recessed channel layer in the isolation film stack. The opening and the recessed channel layer are filled with a dielectric. A trench is formed in the isolation film stack along the second direction. The trench is formed between the pair of prebridge stacks along the first direction. A portion of the sacrificial layer is removed from the isolation film stack through the trench to form a recessed sacrificial layer having a recessed sacrificial layer surface and a word line opening, exposing a surface of the channel layer. A gate oxide layer is formed in the word line opening on the surface of the channel layer exposed through the trench. A conductive layer is deposited in the word line opening on the gate oxide layer. The trench is filled with a dielectric. A slit pattern is formed through the sacrificial layer and the channel layer. The slit pattern is formed outside the conductive layer in the word line opening on either side of where the trench is formed. The slit pattern exposes a sidewall of the channel layer and a sidewall of the sacrificial layer. A portion of the channel layer is removed through the slit pattern to form a capacitor opening, exposing a surface of the sacrificial layer and the recessed channel layer. A capacitor is formed in the capacitor opening adjacent to the recessed channel layer.

[0009]

[0009] In order to allow the above features of the present disclosure to be understood in detail, a more specific description of the present disclosure briefly summarized above can be made by referring to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings show only typical embodiments of the present disclosure, and therefore should not be considered as limiting the scope of the present disclosure, since the present disclosure may admit of other equally effective embodiments. The embodiments described herein are described with the accompanying drawings for illustration and not limitation, in which similar elements are indicated by similar reference numerals. [Brief description of the drawings]

[0010] [Figure 1]

[0010] FIG. 1 illustrates a schematic parallel projection view of a memory device showing coordinate nomenclature, in accordance with one or more embodiments of the present disclosure. [Figure 2A]

[0011] 1 illustrates an isometric view of a memory device having one or two word lines adjacent to an active area in accordance with one or more embodiments of the present disclosure. [Figure 2B] 1 illustrates an isometric view of a memory device having one or two word lines adjacent to an active area in accordance with one or more embodiments of the present disclosure. [Figure 2C] 1 illustrates an isometric view of a memory device having one or two word lines adjacent to an active area in accordance with one or more embodiments of the present disclosure. [Diagram 3]

[0012] 1 illustrates an isometric view of a memory device in accordance with one or more embodiments of the present disclosure. [Figure 4]

[0013] 1 illustrates an isometric view of a section of a memory device in accordance with one or more embodiments of the present disclosure. [Diagram 5]

[0014] 1 shows a cross-sectional schematic diagram of a film stack for a memory device according to one or more embodiments of the present disclosure. [Figure 6]

[0015] 1 shows a schematic top view of a memory device after isolation patterning according to one or more embodiments. [Figure 6A]

[0016] 7 shows a cross-sectional slice of the memory device taken along line A-A in FIG. 6. [Figure 6B]

[0017] 7 shows a cross-sectional slice of the memory device taken along line B-B of FIG. 6. [Figure 6C]

[0018] 7 shows a cross-sectional slice of the memory device taken along line CC of FIG. 6. [Figure 6D]

[0019] 7 shows a cross-sectional slice of the memory device taken along line D-D of FIG. 6. [Figure 7]

[0020] 1 illustrates a schematic top view of a memory device after active isolation, according to one or more embodiments. [Figure 7A]

[0021] 8 shows a cross-sectional slice of the memory device taken along line A-A of FIG. 7. [Figure 7B]

[0022] 8 shows a cross-sectional slice of the memory device taken along line B-B of FIG. 7. [Figure 7C]

[0023] 8 shows a cross-sectional slice of the memory device taken along line CC of FIG. [Figure 7D]

[0024] 8 shows a cross-sectional slice of the memory device taken along line D-D of FIG. 7. [Figure 8]

[0025] 1 shows a schematic top view of a memory device after dielectric filling according to one or more embodiments. [Figure 8A]

[0026] 9 shows a cross-sectional slice of the memory device taken along line A-A in FIG. 8. [Figure 8B]

[0027] 9 shows a cross-sectional slice of the memory device taken along line B-B of FIG. 8. [Figure 8C]

[0028] 9 shows a cross-sectional slice of the memory device taken along line CC of FIG. [Figure 8D]

[0029] 9 shows a cross-sectional slice of the memory device taken along line D-D of FIG. 8. [Figure 9]

[0030] 1 shows a schematic top view of a memory device after trench formation according to one or more embodiments. [Figure 9A]

[0031] 10 shows a cross-sectional slice of the memory device taken along line A-A of FIG. [Figure 9B]

[0032] 10 shows a cross-sectional slice of the memory device taken along line B-B of FIG. [Figure 9C]

[0033] 10 shows a cross-sectional slice of the memory device taken along line CC of FIG. [Figure 9D]

[0034] 10 shows a cross-sectional slice of the memory device taken along line D-D of FIG. [Figure 10]

[0035] 1 illustrates a schematic top view of a memory device after dielectric pullback, according to one or more embodiments. [Figure 10A]

[0036] 11 shows a cross-sectional slice of the memory device taken along line A-A of FIG. [Figure 10B]

[0037] 11 shows a cross-sectional slice of the memory device taken along line B-B of FIG. [Figure 10C]

[0038] 11 shows a cross-sectional slice of the memory device taken along line CC of FIG. [Figure 10D]

[0039] 11 shows a cross-sectional slice of the memory device taken along line D-D of FIG. [Figure 11]

[0040] 1 illustrates a schematic top view of a memory device after gate oxide formation, according to one or more embodiments. [Figure 11A]

[0041] 12 shows a cross-sectional slice of the memory device taken along line A-A of FIG. [Figure 11B]

[0042] 12 shows a cross-sectional slice of the memory device taken along line B-B of FIG. [Figure 11C]

[0043] 12 shows a cross-sectional slice of the memory device taken along line CC of FIG. [Figure 11D]

[0044] 12 shows a cross-sectional slice of the memory device taken along line D-D of FIG. [Figure 12]

[0045] 1 illustrates a schematic top view of a memory device after wordline formation, according to one or more embodiments. [Figure 12A]

[0046] 13 shows a cross-sectional slice of the memory device taken along line A-A in FIG. [Figure 12B]

[0047] 13 shows a cross-sectional slice of the memory device taken along line B-B of FIG. [Figure 12C]

[0048] 13 shows a cross-sectional slice of the memory device taken along line CC of FIG. [Figure 12D]

[0049] 13 shows a cross-sectional slice of the memory device taken along line D-D of FIG. [Figure 13]

[0050] 1 shows a schematic top view of a memory device after oxide filling according to one or more embodiments. [Figure 13A]

[0051] 14 shows a cross-sectional slice of the memory device taken along line A-A of FIG. [Figure 13B]

[0052] 14 shows a cross-sectional slice of the memory device taken along line B-B of FIG. [Figure 13C]

[0053] 14 shows a cross-sectional slice of the memory device taken along line CC of FIG. [Figure 13D]

[0054] 14 shows a cross-sectional slice of the memory device taken along line D-D of FIG. [Figure 14]

[0055] 1 illustrates a cross-sectional slice of a memory device after slit patterning according to one or more embodiments. [Figure 15]

[0056] 1 illustrates a cross-sectional slice of a memory device after formation of a capacitor opening according to one or more embodiments. [Figure 16]

[0057] 1 illustrates a cross-sectional view of a memory device after doping of the active area according to one or more embodiments. [Figure 17]

[0058] 17 shows an enlarged cross-sectional view of region 17 of FIG. 16. [Figure 18]

[0059] 1 illustrates an expanded cross-sectional view of a memory device after capacitor formation according to one or more embodiments. [Figure 19]

[0060] 17 illustrates an enlarged cross-sectional view of region 17 of FIG. 16 of the memory device after enlarging the capacitor opening in accordance with one or more embodiments. [Figure 20]

[0061] 1 illustrates an enlarged cross-sectional view of a memory device after forming a capacitor in the enlarged opening according to one or more embodiments. [Figure 21]

[0062] 17 shows an enlarged cross-sectional view of region 21 in FIG. 16. [Figure 22]

[0063] 1 illustrates an expanded cross-sectional view of a memory device after forming bitline openings and source / drain regions according to one or more embodiments. [Diagram 23]

[0064] 1 illustrates an expanded cross-sectional view of a memory device after forming liners and bitlines according to one or more embodiments. [Figure 24]

[0065] 1 shows a schematic diagram of a memory device in accordance with one or more embodiments of the present disclosure. [Diagram 25]

[0066] 25 shows an enlarged view of area 25 of FIG. [Figure 26]

[0067] 25 illustrates a cross-sectional view of the memory device of FIG. 24 after trench formation and replacement gate recession according to one or more embodiments. [Figure 27]

[0068] 27 illustrates an enlarged cross-sectional view of the memory device of FIG. 26 after formation of an etch stop layer according to one or more embodiments. [Figure 28]

[0069] 29 illustrates an expanded cross-sectional view of the memory device of FIG. 28 after active area formation, according to one or more embodiments. [Figure 29]

[0070] FIG. 29 illustrates an enlarged cross-sectional view of the memory device of FIG. 28 after recessing the dielectric and etch stop layers according to one or more embodiments. [Diagram 30]

[0071] 30 illustrates an expanded cross-sectional view of the memory device of FIG. 29 after wordline formation, according to one or more embodiments. [Diagram 31]

[0072] 31 illustrates an expanded cross-sectional view of the memory device of FIG. 30 after trench filling, slit patterning, and replacement gate etching to form a capacitor opening according to one or more embodiments. [Diagram 32]

[0073] 32 illustrates an expanded cross-sectional view of the memory device of FIG. 31 after removal of the etch stop layer according to one or more embodiments. [Diagram 33]

[0074] 33 illustrates an expanded cross-sectional view of the memory device of FIG. 32 after doping the active areas prior to capacitor formation, according to one or more embodiments. [Diagram 34]

[0075] 1 shows a schematic diagram of a memory device in accordance with one or more embodiments of the present disclosure. [Diagram 35]

[0076] 1 illustrates a cross-sectional view of a film stack having an etching layer according to one or more embodiments. [Diagram 36]

[0077] FIG. 36 illustrates a cross-sectional view of the memory device of FIG. 35 after recessing the sacrificial layer according to one or more embodiments. [Figure 37]

[0078] 37 illustrates a cross-sectional view of the memory device of FIG. 36 after multiple processes for forming word lines and active areas and slit patterning according to one or more embodiments. [Figure 38]

[0079] 38 illustrates a cross-sectional view of the memory device of FIG. 37 after a replacement gate etch into the etch stop layer according to one or more embodiments. [Figure 39]

[0080] 39 illustrates a cross-sectional view of the memory device of FIG. 38 after removing the etch stop layer and doping the active area prior to capacitor formation in accordance with one or more embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011]

[0081] Before describing certain example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description as being capable of other embodiments and of being practiced or carried out in various ways.

[0012]

[0082] As used herein and in the appended claims, the terms "precursor," "reactant," "reactant gas," and the like are used interchangeably to refer to any gas species capable of reacting with the substrate surface.

[0013]

[0083] As used herein, the term "Dynamic Random Access Memory" or "DRAM" refers to a memory cell that stores data bits by storing a packet of charge (i.e., a binary 1) or no charge (i.e., a binary 0) on a capacitor. The charge is gated onto the capacitor through an access transistor and sensed by looking at the voltage perturbation created by turning on the same transistor and dumping the charge packet onto the interconnect line on the transistor output. Thus, a single DRAM cell is made with one transistor and one capacitor. A DRAM device is formed of an array of DRAM cells.

[0014]

[0084] Traditionally, DRAM cells have placed high work function metal structures in a buried word line structure. In DRAM devices, bit lines are formed in a metal level above the substrate, while word lines are formed in a polysilicon gate level at the surface of the substrate. In buried word line (bWL), the word lines are buried below the surface of the semiconductor substrate using metal as the gate electrode.

[0015]

[0085] In one or more embodiments, a memory device is provided having stacked DRAM cells, resulting in an increased bit density of the DRAM cell, which is proportional to the number of membrane pairs. The DRAM device of one or more embodiments has vertical bit lines, minimizing bit line capacitance and reducing capacitance burden on the capacitor.

[0016]

[0086] Some embodiments advantageously provide memory devices with increased device density and methods of forming memory devices with increased device density. Some embodiments provide devices in which the active areas of each unit cell are separated horizontally by an insulator between each active area. Some embodiments provide a word line to each cell in the same row and stack level connected via a bridge. In some embodiments, the bridge is smaller than the width of the gate. In some embodiments, one side of the active area is connected to a capacitor and the other side is connected to a bit line.

[0017]

[0087] Some embodiments provide memory devices and methods of forming memory devices with improved integration for fabricating 3D DRAM. In some embodiments, the length of the capacitor is controlled to eliminate or minimize variations due to the selective removal process of the sacrificial layer. In some embodiments, the length of the capacitor is longer than the gate length of the cell transistor.

[0018]

[0088] FIG. 1 illustrates a general three-dimensional structure of a 3D DRAM device 10 according to one or more embodiments of the present disclosure. The device 10 has a three-dimensional array of active regions arranged in rows, columns, and layers. In the convention used herein, the rows are referred to as the X-axis or first direction 20, the columns are referred to as the Y-axis or second direction 30, and the layers are referred to as the Z-axis or third direction 40. The angle 25 between the first direction 20 and the second direction 30 is any suitable angle ranging from 30 degrees to 150 degrees, or from 45 degrees to 135 degrees, or from 60 degrees to 120 degrees, or from 75 degrees to 105 degrees, or from 85 degrees to 95 degrees. The angle 35 between the first direction 20 and the third direction 40 is any suitable angle ranging from 30 degrees to 150 degrees, or from 45 degrees to 135 degrees, or from 60 degrees to 120 degrees, or from 75 degrees to 105 degrees, or from 85 degrees to 95 degrees. The angle 45 between the second direction 30 and the third direction 40 is any suitable angle in the range of 30 degrees to 150 degrees, or in the range of 45 degrees to 135 degrees, or in the range of 60 degrees to 120 degrees, or in the range of 75 degrees to 105 degrees, or in the range of 85 degrees to 95 degrees. In some embodiments, the angles 25, 35, and 45 are each in the range of 85 degrees to 95 degrees.

[0019]

[0089] 2A-2C show three configurations of active area 115, conductive layer 120, and bridge 130 connecting adjacent conductive layers 120. In FIG. 2A, the conductive layer 120 and bridge 130 are at the bottom of the active area 115. As used herein, the terms "top", "bottom", "upper", "lower", etc. refer to a physical orientation along the Z-axis or third direction 40 and should not be construed as limiting the scope of the present disclosure to any particular orientation relative to the normal attractive force of gravity. In FIG. 2B, the conductive layer 120 and bridge 130 are at the top of the active area 115. In FIG. 2C, the conductive layer 120 and bridge 130 are both above and below the active area 115.

[0020]

[0090] FIG. 3 shows an isometric view of a memory device 100 in accordance with one or more embodiments of the present disclosure. FIG. 4 shows an isometric schematic view of a 3D memory device 100. The device 100 shown has a total of six bit lines 170 and twelve word lines 160. A total of 36 active areas 115 are connected with the conductive layers 120 and bridges 130. The embodiment shown in FIG. 3 shows two unit cells 105 on either side of the bit line 170, with each unit cell 105 including a portion of the bit line 170. Each of the unit cells 105 in some embodiments stores data independently.

[0021]

[0091] 3 and 4, memory device 100 of some embodiments comprises a plurality of active areas 115 spaced apart along a first direction 20 (as shown in FIGS. 3 and 4), a second direction 30 (as shown in FIG. 4), and a third direction 40 (as shown in FIG. 4). The active areas 115 of some embodiments comprise transistors. The active areas 115 of some embodiments comprise a stack of material layers (not shown) including charge tunneling layers, charge trapping layers, and charge blocking layers. One skilled in the art will understand the process for forming a transistor. Individual layers have not been shown for clarity.

[0022]

[0092] The multiple conductive layers 120 are arranged such that at least one conductive layer 120 is adjacent to at least one side of each of the active areas 115 along the third direction 40. When used in this manner, the term "adjacent to" means next to or in direct contact with the described component, or there is a minimum number of components or distance between the described components. For example, the conductive layer 120 shown in FIG. 3 is adjacent to the active area 115 with a gate oxide 140 layer between them.

[0023]

[0093] In some embodiments, at least some of the active regions 115 have one conductive layer 120 adjacent thereto, as shown in Figures 2A, 2B, and 4. In some embodiments, as shown in Figures 2C and 3, each of the active regions 115 has a conductive layer 120 on either side of the active region 115 along the third direction. When used in this manner, the placement of components along a particular direction means that the described components are aligned along that direction. For example, as shown in Figure 3, conductive layers 120 on either side of the active region 115 means that the conductive layers 120 are aligned with the active region 115 along the third direction 40 (the Z-axis direction).

[0024]

[0094] The conductive bridges 130 extend along the second direction 20. The conductive bridges 130 connect the conductive layers 120 with one or more adjacent conductive layers. The conductive bridges 130 shown in FIG. 4 show connections to multiple adjacent conductive layers 120. The conductive bridges 130 form connections between the conductive layers 120 along the second direction 20, i.e., the Y-axis direction.

[0025]

[0095] In some embodiments, a gate oxide 140 is disposed between the active region 115 and the conductive layer 120, as shown in Figure 3. The gate oxide 140 can be any suitable dielectric material, including low-k and high-k dielectric materials. In some embodiments, the gate oxide 140 comprises one or more of silicon oxide, silicon nitride, or silicon oxynitride.

[0026]

[0096] Some embodiments of the memory device 100 include a capacitor 180 on a side of the active area 115 along the first direction 20. The capacitor 180 is electrically isolated from the conductive layer 120 and the conductive bridge 130. In other words, the capacitor 180 is not in direct contact with the conductive layer 120 or the conductive bridge 130.

[0027]

[0097] In some embodiments, the capacitor 180 comprises a bottom electrode 186, a high-k dielectric 184, and a top electrode 182. The bottom electrode 186 is in contact with the active region 115. The high-k dielectric 184 is adjacent to the bottom electrode 186 and is on the opposite side of the bottom electrode 186 from the active region 115. The top electrode 182 is adjacent to the high-k dielectric 184 and is on the opposite side of the bottom electrode 186 from the active region 115. In some embodiments, the high-k dielectric 184 is in direct contact with the bottom electrode 186. In some embodiments, the top electrode 182 is in direct contact with the high-k dielectric 184.

[0028]

[0098] In some embodiments, a doped layer 117 is between the active region 115 and the bottom electrode 186 along the first direction 20. The doped layer 117 may be any suitable material known to those of skill in the art. In some embodiments, the doped layer 117 includes titanium nitride.

[0029]

[0099] In some embodiments, active area 115 includes source / drain regions 119 adjacent bitlines 170. Source / drain regions 119 may be formed by any suitable technique known to those of skill in the art.

[0030]

[0100] In some embodiments, memory device 100 further comprises a bitline 170 extending along third direction 40. Bitline 170 is adjacent to active area 115 spaced apart along third direction 40 (as shown in FIG. 4 ). In some embodiments, bitline 170 is in direct contact with active area 115. In some embodiments, bitline 170 is separated from active area 115 by a conductive material.

[0031]

[0101] For uniformity of measurements and size relationships, the length of any given component is measured along a first direction 20 (X-axis direction), the width is measured along a second direction 30 (Y-axis direction), and the height is measured along a third direction 40 (Z-axis direction).

[0032]

[0102] In some embodiments, the length of the active region 115 along the first direction 20 is in the range of 50 nm to 300 nm, or in the range of about 75 nm to about 200 nm, or in the range of about 100 nm to about 150 nm, or in the range of about 110 nm to about 130 nm. In some embodiments, the source / drain region 119 is located at an end of the active region 115 adjacent to the bit line 170, and the source / drain region 119 is included in the entire length of the active region 115. In some embodiments, the doped layer 117 is located at an end of the active region 115 adjacent to the capacitor 180, and the doped layer 117 is included in the entire length of the active region. In some embodiments, both the doped layer 117 and the source / drain region 119 are included in the length of the active region 115.

[0033]

[0103] In some embodiments, the width of the active region 115 along the second direction 30 is in the range of 50 nm to 300 nm, or in the range of about 75 nm to about 200 nm, or in the range of about 100 nm to about 150 nm, or in the range of about 110 nm to about 130 nm.

[0034]

[0104] In some embodiments, the length of the capacitor 180 along the first direction 20 is in the range of 200 nm to 1500 nm, or in the range of about 300 nm to about 1000 nm, or in the range of about 400 nm to about 750 nm, or in the range of about 450 nm to about 550 nm. In some embodiments, the width of the capacitor 180 along the second direction 30 is in the range of 50 nm to 300 nm, or in the range of about 75 nm to about 200 nm, or in the range of about 100 nm to about 150 nm, or in the range of about 110 nm to about 130 nm.

[0035]

[0105] In some embodiments, the length of the conductive layer 120 along the first direction 20 is in the range of 50 nm to 200 nm, or in the range of 75 nm to 150 nm, or in the range of 90 nm to 125 nm. In some embodiments, the width of the conductive layer 120 along the second direction 30 is in the range of 40 nm to 250 nm, or in the range of 50 nm to 200 nm, or in the range of 75 nm to 150 nm, or in the range of 90 nm to 125 nm.

[0036]

[0106] In some embodiments, the conductive layer 120 is spaced apart from the bit line 170 along the first direction 20. In one or more embodiments, the space between the conductive layer 120 and the bit line 170 along the first direction 20 is in the range of 5 nm to 20 nm, or in the range of 8 nm to 15 nm, or about 10 nm. In some embodiments, the conductive layer 120 is spaced apart from the capacitor 180 along the first direction 20. In one or more embodiments, the space between the conductive layer 120 and the capacitor 180 along the first direction 20 is in the range of 5 nm to 20 nm, or in the range of 8 nm to 15 nm, or about 10 nm.

[0037]

[0107] In some embodiments, the conductive bridge 130 has a length along the first direction 20 in the range of 5 nm to 180 nm, or in the range of 5 nm to about 180 nm, or in the range of 10 nm to 150 nm, or in the range of 15 nm to 100 nm, or in the range of 20 nm to 80 nm, or in the range of 30 nm to 70 nm, or in the range of 40 nm to 60 nm. In some embodiments, the conductive bridge 130 has a length that is shorter than the length of the active region 115. In some embodiments, the conductive bridge 130 has a length that is shorter than the length of the conductive region 120. In some embodiments, the length of the conductive bridge 130 along the first direction 20 is in the range of 10% to 90% of the length of the conductive layer 120. In some embodiments, the length of the conductive bridge 130 along the first direction 20 is in the range of 20% to 80%, or 30% to 70%, or 40% to 60% of the length of the conductive layer 120.

[0038]

[0108] In some embodiments, the width of the conductive bridge 130 along the second direction 30 is in the range of 50 nm to 200 nm, or in the range of 60 nm to 150 nm, or in the range of 70 nm to 125 nm, or in the range of 90 nm to 110 nm. The width of the conductive bridge 130 in some embodiments is the same as the spacing between the rows of unit cells 105.

[0039]

[0109] In some embodiments, the bitlines 170 have a length along the first direction 20 in the range of 50 nm to 150 nm, or in the range of 60 nm to 130 nm, or in the range of 70 nm to 110 nm, or in the range of 75 nm to 90 nm. In some embodiments, the bitlines 170 have a width along the second direction 30 in the range of 50 nm to 150 nm, or in the range of 60 nm to 130 nm, or in the range of 70 nm to 110 nm, or in the range of 75 nm to 90 nm.

[0040]

[0110] In some embodiments, each layer of unit cell 105 has a height along third direction 40 in the range of 10 nm to 50 nm, or in the range of 15 nm to 30 nm, or in the range of 20 nm to 25 nm.

[0041]

[0111] In some embodiments, memory device 100 includes pairs of active areas spaced apart in first direction 20. Figure 3 illustrates an embodiment having a pair of active areas 115 on either side of bit line 170 along first direction 20. In other words, in some embodiments, multiple bit lines 170 extend along third direction 40 between pairs of active areas 115 spaced apart in first direction 20. As shown in Figure 3, bit line 170 and two active areas 115 (forming a pair of active areas) are aligned along first direction 20 (X-axis direction).

[0042]

[0112] Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of exemplary embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are expected. Thus, exemplary embodiments should not be construed as limited to the particular shapes of regions illustrated herein, but may include variations in shapes that result from manufacturing, for example.

[0043]

[0113] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which a film treatment is performed during a manufacturing process. For example, substrate surfaces on which treatment may be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be subjected to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to film treatment directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film treatment steps may be performed on an underlayer formed on the substrate as disclosed in more detail below. The term "substrate surface" is intended to include such underlayers as the context indicates. Thus, for example, when a film / layer or partial film / layer is deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface. In some embodiments, the substrate comprises one or more of an insulator, a metallization layer, or peripheral circuitry. In the illustrated embodiment, for example, the substrate comprises an insulator.

[0044]

[0114] 5-19 illustrate one or more methods for forming the memory device 100 shown in FIGS. 3 and 4. For ease of explanation, each of FIGS. 6-13 is divided into five views. Each of the numbered views, those without an accompanying letter (e.g., FIG. 6), shows a view looking down a third direction 40 (Z-axis) in a plane formed by a first direction 20 (X-axis) and a second direction 30 (Y-axis). Each of the "A" views (e.g., FIG. 6A) and "B" views (e.g., FIG. 6B) show the electronic device looking along a second direction 30 (Y-axis) in a plane formed by the first direction 20 (X-axis) and a third direction 40 (Z-axis). The "A" views are slices of the device of the corresponding numbered view taken along line A-A. The "B" views are slices of the device of the corresponding numbered view taken along line B-B. A "C" view (e.g., FIG. 6C) and a "D" view (e.g., FIG. 6D) show the electronic device looking along the first direction 20 (X-axis) in the plane formed by the second direction 30 (Y-axis) and the third direction 40 (Z-axis). The "C" view is a slice of the device of the corresponding numbered view taken along line C-C. The "D" view is a slice of the device of the corresponding numbered view taken along line D-D. Each of FIGS. 14-19 shows a view of the electronic device similar to the "B" views of FIGS. 6-13. The examples of FIGS. 14-19 show a slice of the electronic device looking along the second direction 30 (Y-axis) in the plane formed by the first direction 20 (X-axis) and the third direction 40 (Z-axis).

[0045]

[0115] 5 shows a substrate 200 having formed thereon a stack of layers 201. The layers of stack 201 are generally formed in a plane formed by a first direction (X-axis) and a second direction (Y-axis) with a thickness (shown from top to bottom on a printed page) along the third direction (Z-axis), with each layer being at a higher height along the third direction 40 (Z-axis) than the layer below.

[0046]

[0116] The stack of layers 201 shown includes a sacrificial layer 202 having alternating channel layers 204 and insulator layers 206. In the embodiment shown, each of the channel layers 204 is sandwiched between sacrificial layers 202. During the process, the active area 115 will be positioned where the channel layers 204 are, and the sacrificial layers 202 will be replaced with word lines 125 comprised of conductive layers 120 and bridges 130. If there are sacrificial layers 202 above and below the channel layer 204, there will be word lines 125 both above and below the active area 115, as shown in FIG. 3. If the channel layer 204 has sacrificial layers 202 only below the active area 115, one word line can be formed below the active area 115, as shown in FIG. 4.

[0047]

[0117] 6 and 6A-6D show the electronic device after patterning the stack 201 to form a separator membrane stack 260 and a pair of pre-bridge stacks 261. The separator membrane stack 260 extends along a first direction 20 (X-axis) as shown in FIGS. 6, 6B, and 6D. When used in this manner, the term "extends along" means that the longer axis of the described component is the described axis or direction. For example, extending along a first direction means that the component has a longer axis in the X-direction. In a stack of films, the longer axis is considered for the individual films rather than the entire stack of films, which may be much larger than the eight layers shown.

[0048]

[0118] The prebridge stacks 261 are formed on either or both sides 265 of the separator stack 260 and extend along the second direction 30 (Y-axis). The prebridge stacks 261 create openings 263 between the prebridge stacks 261 and openings 264 on the outside of the prebridge stack along the first direction 20 (X-axis). The openings 264 form gaps along the second direction 30 (Y-axis) between the separator stack 260 and adjacent separator stacks.

[0049]

[0119] Patterning may be performed by any suitable technique known to one of skill in the art. For example, in some embodiments, patterning the stack 201 includes forming a patterned hard mask (not shown) on top of the stack 201 and then etching (e.g., anisotropically etching) the film stack 201 through openings in the patterned hard mask. The top view shown in FIG. 6 shows the device after etching leaves a pattern 262 in the insulating layer 206. The patterned hard mask of some embodiments is a negative of the pattern formed such that the open areas in the hard mask result in removal of the film stack.

[0050]

[0120] The pair of film stacks 261 are separated along the first direction 20 (X-axis) to generate an opening 263 between the pair of film stacks 261. In some embodiments, a patterning process generates an opening 264 outside the pair of film stacks 261. One skilled in the art will recognize that the illustrated process separates the pair of film stacks 261 in the first direction 20 (X-axis). The width of the film stack 261 along the first direction 20 (X-axis) in some embodiments is approximately the same as the width of the bridge 160. The distance between the pair of film stacks 261, which is the width of the opening 263 along the first direction 20, is the distance between the bridges 160 along the first direction 20.

[0051]

[0121] 7 and 7A-7D show the electronic device after removing the channel layer 204 from the prebridge stack 261 and recessing the channel layer 204 into the separator stack 260 to form a recessed channel layer 270 in the separator stack 260. The removal process is performed through the openings 263 and 264, leaving an opening 271 where the channel layer 204 was removed. The channel layer 204 can be removed by any suitable technique known to those skilled in the art. In some embodiments, the removal of the channel layer 204 is performed by a dry process or an oxidation process. FIG. 7A shows that an etching process removes the channel layer 204 from the prebridge stack 261 to form an opening 271 in the prebridge stack 261. FIGS. 7C and 7D show that an etching process removes a portion of the channel layer 204 to form a recessed channel layer 270 with an opening 271 in the side 265 of the separator stack 260. The sides 265 of the separator laminate 260 are shown in Figure 7D as dashed lines. The central portion of the separator laminate 260 shown in Figure 7B remains unchanged.

[0052]

[0122] The process of recessing the channel layer 204 forms the inner edge of the active area 115, as shown in Figure 3. As used in this manner, the term "inner edge" means the edge of the active area 115 closest to the bitline 170 along the first direction 20. The term "outer edge" means the edge of the active area 115 furthest from the bitline 170 along the first direction 20. The distance between the inner edge and the outer edge of the active area 115 is the length of the active area 115.

[0053]

[0123] 8 and 8A-8D show the electronic device after filling the openings 264, 265, 271 with a dielectric material 280. In some embodiments, the dielectric material is an oxide fill. The dielectric material 280 (also referred to as an oxide fill) is deposited through the openings 264, 265, filling the fill openings 271. In some embodiments, the dielectric material 280 is deposited with an overburden and then planarized so that the dielectric material is substantially flush with the top surface of the separator stack 260. In one or more embodiments, the oxide fill comprises one or more of an oxide, a carbon-doped oxide, silicon oxide (SiO), porous silicon dioxide (SiO2), silicon oxide (SiO), silicon nitride (SiN), silicon oxide / silicon nitride, a carbide, an oxycarbide, a nitride, an oxynitride, an oxycarbonitride, a polymer, a phosphosilicate glass, a fluorosilicate (SiOF) glass, or an organosilicate glass (SiOCH). Dielectric material 280 may be deposited by any technique known to those of skill in the art, including, but not limited to, atomic layer deposition or chemical vapor deposition.

[0054]

[0124] 9 and 9A-9D show the electronic device after forming a trench 290 in the separator stack 260. The trench 290 is formed along the second direction 30 (Y-axis) and is disposed between a pair of pre-bridge stacks 261 along the first direction 20. The trench 290 separates the separator stack 260 into two separator stack sections 260a, 260b. In the following description, unless otherwise specified, the separator stack 260 is used to describe both separator stack sections 260a, 260b. Eventually, the bit line 170 will be formed in the trench 290 to form two unit cells 105. The trench 290 may be formed by any suitable technique known to those skilled in the art. For example, in some embodiments, a patterned mask is applied, followed by etching.

[0055]

[0125] The C-C line shown in Figures 10 to 13 is different from that in Figures 6 to 9. The parts shown in Figures 6 to 9 remain unchanged in the process described in Figures 10 to 13. Figures 10 and 10A-10D show the electronic device after removing a portion of the sacrificial layer 202 from the separator stack 260. The sacrificial layer 202 is removed through the trench 290 to form a recessed sacrificial layer 300. By recessing the sacrificial layer 202 to form the recessed sacrificial layer 300, at least one surface 301 and an end face 303 of the recessed channel layer 270 are exposed. In the illustrated embodiment, the recessed channel layer 270 has two surfaces 301, 302 and an end face 303. When the sacrificial layer 202 is recessed, the surface 305 of the sacrificial layer 202 moves away from the trench 290 in the first direction 20 to form a word line opening 304. The wordline opening 304 is bounded by a surface 305 of the recessed sacrificial layer 300, surfaces 301, 302 of the recessed channel layer 270, and the trench 290. The sacrificial layer 202 may be recessed by any suitable technique known to those skilled in the art.

[0056]

[0126] 11 and 11A-11D show the electronic device after forming the gate oxide layer 140 in the word line opening 304. The gate oxide layer 140 is deposited through the trench 290 by any suitable technique known to one of ordinary skill in the art. The illustrated embodiment shows the gate oxide layer 140 as a conformal layer having a uniform shape. However, one of ordinary skill in the art will recognize that this is merely for purposes of illustration and that the gate oxide layer 140 can be formed isotropically such that the gate oxide layer 140 has a rounded appearance. In some embodiments, the gate oxide layer 140 is selectively deposited as a conformal layer on the surface of the recessed channel layer 270. The gate oxide layer 140 of some embodiments is formed on the edge 303 of the recessed channel layer 270. In some embodiments, the gate oxide layer 140 formed on the edge 271 is removed by an anisotropic etching process to expose the edge 303 and leave the gate oxide layer 140 on the surfaces 301, 302. In some embodiments, the gate oxide 140 is formed by oxidation of the semiconductor surface.

[0057]

[0127] In one or more embodiments, the gate oxide layer 140 comprises a gate oxide material. In one or more embodiments, the gate oxide layer 140 comprises one or more of silicon oxynitride (SiON), silicon oxide, or a high-k dielectric material. The term "silicon oxide" may be used to describe the gate oxide layer 140, but one of ordinary skill in the art will recognize that the present disclosure is not limited to a particular stoichiometry. For example, the terms "silicon oxide" and "silicon dioxide" may both be used to describe a material having silicon and oxygen in any suitable stoichiometric ratio. The same is true for other materials listed in the present disclosure, such as silicon nitride, silicon oxynitride, tungsten oxide, zirconium oxide, aluminum oxide, hafnium oxide, etc.

[0058]

[0128] 12 and 12A-12D show the electronic device after deposition of optional liner 325 and conductive layer 120 in wordline opening 304. Conductive layer 120 has an outer edge 121 and an inner edge 122 that is closer to trench 290 than outer edge 121. Conductive layer 120 forms wordlines and bridges 130 in the electronic device over gate oxide layer 140. The illustrated embodiment shows optional liner 325 as a conformal layer having a uniform shape. However, one skilled in the art will recognize that this is merely for purposes of illustration and that optional liner 325 may be formed isotropically. The cross-sectional views of FIGS. 12A and 12D show bridges 130, while the views of FIGS. 12B and 12C show conductive layer 120.

[0059]

[0129] In one or more embodiments, the wordline metal 112 comprises one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh). The conductive layer 120 (wordline metal) is deposited using any one of several methods known to those skilled in the art, including, but not limited to, chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In some embodiments, the bridge section (shown in FIG. 12D) is filled with the wordline metal.

[0060]

[0130] As used herein, "atomic layer deposition" or "cyclical deposition" refers to the sequential exposure of two or more reactive compounds to deposit a layer of material on a substrate surface. A substrate or portion of a substrate is individually exposed to two or more reactive compounds introduced into a reaction zone of a processing chamber. In a time-domain ALD process, exposure to each reactive compound is separated by a time delay to allow each compound to adhere to and / or react on the substrate surface before being purged from the processing chamber. These reactive compounds are said to be sequentially exposed to the substrate. In a spatial ALD process, separate portions of the substrate surface or materials on the substrate surface are exposed to two or more reactive compounds simultaneously such that any given point on the substrate is not substantially exposed to more than one reactive compound simultaneously. As used in this specification and the accompanying claims, the term "substantially" as used in this manner means that, as will be understood by those skilled in the art, it is possible that a small portion of a substrate may be exposed to multiple reactive gases simultaneously (due to diffusion), but this simultaneous exposure is not intentional.

[0061]

[0131] In one aspect of a time-domain ALD process, a first reactive gas (i.e., a first precursor or compound A, e.g., an aluminum precursor) is pulsed into the reaction zone and then delayed for a first time. Then, a second precursor or compound B (e.g., an oxidizer) is pulsed into the reaction zone and then delayed for a second time. During each time delay, a purge gas, such as argon, is introduced into the process chamber to purge the reaction zone or otherwise remove any residual reactive compounds or reaction by-products from the reaction zone. Alternatively, the purge gas may flow continuously throughout the deposition process such that only the purge gas flows during the time delay between pulses of reactive compounds. The reactive compounds are pulsed alternately until a desired film or film thickness is formed on the substrate surface. In either scenario, the ALD process of pulsing compound A, purge gas, compound B, and purge gas is a cycle. The cycle may start with either compound A or compound B and continue with each sequence of the cycle until a film having a predetermined thickness is achieved.

[0062]

[0132] In an embodiment of a spatial ALD process, a first reactive gas and a second reactive gas (e.g., nitrogen gas) are simultaneously supplied to a reaction zone but separated by an inert gas curtain and / or a vacuum curtain. The substrate is moved relative to the gas supply such that any given point on the substrate is exposed to the first reactive gas and the second reactive gas.

[0063]

[0133] As used herein, "chemical vapor deposition" refers to a process in which a substrate surface is exposed to precursors and / or co-reagents simultaneously or substantially simultaneously. As used herein, "substantially simultaneously" refers to either simultaneous flow or a large overlap of the precursor exposures.

[0064]

[0134] Plasma enhanced chemical vapor deposition (PECVD) is widely known for depositing thin films due to its cost-effectiveness and versatility in film properties. In a PECVD process, a hydrocarbon source, such as a gas-phase or liquid-phase hydrocarbon vapor entrained in a carrier gas, is introduced into a PECVD chamber. A plasma initiating gas, typically helium, is also introduced into the chamber. A plasma is then initiated in the chamber, generating excited CH radicals. The excited CH radicals chemically combine with a surface of a substrate placed in the chamber to form a desired film thereon. The embodiments described herein in connection with a PECVD process may be implemented using any suitable thin film deposition system. Any apparatus description described herein is exemplary and should not be understood or construed as limiting the scope of the embodiments described herein.

[0065]

[0135] 13 and 13A-13D show the electronic device after filling the trench 290 with a dielectric 230. In some embodiments, the dielectric 230 forms an electrical boundary inside the wordline. The dielectric material is deposited using any one of several methods known to those skilled in the art, including but not limited to chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The dielectric material can be of the same composition as any of the other insulating materials in the electronic device. In some embodiments, the dielectric 230 is the same material as the dielectric material 280. In some embodiments, the dielectric 230 is etch selective to the dielectric material 280. In some embodiments, prior to filling the trench with the dielectric 230, the inner ends of the recessed channel layer 270 are doped to form the source / drain regions 119.

[0066]

[0136] Each of Figures 14-19 shows a view of the electronic device taken along line B-B of Figure 13. Each of these figures is a view along the second direction 30 in a slice taken in a plane formed by the first direction 20 and the third direction 40. Figure 14 shows the electronic device after forming a slit pattern 340 through the recessed sacrificial layer 300 and the recessed channel layer 270 to form a slit pattern 340. The slit pattern 340 is formed on both sides of the location where the trench 290 is filled with the dielectric 230. When used in this manner, "both sides" means that one slit is formed on one side of the dielectric 230 in the first direction 20 and the other slit is formed on the other side of the dielectric 230 in the first direction 20. The slit pattern 340 is formed on the outside of the conductive layer 120 formed in the word line opening. When used in this manner, the term "outside" means that the slit pattern 340 is formed on the opposite side of the conductive layer 120 from the dielectric 230. 14, the dielectric 230 is in the center of the drawing, the conductive layer 120 is to the left and right of the dielectric 230, and the slit patterns 340 are on both sides of the dielectric 230 and outside the conductive layer 120 at the left and right edges of the drawing. The slit patterns 340 expose the sidewalls 346 of the recessed channel layer 270 and the sidewalls 342 of the recessed sacrificial layer 300.

[0067]

[0137] FIG. 15 illustrates the electronic device after a portion of the recessed channel layer 270 has been removed through the slit pattern 340 to move the sidewalls 346 of the recessed channel layer 270 toward the conductive layer 120. This process recesses the recessed channel layer 270 from the slit pattern 340 side. The portion of the recessed channel layer 270 may be removed by any suitable technique known to one of ordinary skill in the art. By removing the portion of the recessed channel layer 270, an active area 115 and a capacitor opening 350 are formed. The active area 115 has an outer edge 116 adjacent the capacitor opening 350 and an inner edge 118 adjacent the dielectric 230. This process may be referred to as a "pull back" process. In one or more embodiments, the channel layer 270 comprises polysilicon and the process illustrated in FIG. 15 is a polysilicon pull back.

[0068]

[0138] 16 shows the electronic device after an optional gas phase doping process. The gas phase doping process forms a doped layer 117 on the outer edges of the active region 115. In some embodiments, the doping is performed during deposition of the active region material using a dopant source. For example, phosphorus doped silica glass (PSG) or boron phosphorus doped glass (BPSG) is diffused into the material. In some embodiments, the doped layer 117 is in the range of 1 to 20 nm thick (measured from the outer edge of the active region 115 toward the bitline).

[0069]

[0139] FIG. 17 illustrates an expanded view of region 17 of FIG. 16 showing a capacitor opening 350. As shown in FIG. 18, in some embodiments, a capacitor 180 is formed in the capacitor opening 350 adjacent to the recessed channel layer 115. In some embodiments, the capacitor 180 is formed by first depositing a bottom electrode 186 in the capacitor opening 350. The bottom electrode 186, also referred to as a bottom electrode or bottom contact, can be formed by any suitable technique known to those skilled in the art. In some embodiments, the bottom electrode 186 is a conformal film deposited by atomic layer deposition. In one or more embodiments, the bottom electrode 186 comprises a material selected from one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt). In some embodiments, the capacitor includes a bottom electrode, a capacitor dielectric, and a top electrode. In some embodiments, the capacitor includes a bilayer, for example a silicon germanium bilayer in addition to the top electrode and titanium nitride.

[0070]

[0140] A high-k dielectric 184 is deposited on the bottom electrode 186 in the capacitor opening 350. The high-k dielectric 184 in some embodiments includes hafnium oxide. In some embodiments, the high-k dielectric 184 is deposited as a conformal film by atomic layer deposition. A top electrode 182 is formed within the capacitor opening 350 within the high-k dielectric 184. The top electrode 182, also referred to as a top contact or top electrode, can be formed by any suitable technique known to those skilled in the art. In one or more embodiments, the top electrode 182 comprises a conductive material including one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt). In some embodiments, a dielectric 188 is deposited to fill any open space remaining in the capacitor opening 350 after formation of the top electrode 182. The dielectric 188 in some embodiments separates individual unit cells from adjacent unit cells to prevent shorting.

[0071]

[0141] FIG. 19 illustrates another embodiment of the present disclosure, region 17, where capacitor opening 350 is widened prior to forming the capacitor to form widened capacitor opening 351. Capacitor opening 350 may be widened by any suitable technique known to one of ordinary skill in the art. After capacitor opening 350 is widened, capacitor 180 is formed therein, as shown in FIG. 20. The capacitor opening of some embodiments is widened by a percentage of the thickness of the insulating layer (layer between active areas). In some embodiments, the capacitor is widened by an amount ranging from 10% to 80% of the thickness of the insulating layer (measured as a combination of top and bottom widening). In some embodiments, the capacitor is widened by an amount ranging from 20% to 75%, or 30% to 60%. The capacitor opening 350 of some embodiments is widened in the second direction 30 (Y-axis) and the third direction 40 (Z-axis). In some embodiments, the capacitor opening 350 is widened using a dilute HF (about 1% HF in water) wet etch. In some embodiments, widening the capacitor opening results in an increase in capacitor surface area in the range of 1% to 85%, or in the range of 5% to 80%, or in the range of 10% to 75%, or in the range of 20% to 60%.

[0072]

[0142] FIG. 21 shows a partial view of region 21 of FIG. 16. FIG. 22 shows the electronic device after forming bitline holes 360 (also referred to as bitline openings) between the recessed channel layers that form the active region 115. In some embodiments, the electronic device is patterned to form a plurality of bitline holes 360. The bitline holes 360 may be formed by any suitable process known to one of ordinary skill in the art. In some embodiments, the bitline holes 360 are formed by depositing a patterned hard mask and etching the dielectric 230 through the hard mask.

[0073]

[0143] In the illustrated embodiment, source / drain regions 119 are formed on the inner ends of active region 115. In some embodiments, source / drain regions 119 are formed by exposing end surface 303 to a dopant gas. Source / drain regions 119 may be formed by any suitable technique known to those of skill in the art.

[0074]

[0144] Figure 23 shows a partial view of region 21 of Figure 16 after depositing bitline 365 in bitline hole 360. In the embodiment shown, bitline 365 includes an optional bitline liner 370 (also called a bitline barrier layer), and bitline metal 375.

[0075]

[0145] The optional bitline liner 370 may be made of any suitable material deposited by any suitable technique known to one of skill in the art. In some embodiments, the bitline liner 370 is conformally deposited within the plurality of bitline holes 360 and deposited on the exposed surface of the dielectric 231 and the edge surface 303 (or exposed surface) of the active material 115. In the illustrated embodiment, the bitline liner 370 is deposited on the source / drain region 119 at the inner end of the active material 115. The bitline liner 370 may be any suitable material, including, but not limited to, titanium nitride (TiN) or tantalum nitride (TaN). In some embodiments, the optional bitline liner 370 comprises or consists essentially of titanium nitride (TiN). When used in this manner, the term "consist essentially of" means that the composition of the film is greater than or equal to about 95%, 98%, 99%, or 99.5% of the described species. In some embodiments, optional bitline liner 370 includes or consists essentially of tantalum nitride (TaN). In some embodiments, bitline liner 370 is a conformal layer. In some embodiments, bitline liner 370 is deposited by atomic layer deposition.

[0076]

[0146] In some embodiments, the bitline metal 375 includes or consists essentially of one or more of tungsten silicide (WSi), tungsten nitride (WN), or tungsten (W). The bitline metal 375 may be deposited by any suitable technique known to one of skill in the art and may be any suitable material. In one or more embodiments, forming the bitline metal 375 further includes forming a bitline metal seed layer (not shown) prior to depositing the bitline metal 375.

[0077]

[0147] Some embodiments of the present disclosure are directed to electronic devices incorporating an etch stop layer (ESL) for improved process control. Figures 24-33 show cross-sectional schematic views of an electronic device similar to that shown in Figure 3. Those skilled in the art will recognize the similarities between the processes described in Figures 26-33 and those described in Figures 5-23. The view in Figure 24 is taken through a plane formed by the first direction 20 (X-axis) and the third direction 40 (Z-axis) at a location along the second direction 30 (Y-axis). Figure 25 shows an enlarged view of region 25 from Figure 24.

[0078]

[0148] In the illustrated embodiment, the etch stop layer 410 is adjacent to the outer edge 116 of the active region 115. The etch stop layer 410 is adjacent to the bottom electrode 186 of the capacitor along the third direction 40 (Z-axis) and adjacent to the outer edge 116 of the active region 115 along the third direction 40 (Z-axis). The etch stop layer 410 of some embodiments is adjacent to the doped layer 117 along the third direction 40 (Z-axis) and adjacent to the outer edge 116 of the active region 115 along the third direction 40 (Z-axis). In some embodiments, the etch stop layer 410 is adjacent to the doped layer 117 and the bottom electrode 186 of the capacitor along the third direction 40 (Z-axis). In some embodiments, the etch stop layer 410 is substantially absent from the region between the outer edge 116 of the active region 115 (and / or doped region 117) and the capacitor 186 along the first direction 20. When used in this manner, the term "substantially absent" means that the etch stop layer 410 occupies less than 25%, 20%, 10%, or 5% of the area between the active region 115 and the bottom electrode 186 along the first direction 20 (X-axis).

[0079]

[0149] One or more embodiments of the present disclosure are directed to a method of fabricating the electronic device of Figure 24. Figure 26 illustrates an embodiment of an electronic device in which a trench 290 is formed through an alternating stack of sacrificial layers 202 and replacement channel layers 420. The replacement channel layers 420 in some embodiments are the same material as the channel layers 204 shown in Figures 5-23. In some embodiments, the replacement channel layers 420 are a different material than the channel layers 204 shown in Figures 5-23. The material of the replacement channel layers 420 does not affect the process flows described.

[0080]

[0150] After forming the trench 290, as shown in FIG. 26, the replacement channel layer 420 is recessed to form a recessed replacement channel layer 420 as shown, and to form an opening 425 between adjacent sacrificial layers 202 (if there are two) in the third direction 40 (Z-axis). The replacement channel layer is recessed to a depth sufficient to form a length of active material in the final electronic device. In the illustrated embodiment, the opening 425 is bounded along the first direction 20 (X-axis) by the recessed replacement channel layer 420 and inner edge 422 of the trench 290, and bounded above and below along the third direction 40 (Z-axis) by the exposed surface 203 of the sacrificial layer 202.

[0081]

[0151] After forming the opening 425, an etch stop layer 410 is formed on the exposed sacrificial surface 203 of the sacrificial layer 202 and on the inner edge 422 of the recessed replacement channel layer 420, as shown in FIG. 27. A portion 432 of the etch stop layer 410 is on the surface 203 of the sacrificial layer 202, and an end wall 411 of the etch stop layer 410 is formed on the inner edge 422 of the recessed replacement channel layer 420. The opening 425 remains intact and is bounded by the etch stop layer 410. The size of the opening 425 in some embodiments increases, decreases, or remains the same after forming the etch stop layer 410. The etch stop layer 410 may be any suitable material formed by any suitable process known to one of ordinary skill in the art. The etch stop layer 410 in some embodiments is a material that is etch selective to the sacrificial layer 202 and the replacement channel layer 420. In some embodiments, the etch stop layer 410 is a conformal film deposited by atomic layer deposition.

[0082]

[0152] In some embodiments, the openings 425 are widened by any suitable technique known to one of skill in the art prior to depositing the etch stop layer 410. The size of the openings 425 can be tailored to provide active material 115 with predetermined dimensions.

[0083]

[0153] Figure 28 shows the electronic device of Figure 27 after depositing active material 115 in opening 425 in etch stop layer 410. The active material 115 forms a pair of channel layers 204 on either side of trench 290 along first direction 20 (X-axis).

[0084]

[0154] FIG. 29 shows the electronic device of FIG. 28 after removing a portion of the sacrificial layer 202 to form a recessed sacrificial layer 300 similar to that shown in FIG. 10B.

[0085]

[0155] In some embodiments, the sacrificial layer 202 is recessed to a depth less than the depth to which the replacement channel layer 420 was recessed prior to forming the etch stop layer 410. In some embodiments, the sacrificial layer 202 is recessed to a depth less than sufficient to avoid exposing the end wall 411 portion of the etch stop layer 410 on the surface 422 of the recessed replacement channel layer 420. In some embodiments, the surface 305 of the recessed sacrificial layer 300 is in the range of 5 nm to 20 nm closer to the trench 290 along the first direction 20 (X-axis) than the end wall 411 of the etch stop layer 410. In some embodiments, the surface 305 of the recessed sacrificial layer 300 is in the range of 5 nm to 20 nm closer to the trench 290 along the first direction 20 (X-axis) than the outer edge 116 of the active material 115.

[0086]

[0156] 29, a portion 432 of the etch stop layer 410 on the surface 203 of the sacrificial layer 202 is removed. In some embodiments, the portion 432 of the etch stop layer 410 is removed simultaneously with recessing the sacrificial layer 202 to form the recessed sacrificial layer 300. In some embodiments, the removal of the portion 432 of the etch stop layer 410 is performed separately from recessing the sacrificial layer 202, thereby forming the recessed sacrificial layer 300, followed by the removal of the portion 432 of the etch stop layer 410.

[0087]

[0157] FIG. 30 shows the electronic device of FIG. 29 after forming a gate oxide 140 on the active material 115, forming an optional liner 325 in the opening 435 in which the recessed sacrificial layer 300 was formed, and forming a conductive layer 120 in the optional liner 325.

[0088]

[0158] Figure 31 shows the electronic device of Figure 30 after filling the trenches 290 with dielectric 230, forming the slit pattern 340, and removing the replacement channel layer 420 through the slit pattern 340 in one or more processes similar to those described with respect to Figures 13 to 16. After removing the replacement channel layer 420, a capacitor opening 350 is formed. An inner edge 352 of the capacitor opening 350 (the edge furthest from the slit pattern) is bounded by an end wall 431 of the etch stop layer 410.

[0089]

[0159] 32 illustrates the electronic device of FIG. 31 after removing the end wall 411 of the etch stop layer 410 from the inner edge 352 of the capacitor opening 350. By removing the etch stop layer 410, the outer edge 116 of the active material 115 is exposed. In some embodiments, portions of the etch stop layer 410 remain above and below (with respect to the third direction 40) the inner edge 352 of the capacitor opening 350. In some embodiments, portions of the etch stop layer 410 straddle the interface between the outer edge 116 of the active material 115 and the capacitor opening 350.

[0090]

[0160] Figure 33 shows the electronic device of Figure 32 after doping the outer end 116 of the active material 115 through the capacitor opening 350 to form the doped layer 117. The process in some embodiments proceeds as shown and described with respect to Figures 16-23, leaving the etch stop layer 410 in the final device as shown in Figure 24. In some embodiments, the capacitor opening 350 is widened in a similar manner as described with respect to Figures 19 and 20.

[0091]

[0161] FIG. 34 illustrates an electronic device 500 according to one or more embodiments of the present disclosure. The device 500 is similar to the device of FIG. 3 with the addition of an etch stop material 410 formed along the third direction 40 (Z-axis). The etch stop material 410 extends through the device 500 at a location equivalent to the inner edge 352 of the capacitor opening 350. The etch stop material 410 in some embodiments includes a dielectric material to prevent electrical shorting. The etch stop material 410 passes through the insulator layer 206 and the recessed sacrificial layer 300. In some embodiments, the etch stop material 410 interrupts the continuity of the insulator layer 206 and the recessed sacrificial layer 300 along the first direction 20 (X-axis).

[0092]

[0162] Some embodiments of the present disclosure are directed to a method of forming an electronic device 500. Figures 35-39 provide cross-sectional views illustrating a method according to one or more embodiments. The process of forming device 500 is similar to that shown in Figures 5-23, with certain points along the process being shown to point out differences.

[0093]

[0163] 35 illustrates a film stack similar to that of FIG. 5 with an etch stop layer (ESL) opening 405 formed through the stack along a third direction 40 (Z-axis). The ESL opening 405 is filled with an etch stop material 410. The etch stop material 410 may be any suitable material deposited by any suitable technique known to one of ordinary skill in the art. In some embodiments, as shown, the ESL openings 405 are formed on either side in the first direction 20 (X-axis) of the point where the trench 290 is formed.

[0094]

[0164] Figure 36 shows the electronic device of Figure 35 after processing similar to that of Figures 9, 9A-9D, 10, and 10A-10D. The trench 290 of some embodiments is formed approximately in the middle of the two ESL openings 405 along the first direction 20 (X-axis).

[0095]

[0165] The sacrificial layer 202 is etched to form the recessed sacrificial layer 300. In some embodiments, the etching process moves the surface 305 of the recessed sacrificial layer 300 away from the trench 290 a distance that is less than the distance from the trench 290 to the ESL opening 405. In some embodiments, the etching process moves the surface 305 to the etch stop material 410.

[0096]

[0166] Figure 37 shows the electronic device of Figure 36 after processing similar to that of Figures 11-13 (including subfigures A-D). Conductive layer 120, optional liner 325, gate oxide 140, and dielectric 230 are formed. The illustrated embodiment also includes forming source / drain regions 119 on the inner ends of active material 115.

[0097]

[0167] Figure 38 shows the electronic device of Figure 37 after processing similar to that of Figures 14-16 (including subfigures A-D). A slit patterning 340 and etching process forms a capacitor opening 350. The recessed channel layer sidewalls 346, which are the inner walls of the capacitor opening 350, are moved down to the etch stop material 410 in the ESL opening 405.

[0098]

[0168] Figure 39 shows the electronic device of Figure 38 after removal of the etch stop material 410 through the capacitor opening 350. The outer ends 116 of the active material 115 are optionally doped to form doped regions 117. The process flow of some embodiments concludes with the formation of a capacitor according to a process similar to that described in Figures 17-20, and the formation of bitlines 375 according to a process similar to that described in Figures 21-23.

[0099]

[0169] Spatially relative terms, such as "below," "lower," "lower side," "up," "above," "upper," and the like, may be used herein to facilitate describing the relationship of one element or feature to another element(s) or feature(s) as depicted in the drawings. It should be understood that the spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if a device in the drawings were turned over, an element described as "below" or "below" the other element or feature would be oriented "above" the other element or feature. Thus, the exemplary term "below" may include both an orientation above and below. The device may be otherwise oriented (rotated 90 degrees or to other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0100]

[0170] In the context of describing the materials and methods described herein (particularly in the context of the claims below), the use of the terms "a" and "an" as well as "the" and similar referents are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. Recitation of ranges of values ​​herein is merely intended to serve as a shorthand method of individually referring to each individual value falling within the range, unless otherwise indicated herein, and each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein may be performed in any suitable order, unless otherwise indicated herein or clearly contradicted by context. The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended merely to better describe the materials and methods and does not limit the scope, unless otherwise claimed. No language in the specification should be construed as indicating any element not claimed as essential to the practice of the disclosed materials and methods.

[0101]

[0171] Throughout this specification, references to "one embodiment," "certain embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of "in one or more embodiments," "in a particular embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification do not necessarily refer to the same embodiment of the disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0102] Although the disclosure of this specification has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the invention. Therefore, it is intended that the present invention cover modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. A method of forming a memory device, comprising: patterning a stack of films including a sacrificial layer and a channel layer to form a pair of pre-bridge stacks separated along a first direction and a separation film stack extending along the first direction, wherein the pre-bridge stacks are formed on both sides of the separation film stack along a second direction, generating openings between the pre-bridge stacks and openings outside the pre-bridge stacks along the first direction, and generating a gap between the separation film stack and an adjacent film stack along the second direction; removing the channel layer from the pre-bridge stack and recessing the channel layer into the separation film stack through the opening to form a recessed channel layer in the separation film stack; filling the opening and the recessed channel layer with a dielectric; forming a trench in the separation film stack along the second direction, the trench being formed between the pair of pre-bridge stacks along the first direction; removing a portion of the sacrificial layer from the separation film stack through the trench to form a recessed sacrificial layer having a recessed sacrificial layer surface and a word line opening, and exposing the surface of the channel layer; forming a gate oxide layer in the word line opening on the surface of the channel layer exposed through the trench; depositing a conductive layer in the word line opening on the gate oxide layer; filling the trench with a dielectric; forming a slit pattern through the sacrificial layer and the channel layer, the slit pattern being formed outside the conductive layer in the word line opening on both sides of the position where the trench is formed, and the slit pattern exposing sidewalls of the channel layer and sidewalls of the sacrificial layer; removing a portion of the channel layer through the slit pattern to form a capacitor opening exposing the surfaces of the sacrificial layer and the recessed channel layer; and forming a capacitor in the capacitor opening adjacent to the recessed channel layer.

2. The method according to claim 1, further comprising widening the capacitor opening before forming the capacitor.

3. The capacitor is formed by depositing a lower electrode on the surface of the sacrificial layer and the recessed channel layer exposed by the capacitor opening, depositing a high-k dielectric on the lower electrode, and depositing an upper electrode on the high-k dielectric, according to the method of claim 1.

4. further comprising opening bit line holes penetrating the dielectric between the plurality of recessed channel layers, and depositing bit lines in the bit line holes, according to the method of claim 3.

5. After removing a portion of the sacrificial layer through the trench and before forming the gate oxide layer, the method further comprises forming a first sacrificial film on the recessed channel layer and the exposed surface of the sacrificial layer, depositing an active material on the first sacrificial film to form a pair of recessed channel layers, and removing a portion of the sacrificial layer and a portion of the first sacrificial film to expose the pair of recessed channel layers, according to the method of claim 1.

6. Before forming the trench between the pair of openings, the method further comprises forming a pair of ESL openings extending through the sacrificial layer and the channel layer, the pair of ESL openings being positioned outside the pair of openings, depositing an etching stop material in the ESL openings to form an etching stop layer extending through the sacrificial layer and the channel layer, according to the method of claim 1.

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