Reconfigurable processor circuit architecture

Abstract

To allow multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use.SOLUTION: A reconfigurable processing circuit disclosed herein may include input reordering queues, a multiplier shifter and a combiner network coupled to the input reordering queues, an accumulator circuit, and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS]

[0002] This application is a nonprovisional application and claims the benefit of and priority to U.S. Provisional Patent Application No. 62 / 898,452, filed September 10, 2019, entitled “Reconfigurable Arithmetic Engine,” which claims the benefit of and priority to U.S. Provisional Patent Application No. 62 / 899,025, filed September 11, 2019, entitled “Reconfigurable Processor Circuit Architecture with an Array of Fractal Cores,” which further claims priority to commonly assigned U.S. patent application Ser. No. 17 / 015,950, filed September 9, 2020, and U.S. patent application Ser. No. 17 / 015,973, filed September 9, 2020, all of which are incorporated by reference herein as if set forth in their entireties. [Background technology]

[0003] The present invention relates generally to configurable and reconfigurable computing circuits, and more particularly to configurable and reconfigurable compute engines having electronic circuits for arithmetic and logical computations.

[0004] Many existing computing systems have reached significant limits in their computing power, such as insufficient computing speed for mathematically intensive applications, including neural network calculations, digital currencies, blockchain, etc. In addition, many existing computing systems consume excessive energy (or power) and dissipate heat accordingly. For example, existing computing solutions are becoming increasingly inadequate as the need for advanced computing technology to accommodate artificial intelligence, neural networks, encryption, decryption, and other critical computing applications grows.

[0005] Thus, there is a continuing need for computing architectures that can provide high performance and energy efficient solutions for mathematically intensive applications, including, but not limited to, artificial intelligence, neural network computations, digital currencies, blockchain, encryption, decryption, Fast Fourier Transform (FFT) computations, and machine learning.

[0006] Moreover, there is a continuing need for configurable and reconfigurable computing architectures that can be configured for any of these various applications. Such configurable and reconfigurable computing architectures should be easily scalable, such as to millions or multiple processing cores, should be low latency, should be computationally and energy efficient, should be capable of processing streaming data in real time, should be reconfigurable to optimize the computing hardware for a selected application, and should be capable of massively parallel processing.

[0007] Numerous other advantages and features of the present invention will become readily apparent from the following detailed description of the invention and the embodiments thereof, from the claims and from the accompanying drawings. Summary of the Invention [Problem to be solved by the invention]

[0008] As described in more detail below, the representative apparatus, systems, and methods provide a computing architecture that can provide high performance and energy efficient solutions for mathematically intensive applications, including, but not limited to, artificial intelligence, neural network computations, digital currency, encryption, decryption, blockchain, Fast Fourier Transform (FFT) computations, and machine learning.

[0009] Moreover, the reconfigurable processors disclosed herein, as devices and systems, can be configured for any of these various applications, some such examples are described in more detail below. Such reconfigurable processors are easily scalable to millions of computational cores or the like, are low latency, computationally and energy efficient, can process streaming data in real time, are reconfigurable to optimize the computational hardware for selected applications, and are capable of massively parallel processing. For example, on a single chip, multiple reconfigurable processors can be arrayed and connected using an interconnection network to provide hundreds to thousands of computational cores per chip. Multiple such chips can then be arrayed and connected on a circuit board to provide thousands to millions of computational cores per board. Any selected number of computational cores can be implemented within a reconfigurable processor, any number of reconfigurable processors can be implemented on a single integrated circuit, and any number of such integrated circuits can be implemented on a circuit board. In this manner, a reconfigurable processor having an array of computational cores is scalable to any selected degree (subject to other constraints such as, but not limited to, routing and heat dissipation). [Means for solving the problem]

[0010] In an exemplary embodiment, a reconfigurable arithmetic circuit includes a plurality of input reordering queues, a multiplier-shifter-combiner network coupled to the plurality of input reordering queues, an accumulator circuit, and at least one control logic circuit coupled to the multiplier-shifter-combiner network and the accumulator circuit.

[0011] In a representative embodiment, such a reconfigurable arithmetic circuit may further include a configurable multiplier having a plurality of operating modes, coupled to the plurality of input reordering queues and the multiplier shifter combiner network, the plurality of operating modes including a fixed-point operating mode and a floating-point operation, the configurable multiplier having a native operating mode of a 27×27 unsigned multiplier further configurable to process signed inputs. The configurable multiplier may be further configurable to be four 8×8 multipliers, two 16×16 single instruction multiple data (SIMD) multipliers, one 32×32 multiplier, and one 54×54 multiplier. For example, the configurable multiplier may be further configurable to reallocate one or more partial products to a 32×32 multiplier.

[0012] In an exemplary embodiment, the multiplier-shifter combiner and combiner network may include a shifter circuit and a plurality of serially coupled adder circuits coupled to the shifter circuit, and the multiplier-shifter combiner network may be adapted to shift multiplier products to convert floating-point products to products having radix-32 exponents. In an exemplary embodiment, the multiplier-shifter combiner network may be adapted to sum a plurality of single instruction multiple data (SIMD) products to form a SIMD dot product.

[0013] In an exemplary embodiment, such a reconfigurable arithmetic circuit may further include a configurable interconnect network that selectively couples said multiplier-shifter-combiner network to one or more adjacent reconfigurable arithmetic circuits to perform single cycle 32×32 and 54×54 multiplications, single precision 24×24 multiplications, and single instruction multiple data (SIMD) dot products.

[0014] In a representative embodiment, the multiple input reordering queues are adapted to store multiple inputs, and the input reordering queues further include an input reordering logic circuit configured to reorder a sequence of the multiple inputs and adjust sign bits for negation and absolute value functions. In a representative embodiment, the input reordering logic circuit may be further adapted to deinterleave I and Q data inputs and odd and even data inputs.

[0015] In a representative embodiment, such a reconfigurable computing circuit may further include an output reordering queue coupled to receive and reconfigure outputs from the multiple reconfigurable computing circuits. In a representative embodiment, the accumulator circuit may be a single clock cycle fixed floating point accumulator having a 128-bit carry save format.

[0016] In an exemplary embodiment, the reconfigurable arithmetic circuit has a plurality of inputs, the plurality of inputs including a first X-input, a second Y-input, and a third Z-input, and the at least one control logic circuit includes one or more circuits selected from the group consisting of a comparison circuit, a Boolean logic circuit, a Z-input shifter, an exponential logic circuit, an add circuit, a saturation circuit, a round circuit, and combinations thereof.

[0017] In an exemplary embodiment, the Z input shifter may be adapted to shift floating point Z input values ​​to base 32 exponent values ​​and shift by a multiple of 32 bits to match the scaling of the multiplier sum output, and has multiple integer modes where the Z input shifter is used as a shifter or rotator having 64, 32, 2×16 and 4×8 bit shift or rotate modes.

[0018] The Boolean logic circuit may include an AND-OR-INVERT logic unit adapted to perform AND, NAND, OR, NOR, XOR, XNOR, and SELECTOR operations on 32-bit integer inputs.

[0019] In an exemplary embodiment, the comparison circuit may be configured to extract a minimum or maximum data value from an input data stream, extract an index from the input data stream, and further may be configured to compare two input data streams. In an exemplary embodiment, the comparison circuit may be configured to swap two input data streams and place the minimum value of the two input data streams at a first output and the maximum value of the two input data streams at a second output. In an exemplary embodiment, the comparison circuit may be configured to perform data steering, generate address sequences, and generate a plurality of comparison flags, such as equal, greater than, and less than.

[0020] Also disclosed are a plurality of reconfigurable arithmetic circuits arranged in an array, the plurality of reconfigurable arithmetic circuits further including an input reordering queue adapted to store a plurality of inputs, an input reordering logic circuit adapted to reorder a sequence of the plurality of inputs of the reconfigurable arithmetic circuits, and adjacent reconfigurable arithmetic circuits of the plurality of reconfigurable arithmetic circuits, a multiplier-shifter-combiner network coupled to the input reordering queue, an accumulator circuit, and at least one control logic circuit coupled to the multiplier-shifter-combiner network and the accumulator circuit, and an output reordering queue coupled to receive and reorder outputs from the reconfigurable arithmetic circuits and adjacent reconfigurable arithmetic circuits of the plurality of reconfigurable arithmetic circuits.

[0021] In an exemplary embodiment, such an array of reconfigurable arithmetic circuits may further include a configurable interconnection network coupled to the multiplier-shifter-combiner network for merging multiple reconfigurable arithmetic circuits and performing double precision multiply-add, single precision single cycle complex multiply, FFT butterfly, exponential decomposition, multiply-accumulate, and logic operations. For example, the configurable interconnection network may include multiple direct connections linking adjacent multiple reconfigurable arithmetic circuits of the multiple computation cores as pairwise configurations of reconfigurable arithmetic circuits and as quad configurations of multiple reconfigurable arithmetic circuits.

[0022] In a representative embodiment, in an array of such reconfigurable arithmetic circuits, a single reconfigurable arithmetic circuit may perform one IEEE single or integer 27×27 multiplication per cycle, two parallel IEEE half-precision, 16-bit Brain Floating Point ("BFLOAT") (BLOAT16), or 16-bit integer (INT16) multiplications per cycle of signed and unsigned 16-bit integer values, four parallel IEEE quarter-precision, or signed and unsigned 8-bit integer (INT8) multiplications per cycle, and two parallel IEEE half-precision, or 16-bit integer (INT16) multiplications per cycle of signed and unsigned 8-bit integer values. The microprocessor may be adapted to perform at least two mathematical calculations or functions selected from the group consisting of sum of precision, BFLOAT16 or INT16 complex multiplication per cycle, one ¼ precision or INT8 complex multiplication per cycle, fused addition, accumulation, 64, 32, 2×16 or 4×8 bit shifts by any number of bits, 64, 32, 2×16 or 4×8 bit rotates by any number of bits, 32-bit bitwise Boolean logic, comparison, minimum or maximum of data streams, sorting of two operands, and combinations thereof.

[0023] In a representative embodiment, in an array of such reconfigurable arithmetic circuits, two adjacent linked reconfigurable arithmetic circuits having a pairwise configuration perform one 32-bit integer multiplication per cycle for signed and unsigned 32-bit integer values ​​(INT32), one 64-bit integer multiplication in a four-cycle sequence using the accumulation circuit that adds four 32×32 partial products for signed and unsigned 64-bit integer values ​​(INT64), and a sum of two IEEE single precision or two 24-bit integers for signed and unsigned 24-bit integer values ​​(INT24). The microprocessor may be adapted to perform at least two mathematical calculations or functions selected from the group consisting of a sum of four parallel IEEE half-precision, 16-bit Brain Floating Point ("BFLOAT") (BLOAT16), or 16-bit integer (INT16) multiplications per cycle of signed and unsigned 16-bit integer values, a sum of eight parallel IEEE quarter-precision, or signed and unsigned 8-bit integer values ​​(INT8) multiplications per cycle and one quarter-precision, or complex multiplication per cycle of an INT16, a fused add, and an accumulate, and combinations thereof.

[0024] In a representative embodiment, in such an array of reconfigurable arithmetic circuits, four linked reconfigurable arithmetic circuits having a quad configuration can perform a total of two 64-bit integer multiplications per cycle for signed and unsigned 64-bit integer values ​​(INT64), two 32-bit integer multiplications per cycle for signed and unsigned 32-bit integer values ​​(INT32), two INT32 multiplications per cycle, four IEEE single-precision or 24-bit integer multiplications for signed and unsigned 24-bit integer values ​​(INT24), eight parallel IEEE half-precision, 16-bit ... The microprocessor may be adapted to perform at least two mathematical calculations or functions selected from the group consisting of a single-precision, complex multiplication per cycle for one single-precision or signed and unsigned 24-bit integer value (INT24), a fused add, an accumulate, and combinations thereof.

[0025] In a representative embodiment, in such an array of reconfigurable arithmetic circuits, each reconfigurable arithmetic circuit of the plurality of reconfigurable arithmetic circuits further comprises a configurable multiplier having a plurality of operation modes, the configurable multiplier being coupled to the plurality of input reordering queues and coupled to the multiplier shifter combiner network, the plurality of operation modes including a fixed-point operation mode and a floating-point operation, the configurable multiplier may have a native operation mode of a 27×27 unsigned multiplier further configurable to process signed inputs. For example, the configurable multiplier may be configurable to be four 8×8 multipliers, two 16×16 single instruction multiple data (SIMD) multipliers, one 32×32 multiplier, and one 54×54 multiplier. For example, the configurable multiplier may be further configurable to reallocate one or more partial products to a 32×32 multiplier.

[0026] In a representative embodiment, in such an array of reconfigurable computing circuits, the multiplier-shifter combiner network may include a shifter circuit and a plurality of serially coupled adder circuits coupled to the shifter circuit. For example, the multiplier-shifter combiner network may be adapted to shift multiplier products to convert floating-point products to products having radix-32 exponents and to sum a plurality of single instruction multiple data (SIMD) products to form a SIMD dot product. In a representative embodiment, in such an array of reconfigurable computing circuits, the multiplier-shifter combiner network may further include a plurality of direct connections coupling the multiplier-shifter combiner network to one or more multiplier shifters and combiner networks of adjacent reconfigurable computing circuits of the plurality of computation cores to perform single cycle 32×32 and 54×54 multiplications, single precision 24×24 multiplications, and single instruction multiple data (SIMD) dot products.

[0027] In a representative embodiment, in such an array of reconfigurable computing circuits, the multiplier-shifter-combiner network may be configured to add products from another reconfigurable computing circuit in a pair configuration of the reconfigurable computing circuits to generate a sum of products from another half of the reconfigurable computing circuit in a quad configuration of the reconfigurable computing circuits. For example, the multiplier-shifter-combiner network may be configured to shift the Z input from the other reconfigurable computing circuit in the quad configuration by a multiple of 32 bits to match the scaling of the Z input to sum the products.

[0028] In an exemplary embodiment, a reconfigurable computing circuit includes a plurality of data inputs, the plurality of data inputs including a first X data input, a second Y data input and a third Z data input, a plurality of data outputs, a plurality of output reordering queues coupled to the plurality of data outputs and configured to receive and reorder output data, a plurality of input reordering queues coupled to the plurality of data inputs and configured to store input data, the input reordering queues further including an input reordering logic circuit adapted to reorder a sequence of the input data, and a plurality of input reordering logic circuits coupled to the plurality of data inputs and configured to reorder a sequence of the input data. a configurable multiplier coupled to the reconfiguration queue, the configurable multiplier having a plurality of operational modes, the plurality of operational modes including a fixed-point operational mode and a floating-point operational mode, the configurable multiplier having a native operational mode of a 27×27 unsigned multiplier further configurable to process signed inputs, the configurable multiplier being further configurable to be four 8×8 multipliers, two 16×16 single instruction multiple data (SIMD) multipliers, a 32×32 multiplier, and a 54×54 multiplier; the multiplier-shifter combiner network connected to the configurable multiplier includes a shifter circuit, a plurality of serially coupled adder circuits connected to the shifter circuit, and a plurality of direct connections connecting the multiplier-shifter combiner network to one or more adjacent reconfigurable arithmetic circuits to perform single cycle 32×32 and 54×54 multiplications, single precision 24×24 multiplications, and single instruction multiple data (SIMD) dot products; a single clock cycle fixed and floating point carry-save accumulator circuit; and a plurality of control logic circuits connected to the multiplier-shifter combiner network and the accumulator circuit, the plurality of control logic circuits including a comparison circuit adapted to extract a minimum or maximum data value from an input data stream and an index from the input data stream, the plurality of control logic circuits comparing two input data streams, swapping the two input data streams to place a minimum value of the two input data streams in a first output and a maximum value of the two input data streams in a second output, and performing data steering;and further adapted to generate address sequences and generate comparison flags of equal, greater than, and less than, the Boolean logic circuit includes an AND-OR-INVERT logic unit adapted to perform AND, NAND, OR, NOR, XOR, XNOR, and selector operations on 32-bit integer inputs, the Z input shifter is configured to shift floating-point Z input values ​​to base 32 exponent values ​​and by multiples of 32 bits to match the scaling of the multiplier sum output, the Z input shifter has multiple integer modes used as a shifter or rotator having 64, 32, 2×16, and 4×8 bit shift or rotate modes, an exponent logic circuit, and an add, saturate, and round circuit.

[0029] A reconfigurable processor circuit is also disclosed, and a representative embodiment includes a first interconnection network, a processor coupled to the first interconnection network, and a plurality of computational cores arranged in an array, the plurality of computational cores coupled to the first interconnection network and a second interconnection network that directly couples to adjacent computational cores of the plurality of computational cores, each computational core including a memory circuit and a reconfigurable arithmetic circuit, the reconfigurable arithmetic circuit including an input reordering queue, a multiplier-shifter-combiner network connected to the input reordering queue, and at least one control logic circuit coupled to the multiplier-shifter-combiner network and the accumulator circuit.

[0030] In an exemplary embodiment, the reconfigurable arithmetic circuit is a configurable multiplier having a plurality of operating modes, the configurable multiplier coupled to the plurality of input reordering queues and coupled to the multiplier shifter combiner network, the plurality of operating modes including a fixed-point operating mode and a floating-point operating mode, the configurable multiplier having a native operating mode of a 27×27 unsigned multiplier further configurable to process signed inputs.

[0031] In a representative embodiment, the reconfigurable processor circuit may further include a third interconnect network selectively coupling the multiplier-shifter-combiner network to one or more adjacent reconfigurable arithmetic circuits to perform single-cycle 32×32 and 54×54 multiplications, single-precision 24×24 multiplications, and single instruction multiple data (SIMD) dot products.

[0032] In a representative embodiment, the configurable multiplier is further configurable to be four 8x8 multipliers, two 16x16 single instruction multiple data (SIMD) multipliers, one 32x32 multiplier, and one 54x54 multiplier.

[0033] In an exemplary embodiment, each computational core of the multiple computational cores may further include: a plurality of input multiplexers coupled to the reconfigurable arithmetic circuit, the first interconnection network, and a second interconnection network; a plurality of input registers, each input register coupled to a corresponding input multiplexer of the multiple input multiplexers; a plurality of output multiplexers coupled to the reconfigurable arithmetic circuit, each output multiplexer coupled to a corresponding input register of the multiple input registers; and a plurality of output registers, each output register coupled to a corresponding output multiplexer of the multiple output multiplexers, the first interconnection network, and the second interconnection network.

[0034] In an exemplary embodiment, each computational core of the multiple computational cores may further include a plurality of zero decompression circuits, each zero decompression circuit coupled to a corresponding input multiplexer of the multiple input multiplexers, and a plurality of zero compression circuits, each zero compression circuit coupled to a corresponding output multiplexer of the multiple output multiplexers.

[0035] In the exemplary embodiment, multiple data packets having all zeros in their data payload are encoded as a suffix to the next data packet having a non-zero data payload.

[0036] In an exemplary embodiment, the first interconnection network may be a hierarchical network having a FAT tree configuration and may include a plurality of data routing circuits.

[0037] In an exemplary embodiment, the reconfigurable processor circuit is adapted to execute any and all RISC-V processor instructions using the processor and the multiple computational cores.

[0038] In another representative embodiment, a system includes a first interconnection network, a processor coupled to the first interconnection network, a plurality of computational cores arranged in an array, the plurality of computational cores coupled to the first interconnection network and a second interconnection network directly coupling adjacent computational cores of the plurality of computational cores, each computational core comprising: a reconfigurable processor circuit including a memory circuit and a reconfigurable arithmetic circuit, the reconfigurable arithmetic circuit further comprising: a plurality of input reordering queues coupled to store a plurality of inputs, the input reordering queues further comprising input reordering logic adapted to reorder a sequence of the plurality of inputs of the reconfigurable arithmetic circuit and adjacent reconfigurable arithmetic circuits of the plurality of computational cores; and a configurable multiplier having a plurality of operating modes, the configurable multiplier coupled to the plurality of input reordering queues, the plurality of operating modes being a fixed point operating mode, and a multiplier shifter combiner network coupled to the configurable multiplier, the multiplier shifter combiner network including a shifter circuit, a plurality of serially coupled adder circuits coupled to the shifter circuit, an accumulator circuit, at least one control logic circuit coupled to the multiplier shifter combiner network and the accumulator circuit, and a plurality of output reordering queues coupled to receive and reorder outputs from the reconfigurable arithmetic circuits and the adjacent reconfigurable arithmetic circuits of the plurality of computation cores.

[0039] In another representative embodiment, a reconfigurable processor circuit includes a first interconnection network, a processor coupled to the first interconnection network, a plurality of computational cores arranged in an array, the plurality of computational cores coupled to the first interconnection network and a second interconnection network directly coupling to adjacent computational cores of the plurality of computational cores, each computational core including a memory circuit and a reconfigurable arithmetic circuit, the reconfigurable arithmetic circuit further including a plurality of input reordering queues coupled to store a plurality of inputs, the input reordering queues further including an input reordering logic circuit adapted to reorder a sequence of the plurality of inputs of the reconfigurable arithmetic circuit and adjacent reconfigurable arithmetic circuits of the plurality of computational cores, and a configurable multiplier having a plurality of operating modes, the configurable multiplier coupled to the plurality of input reordering queues, the plurality of operating modes including a fixed point operating mode and a floating point operation, the configurable multiplier further including a 27×27 signed multiplier further configurable to process signed inputs. and a multiplier shifter combiner network coupled to the configurable multiplier, the multiplier shifter combiner network having a native operating mode of a signal-free multiplier, the configurable multiplier being further configurable to be four 8×8 multipliers, two 16×16 Single Instruction Multiple Data (SIMD) multipliers, a 32×32 multiplier, and a 54×54 multiplier, the multiplier shifter combiner network comprising a shifter circuit, a plurality of serially coupled adder circuits coupled to the shifter circuit, an accumulator circuit, and a multiplier shifter combiner network and a multiplier shifter combiner network. and at least one control logic circuit coupled to the accumulator circuit; a plurality of output reordering queues coupled to receive and reorder outputs from the reconfigurable arithmetic circuits and the adjacent reconfigurable arithmetic circuits of the plurality of compute cores; and a third interconnection network selectively connecting the multiplier-shifter-combiner network to one or more adjacent reconfigurable arithmetic circuits to perform single cycle 32x32 and 54x54 multiplications, single precision 24x24 multiplications, and single instruction multiple data (SIMD) dot products.

[0040] Numerous other advantages and features of the present invention will become readily apparent from the following detailed description of the invention and the embodiments thereof, from the claims and from the accompanying drawings.

[0041] The objects, features and advantages of the present invention will be more readily understood by reference to the following disclosure when considered in conjunction with the accompanying drawings, in which like reference numerals are used to identify identical components in the various figures, and reference numerals having alphabetical letters are used to identify additional types, instantiations or variations of embodiments of selected components in the various figures. [Brief description of the drawings]

[0042] [Figure 1] FIG. 1 is a block diagram of a reconfigurable processor having an array of fractal cores. [Diagram 2] FIG. 1 is a high-level block diagram of the fractal core and RAE circuitry. [Diagram 3] FIG. 2 is a block diagram of an array of fractal cores showing multiple direct connections between adjacent fractal cores. [Figure 4A] FIG. 2 is a detailed block diagram of a fractal core. [Figure 4B] FIG. 2 is a detailed block diagram of a fractal core. [Diagram 5] 1 is a block diagram illustrating a first exemplary or representative embodiment of a reconfigurable compute engine ("RAE") circuit. [Figure 5A] FIG. 2 is a high-level block diagram illustrating a second exemplary or representative embodiment of an RAE circuit. [Figure 6] FIG. 1 is a high-level block diagram illustrating several exemplary or representative RAE circuits with dedicated connections. [Figure 7] Shows RAE multiplier for native 27x27 configuration connected as 24x24. [Figure 8] Shows how to use a 32x32 multiplier as two 16x16 SIMD multipliers. [Figure 9]1 shows a modification of a 27×27 multiplier to two 16×16 SIMD multipliers. [Figure 10] 1 shows the structure of a multiplier with a floating partial product. [Figure 11] We demonstrate the use of a pruned 32x32 multiplier as four 8x8 SIMD multipliers. [Figure 12] Shown is a 32×32 multiplication formed by the shifted sum of two RAE multipliers, one of which is modified. [Figure 13] 5 shows a 54×54 multiplication formed by a shifted sum of four unmodified RAE multipliers. [Figure 14] 1 shows a signed correction circuit for signed multiplication using an unsigned multiplier. [Figure 15] Indicates the input, sign correction, and output alignment for each signed integer mode. [Figure 16] A signed correction circuit is shown that can also perform selective negation. [Figure 17] FIG. 1 is a dot diagram of a 27×27 multiplier with reduced 32-bit SIMD extensions. [Figure 18] FIG. 13 is a reconstructed dot plot with a first layer Dadda adder. [Figure 19] FIG. 13 is a dot diagram of the second layer DADA tree for the flexible multiplier. [Figure 20] FIG. 13 is a dot diagram of the third layer DADA tree for flexible multipliers. [Figure 21] FIG. 13 is a dot plot of multiple remaining layers of a Dada tree for flexible multipliers. [Figure 22] 1 shows an equivalent circuit of a 4:2 compressor and a segment of layer 5, and illustrates the use of the 4:2 compressor to implement layers 5 and 6 in one stage. [Figure 23] FIG. 3 is a logic and block diagram of a post-multiplier shifter combiner network 310. [Figure 24] Indicates the alignment of the multiplier product relative to the accumulator by mode. [Diagram 25] FIG. 13 is a diagram showing the shift after multiplication for each mode. [Figure 26] FIG. 2 is a block diagram showing details of a lane shift and a first compressor circuit. [Figure 27] FIG. 13 is a block diagram showing additional logic to a 4:2 compressor for lane carry blocking. [Figure 28] FIG. 2 is a block diagram illustrating a first alternative embodiment of a multiplier shift combiner network. [Figure 29] FIG. 13 is a block diagram illustrating a second alternative embodiment of a multiplier shift combiner network. [Diagram 30] FIG. 13 is a block diagram illustrating the Z-input rotate / shift logic data path. [Diagram 31] FIG. 13 illustrates a Z-input shifter configuration for each mode. [Diagram 32] FIG. 2 is a block diagram showing a configuration of a shift network. [Diagram 33] Z-Indicates bit alignment by input logic mode. [Diagram 34] FIG. 2 is a block diagram illustrating IEEE single precision to base 32 floating-point format conversion. [Diagram 35] FIG. 2 is a block diagram showing an exponential logic circuit. [Diagram 36] FIG. 13 is a block diagram illustrating excess shift logic for the Z-shifter and multiplier-shifter combiner network. [Figure 37] FIG. 1 is a block diagram showing a 3-bit index to 8-bit bar circuit having multiple 2-input x fanout-2 (2×2) gates, where 1 is a buffer. [Figure 38] FIG. 13 is a block diagram showing a tally circuit that uses a full adder to convert the XOR difference of bars into an index. [Figure 39] FIG. 1 is a block diagram showing an 8-bit bar to 3-bit index circuit having a plurality of 2-input x fanout-2 (2×2) gates. [Diagram 40] FIG. 2 is a block diagram illustrating multiplier and shift / combiner exponent logic. [Diagram 41] FIG. 2 is a block diagram illustrating the Z-input exponent logic. [Diagram 42] FIG. 2 is a block diagram showing an accumulator. [Diagram 43] FIG. 2 is a circuit diagram showing an accumulator. [Diagram 44] FIG. 1 is a circuit diagram showing a leading code and an N*32 shift circuit. [Diagram 45] FIG. 13 is a circuit diagram showing a tally to bar circuit structure having depth Log2(n) with logic added for SIMD partitioning. [Diagram 46] FIG. 2 is a circuit diagram showing a Boolean logic stage. [Figure 47] FIG. 2 is a high level circuit and block diagram showing a min / max sort and compare circuit. [Figure 48] FIG. 13 is a detailed circuit and block diagram showing a comparator of the min / max sort and compare circuit. [Figure 49] FIG. 2 is a circuit diagram showing a decoder circuit. [Figure 50] FIG. 13 is a detailed circuit and block diagram illustrating streaming min / max with index application using a comparison circuit. [Figure 51] FIG. 13 is a detailed circuit and block diagram showing a two-input sorting application using a comparison circuit. [Figure 52] FIG. 1 is a detailed circuit and block diagram illustrating a data substitution application using a comparison circuit. [Figure 53] FIG. 13 is a detailed circuit and block diagram showing threshold with hysteresis application using a comparison circuit. [Figure 54] FIG. 13 is a detailed circuit and block diagram illustrating a flag trigger event application using a comparison circuit. [Figure 55] FIG. 13 is a detailed circuit and block diagram illustrating threshold trigger event application using a comparison circuit. [Figure 56] FIG. 2 is a detailed circuit and block diagram illustrating a data steering application using a comparison circuit. [Figure 57]FIG. 1 is a detailed circuit and block diagram illustrating a modulo-N counting application using a comparison circuit. [Figure 58] FIG. 13 is a block diagram showing the derivation of a corner turn address. [Figure 59] FIG. 13 is a block diagram showing the derivation of an FFT bit reverse corner turn address. [Figure 60] FIG. 1 is a detailed circuit and block diagram showing the logic circuit structure of the RAE input reordering queue. [Figure 61] FIG. 13 is a detailed circuit and block diagram showing the sequencer logic structure for the input / output reordering queues. [Figure 62] Illustrates FFT combination using a mixed-radix algorithm. [Figure 63] FIG. 13 is a detailed circuit and block diagram showing an RAE pair for the implementation of a radix-2 FFT kernel. [Figure 64] FIG. 1 is a detailed circuit and block diagram showing a pair of RAEs 300 configured for a complete rotor. [Figure 65] FIG. 13 is a detailed circuit and block diagram showing an RAE circuit quad for performing a radix-4 FFT (butterfly) kernel. [Figure 66] FIG. 1 is a detailed circuit and block diagram showing multiple RAE300 cascaded pairs for executing an FFT kernel. [Figure 67] FIG. 1 illustrates a string matching use case. [Figure 68] FIG. 2 is a diagram of a representative data packet for use with a reconfigurable processor. [Figure 69] FIG. 2 is a diagram of typical data payload types utilized in a data packet. [Figure 70] 1A and 1B are block and circuit diagrams of a routing controller. [Figure 71] FIG. 4 is a block diagram of a suffix control circuit. [Figure 72] FIG. 2 is a block and circuit diagram of a zero compression circuit. [Figure 73]FIG. 2 is a diagram of a representative zero compression data packet sequence. [Figure 74] FIG. 2 is a block diagram and a circuit diagram of a zero decompression circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0043] While the present invention is susceptible to embodiment in many different forms, as shown in the drawings, specific exemplary embodiments thereof will be described in detail herein, with the understanding that the present disclosure should be considered as an exemplification of the principles of the invention and is not intended to limit the invention to the specific embodiments illustrated. In this regard, before describing in detail at least one embodiment consistent with the present invention, it should be understood that the invention is not limited in its application to the details of construction and the arrangement of components described above and below, the arrangement of components shown in the drawings, or the arrangement of components described in the examples. Methods and apparatus consistent with the present invention are capable of other embodiments and can be practiced and carried out in various ways. It should also be understood that the terms and terminology used in this specification, as well as the summary included below, are for the purposes of illustration and should not be considered as limiting.

[0044] 1. Reconfigurable Processor 100 FIG. 1 is a block diagram of a reconfigurable processor 100 having an array of fractal cores 200. FIG. 2 is a high-level block diagram of the fractal cores 200 and the RAE circuitry 300. FIG. 3 is a block diagram of the array of fractal cores 200 showing a second interconnection network 220 forming multiple direct connections between adjacent computational cores 200. FIG. 4 is a detailed block diagram of a fractal core 200. With reference to FIGS. 1-4, a reconfigurable processor 100, such as an integrated circuit or chip, comprises a processor circuit 130 and multiple computational (or "fractal") cores 200 (i.e., computational core circuitry that may be abbreviated in the figures as "FC" and also referred to herein as "fractal cores" 200). A number of computational (fractal) cores 200 are typically arranged in an array and coupled to the processor circuit 130 via a first interconnection network 120 having a number of routing (switching) circuits 225 and other connections that are typically hierarchical (e.g., as implemented as a FAT tree, all such interconnection networks are considered equivalent and within the scope of the disclosure). A second interconnection network 220 is also shown, which provides a number of direct, unrouted or unswitched connections between the inputs and outputs of adjacent (e.g., nearest) computational cores 200, as illustrated as the North (N), South (S), East (E) and West (W) connections of the second interconnection network 220. The first interconnection network 120 has a number of levels for data packet routing between the array of computational cores 200, as described in more detail below, and the second interconnection network 220 provides a number of direct connections between the various computational cores 200. The formats of various data packets, including the position of the bits for the suffixes, are described below with reference to Figures 68 and 69.

[0045] The processor circuit 130 may be implemented or embodied as a general-purpose processor (e.g., a RISC-V processor) or may be more limited and may include various computational logic and control logic circuits such as multiple state machines for processing C code. For example, the processor circuit 130 may be implemented as computational logic and one or more state machines (e.g., a highly "lightweight" RISC-V processor in which components such as multipliers and / or dividers are omitted or removed). The processor circuit 130 typically includes a program counter ("PC") 160, an instruction decoder 165, and various state machines and other control logic circuits for processing C code not processed by the multiple fractal cores 200, such as recursive C code. The multiple computational cores 200 are referred to as "fractal" cores because they are self-similar, and the reconfigurable processor 100 is "fractured" into the multiple fractal computational cores 200 that function not only as a reconfigurable processor overall, but also as a massively parallel reconfigurable accelerator integrated circuit. Reconfigurable processor 100 also includes input / output interface 140 for off-chip and other network communications, optional arithmetic logic unit ("ALU") 135, optional memory controller 170, and optional memory (and / or registers) 155. Optional memory controller 170 and / or optional memory (and / or registers) 155 may also be provided as memory subsystem 175 (shown in FIG. 3). For example, reconfigurable processor 100 may not only replace an entire RISC-V processor, but may also provide massive computational acceleration.

[0046] The reconfigurable processor 100 provides a high-performance and energy-efficient solution for mathematically intensive applications including, but not limited to, artificial intelligence, neural network calculations, digital currency, encryption, decryption, blockchain, Fast Fourier Transform (FFT) calculations, and machine learning.

[0047] Moreover, the reconfigurable processor 100 can be configured for any of these various applications, some such examples are described in more detail below. Such reconfigurable processors 100 are easily scalable to millions of computational cores 200 or the like, have low latency, are computationally and energy efficient, can process streaming data in real time, are reconfigurable to optimize the computational hardware for a selected application, and are capable of massively parallel processing. For example, multiple reconfigurable processors 100 can be arrayed on a single chip and connected using an interconnect network 120 to provide hundreds to thousands of computational cores 200 per chip. Multiple such chips can then be arrayed and connected on a circuit board to provide thousands to millions of computational cores 200 per board. Any selected number of computational cores 200 can be implemented within the reconfigurable processor 100, any number of reconfigurable processors 100 can be implemented on a single integrated circuit, and any number of such integrated circuits can be implemented on a circuit board. In this manner, a reconfigurable processor 100 having an array of computational cores 200 is scalable to any selected degree (subject to other constraints such as, but not limited to, routing and heat dissipation). In an exemplary embodiment as shown in Figure 3, 16 computational cores 200 are implemented per processor circuit 130 for each reconfigurable processor 100, and the reconfigurable processors 100 are tiled across the IC, for example, but not limited to.

[0048] 2. 200 calculation cores 2, the computational core 200 includes a reconfigurable computing circuit 300, referred to herein as a reconfigurable computing engine 300 or reconfigurable computing engine circuit 300 (referred to herein as a “RAE” 300 or RAE circuit 300). The RAE circuit 300 is coupled to a first plurality of input multiplexers 205 (generally via an RAE input multiplexer 105) and to a plurality of output multiplexers 110. The first plurality of input multiplexers 205 and the plurality of output multiplexers 110 are coupled to a first interconnect network 120 and a second interconnect network 220. The RAE circuit 300 is also coupled to a memory 150 and an optional control interface circuit 250. The control interface circuit 250 may include an optional configuration storage or memory 180 for storing, for example, configuration and / or instructions for the RAE circuit 300, and may also include optional registers, an optional program counter, and an optional instruction decoder, and may further include, but is not limited to, various state machines and other control logic circuits for processing C code. The memory 150 may store operand data and may also optionally store configuration or other instructions for the compute core 200 for execution by the RAE circuit 300. Alternatively, configuration or other instructions for the compute core 200 for execution by the RAE 300 may be stored in a register (e.g., configuration storage or memory 180) that may be included in the control interface circuit 250. In an exemplary embodiment, the configuration storage or memory 180 is optionally distributed within the RAE circuit 300, as described below. The compute core 200 may also include other components described with reference to FIG. 4. In an exemplary embodiment, the memory 150 is implemented using, for example, but not limited to, SRAM. An exemplary embodiment of a routing controller 820 used to provide data selection via the input multiplexers 205 and output multiplexers 110 is shown and described below with reference to FIG.

[0049] The RAE circuit 300 is a dataflow architecture designed primarily to process streaming data using floating-point or integer arithmetic and Boolean logic, including various integer and floating-point modes, including SIMD modes, executed upon receipt of associated data. It adds comparison logic that can be used to set exception flags, gate data flow, or replace data based on the comparison result. Furthermore, as described in more detail below, the RAE circuits 300 can be grouped in pairs, in groups of four (e.g., but not limited to, two rows and two columns as shown in FIG. 6), and in groups of four or more RAE circuits 300. This includes special dedicated selectable wired connections (multiple buses) 360, 445 that connect the multiplier adder trees (of the multiplier shifter combiner network 310), allowing the RAE circuits 300 in a group to be combined, for example, but not limited to, larger adders, complex multipliers, and general multiply-accumulate uses. All of the various buses referred to herein can be considered to be "N" bits wide (to transmit a corresponding variable number of bits of a data packet or control word) as necessary or desirable for the particular bus or interconnect network 120, 220, 295.

[0050] These dedicated, selectable wired connections (buses) 360, 445 between the RAE circuits 300 form a configurable third interconnection network 295 to merge the RAE circuits 300 into RAE circuit pairs 400 and RAE circuit quads 450 to perform logic operations such as, but not limited to, double precision multiply-add, multiply-accumulate, and other applications as described below, such as using four linked RAE circuits 300 as single precision single cycle complex multiplication, performing FFT butterfly operations, and performing exponential decomposition. The RAE circuits 300 are described in more detail below with reference to FIGS. 2, 5, and 6.

[0051] 4, the computation core 200 includes the RAE circuit 300 and memory 150 (shown in simplified form in FIG. 4), as well as the input multiplexer 205 (and / or multiple RAE input multiplexers 105), the output multiplexer 110, and optionally the control interface 250 (which may include configuration storage or memory 180 and other components (such as an instruction decoder) discussed above). Not shown separately in FIG. 4 are the suffix (and / or conditional flag) input 380 and the suffix (and / or conditional flag) output 405 of the RAE circuit 300 (shown in FIGS. 5 and 5A). In a representative embodiment, the multiple input multiplexers 205 include a first input multiplexer 205A, a second input multiplexer 205B, and a third input multiplexer 205C, which are coupled to receive inputs from the first interconnect network 120 and the second interconnect network 220. Thus, each of the computational cores 200 is coupled to receive data from adjacent respective computational cores 200 (via the direct connections of the second interconnection network 220) and from non-adjacent computational cores 200, processor circuitry 130, and other components (via the first interconnection network 120), all of which are fed to each of the first, second, and third input multiplexers 205A, 205B, 205C, respectively. Dynamic selection control (not shown separately) for each of the first, second, and third input multiplexers 205A, 205B, 205C may be provided from a plurality of configurations and / or instructions, such as configurations, that may be stored in the configuration storage device or memory 180. The outputs from each of the first, second, and third input multiplexers 205A, 205B, 205C may be registered before being provided to other components such as memory 150, a second plurality of (RAE) input multiplexers 105 for the RAE circuit 300, or an output multiplexer 110, such as using a corresponding input register 230 (shown as input registers 230A, 230B, 230C), respectively, as shown in Figure 4. In an exemplary embodiment, the plurality of input registers 230 are typically double buffered.

[0052] In a representative embodiment, the computation core 200 also includes a first output multiplexer 110A, a second output multiplexer 110B, and a third output multiplexer 110A, which are coupled to receive inputs from the RAE circuit 300, the memory 150, and the first, second, and third input multiplexers 205A, 205B, 205C, and provide outputs to the first interconnection network 120 and the second interconnection network 220. Thus, each computation core 200 is coupled to provide data to each of its adjacent computation cores 200 (through the direct connections of the second interconnection network 220) and to a plurality of non-adjacent computation cores 200 and processor circuits 130 (through the first interconnection network 120), all of which receive inputs from each of the first, second, and third output multiplexers 110A, 110B, 110C. Dynamic selection control (not shown separately) for each of the first, second, and third output multiplexers 110A, 110B, 110C may be provided from a number of configurations and / or instructions, such as configurations that may be stored in a configuration store or memory 180. The outputs from each of the first, second, and third output multiplexers 110A, 110B, 110C may be in a register stage before being provided to these other components, such as using a corresponding output register 242 (shown as output registers 242A, 242B, 242C, respectively) as shown in Figure 4. In an exemplary embodiment, the multiple output registers 242 are typically double buffered.

[0053] 4, the computation core 200 has multiple separate and independent data paths, shown as a first data path 240 ("left distributor") (extending along bus 241), a second data path 245 ("right distributor") (extending along bus 243), and a third data path 255 ("aggregator") (extending along bus 247), each having separate and independent control from one another, such as via configurations or instructions that may be stored in a configuration storage device or memory 180. Note also that within each computation core 200, each of these data paths includes one or more path-through connections between the first, second, and third input multiplexers 205A, 205B, 205C, respectively, on one side, and the first, second, and third output multiplexers 110A, 110B, 110C, respectively, on the other side. For example, data from the first input multiplexer 205A may be passed directly to any or all of the first output multiplexer 110A, the second output multiplexer 110B, and the third output multiplexer 110C, respectively; data from the second input multiplexer 205B may be passed directly to any or all of the first output multiplexer 110A, the second output multiplexer 110B, and the third output multiplexer 110C, respectively; data from the third input multiplexer 205C may be passed directly to any or all of the first output multiplexer 110A, the second output multiplexer 110B, and the third output multiplexer 110C. Also, there are several independent data paths within the RAE circuit 300, and another independent data path within the memory 150. All of these various data paths can be used in parallel to perform different calculations simultaneously and separately and independently of each other. In an exemplary embodiment, a third data path 255 ("aggregator") is utilized to aggregate data from multiple sources, for example, but not limited to, generating a stream of output data packets and / or interleaving the data from the multiple sources.In addition, data from or within each of the first data path 240, second data path 245 and third data path 255 may be provided to each of the RAE circuit 300 and memory 150 (via RAE input multiplexers 105A, 105B and 105C), and data from each of the RAE circuit 300 and memory 150 may be provided to each of the first data path 240, second data path 245 and third data path 255.

[0054] Configurations and programs (e.g., configurations, instructions, instruction sequences) may also be provided locally (and separately and independently) within the computational core 200, including in memory 150 (e.g., SRAM program 262), rather than utilizing a more centralized program or configuration store (such as configuration store or memory 180). For example, program stores (or memories) 264 and 266 are provided for each of the first data path 240 and the second data path 245 (and optionally the third data path 255, not separately shown) to provide two separate programs for the RAE circuitry 300, the memory 150, and the input selection of the RAE input multiplexer 105. Also, for example, several output program storage devices (or memories) 272, 274, and 276 are provided to each of the first, second, and third output multiplexers 110A, 110B, 110C, respectively, as part of configurations or instructions for each of the first data path 240, second data path 245, and third data path 255. The first data path 240, second data path 245, and third data path 255 may also implement "zero compression," where relatively long strings of zeros in the data stream are encoded (and thereby compressed) for transmission, rather than being transmitted directly.

[0055] Input data from any of memory 150, first data path 240, second data path 245, and third data path 255 is supplied to RAE circuit 300 via RAE input multiplexers 105A, 105B, and 105C, and more specifically, to a first ("X") input 365, a second ("Y") input 370, and a third ("Z") input 375 of RAE circuit 300, respectively. The output results from RAE circuit 300 are provided via first ("X") output 420, second ("Y") output 415, and third ("Z") output 410 to memory 150, first data path 240, second data path 245, and third data path 255 (via bus 303), to output multiplexer 110 (via bus 303), and fed back to any of the various RAE inputs 365, 370, 375 via bus 303 and RAE input multiplexers 105A, 105B, and 105C. Input data from any of the RAE circuitry 300, first data path 240, second data path 245, and third data path 255 is provided via memory write multiplexer 268 (illustrated as memory input multiplexers 268A and 268B) and RAM write interface 290 (of RAE memory system 152) for storage in memory 150, and data to be read from memory 150 by any of the RAE circuitry 300, first data path 240, second data path 245, and third data path 255 may be selected using memory read (or load) multiplexer 287 and provided (on bus 301) using RAM read interface 297 (of RAE memory system 152), as shown. RAE memory system 152 may also optionally include tracking counter 292, write pointer store 294, and read pointer store 296.

[0056] 3. RAE Circuit 300, RAE Circuit Pair 400, and RAE Circuit Quad 450 2, 5, and 6, the RAE circuit 300 comprises an input reordering queue 350, a multiplier shifter combiner network 310 (also referred to as a multiplier shifter combiner network 310 or a shifter combiner network 310), an accumulator 315, and one or more control logic circuits 275. The input reordering queue 350 is coupled to data inputs (a first ("X") input 365, a second ("Y") input 370, a third ("Z") input 375) (and to data inputs of adjacent RAE circuits 300 of an RAE circuit pair 400), and the input reordering queue 350 is coupled to the multiplier shifter combiner network 310 and the one or more control logic circuits 275, which are also coupled to the accumulator 315. The multiplier-shifter combiner network 310 comprises a shifter circuit 425 and an adder tree including multiple serially coupled adders (carry-save configuration) 430, 435, 440, and is thus capable of performing multiple modes of multiplication in addition to shifting and adding (and also utilized to compute single instruction multiple data ("SIMD") dot products). In the exemplary embodiment shown in FIG. 5, an additional (configurable) multiplier 305 may be included in the RAE circuit 300 as a separate component or as part of the shift-combiner network 310, or may be included as a whole. The multiplier-shifter combiner network 310 is also coupled to the multiplier-shifter combiner networks 310 of adjacent RAE circuits 300 (of the RAE circuit pair 400 and the RAE circuit quad 450) via dedicated communication lines 360, 445 (e.g., wires) of the third interconnect network 295.

[0057] A plurality of separate and independent data paths 280, 281, 282, 283 are utilized within the RAE circuit 300, including a first data path 280 from the plurality of input reordering queues 350 through the multiplier-shifter combiner network 310, second and third data paths 281, 282 from the plurality of input reordering queues 350 through the plurality of control logic circuits 275, a fourth data path 283 from the plurality of control logic circuits 275 through the multiplier-shifter combiner network 310 and an accumulator 315, and a second RAE circuit 300 of the (first) RAE circuit pair 400 of the RAE circuit quad 450. a fifth bidirectional data path 284 through a third interconnection network 295 (communication lines 360, 445) between any two of the third RAE circuits 300 of another (second) RAE circuit pair 400 of the first pair 400 of the second ... Also, note that any of the outputs (582, 584, 586) from the input reordering queue 350 may be provided to any of the various components of the RAE circuit 300 in addition to or instead of those shown in FIG. 5.

[0058] FIG. 5 is a block diagram showing an exemplary or representative first embodiment of the RAE circuit 300. FIG. 5A is a simplified high-level block diagram showing a software programming diagram of an exemplary or representative second embodiment of the RAE circuit 300A, showing the additional location or circuit structure of the input reordering queue 350 and the output reordering queue 355, and is used to show the distribution of suffix information from the suffix (and / or conditional flag) input 380 and / or suffix control circuit 390. Note that, although not shown in FIG. 5A, in the RAE circuit 300A, no components of the RAE circuit 300 have been removed or eliminated. The RAE circuit 300A is a modified version of the RAE circuit 300, and as described above, only the arrangement (circuit arrangement) of the input reordering queue 350 and the output reordering queue 355 is different from the RAE circuit 300, and otherwise is configured exactly the same as the RAE circuit 300 and has the same functions. Thus, unless otherwise specified, any reference to RAE circuitry 300 means and includes RAE circuitry 300A, which is not otherwise addressed separately herein.

[0059] 5 and 5A, the RAE circuit 300 includes a plurality of input reordering queues 350, a multiplier-shifter-combiner network 310 (which may include a multiplier 305), a configurable (or flexible) multiplier 305 (wherein the multiplier 305 has a plurality of configurable modes of operation) (if not included as part of the multiplier-shifter-combiner network 310), an accumulator 315, and an optional output reordering queue 355, and the control logic circuit 275 is configured to: The RAE circuit 300 includes one or more of: (1) a max sort and compare circuit 320 (more generally referred to as “compare circuit” 320) (where “min” is referred to as “minimum” and “max” is referred to as “maximum” herein); (2) a Boolean logic circuit 325; (3) a Z input shifter circuit 330; (4) an exponent logic circuit 335; (5) a suffix control circuit 390 (if optionally included in the RAE circuit 300); (6) a tail saturation and round circuit 340; and (7) an optional bit inversion circuit 345. Optionally, the RAE circuit 300 may further include various data steering components, such as a first data selection (steering) multiplexer 387, a second data selection (steering) multiplexer 392, and a third data selection (steering) multiplexer 397. The first multiplexer 387, the second multiplexer 392, and the third multiplexer 397 are configured using multiple configurations and / or multiple instructions for data routing selection within the RAE circuit 300. Also as shown in FIG. 4, the RAE circuit 300 generally includes a first ("X") input 365, a second ("Y") input 370, a third ("Z") input 375, a suffix (and / or conditional flag) input 380, and a first ("X") output 420, a second ("Y") output 415, a third ("Z") output 410, and a suffix (and / or conditional flag) output 405. The multiplier-shifter-combiner network 310 includes a shifter circuit 425 (which may also perform single instruction multiple data ("SIMD") dot products) and multiple adders 430, 435, and 440 coupled in series to form an adder "tree."The multiplier-shifter-combiner network 310 also includes dedicated communication lines 360 and 445, with communication line 360 ​​selectively coupleable or connectable to another adjacent RAE circuit 300 in the pair of RAE circuits 300, and communication line 445 selectively coupleable or connectable to another adjacent RAE circuit 300 in the RAE circuit quad 450, as described below with reference to FIG. 6.

[0060] Also, note that one or more of the circuits 320, 325, 330, 335, 340, and 345 that comprise the control logic 275 may be combined or implemented in different ways and need not all be included in the control logic 275. For example, and without limitation, the sorting of the comparison circuit 320 may be performed within the input reordering queue 350 or the Boolean logic circuit 325, and the bit inversion of the bit inversion circuit 345 may be performed by the comparison circuit 320, the Boolean logic circuit 325, or multiple input reordering queues 350.

[0061] As an option in the exemplary embodiment, the RAE circuit 300 may also be coupled to the control interface circuit 250 or other configuration and / or instruction stores discussed above for various components to receive configuration, instruction, and / or other control words or bits; for clarity, these separate connections are not separately shown in FIG. 5 and are merely illustrative of the multiplier 305, multiplier-shifter-combiner network 310, accumulator 315, min / max sort and compare circuit 320, Boolean logic circuit 325, Z-shifter circuit 330, exponent logic circuit 335, suffix control circuit 390, and the like. , final add, saturate and round circuit 340, input reorder queue 350, output reorder queue 355, and optionally bit inversion circuit 345, first multiplexer 387, second multiplexer 392, third multiplexer 397, and other multiplexers and configurable components, all of which are coupled to control interface circuit 330 or other configuration and / or instruction storage devices to receive such configuration, instructions and / or other control, such as to select various operating modes and route data within RAE circuit 335 and between RAE circuit 390.

[0062] In a representative embodiment, the multiplier 305 is implemented as a carry-save adder (e.g., including shift register and adder circuits implemented similarly or identically to the shifter 425 and adder circuits 430, 435, 440 of the multiplier shifter combiner network 310, not shown separately for the multiplier 305), but is configurable to have both fixed-point and floating-point modes. Various different configurations are achieved and described by moving / rearranging the various partial products, which are then added together using any type of carry-save adder known or that becomes known in the art, any and all of which are considered equivalent and within the scope of the disclosure. The multiplier 305 has a "native mode" as a 27x27 unsigned multiplier with multiple extensions (additional circuits) to handle signed inputs. The multiplier 305 is configurable and reconfigurable to be four 8x8 or two 16x16 SIMD multipliers. This is accomplished by reallocating some of the partial products to place the multiplier as a 32×32 pruned multiplier with the off-diagonal partial products removed. A third configuration of multiplier 305 reconfigures the partial products such that reconfigured multiplier 305 can be paired with native mode multiplier 305 to form a 32×32 multiplier using two RAE circuits 300.

[0063] The multiplier 305 is followed by a multiplier shifter combiner network 310 that shifts the products (output from the multiplier 305) to convert the floating-point products to a system with a radix-32 exponent (using a shifter 425). The multiplier shifter combiner network 310 can also sum SIMD products to form dot products. This multiplier shifter combiner network 310 also adds a scaled third (Z) input to the product. In addition, products from other RAE circuits 300 can be added in pairs and sums of products from adjacent RAE circuits 300 in a pair or the other half of the RAE circuit quad 450 using adders 430, 435, 440. An additional shift by a multiple of 32 bits is performed by the shifter 425 to match the scaling of the Z inputs in the RAE circuit quad 450 and the inputs from the other RAE circuits 300 to sum the products as needed. Multiple adders 430, 435 and 440 as an addition network (or “adder tree”) couple adjacent RAE circuits 300 to enable them to perform single-cycle 32×32 and 54×54 multiplications, as well as single-precision 24×24 and SIMD dot products of up to 4 terms (8 or 16 terms in SIMD mode).

[0064] The Z input shifter 330 shifts the floating-point Z input value to convert it to a system with a base-32 exponent, and also shifts it by a multiple of 32 bits if necessary to match the scaling of the multiplier sum output (of the multiplier shifter combiner network 310). In integer mode, the Z input shifter circuit 330 is used as a shifter or rotator with 64, 32, 2×16 and 4×8 bit shift / rotate modes.

[0065] Accumulator 315 is implemented as a single clock cycle floating-point accumulator. Accumulator 315 supports fixed and floating-point multiply-accumulate for single and two floating-point and one, two or four lane INTEGER arguments. Accumulator 315 hardware is a carry-save 128-bit adder (and may be embodied as a known carry-save accumulator) with additional floating-point exponent control for 128-bit and 64-bit segments (four-lane SIMD floats are treated as integers in Accumulator 315).

[0066] The Boolean logic circuit 325 includes an AND-OR-INVERT logic unit that couples to a floating-point aligned shift network of the Z inputs to perform AND, NAND, OR, NOR, XOR, XNOR, and selector operations on the 32-bit INT inputs after shifting / rotating the Z inputs.

[0067] The Min / Max Sort and Compare circuit 320 is designed to extract the minimum or maximum value along with an index from an input stream, or to compare two input streams and swap the streams to always put the minimum of the pair in one output and the maximum in the other output (two argument sort). The Min / Max Sort and Compare circuit 320 can also generate equal, greater than, or less than comparison flags. This Min / Max Sort and Compare circuit 320 supports SIMD operations so that multiple lanes can be sorted independently or the minimum or maximum can be extracted from a stream.

[0068] Input reordering using multiple input reorder queues 350 allows for, but is not limited to, swapping between the X and Z inputs (365, 375) to resequence the history of up to four inputs and deinterleave I and Q or odd / even samples. Additional logic selects data sources (365, 370: 375) for the X, Y, and Z inputs and data sinks for the X, Y, and Z outputs (420, 415, 410). Logic is also added at key locations in the circuit to optionally adjust the sign bit for negation and absolute value functions, and logic is added to the input selector of the Y input to support conditional multiplication based on the sign of X. The input reorder queue 350 may be placed between the inputs (365, 370 375, 380) and other components of the RAE circuit 300, as shown in FIG. 5, or between the input multiplexer 105 and the inputs (365, 370 375, 380) (as shown in FIG. 5A). The output reordering queue 355 is implemented similarly to the input reordering queue 350, as described in more detail below. The output reordering queue 355 may be located between the output multiplexer 110 and the outputs (405, 410 415, 420), as shown in FIG. 5, or between the outputs (405, 410 415, 420) and other components of the RAE circuit 300 (as shown in FIG. 5A). The input reordering queue 350 and the output reordering queue 355 are typically shared between adjacent RAE circuits 300 of an RAE circuit pair 400. In another representative embodiment, although the output reordering queue 355 is illustrated as sharing only the X outputs 420, all of the X, Y, and Z outputs 420, 415, and 410 may be shared using the output reordering queue 355.

[0069] The suffix control circuitry 390 is utilized for (1) programming and control in applications (conditions, branches, etc.) and (2) lossless zero compression and decompression. Some algorithms generate many zero data values. These may be due to ReLU operations in neural networks or due to sparse matrix operations. Operations such as multiplying a number by zero or adding zero to an accumulated value are essentially meaningless. Similarly, sending zero values ​​between processing elements of the computation core 200 wastes bandwidth and power. Optionally, representative embodiments (computation core 200 and / or RAE circuitry 300) may include a suffix control circuitry 390 capable of compressing and decompressing data transfers by removing zeros in the data path, in addition to handling various flags (such as condition flags) or other conditions that utilize suffix bits overall. The suffix control circuitry 390 is described in more detail below.

[0070] Additionally, as described in more detail below, the suffix control circuitry 390 may also be implemented in a distributed manner within the computation core 200, such as, but not limited to, including zero compression (using the zero compression circuitry 800) as part of the output of data via the output multiplexer 110 and zero decompression (using the zero decompression circuitry 805) as part of the input of data via the input multiplexer 205.

[0071] 6 is a high-level block diagram showing a plurality of exemplary or representative RAE circuits 300 forming an RAE circuit "quad" 450 and two RAE circuits 300-400, shown as a first RAE circuit pair 400A and a second RAE circuit pair 400B, with dedicated connections 360, 445 of the third interconnection network 295. Four adjacent RAE circuits 300 (two rows and two columns) are connected by dedicated wiring 360, 445 of the third interconnection network 295 and can be merged as an RAE circuit quad 450 to perform double-precision multiply-add, multiply-add, and logic operations. The merge also includes connections for using the four linked RAE circuits 300 as single-precision single-cycle complex multiplication or FFT butterflies, wires for exponential decomposition, and wires for negation based on the sign of adjacent RAE circuits 300. Configuration of the RAE circuit pairs 400 and RAE circuit quads 450 is achieved by selection between the dedicated wiring 360, 445 of the third interconnect network 295, for example, but not by way of limitation, using one or more multiplexers 383 having a select ("SEL") signal 381 and / or the illustrated AND gate 385 having an enable ("EN") signal 389.

[0072] In a representative embodiment, as an example, the RAE circuit 300 has three data path inputs, three data path outputs, and a control interface 250 used to configure the RAE 300 functions. There are also dedicated auxiliary data path and control connections 360, 445 of the third interconnect network 295 between the four RAE circuits 300 that make up the RAE circuit quad 450. Each data input and output includes a 32-bit data word, a single bit of valid data (AXI-4 stream tvalid), and a single bit marker used to mark the first or last sample of a set (initializing an accumulator, the complete sum or maximum value of a set, etc.). Optionally, a ready signal can be output on the input interface as flow control and is an input on the output interface to stop operation.

[0073] In a representative embodiment, the X and Z inputs (365, 375) each have a 4-deep reordering queue that can be bypassed, sequenced through up to four 32-bit constant values, or used for a set of constant registers that can be programmed to rearrange the input data. The X and Z input reordering queues 350 contain selection multiples that can also select the inverse input (X and Z each select between four registers from Z and four registers from X, or bypass). The input reordering queues 350 allow IQ interleaving / deinterleaving, FFT and complex multiple reordering of up to four samples in a representative embodiment. Optionally, in a representative embodiment, the Y input 370 does not have a cross-connect to another input. A constant is loaded through input 370 before use. The Y input bypass selection can be controlled by the sign of the X input of the conditional multiplication, and can select between the Y input and a constant value (or up to four sequence constant values). The output of each RAE circuit 300 also has a four-deep output reordering queue 355 that can select and order any of the four delay taps from the Z outputs of either of the two paired RAE circuits 300. This reordering queue is implemented in a similar manner to that at the input to each RAE circuit 300, as described in more detail below.

[0074] The RAE circuit 300 operates in several modes, such as, but not limited to, operating as an ALU and many additional functions. These include several floating point and multiple integer arithmetic modes, multiple logical operation modes (Boolean logic and shift / rotate), multiple conditional operations, and format conversions. Each RAE circuit quad 450 effectively contains four ALUs that can be used independently or linked together using dedicated resources. The single ALU has pipeline fused multiple integration. The base multiplier is 27x27. Some of the partial products are routed to two weights in the reduction tree to multiplier 305, which (1) multiplies by zeroing the most significant 3 bits of each 24×24 input, (2) is an L-shaped partial product to complete a 32×32 multiplier when paired (added) with a second multiplier configured as a 24×24 multiplier, and sums the outputs of the two multipliers 305 to achieve a composite 32×32 multiplier consisting of two multipliers, and (3) is reconfigured as a “pruned 32×32” where only the multiple parts that form two 16×16 multipliers on the diagonal are present to perform SIMD multiplication.

[0075] A single RAE circuit 300 includes: 1. It can perform up to 27x27 multiplications per cycle (pipelined) on IEEE single or integer. 2. It is capable of performing two parallel IEEE half-precision, BFLOAT16, or INT16 integer multiplications per cycle (pipelined); 3. Capable of executing 4 parallel IEEE 1 / 4 precision or INT8 per cycle (pipelined); 4. A single RAE circuit 300 can multiply two parallel IEEE halves, i.e., sums of BFLOAT16 or INT16, per cycle (pipelined); 5. It can perform 4 parallel IEEE quarter add or INT8 multiply per cycle (pipelined), 6. 1 / 4 precision or INT8 per cycle (pipelined) complex multiplication - two complex inputs can be performed as one complex output, 7. Capable of performing fusion addition having any of the above functions; It can execute one IEEE double in 8.4 cycles, 9. Any of the above accumulations can be carried out, 10. It is possible to perform 64, 32, 2x16 or 4x8 bit shifts by any number of bits. 11. It is possible to perform 64, 32, 2x16 or 4x8 bit rotations of any number of bits. 12. Capable of performing 32-bit bitwise Boolean logic; and 13. Streams,It is possible to compare the minimum or maximum in a sort of two,operants.

[0076] The two adjacent linked RAE circuits 300 further include: 1. It can perform one INT32 multiplication per cycle, It is capable of performing one INT64 multiplication (adding 432 × 32 parts using the accumulator) in a 2.4 cycle sequence, 3. It can perform two IEEE single sums or two INT 24 multiplications per cycle; 4. It is possible to multiply four parallel IEEE half-precision, BFLOAT 16 or INT 16 sums per cycle (pipelined), 5. Capable of performing eight parallel IEEE 1 / 4 precision sums or INT8 multiplications per cycle (pipelined); 6. One half-precision or INT16 complex multiplication per cycle (pipelined) - capable of performing two complex inputs, one complex output, four multiplications, and two additions; 7. Capable of performing fused addition having any of the above functions; and 8. Any of the above accumulations may be performed.

[0077] The RAE circuit 300 internally performs arithmetic with precision equal to or greater than the multiplier output width for all modes, implementing a "fused multiply-add" or "fused multiply-accumulate" function. Rounding is performed at the final accumulator / adder stage and follows the "round to nearest even" rounding mode of IEEE-754(2008). The RAE circuit 300 does not generate or handle floating-point exceptions. Comparison logic can be used to detect and flag floating-point exceptions (Infinities and NANs) in the input data, and flags can be used to handle exceptions at the expense of additional RAE circuits 300 if these conditions are important. There is no dedicated logic in the RAE circuit 300 to handle exceptions. Denormality is treated as 0. If a 0 exponent is present in the input, the input is interpreted as 0 regardless of the value of the mantissa.

[0078] The final add, saturate and round circuit 340 detects integer overflow and replaces the output with the maximum value of the same sign as the output would have if there had been no overflow. Overflow detection requires that the internal data paths are wide enough to accommodate the overflow without error, and that the output stage detects the overflow and replaces the output with a saturated value.

[0079] The suffix (and / or conditional flag) output 405 comprises a selector from an internal source set by configuration. The condition sources can include, for example, integer overflow, exponent overflow, exponent underflow nonzero, compare block flag, multiplier product sign, Z-shifter output sign, and accumulator sign. The selected condition flag has appropriate pipeline delay registers that match the pipeline delay of the associated output. The condition flag output is wired to other RAEs in the same quad, FC sequencers in the same quad, and sequencers in adjacent quads. A suffix (and / or conditional flag) input 380 can be provided in addition to the data input, which can come from another RAE circuit 300 or another system component. The suffix (and / or conditional flag) input 380 can control, for example, any of the following: negation or zeroing of the multiplier output, negation or zeroing of the Z-input shift logic output, comparison of counter reload / reset, and accumulator initialization.

[0080] Referring again to FIG. 6, the RAE circuits 300 can be grouped into RAE circuit pairs 400, which are further grouped into pairs of pairs called RAE circuit quads 450. A pair of RAE circuits 300 is designed for use as a 32×32 multiplication or single-cycle sum of products (also useful for half-complex multipliers). The RAE circuit quad 450 is designed to combine four 27×27 multipliers into a 54×54 single-cycle multiplier to support double-precision floating point. The tight coupling includes dedicated wiring 360, 445 for sharing preaccumulator sum of products and exponent information between the four RAE circuits 300. It also includes additional dedicated input wiring (not shown separately) for sharing inputs between the four RAE circuits 300 and for sharing conditional flags to support conditional algorithms such as CORDIC and Newton-Rhapson. Additionally, in exemplary embodiments, adjacent RAE circuits 300 of an RAE circuit pair 400 may also share input reordering queues 350 and output reordering queues 355, allowing for sharing, swapping, and substitution of inputs and outputs, respectively, controlled by selectable configurations.

[0081] 4. Multiplier 305 The multiplier 305 is specifically formulated to support one-lane, two-lane, and four-lane SIMD operations for signed and unsigned fixed point, as well as double, single, half, and quarter IEEE precision floating point, and BFLOAT formats. These formats require various sizes of multipliers and the ability to break the multiplier 305 to support SIMD modes and combine it for higher order modes. The modes and associated multiplier sizes are summarized in Table 1. Additionally, the multiplier 305 allows the sum of products of multipliers in the RAE circuit quad 450 to be performed in a multiplier tree, and allows multipliers 305 of the same RAE circuit quad 450 to be combined to generate infrequently used double precision and INT32 multipliers to minimize ALU size for the most commonly used single precision use case.

[0082] [Table 1]

[0083] The multiple data inputs for the multiplier 305 are obtained from the X and Y inputs 365, 370 of the RAE circuit 300 via an input reordering queue 350. The input reordering queue 350 includes logic capable of asserting a constant, a sequence of up to four constants, or input data that reorders up to four samples to the X input of the multiplier block. The Y input sign bit (bit 31) controls the X input to selectively replace the X input with a constant based on the value of the Y sign. The X and Y inputs are 32-bit signals that are interpreted in various ways depending on the mode. For floating-point formats, the sign bit is always the left-most bit of each SIMD lane and the exponent is the next most significant bit. The hidden bit is the same bit as the least significant bit of the exponent, and is always forced to "1" at the multiplier array input for floating-point formats because denormality is interpreted as 0. The remaining exponent bits and sign are masked and forced to "0" at the multiplier array input for each floating-point mode. In unsigned integer (uINT) mode, all bits are passed to the multiplier array, except in INT24-bit mode, where the most significant byte of the input is masked, forcing the most significant 3 bits of the multiplier array to "0".

[0084] Signed integers mask the sign bit, forcing these bits to "0" in the multiplier array, and pass the input sign bit value to the multiplier output logic to apply sign correction. The format is summarized in Table 2. Bits beyond 27 from each input are not connected to the 27x27 multiplier array. The double, INT32, and INT64 modes are special cases that use multiple multipliers. In these cases, the input must be propagated to the relevant RAEs. In these special cases of signed integer modes, the most significant input segment is treated as signed and the others as unsigned to obtain the proper result. For 64-bit signed integers, the multiplication is a sequence of four 32-bit multiplications. The signs of the inputs in this case must be sequenced so that only the most significant half of each input is signed. The exponent and sign bits of both inputs are also connected to the exponent logic, which controls the negation.

[0085] [Table 2]

[0086] Each multiplier (X and Y) input has a signedness control to individually specify the input as signed or unsigned. For floating-point mode, the signed input must be "0" to specify it as unsigned. This input must be sequenceable to support signed INT64 mode. The signedness control applies equally to all SIMD lanes. The multiplier also has a negate input that negates the multiplier output when asserted. This control must be sequenceable.

[0087] The configuration input sets the multiplier SIMD mode (setting the appropriate carry block bits, and formatting sign correction and negated addition) and selects the input mask. The configuration may also include settings for signed or unsigned, negation, absolute value, and zero as mentioned above (these can be set elsewhere in the configuration).

[0088] The multiplier product is a 64-bit two's complement product represented as a pair of 64-bit vectors in carry-save format. The sum of these two vectors is the two's complement value of the product. This product is split across four 16-bit lanes, two 32-bit lanes, or a single 64-bit lane, depending on the mode. Signed SIMD mode applies sign correction to each lane individually and has a carry blocker to prevent overflow into adjacent lanes. Each of the two multiplier inputs has an associated data_valid_in bit. These bits are ANDed and delayed to match the multiplier pipeline delay, resulting in data_valid_out from the multiplier.

[0089] The multiplier designs are a 27x27 unsigned multiplier modified to rearrange the product terms to achieve 27x27 multiplication, a pruned 32x32 multiplier with only two 16x16 partial products on the diagonal for SIMD use, and an "L" shaped extension that allows two multipliers to be summed together to achieve 32x32 multiplication. Additionally, the unsigned multiplier adds correction to the output to support use with signed two's complement inputs. Output correction logic also converts the sign-magnitude product to two's complement and provides controls to negate the multiplier output.

[0090] A. RAE Multiplier 305 in native 27x27 mode FIG. 7 illustrates the multiplier 305 in native 27×27 mode. Block 402 represents the virtual 8×8 partial products, and the numbers 404 within block 402 represent the number of 8-bit left shifts applied to the partial products when summing them. The shaded blocks on the top and right side of FIG. 7 are forced to zero in 24-bit mode. The X input along the bottom is broadcast to all cells in the column, and the Y input along the left is broadcast to all cells in the row. It should be noted that this representation is for illustration purposes only. The 24-bit mode is used for single precision floating point and 24-bit integer modes. In 24-bit mode, a 27-bit multiplier is used, with the top 3 bits of each input forced to 0. Alternatively, individual bit products corresponding to zeroed input bits may be forced to 0. The floating-point format includes a sign bit in bit 31, and mantissa bits in bits 22:0. There is also a hidden bit that is "1" unless the exponent is all zeros, in which case it is "0". Input gating to the multiplier assigns input bits 42:0 on the X and Y inputs to bits 32:0 of ​​the multiplier array, floating point forces bit 23 of each input to a "1", and zero pads the most significant 3 bits on each input of the 27x27 multiplier.

[0091] B. RAE Multiplier 305 in SIMD Mode Figure 8 illustrates the use of a 32x32 multiplier as two 16x16 SIMD multipliers. Off-diagonal partial products in the partial product array are zeroed so that all remaining non-zeroed partial products use independent subsets of inputs, and the weighting of cells in the native array ensures that products do not overlap at the output of the array. Thus, by zeroing partial products 403 off the diagonal as shown in Figure 8, an otherwise unmodified unsigned multiplier can be used as a group of smaller independent multipliers of any size. In the illustrated case, a 32x32 unsigned multiplier is used to perform two 16x16 multiplications. As long as the multiplications are unsigned, the 16-bit inputs and 32-bit products do not overlap. A similar method is used to perform four 8x8 unsigned multiplications with a 32x32 unsigned multiplier. Note that hardware for zeroed partial products does not need to be present for SIMD operations. If they are present, they are disabled to prevent the resulting partial products from combining with the desired partial products.

[0092] FIG. 9 shows the modification of a 27×27 multiplier for two 16×16 SIMD multipliers. Because multiplier 305 is only 27×27 bits, the upper right partial product shown in FIG. 8 is truncated to 11×11 instead of 16×16 (the dotted line indicates the 27×27 multiplier size) using the unmodified 27×27 multiplier. Instead of adding an extension to the multiplier to increase the upper SIMD product, the existing invalid partial products can be reallocated to achieve a pruned 32×32 multiplier suitable for SIMD mode. The partial products, if carefully selected, have the same weight as each other in the extension, just as they did in the original multiplier. This allows the moving partial products and carry-save trees under the ported partial products to be moved as intact carry-save trees that are added to the main multiplier tree of the carry-save adder one level above the output. The selection of the moving partial products is indicated in FIG. 9 by the shaded blocks (block 406 at the 27×27 location, block 408 at the SIMD location). The unshaded portion of the 27x27 multiplier inside the dotted line is disabled in SIMD mode. As shown, the division of the multiplier into 8x8 segments is for illustration purposes only; the actual multiplier has 5x16-bit and 11x5-bit sums of partial products that are reassigned with a 24-bit left shift relative to their original positions. The inputs to these partial products may also require selectors to reassign the input bits.

[0093] Alternatively, a 27×27 multiplier can be constructed by always using the SIMD extensions and disabling them when using the 27×27. This eliminates switching in the carry-save tree and reduces the selection at the bit product input, slightly reducing the propagation delay, but increases the gate count to account for the added bit portion and the carry-save tree below. Another option for the design of multiplier 305 is to use a 24×24 multiplier as a base and switch 8×8 blocks. This moves more 1-bit products, but the additional cost of the carry-save tree may be offset by the increased switching complexity since bits 27:24 are not zero at both inputs.

[0094] FIG. 10 shows the configuration of a multiplier 305 with movable partial products. As shown in FIG. 10, the numbers in block 402 represent an array of 1-bit partial products generated by logical ANDing of 1-bits from each input. These 1-bit products are added to the addition tree 306 with squares of weights corresponding to the sum of the bit positions of the inputs. As shown on the left side 412 of the figure, the 27×27 multiplier 305 is pruned to remove 1-bit partial products corresponding to the movable parts. The removed partial products are summed separately on the right side 414 and added to the reduced 27×27 multiplier carry-save output in the last layer of the carry-save tree. Due to the use of 27 / 27, the added tree 306 retains the original weights.

[0095] When using SIMD pruned 32x32, the partitioned tree output has a wired shift of 24 bits added to the left of its original position. The input to the partition tree is selected between two possible bits depending on whether it is 27x27 or 32x32 mode. The output of the adder shown in Figure 10 is a pair of vectors whose sum is the product (in carry-save form). Using the carry-save form defers the costly propagation of carries to the output from the ALU. Figure 10 illustrates the concept of moving partial products. For clarity, Figure 10 shows an 8x8 block of 1-bit partial products. In an actual design, there would be a 27x27 array of partial products, of which 5x16 and 11x5 regions would be removed and summed separately. The multipliers in SIMD mode are unsigned only. When signed operation is selected, a correction is applied to the multiplier 305 output for each SIMD lane, as described below.

[0096] FIG. 11 illustrates the use of pruned 32×32 multipliers as four 8×8 SIMD multipliers. The four lanes of the 8×8 SIMD mode are a subset of the two lane 16×16 pruned 32×32 multiplier 305. The multiplier mode described above has an additional control to disable four blocks of 8×8 bit partial products 308 to arrive at four 8×8 multipliers 307 arranged diagonally in a pruned 32×32 as shown in FIG. 11. As with 16-bit SIMD, the 1-bit partial products need to be gated to disable them so that they are not added to the product. The multipliers 305 in SIMD mode are unsigned only. When signed operation is selected, a sign correction is added to the multiplier 305 output of each SIMD lane.

[0097] C.RAE Multiplier 305 (32x32 mode) FIG. 12 shows a 32×32 multiplication formed by a shifted sum of two RAE multipliers 305, one of which is modified. Two adjacent multipliers 305 are combined to form a single-cycle pipelined 32×32 multiplier for use in INT32 and INT64 modes. The resulting multiplier 305 operates in both signed and unsigned modes and is used for integer arithmetic. The multiplier 305 is constructed using two multipliers 305 of the RAE circuit pair 400 configured for 24×24 (the upper 3 bits of both partial products forced to 0 or negated). The lower multiplier is a native 24×24 and accepts the lower 24 bits of each of the X input 365 and Y input 370. The second multiplier 305 is modified to form an “L” shaped partial product to extend the multiplier array by 8 bits on the upper and right side 416 as shown in FIG. 12.

[0098] The two ends of the L leg are taken from the first left column of the middle row and the middle 8×8 block of the bottom row. Both of these have a relative weight of 28 relative to the rest of the upper part as their weight when rearranged, so no modifications need to be made to the adder tree to change the relative weight of these two 8×8 blocks of partial products. Since the inputs to these two blocks of the 8×8 partial product multiplier no longer match the inputs to the physical columns and rows, these inputs must be switched to connect the correct inputs to realize the virtual shape. The remaining two partial products are unused and are therefore disabled by zeroing at least one of the inputs to each bit partial product or by disabling these partial products to prevent unnecessary addition to the sum of products. The upper "L" shaped partial products are shifted left by 16 bits relative to the lower multiplier product. This shift is accomplished by a right shift of the lower product in the post-multiply shift / combiner logic where the products from the two RAEs are summed. The Z input 375 of the lower product is appropriately aligned to sum the Z input 375 with the 32×32 product. Note that both 32-bit inputs are distributed to both RAE multipliers 305 of the pair. Note that dedicated wiring in the RAE circuit quad 450 interconnects the two RAE inputs and provides wiring to sum the outputs. The 32×32 is rendered more efficiently by using the first 27×27 as a 24×24 (making the upper 3 bits of each input 0) and shifting an 8×8 portion of the second 24×24 to form the 32×32 bit L. This uses the same portion subset with no zeros between the lane portions and adds to the lower 24×24 using a 16-bit shift in the extension. The 16-bit shift can be achieved with the existing mode shift, eliminating the shift with the 16 pair shift input.

[0099] D.RAE Multiplier 305 (54x54 mode) FIG. 13 shows a 54×54 multiplication formed by the shifted sum of four unmodified RAE multipliers 305. A 53×53 bit unsigned multiplier 305 is required for IEEE double precision mode. In this case, the four 27×27 multipliers 305 in the RAE circuit quad 450 are simply summed together with the appropriate shifting of the sum and reassignment of the inputs. The sum is added by shifting the right multiplier left by 3×9=27 bits to the left multiplier, then adding the upper sum to the lower sum with an additional 27 bit shift, as shown in FIG. 13, to arrive at the 54×54 product. Note that the same Y input bits to the left multiplier should also be distributed to the right multiplier, and the same X inputs applied to the lower row of multipliers should also be applied to the upper row. The wiring in the RAE circuit quad 450 includes dedicated routing to allow this.

[0100] E. 64-bit sequential multiplication and sign correction The shift combiner design coupled with the 128-bit accumulator allows for a four-cycle sequential computation of a 64-bit multiply using two RAE circuits 300 as a 32-bit multiply accumulate. The second layer of input and shift combiners are sequenced to compute the four 32×32 partial products and shift them by the appropriate amount to sum them for a 128-bit result. The lower*lower partial products are not shifted, the upper*lower and lower*upper partial products are shifted left by 32 bits, and the upper*upper partial products are shifted left by 64 bits before being added to the accumulated sum. The shifting is done in the post-multiplier shifter combiner network 310 described below. The output requires selectors and / or shift registers to take in, select, and output the 32-bit or 64-bit segments of the 128-bit product. In signed arithmetic, only the upper half of each 64-bit input is signed, so each input to the multiplier needs to be ordered with the upper half signed and the lower half unsigned. The partial product sequence begins with the product of the lower half of each input and ends with the product of the upper half of each input. Signed controls are sequenced with a sequence that treats only the upper half of each input as signed.

[0101] An additional consideration is the need to handle both signed and unsigned multiplication for all integer modes. This is a simple extension to the control logic that also supports integer representation of the sign magnitude. Floating-point modes all use unsigned multipliers because the data is represented in sign-magnitude form. For the floating-point use case, the signs are exclusively ORed and passed around the multiplier, and the multiplier itself is unsigned. The integer formats support both signed and unsigned integer inputs for each integer mode.

[0102] Unsigned multipliers do not handle negative two's complement multiplicands correctly because they do not consider the weight of the most significant bit of each multiplicand, which is -2n-1 for unsigned data versus -2n-1 for signed arithmetic. When summing partial products, negative partial products need to be sign-extended to the width of the product and treated as negative to get the correct answer. There are multiplier optimizations such as Booth and Bah-Wooley that involve encoding tricks to avoid generating partial product terms for extended signs to achieve signed multipliers.

[0103] In representative embodiments, the need to support SIMD operations and the design choice to split the multiplier into partial products in order to reduce hardware to support all modes significantly complicates or completely destroys these signed multiplier schemes. One method is to perform a two's complement absolute value of each input, preserving the sign, to convert the two's complement signed inputs to sign magnitude form and feed it to the multiplier 305 without further manipulation, allowing unsigned multiplication to be used. The two's complement conversion is done by inverting all bits of the input (one's complement) and adding a one to it to generate two's complement. The carry propagation from adding a one adds significant gate delay even for fast carry schemes and incurs a large area penalty even for fast schemes.

[0104] Representative embodiments use a different approach that involves understanding the error that occurs when unsigned multiplier 305 is used to multiply signed values, and then applying a correction for that error. The error that occurs is analyzed as follows: Consider a multiplication where multiplicand A is negative and B is non-negative.

[0105]

number

[0106] The subtraction is performed by adding the two's complement of the correction. Because the correction is an addition and the output of the multiplier is a tree of adders, the correction can be applied at any point in the multiplier's adder tree rather than at the output. Because the correction logic depends only on the multiplier mode and the inputs to the multiplier, the correction value can be calculated in a path parallel to the unsigned multiplier partial products, and the final correction in carry-save form can be applied at any convenient point in the adder tree.

[0107] FIG. 14 illustrates a signed correction circuit 428 for signed multiplication with an unsigned multiplier 305, showing logic for performing the sign correction as described above. Two's complements are calculated for each input by inverting all input bits and adding a one (418). The two's complements are each gated by the sign bit of the opposite input (422), and the gated corrections are summed (424) and added to the upper half-product via a wired shift (426). The gate for the two's complement value in the figure includes a signed int control that disables generation of the correction (forced 0) when asserted high, so that the mode can be switched between signed and unsigned. In practice, the correction calculation adders are moved together as an optimized tree, and the gate is applied with an inversion at the input to the correction logic.

[0108] In SIMD arithmetic, each lane has its own sign correction circuitry that uses only the input field and sign of that lane, and the correction is not allowed to propagate the carry to the next lane. This means that at least one buffer bit or carry-blocking logic is required between each SIMD lane. In this design, we choose to keep the lanes in multiples of 8 bits. Therefore, carry-blocking gating is used at the lane boundaries to avoid the extra switching of inputs required for the guard bits in each lane. In the absence of guard bits, carry-blocking is applied at the stage where the correction is applied and in all subsequent stages. For this reason, this design defers the correction until the output of the multiplier carry tree.

[0109] Figure 15 shows the alignment of input, sign correction, and output for each signed integer mode, i.e., the alignment of input and sign correction to output for each signed integer mode. The correction for each lane is calculated independently from the other lanes. For 32-bit signed multipliers, the correction is applied to only one of the multipliers (the alignment shown is for the correction applied to the lower multiplier). Otherwise, the correction is applied twice with two different alignments.

[0110] FIG. 16 shows a sign correction circuit 432 that can also perform selective negation. When using floating-point multiplication and addition, it is usually necessary to convert the numeric format to two's complement format to perform the addition. Rather than adding a separate two's complement stage between the multiplier and the adder, the product can be selectively negated as a function of the floating-point sign and negation control by performing a two's complement on the product before the multiplier output. Two's complement is done by either inverting all bits of the product and then adding a one (418) or by subtracting a one from the product and then inverting all bits. The latter suggests that the sign correction logic described above can be augmented to selectively add a negative one to the product in the multiplier tree and then invert the completed product to achieve the negation without affecting the propagation or gate count in the tree. In this case, however, the multiplier has a carry-save output, so the sum of the two output vectors is the product.

[0111] To negate the product, both the sum and carry outputs of -(C+S)=-CS=~(C-1)+~(S-1) are negated. Therefore, before inverting the output, the corrected product is C+S-2, so if two vectors are to be inverted at the output, a -2 must be added to the tree. Figure 16 shows the modification of the sign correction logic to include selective negation of the product. In the floating point or sign magnitude case, the sign bit must be evaluated along with the negation control to determine if the multiplier output is negated. In this case, the multiplier output is always a two's complement carry-save vector. A sign correction is added to the upper half of the product, and the lower half correction is 0. In the negation case, an all-'1' bit is added to the multiplier sign correction, since the lower half is -2 and the upper half is sign extended + sign correction (for a two's complement signed multiplier). The negation control is extended to include the absolute value control of the product. This simply makes the negation control an exclusive OR of the signs of the inputs if absolute value is selected.

[0112] When multipliers 305 are combined for 36×36 or 54×54 modes, two's complement is performed on the partial products of each RAE circuit 300, so no adjustments are required to sum the RAE products other than ensuring that the negative control is the same for all multipliers involved.

[0113] If floating-point arithmetic is selected, the exponent is part of the 32-bit input. When in floating-point mode, the input to multiplier 305 corresponding to the exponent is masked to "0" except for the least significant bit of the exponent, which is forced to "1" as a hidden bit. Denormality is interpreted as 0 and, when detected, forces a 0 in the data path after the multiplier. Multiplier exponent processing (zero detection, addition, alignment shift) is performed in exponent logic 335. Details of the shift combiner exponent logic 335 are described below. The unmasked values ​​of the exponent bits are passed to the multiplier shift combiner exponent logic 335 unchanged.

[0114] The multiplier inputs require some switching to invalidate some partial products and reallocate inputs for the 32-bit and SIMD extended modes, which can be performed in the input reorder queue 350 or other switching circuitry. The input logic also asserts the hidden bit in floating-point mode.

[0115] F. Multiplier 305 Mode There are three basic multiplier configurations: 27x27 multiplication, 32x32 reduction for SIMD, and 32-bit extension. Also, 24x24 is a subset of 27x27, where 3msbs of each input are forced to zero, and 4-lane SIMD is a subset of 2-lane SIMD, where 4 blocks of 8x8 bit partial products are disabled and forced to zero. In floating-point mode, a mask is applied to the inputs, where the bits associated with the sign and exponent are set to zero. SIMD configurations require some partial product weight changes, which are achieved by moving parts of the adder tree as described above. All other configurations are handled strictly by switching the inputs into groups of partial products.

[0116] The native mode of the multiplier 305 array is multiplier 305. In this mode, each 27-bit input to the multiplier is taken from the least significant 27 bits of the X and Y inputs, or for double precision multiplication, the input is taken from the least significant 27 bits for the lower product and bits 53:27 for the upper product. For the hidden bit, bit 53 is forced to 0 and bit 52 is forced to '1'. The doubles switch is performed before the multiplier 305.

[0117] The inputs for the 24x24 mode are the same as for the 27x27 mode, except that the most significant 3 bits of the X and Y inputs are forced to 0, making the effective multiplier an unsigned 24x24 multiplier. Table 3 shows the input assignments for each 8x8 subset of the multiplier. Each block represents the input to the lower 24 bits of an 8x8 partial product. In this mode, the most significant 3 bits of the input for each 27-bit multiplier input are forced to 0.

[0118] Table 3: 24x24 Multiplier Inputs [Table 3]

[0119] The 32-bit extension is the upper multiplier when two multipliers are combined to achieve a 32×32 multiplication. The lower multiplier is set to the 24×24 mode described above. The upper multiplier switches the inputs to two virtual 8×8 partial products, and zeros two more, making the multiplier an L-shaped partial product that corresponds to the eight most significant rows and columns of the 32×32 multiplier. This extension uses the most significant 24 bits of the X and Y inputs as inputs to the 24×24 array described above, but replaces the lower 16-bit partial inputs of both inputs, forcing the lower diagonal to zero and the other two products to the top row, and similarly for the lowest 8 bits. Table 4 shows the inputs for each virtual 8×8 partial product that makes up the 24×24 array. The most significant 3 bits of each input to the 27×27 multiplier are forced to zero. The bold legend in Table 4 indicates the inputs that differ from the normal 24×24 in this mode.

[0120] Table 4: 32x32 Multiplier Extensions [Table 4]

[0121] SIMD mode changes the weighting of three of the 8×8 partial product blocks by a common offset of 24 bits. The inputs to the virtual partial products corresponding to the 16 least significant bits of both inputs are the same as the inputs to the 24×24 multiplier 305, as are the eight x8 partial products corresponding to the eight most significant bits of both inputs. The three movable partial products require input reassignment, and the red legends are the same as the inputs used in the 32×32 extended mode. The bold legends indicate SIMD mode specific input assignments. In 4×8×8 SIMD mode, the grey shaded cells must be forced to zero. To make these virtual partial products zero for 8-bit SIMD, one can force one of the X's and Y's inputs to zero for these partial products only.

[0122] Table 5: Multiplier SIMD Mode Inputs [Table 5]

[0123] The above modes require up to three input multiplexers for each multiplier input bit. The charts for each mode are summarized in the summary charts in Tables 6 and 7. Each block in Table 6 represents a virtual 8x8 partial product for a 24x24 multiplier 305. The most significant three bits to each of the multiplier inputs are forced to "0" to effectively block the top row and column of the partial product, except for 27-bit integer and double precision floating point modes. The top row of each partial product cell corresponds to the X and Y inputs for 24x24 mode, the middle row corresponds to the 32-bit extended mode, and the bottom row of each cell corresponds to the inputs for SIMD mode. Bold cells are forced to 0 for 8-bit SIMD. / 0 indicates an input that is forced to 0 in SIMD8 mode. "&0" indicates right padding is 0, and "0&" indicates left padding is 0.

[0124] Table 6: Summary of multiplier inputs [Table 6]

[0125] [Table 7]

[0126] Floating-point inputs represent the IEEE hidden bit. Since denormality is interpreted as 0 by the ALU, the hidden bit can always be asserted when the corresponding floating-point mode is selected. If the exponent becomes 0 on either input, the data is forced to 0. The hidden bit appropriate for floating-point must be asserted to "1" on both the X and Y inputs of the multiplier when the corresponding mode is selected. Otherwise, the inputs follow the multiplier settings above. The hidden bits are shown in Table 8. If the specified mode is selected, the hidden bit is forced to 1. If not selected, the inputs track the inputs tabulated in the input summary above.

[0127] [Table 8]

[0128] Conditional multiplicand operations are handled within the input reordering logic of input reordering queue 350, which replaces the X inputs with a constant as a function of the Y input sign. Conditional multiplicands do not support SIMD arithmetic.

[0129] G. Multiplier 305 Carry Save Adder Tree Figure 17 is a dot diagram of a 27x27 multiplier with pruned 32-bit SIMD extension. Multiplication is done in a manner similar to the long multiplication taught in elementary school, but using a binary radix rather than a decimal radix. Long multiplication is actually two distinct operations: the generation of partial products, and the accumulation of those partial products. A partial product is generated for each pair of digits in the multiplicand and multiplier. The resulting partial product is weighted by the sum of the digit weights used for that partial product. Since the weights of the digits in the multiplicand are powers of the number system radix, the weights are achieved by position shifts. These shifts are represented by inserting the appropriate number of zeros to the right of the partial products. The shift p of each partial product is equal to the sum of the position shifts m and n of the multiplicand and multiplier. In a binary multiplier, a 1-bit partial product is the same as a logical AND (only 1*1 combinations are not multiplication by 0). For an N-bit by N-bit multiplier, there are N2 1-bit partial products, each bit resulting from a unique pair of bits from the multiplicand and multiplier. Figure 17 shows a 27x27 multiplier augmented to accommodate the pair of 16x16 SIMD multipliers mentioned above. Each dot in this diagram represents a 1x1 partial product. Dots of the same product weight are arranged vertically. This layout is reminiscent of partial products in long multiplication, where each row is one digit of the multiplier multiplied by each digit of the multiplier (in this case, there is no shifting to the next digit, since each product is either 0 or 1).

[0130] A property of integer addition is that the additions can be done in any convenient order. In a simple multiplier construction, just adding the rows with the shift of the diagram gives the correct answer. However, this method is not optimal for speed or area, since it involves a carry propagation for each row as the previous sum is added. Instead, we sum the columns and defer the row carries until the final addition. Groups of bits with the same weight are summed using full and half adds (and most libraries have technology-dependent higher-order tally adders, commonly called compressors, that can improve performance and reduce area).

[0131] A full adder reduces three input bits of equal weight to a sum and a carry output. The weight of the carry output is one greater than the sum output. The added benefit of the column is that the carry is propagated towards the output instead of across the row, but the product is only reduced to a pair of vectors (one that involves a sum to the carry, hence the name carry-save). The sum of these vectors becomes the multiplier product. In this design, the product is left in carry-save form until after the accumulator to maintain performance and minimize area.

[0132] There are several algorithms for generating optimal trees. One tree known for its minimum propagation delay and number of gates is the Dadda tree. Traditionally, Dadda trees are constructed only from full and half adders, but they can be modified to use higher order compressors if the technology library contains compressors that reduce area and / or improve propagation delay compared to using discrete full and half adders. In most cases, there are advantages to using higher order compressors. For the sake of discussion and illustration, this specification uses the traditional Dadda tree structure. Circuit designers are free to use higher order compressors and modify the tree structure to reduce the footprint of flexible multipliers.

[0133] The dot diagram in Figure 17 is highlighted to illustrate the design of the partial product shift between the 27x27 and SIMD modes. The large diamond 436 on the right is the 27x27 multiplication. It has been extended left and down (in the most significant bits) to accommodate the pruned 32x32 SIMD multiplication previously described. The extensions 438 indicate that these partial characters are borrowed from elsewhere. The borrowed dots 434 are for SIMD. They occupy two regions, one five rows high with 16 bits per row near the bottom center of the diagram, and the other eleven rows with 5 bits per row near the top left of the array. These two shifted together vertically form the same shape as the extended dot 438. The dots filled with black represent partial products that are common to both the SIMD and 27x27 modes, and the unfilled dots are those that are disabled (forced to zero) in the SIMD mode.

[0134] FIG. 18 is a reconstructed dot diagram with first layer Dada adders. In FIG. 18, the dot diagram of FIG. 17 is rearranged by top-justifying the columns of the 27×27 multipliers. The dots representing the borrowed partial products (442) are moved to the bottom of the corresponding columns, and the dots corresponding to the SIMD extensions, shown with blue fill, are vertically separated from the rest of the array, but in the correct columns for weighting. Here, we leave the layout of the extension regions in the same layout as the partial product (442) borrowed regions to highlight the similarity between the borrowed and extended regions. In the Dada tree reduction, the partial product (442) dots are treated as if they are not there, so that the movable partial products are combined into a separate tree. The Dada algorithm minimizes layers by reducing the number of rows to a certain number of rows per iteration or layer. The sequence of row targets for the 3:2 adder is 19, 13, 9, 6, 4, 3, 2. At each iteration, full and half adders are placed in the columns to reduce the number of entries in the columns. Each adder has one output in the column it is in and one output in the column to the left of it in the next level. When counting rows, the previous column has a row for each adder, the current column has a row for each adder, and the current column has a row of hidden dots. The dots in Figure 18 represent the inputs to the Dada layer, the box 437 covering 3 dots is a full adder, and the box 439 covering 2 dots is a half adder. The adders represent the adders for this layer. The dots that are not covered are moved to the next layer as is. It should be noted that the expansion tree is already below 10 dots per column, so in this first iteration we simply pass the entire expansion through unchanged (i.e. the expansion starts in a later layer).

[0135] FIG. 19 is a dot diagram of the second layer Dada tree for flexible multiplier 305. The next layer has in each column a dot for each uncovered dot in the previous layer, a dot for each carry from the column to the right (the carry for each adder in the right column of the previous layer), and a dot for the sum output of each adder in that column in the previous layer. FIG. 19 shows the rows reduced by the first layer to a maximum of 13 dots per column. The expansion array is the same as the previous layer, but the columns are top-justified to make the reduction process clear. This iteration reduces the output to 9 rows.

[0136] Figure 20 is a dot diagram of the third layer Dada tree for the flexible multiplier. The next layer of the tree shows the rows reduced to 9 rows, and the target for this layer is 6 rows. This third layer is shown in Figure 20.

[0137] FIG. 21 is a dot diagram of the remaining layers of the Dada tree for the flexible multiplier 305. FIG. 21 shows the remaining layers arriving at two rows at each output. The two rows 447 are the output from the 27×27 multiplier 305 without the moving body partial products, dot 444 is the output of the tree for the moving volume shown in the alignment for the SIMD expansion, and dot 446 shows the alignment of the moving volume for the 27×27 multiplication. One additional layer of 4:2 compressors is used to combine the stationary tree and the moving tree. The moving tree is wired in both places via a gate that selects which connection to make. The adder for the mobile product only requires 4:2 compressors in the columns occupied by the two images of the expansion tree, and additionally requires full adders in the columns immediately to the left of the leftmost column of each group, and 4:2 compressors and half adders in the columns to their left, shown by the gray shaded areas of the output. The reason for the full adder on the left is because the 4:2 compressor has an additional carry out and carry in. The added green dots are for the run out of the 4:2 compressor chain. The adder tree does not show the additional layer of adders (4:2 adders) for selectable inversions and XORs for combining and adding sign correction and negation vectors. The RAE circuit 300 has the freedom to substitute other tree construction algorithms and use higher order compressors in actual designs. The traditional Dada tree becomes a 7-layer tree with adders that combine parts of the moving tree and the stationary tree. The moving tree is only 6 layers deep including the output adder, so the input selection gates and output steering gates required to move the moving partial products (which are in the path of the moving tree) do not contribute to the longest propagation path through the 7-layer fixed tree.

[0138] A simple 27x27 multiplier using traditional Dadda is also 7 layers, so there is no performance degradation for the mobile tree. Depending on the vendor library, Dadda trees can be improved by using a higher level compressor. For example, the 5th and 6th layers of the tree in Figure 21 can be easily replaced with a single layer using a 4:2 compressor. A 4:2 compressor has 5 inputs, 4 equally weighted inputs, a carry in from another level at the same level, a carry out to another level at the same level, and a sum and carry out to the next level.

[0139] FIG. 22 shows a segment of the 4:2 compressor and layer 5 from an equivalent circuit 448, showing the use of a 4:2 compressor to perform layers 5 and 6 (447) in one stage. The combination of the carry out and the carry is a jog to the next column and then propagates to the next layer with a similar delay as the other inputs. FIG. 22 shows an equivalent circuit for a 4:2 compressor using a full adder 448 (abbreviated as "FA" in various figures). This does not appear to have any advantage over two layers of full adders, but there are circuit-level implementations of 4:2 compressors that are faster and smaller than the cascaded full adders in most libraries.

[0140] Multiplier 305 may also be constructed from a pruned 32x32 with a 27x27 multiplier extended with a 16x16 SIMD extension as a fixed rather than movable extension. The move extension constitutes approximately 14% of the carry-save adder array and is therefore likely to be the preferred implementation. However, layout considerations may result in a fixed pruned 32x32 occupying less silicon area when additional inputs and tree switching are considered, even with a higher gate count. Circuit designers are allowed discretion in selecting a multiplier structure for minimum area. Additionally, product term optimizations such as Booth encoding are not considered in this specification, although such optimizations are permitted if overall functionality is maintained and the optimization results in a smaller physical footprint.

[0141] 5. Multiplier-shifter-combiner network 310 FIG. 23 is a logical block diagram of the post-multiplication multiplier shifter combiner network 310. The multiplier 305 is followed by the multiplier shifter combiner network 310, which is primarily designed to left-shift the mantissa up to 32 bits to convert to a system with a radix-32 exponent. Using a radix-32 exponent simplifies dynamic alignment shifts in critical accumulator loops. This multiplier shifter combiner network 310 also works to widen the SIMD lanes 309 (illustrated as four SIMD lanes 309A, 309B, 309C, 309D) to allow space for accumulation and alignment shifts when in one of the SIMD modes. The multiplier shifter combiner network 310 also includes the ability to align the SIMD lanes separately for single-clock summation of SIMD products in the RAE circuit 300 and sum them, as well as summing the sum of products from the four RAEs 300 in the RAE circuit quad 450.

[0142] The multiplier shifter combiner network 310 also right shifts 32-bit aligned products by multiples of 32 bits to facilitate summing with the add-Z input for fused multiply-adds, as well as aligning products with sums of products from other RAEs 300 in the same RAE circuit quad 450 for larger sums of products. The structure of the post-multiplication tree is shown in Figure 23. As shown, the multiplier shifter combiner network 310 includes multiple multiplexers, shifters, and compressors (described and discussed in more detail below, along with additional multiplier shifter combiner network 310 embodiments 310A, 310B).

[0143] In summary, the multiplier-shifter-combiner network 310: 1. A function to convert floating-point products to base 32 exponents (left-shifting by the exponent value of 5 lsbs), 2. The function to force the multiplier product to 0 when the multiplicand is a denormalized right shift or an excessive right shift, 3. The ability to add a right shift of 0 bits, 32 bits, 64 bits, or 96 bits to complete floating-point alignment with respect to the other addend, and 4. The ability to expand the SIMD lanes to 128-bit (four 32-bit lanes, two 64-bit or one 128-bit) lanes 309 that match the accumulator 315; and 5. The function to expand the complementary product of sign 2 to the width of the lane, 6. Ability to sum SIMD lanes in SIMD dot-product mode 7. The ability to add the sum of products from other RAEs in for the dot product mode, 8. The ability to combine partial products of single cycle 32×32 and double precision multiplications of the RAE circuit 300; 9. Ability to place 64-bit products into the upper, middle, or lower 128-bits to support INT64 multiplication Execute.

[0144] For floating-point products, the multiplier-shifter-combiner network 310 converts the data to base 32 exponent format by left-shifting the mantissa by a number of bits equal to the five least significant bits of the exponent. When this is done, the five least significant exponent bits are discarded and only the remaining exponent bits are used downstream.

[0145] The multiplier shifter combiner network 310 sums the products and Z-input adders before the accumulators. When operating in dot product mode, the products from all SIMD lanes, and also sums from other RAEs 300 in the same RAE circuit quad 450, are added to the sum. In floating-point arithmetic, addition requires all addends to have the same alignment, i.e., all exponents must be the same. The exponent logic 335 determines the largest base-32 exponent of all addends and right-shifts each addend by a multiple of 32 bits indicated by the difference between that exponent and the largest exponent. The exponent logic 335 is also responsible for determining the excess right shifts required to align products and Z-inputs with each other and with products from adjacent RAE units when those products contribute to the sum of products.

[0146] Because the quarter-precision and half-precision exponents are 4 and 5 bits, respectively, the base-32 exponent pre-shift perfectly aligns the mantissa in these cases and no further alignment shifts are needed to sum the products before the accumulator 315. In this case, the mantissa to the accumulator 315 is treated as an integer and the accumulator operates in integer mode. The final add / round / saturate logic can either leave it as an integer or convert it back to floating-point format.

[0147] The Z input 375 is combined with the sum of products to support functions requiring a common sum of products and simultaneous sum or difference of independent Z inputs. The FFT butterfly is an example using Z±(A*cos+B*sin). Negation and zero controls are added between the sum of products and the Z input adder to allow this and also to allow the Z input 375 to be used in conjunction with the accumulator 315 when products are used to feed the sum of products in adjacent RAEs 300. In modes with more than 5 exponent bits (double and single precision IEEE and BFLOAT16), an additional shift is required to equalize the exponent. If an additional shift is required, each small addend in the exponent is right shifted (and rounded to nearest as per the IEEE standard). The right shift distance is calculated using the excess exponent (the exponent remaining after converting to a base 32 exponent) as the number of 32-bit right shifts. If the number of right shifts is greater than 3, the addend is zeroed. In addition, there is a mode-dependent fixed bias required to align the output radix point to the correct position in the output format. These three shift amounts (translation left shift, alignment right shift, and bias shift) are summed to determine the net shift amount for each addend, and the net shift amount is recorded in the shifter control. The net shift decision for each addend is calculated and converted to a shift control in the exponent logic block 335. There are up to eight adders (four RAEs, each with a Z input and product) for single precision, and up to twelve adders for BFLOAT16, with two product and one integer adder per RAE300.

[0148] FIG. 24 illustrates the alignment of the multiplier product for each mode relative to the 128 bits of the accumulator 315. The multiplier product width is indicated by multiple shaded cells where cell 451 corresponds to the multiplier input width. Cell 441 indicates the location of the sticky bit in the unfused accumulator. In this design, the accumulator and adder have sticky bits that are 128 bits wide or less. The lines 453 between the cells indicate the location of the floating-point radix point when aligned on a 32-bit boundary. The cells labeled "X" indicate the sign of the floating-point. The cells labeled "Y" in the integer part indicate the location of the carry blocker.

[0149] Dot sums are accumulated in the RAE circuit 300 as ALUs into larger SIMD lanes and aligned to 32-bit boundaries by a shift network. For half-precision and quarter-precision floating-point, there is a maximum of 5-bit exponent, so a shift to a 32-bit boundary represents the entire representable range. Therefore, no further shifting or processing of the exponent is required in these modes. Bfloat16 has an 8-bit exponent, so an additional shift is required to align the product of sum of products in dot product mode. Depending on the mode, the exponent logic selects one of the BFLOAT16 dot product modes based on the difference between the most significant 3 exponent bits of that lane and the most significant 3 exponent bits in the RAE circuit 300, RAE circuit pair 400, or RAE circuit quad 450 (the number pair in the name indicates an additional right shift for the upper and lower lanes, respectively).

[0150] These additional BFLOAT16 modes shift one or both lanes right by 0 or 32 bits, or larger differences zero the lanes. The largest exponent (3msbs) in each RAE circuit 300 should be shared with the other RAE 300 in the RAE circuit quad 450 to resolve the shift. Resolution occurs in parallel with the multiplication in time for the shifting of the product. Single precision dot products require similar inter-RAE 300 exponent processing to determine if a 32-bit shift is required to align before the addition. For this reason, provisions for single>>32, single>>64, and single>>96 have been added to the shifter combiner network's function table. Like the BFLOAT dot product, the single precision dot product also requires the resolution of the upper exponent bits between the RAE EALUs to predetermine the additional shift.

[0151] To align with IEEE standard rounding, the shift combiner must incorporate the 128 accumulator bit width, plus the round, guard, and sticky bits for single and bfloat dot modes (which are also passed on to the accumulator round bits). For other dot modes, the fully expanded floating point is treated as an integer, so no bits are shifted in from the right side of the adder tree, except for double, single, and bfloat dot modes.

[0152] Floating point modes that hold floats in the accumulator (double, single, and bfloat) must shift by 3 or 4 bits in each lane to allow for growth in the pre-accumulator. The accumulator 315 is adjusted accordingly to maintain proper 3-bit alignment. The pre-add is also set to the lsb of the lane as the float's sticky bit when shifting out a "1" bit off the right.

[0153] Table 9 describes the output configuration of the flexible multiplier 305 along with the multiplier shifter combiner network 310. The logic of the multiplier shifter combiner network 310 receives its primary input data from the pruned 32-bit / 27-bit flexible multiplier 305. The input is 64-bit in carry-save format (two 64-bit vectors whose sum is the multiplier product). The data is separated into four 16-bit lanes 309 that are combined as needed to create two 32-bit lanes or one 64-bit lane. Each combined lane is negated or sign-extended for negative products using the multiplicand sign and negation control to determine the output sign. The contents of the multiplier output depend on the multiplier mode, as shown in Table 9.

[0154] [Table 9]

[0155] This configuration includes SIMD control to properly set the carry blocking for each lane. Static shift / zero control for inputs from the other RAEs is also included in the control inputs. Static configuration controls include or are decoded for (a) 1-bit sign extension control (one for each of the four lanes), (b) 2-bit multiplier SIMD size selection control for the first layer 4:2 compressor, (c) 2-bit accumulator SIMD size selection control (for the remaining compressor layers), (d) 2-bit shift / zero selection for the other RAEs 300 for paired inputs, (e) 2-bit shift / zero selection for inputs from the remaining half of the quad, and (f) 2-bit negate / zero control for the sum of products at the input to the Z input adder. Negation and zero control can be dynamically controlled using suffix (and / or conditional flag) input 380 logic.

[0156] The shift control for each shift selector is set by the exponent logic 335 block, which uses the exponent value and configuration to calculate the appropriate shift setting for each shift selector selection shown in the block diagram of Figure 23. The zeroing control for each lane is also derived from the exponent logic 335, which uses the exponent value and configuration to determine if and when a lane is zeroed (zeroed due to denormalization or multiplication by zero or right shift beyond a 128-bit accumulator). This includes the following shift controls: 1.5 bits 0:31 bits of left shift control are set for every 4 lanes 309. The lane is shifted left by the number of bits specified by the 5-bit unsigned binary control. 2.1-bit 0 / 32-bit right shift control, one for each of the 4 lanes. A "1" causes a shift, a "0" passes the data through unchanged. 3. One bit of zero-size control, one for each of the four lanes. A "1" zeros the lane, and a "0" passes the data unchanged. 4. 1-bit 0 / 32-bit right shift control (one for each of the two double lanes). A "1" causes a shift to occur, and a "0" passes the data through unchanged. 5. 1-bit 0 / 64 right shift control for the most significant 32-bit lane. A "1" causes a shift, a "0" passes the data through unchanged. 6. 1-bit 0 / 64 left shift control for the lowest 32-bit lane. A "1" causes a shift, a "0" passes the data through unchanged.

[0157] The Z-axis adder from the arithmetic output of the Z-input shifter 330 block is a 128-bit sum vector and a 4-bit carry vector consisting of two's complement increments for each of the four 32-bit lanes of the Z input. The carry vector bits replace the carry input to the LSB of each active lane that is blocked from the previous bit position from the 4:2 compressor stage 454 on the product data path preceding the 3:2 compressor 456 that applies the Z input. When lanes are combined, their carry vector LSB is taken from the carry output of the next lower lane. The Z input 375 is disabled by turning off the arithmetic output of the Z input shifter 330 block, thereby forcing the output to zero.

[0158] The input from the other RAE 300 in a linked pair of RAEs 300 and the output to that same RAE 300 are both 128-bit wide signals (two 128-bit vectors) in carry-save format. At the input there is a selector that chooses between unshifted data and data right-shifted with 27 bits of data. This selector also has a choice to zero the input if no link from the other RAE 300 is desired. The input shift mux is controlled by the decoded configuration word. The sum from the Z-input adder is the output to the other RAE of the pair. That signal from the Z-input adder is also summed with the input from the other RAE 300. These connections are always single lane, since the dot product mode pre-combines the SIMD lanes into one value before output to the other RAE 300.

[0159] The inputs from and outputs to the other half of the RAE circuit quad 450 are also 128-bit wide signals (two 128-bit vectors) in carry-save format. The inputs have a shift mux that selects whether they are unshifted or right-shifted by 27 bits of data. This mux also has a selection to force the input to 0 if a link from the other half of the quad is not desired. The input shift mux is controlled by the decoded configuration word. The sum from the pair adder of the RAE circuit 300 is the output to the other RAE 300 in the pair. That signal from the RAE pair adder is also summed with the input from the other half of the quadrilateral to form the accumulator output. These connections are always single lane, since the dot product mode precombines the SIMD lanes into a single value before output to the other RAE 300.

[0160] The output to the accumulator 315 is also a 128-bit output (two 128-bit vectors) in carry-save format. The output is split into two 64-bit lanes or four 32-bit lanes for SIMD operations. One or two lane accumulator outputs can be floating-point values, so are accompanied by accumulator exponent outputs for two lanes from the exponent logic 335. The exponent in the upper lane is a 6-bit base 32 exponent since it also functions as a single lane exponent with double precision. The lower lane is only used in BFLOAT16 SIMD mode and has a 3-bit base 32 exponent. The output of the accumulator 315 also has a data valid output to the accumulator, which is a delayed copy of the AND of the multiplicand data valid value and the Z input addend data valid value. The data valid value of the invalid input is ignored unless there is no valid input.

[0161] The post-multiply shifter combiner circuit operation and dynamic control inputs are controlled by a configuration word partially fed by the exponent logic block 335. The configuration sets the lane carry blockers and the static shift / 0 selects the input from the other RAE 300. The dynamic control sets the shift distance for each lane and shifter in the lane combining and alignment process. The 64-bit input from the multiplier is expanded to 128 bits and, in floating-point mode, a shift offset is also introduced to properly align the floating-point value within the 128-bit word and an exponent shift left further converts the mantissa to a radix 32 exponent. In SIMD mode, the width of each lane is twice the multiplier output. The shift of each input lane varies depending on the mode and its shift distance is the base to add the exponent radix shift. The lane expansion to obtain the proper lane and exponent=0 alignment is shown in Table 10.

[0162] The output from the multiplier with 16-bit spacing between each 16-bit lane going into the shifter. When multiple lanes are combined for wider lanes, the lanes are moved to fill the gaps. For a SIMD dot product, all lanes are shifted to the position of the lowest lane of the output and summed. For point 4, each lane is sign-extended before summing. For point 2, each input lane is sign-extended to 32 bits before summing.

[0163] [Table 10]

[0164] The lane shift is calculated by summing the lane exponent 4 or 5 lsbs with the mode dependent shift bias. The lower 5 bits of that sum directly control the initial 0:31 shift. The upper bit of the biased exponent is added to the excess shift distance from the excess shift logic for lanes 1 and 3, and then the sum is recorded in the shift control for the multiplexer in the combiner stage. Figure 25 shows the shift distance per mode for each lane and each second level shifter. Some modes in Figure 25 have additional refinements to the mode. A floating point dot 4 sum can be mapped to a quarter precision or half precision alignment in the left most output lane of that size. This requires a different shift bias. The BFLOAT dot mode takes into account the extra alignment shift required to equalize the base 32 exponent. The two numbers indicate the relative right shift of the upper and lower lanes as determined by the exponent logic.

[0165] The shift amount is different for each 32-bit lane depending on the exponent. Similarly, single and double have different shift settings for the four possible 32-bit shift distances, resulting in non-zero right-shifted data when adding to the Z input or other RAEs. These also require modulation of the shift setting controlled by the exponent difference from the maximum exponent, and therefore have separate row entries in the table. INT64 has three shift settings, supporting four cycles of shift-add-accumulate of partial products. The 64x64 multiply sequencer must sequence these shift settings in coordination with the multiplier sequence.

[0166] The block diagram of FIG. 23 shows the architecture of the multiplier shifter combiner network 310. The circuitry controls the shifters of each lane 309 individually to perform the lane shifting indicated on the shifter. Lanes 0 (309A) and 2 (309C) have a left shift range of −16 bits to 47 bits for a 64-bit bus. Lanes 1 (309C) and 3 (309D) have a left shift range of −32 bits to 31 bits. Each lane shifter contains a series of six 2:1 squares (316 in FIG. 26) arranged such that each data is either unshifted or shifted left by a power of 2 greater than the previous stage. The last stage has bias built in so that the last stage of the even lanes shifts 16 bits to the right or left and the last stage of the odd lanes shifts 32 bits to the right or does not shift. The output of the last stage is gated to force the lane output to 0 when the 0 control is asserted. The first stage is 16 bits wide, and includes the 16 bits from the multiplier lane plus the most significant bit, gated for unsigned and overlap.

[0167] Subsequent stages are wider by the amount of the bit shift, and the input most significant bit is duplicated to fill the output width (that input bit is the gate-extended sign from the input). The widths of the stages are 18, 20, 24, 32, 48, and 64 bits, respectively. The outputs of these lane-shifting networks are fed to a pair of 64-bit 2:1 compressors (multiplexers 311), one for the two lower-order lanes and one for the two higher-order lanes. When used for SIMD dot mode, the shift distance of the two lanes is set so that the lanes overlap and are summed in the 4:2 compressor 313 (the data is all in carry-save form through a shift combiner). In this case, the sign is extended to 64 bits wide. In other modes, the shifted data with the appropriate sign extension does not overlap, so the sum is the same as if an OR gate were used to combine the two lanes. The first compressor stage does not require a bit to handle overflow, since the bus width is extended to twice the maximum sum in dot mode.

[0168] FIG. 26 is a block diagram showing details of the lane shifting and first compressor circuitry. FIG. 27 is a block diagram showing additional logic to the 4:2 compressor for lane carry blocking. A second layer of shifters 452, also controlled by exponent logic, shifts the two combined lanes separately by multiples of 32 bits. The shift range for the lower lane is -32 to 64-bit left shift. The shift range for the upper lane is -96 to 0-bit left shift. These shifts are performed using two cascaded 2:1 multiplexers 449 as shown in FIG. 24. The data path width is sign extended to 96 bits at the input to the first shifter with a gated replica of the sign bit for both the upper and lower lanes, and the first shifter either passes the data unchanged or shifts it left by 32 bits on both lanes. The multiple lanes are independently controlled. The input is expanded to 128 bits at the input to the second level shifter. The bottom lane is sign extended to 128 bits, and the top lane is zero extended to 128 bits. Also, no overflow bits are needed because the dot combination doubles the lane width. The shifted lane outputs are summed using a 128-bit 4:2 compressor 461. The output of that compressor 461 then has the shifted Z= input, then the sum from the other RAE 300 in the RAE circuit pair 400, which is then added to it in turn by a series of 4:2 compressors 454 with the sums of the other half of the RAE circuit quad 450. The Z input uses a 3:2 compressor 456 because its carry vector is just four lane carry bits. Each compressor in the shift combiner has a gate that blocks carries across lane boundaries that is activated when the SIMD lane is enabled. The carry gate of the second level compressor connects to the carry from the Z input when the SIMD blocks internal carries. Figure 27 shows the additional logic for lane carry blocking. The compressor used to combine the adders requires three additional bits at the least significant end to implement the guard, round and sticky bits to comply with IEEE rounding for fused operations.

[0169] FIG. 28 is a block diagram illustrating an alternative embodiment of the multiplier shifter combiner network 310A. A possible alternative configuration adds a carry propagate adder 702 to the output of the multiplier 305 (along with gating the carry block of each lane) to resolve the carry save format of the multiplier tree to a non-redundant two's complement (single 64-bit vector) representation. This eliminates the duplication of the shift tree in the first layer required for the carry save output, saving many 2:1 multiplexer instances. The first stage 4:2 compressor used to sum the lane pairs is also eliminated, since the two single vector shifted lanes together represent a carry save pair. This removes many 4:2 compressor instances. As long as the added carry propagate adder architecture occupies less logic and meets timing, this should save a significant amount of silicon area. The logic after the first level remains unchanged. Also, lane zeroing can be pushed back to the multiplier output, where the data path is narrower. FIG. 29 is a block diagram illustrating another alternative embodiment of the multiplier shifter combiner network 310B.

[0170] 6. Z-input shifter 330 FIG. 30 is a block diagram showing the Z-input rotate / shift logic 330 data path. The RAE 300 includes a third 32-bit Z-input 375 that serves as an add input to the accumulator / adder, as well as an input to the Boolean logic circuit 325 and the compare circuit 320. This Z-input can be expanded to 64 bits by concatenating either the Z-input 375 of an adjacent RAE 300 (the other RAE 300 of the pair) or the Y-input 370 of this RAE 300 to the Z-input 375. The selection of the expansion source is controlled by the RAE 300 mode setting. The Z-input 375 is adjusted by a shift network designed to perform an alignment shift to match the multiplier product alignment. This shift network is also used by the Boolean shift / rotate functions required when the word size is 8, 16, 32, or 64 bits. The input of the Boolean logic circuit 325 is also connected to one of the compare block inputs for min-max comparison and sorting. The Z-input 375 and Z-input rotate / shift logic 330 support 1-lane, 2-lane and 4-lane SIMD operations for both arithmetic and logical operations. The Z-input rotate / shift logic 330 associated with the Z-input 375: 1. A function to recover the hidden bits of the floating-point input of each SIMD lane; 2. A function that sets the output data to 0 when a subnormal (exponent = 0) input is presented in floating-point mode, and 3. Functions to extend the SIMD lanes to 128 bits (four 32-bit lanes, two 64-bit or one 128-bit) to accommodate the adder, and 4. A function to convert a floating-point sign magnitude to a two's complement mantissa; A function to sign-extend the 5.2's complement output to the width of the lane, 6. Functions for integer logical shift and rotate operations on 8, 16, 32, and 64 bit lanes, 7. Functions that can place a 64-bit input at an upper, middle, or lower 32-bit boundary of a 128-bit input; 8. A function to select 0, inverted, or negated output for each lane; 9. A function to select 0 or inverted logic output for each lane; 10. Absolute value function and 11. Function to convert floating-point number to base 32 exponent (left shift with 5 lsbs exponent) and 12. Functions to add a 0-bit, 32-bit, 64-bit, or 96-bit right shift to complete a floating-point adjustment to the multiplier, and 13. Reorder lanes (8-bit lanes) function and To do so.

[0171] A typical Z input 375 is 32 bits in one of the following formats: single precision floating point, SIMD-2 half precision floating point, SIMD-4 quarter precision floating point, SIMD-2 BFLOAT-16, 32 bit integer, SIMD-2 16 bit integer, or SIMD-4 8 bit integer. The integers may be signed or unsigned. The input and comparison 320 blocks to the logical shift / rotate operations and Boolean logic 325 are only valid for unsigned integers. Other formats may be passed through, but when in logical mode they must be treated as unsigned integers by this block.

[0172] The Z input 375 may be extended to 64 bits by concatenating either the Y input 370 of this RAE or the Z input 375 of another RAE 300 to the left RAE pair of this input such that the extension becomes the most significant 32 bits of the 64-bit input. The 64 inputs may be signed integers, unsigned integers, or IEEE double precision floating point. When used as 64 bits, the most significant 12 bits of the extension are the sign and exponent of the double precision floating point. The extension is treated as an integer in logical operations and output. The extension inputs may also be concatenated such that the extension becomes the least significant 32 bits by adding an offset of 64 to the shift bias for the four main lanes and an offset of -64 to the shift bias for lane 4. The hidden bit and exponent mask bits must also be swapped up or down. This extension swap is necessary to allow the Z input division to match the x or y input division because the double exponent logic exists in a high x * high y RAE.

[0173] The configuration inputs set the shift or shift bias for each lane, select a mask, set the operating mode, select logical shift, rotate or zero and invert for logical outputs, and set signed or unsigned, negate, absolute value, and zero for arithmetic outputs. Negation and zero can also be controlled by an internal condition flag or a Z symbol. The configuration inputs set the shift or shift bias for each lane, select a mask, set the operating mode, select logical shift, rotate or zero and invert for logical outputs, and set signed or unsigned, negate and zero for arithmetic outputs.

[0174] The shift distance for integer formats is controlled by a bit in the configuration or by an external shift control applied via the X input 365 of the RAE. When the X input is selected, the 32-bit X value is separated into multiple 48-bit shift controls corresponding to each 8-bit input lane. The lower 7 bits of each control lane correspond to the shift distance, and the 8th bit is a lane disable. When the SIMD mode is set to 4, the four lanes of the X control correspond 1:1 to the four lanes of the Z input. When the SIMD mode is set to 2 or 1, shift sharing is enabled using the control lane associated with the most significant byte of the SIMD lane (control bits 15:8 control the lower 16-bit lane, bits 31:24 control the upper 16-bit lane, and bits 31:24 control all lanes for single lane SIMD). Similarly, the control word fixed shift setting is a 32-bit word divided in a similar way. For floating-point operations, the X shift adds to the floating-point exponent, providing a means to increment or decrement the exponent. A shift value of 0 (the sum of a lane's shift control and shift bias) places the data for the associated lane into the least significant bit, bit 0, of the 128-bit internal word. A non-zero shift value left shifts the data such that the LSB of the input becomes the bit of the 128-bit internal word equal to the sum of the shift control and shift bias. The dynamic control is generated by the exponent logic 335 and configuration.

[0175] The arithmetic output is the Z input to the post-multiply shift combiner 310 logic. This output is a 128-bit wide two's complement number (two 128-bit vectors) in carry-save format. The output is formatted to match the accumulator input (different for dot and complex product modes than for multiplier SIMD modes). The output can be a single 128-bit lane, two 64-bit lanes, or four 32-bit lanes. The 4-lane output is strictly signed or unsigned integer (quarter-precision and half-precision IEEE floats are fully expanded to integers with a left shift of 5 lsbs of the exponent). The 2-lane SIMD is two independent BFLOAT16 in the case of BFLOAT16SIMD multiply-add-accumulate, and signed integer otherwise. The BFLOAT16 output leaves the least significant 5 bits of the exponent shifted to 0 in the accumulator. A single 128-bit lane is a single or double precision float left-shifted to a base-32 exponent, then right-shifted by a multiple of 32 bits as necessary to fit the other addend. Alternatively, a single 128-bit lane is a 128-bit signed integer. The operation output 128-bit sum vector is the Z input that has been shifted, masked, passed on, and inverted or zeroed. The carry vector output contains only a two's complement increment of +1 in the least significant bit position of each lane. All other bits are implicitly 0, so there are only four non-zero bits in the carry vector. The carry vector bits replace the always-zero least significant bit output from the multiplier shifter stage before the Z input adder in the shift-combiner network.

[0176] The logic output of Z input rotate / shift logic 330 is a 32 (64 bit when extended) logic shift output that is connected to Boolean logic 325 and compare logic 320. This is the shifted and masked Z input, which has a second image of the shifted input shifted by the lane width, and is optionally ORed with the Z input shifted data to achieve the rotation. This output can be inverted (only shifts, not rotates) or zero. There is no two's complement increment on the logic output. This is to avoid an expensive carry propagate adder for increments. The logic output is for signed or unsigned integer inputs only. Signed integer inputs should not be used for rotate or lane reassignment operations, as sign extension would prevent proper operation of these functions. Signed inputs to shift results in sign extended shift data. With unsigned inputs, the sign of the shift is not extended. The unshifted data is passed as is (shift distance is biased by the width of the input lane, so a 0 shifted input will be right shifted by the width of the lane resulting in a 0 or an extended sign) input to the logic output. The X, Y, and Z input data valid flags are not used internally by the Z input logic.

[0177] The Z input operation and sources of dynamic inputs are controlled by a configuration word that is partially supplied by the Exponent Logic 335 block. The configuration selects the input mask for floating point, sign extension, shift distance or source of shift distance, lane mask, inversion / negation control or its source, rotate / shift function selection, lane disable, enable arithmetic and logic outputs (disabled outputs are forced to 0), logic window selection, exponent source selection for each lane, exponent input mask, and shift bias. Figure 31 shows the configuration of the Z input 375 by mode.

[0178] The RAE circuit 300 may also include a data path control device as follows. 1. Input Mask: The input mask filters the exponent by zeroing the masked bits and encodes the bits from the shift data in floating point mode. It can be used as a means to zero the exponent or lane disable (there are several points in the data path where lanes can be zeroed, but the entry points are at the designer's discretion). The input mask is set by the SIMD mode and input format. 2. Hidden bit: If a floating-point format is selected, the hidden bit forces a "1" bit into the floating-point hidden bit position. The hidden bit is overwritten by the zeroing of the lane. The hidden bit is dependent on the SIMD mode and input format. 3. Sign Extension: There is a sign extension control for each 8-bit input lane. If set, the shifter network will sign extend within that lane up to the width of the 128-bit shifter. When combining lanes to create 16, 32 or 64-bit input lanes, sign extension should only be set on the most significant lane. Sign extension should only be used for signed integer mode and in conjunction with a lane mask appropriate for SIMD mode to include the sign extension within the lane. The sign extension control is set in SIMD mode, entering format=signed. 4. Shift Distance Source: The shift distance source control selects whether the source of the shift distance is the configuration bits or the RAEX input. 5. Configuration Shift Distance: Sets a fixed shift distance for each lane when Shift Distance Source is set to Environment Settings. The shift distance is added to the shift bias and exponential shift for each lane to arrive at the lane's shift distance. If Shift Distance Source is set to X Input, the configuration shift distance is ignored. 6. Shift Bias: A 7-bit shift bias value for each lane is added to the shift distance and exponential shift to arrive at an 8-bit total shift setting per lane. 7. Floating-point alignment: The floating-point alignment indicates the source of the multiple of an additional 32-bit right shift for alignment of double, single, and bfloat modes. This is set in floating point format. 8. Shift sharing: Shift sharing selects the lane that controls the shift for each 8-bit lane. This allows the shift control to be shared by multiple 8-bit lanes, so there is no need to duplicate the shift settings on each lane. 9. Lane Mask Selection: The lane mask is selected from among the 32-bit fixed lane masks that are applied to the output of the shifter for each lane. You can select off, 2 lanes, or 4 lanes. This is set in SIMD mode and is overridden by the lane reassignment feature. 10.Negate / Invert: The source select selects the source of the negate / invert, and the bits for each lane control the 32-bit output lane. The sources are common to all lanes and include the settings of the X configuration word, the negate flag, and the msb of the lane. When the lane source is "1", the lane is inverted and the lane carry bit is asserted to the arithmetic output if the arithmetic output is valid. The lane inversion control follows the source lane shift share selection. When multiple lanes are combined per SIMD mode, the carry is only asserted for the least significant lane. 11. Rotate / Shift Mode: One configuration bit that sets whether the rotated image is combined with the shifted image to produce a logical output. A "1" indicates rotate mode. If logical output is disabled, the rotate setting is irrelevant. 12. Rotation Width: The rotation lane width is set to the lane width selected for SIMD and 64-bit extended instructions. 13. Enable Arithmetic and Logic: Two bits are used individually to enable the arithmetic and logic outputs. A value of "1" enables the output. When an output is disabled, the output is forced to 0 and the corresponding enabled data output is held at 0. 14. Logical Window: The logical window setting selects one of four windows that selects which bits are output to the logical shift / rotate output. The setting is determined from the logical output SIMD. 15. Exponent Mask - The exponent mask selects the number of bits passed to the exponent logic from the Z or Y input for each lane where multiple exponent widths apply.

[0179] The mask is selected in floating-point format. There are 14 modes that encapsulate format, SIMD, function, plus rotate select, output enable, and shift distance into minimal control inputs. In double precision mode, exponent logic in the RAE that processes the high*high partial products is required to access the exponent bits of each multiplicand. This requires adding a 64-bit extension to the lower half of the 64-bit and four local lanes to the upper half of the 64-bit Z input. This also places the exponent mask in the proper position. To achieve this, the shift distance is modified. The double HL inversion mode reflects this.

[0180] Referring to FIG. 30, the Z input rotate / shift logic 330 includes a variable 0-127 bit left shifter 458 for each of the five input lanes. Four lanes have 8-bit inputs corresponding to the four lane SIMD. The lanes are a combination of 2-lane and 1-lane. The fifth lane is a 32-bit wide lane connected to the extended input for 64-bit operations. The shifter is preceded by a mode-dependent mask 462 intended to mask the exponent and sign bits of the floating point numbers on input. The shifted data lanes are combined with a logical OR gate 464 and inverted to convert the negation or sign magnitude to a negative two's complement output. The inversion is performed for each 32-bit arithmetic output lane. The 32-bit arithmetic lane is mapped to an 8-bit lane for the logical output.

[0181] The selectively inverted outputs form the sum portion of the carry-save formatted output to the operation. The carry vector of that output contains the increment of the two's complement complement of each lane as required. The sum of the carry and save outputs is the two's complement representation of the shifted Z input of each lane, negated if the negate control is set. Setting the zero control forces the output to zero. Zero is asserted for floating-point inputs with exponent equal to zero, or in response to the zeroing configuration control of each lane. The Z-input logic pipeline latency matches the multiplier and post-multiply shift / combiner network latency from the input to the Z-input shift / combiner. When the shift is zero, the Z-shifter is zero-based so that the LSB of the lane input maps to bit 0 of the 128-bit output of all lanes. An input of 0 allows adding another mask between the shifter and the OR combiner to shift the lanes to the right, and also allows arbitrary permutations and combinations of lanes (e.g. 2-4 precision and half precision lanes), or even mantissa and exponent splitting.

[0182] Each lane has a mask 462 that replaces the floating-point sign bit and exponent bits with zeros and asserts a hidden bit at the input to the shifter. These mask values ​​per lane and mode are detailed in Table 11 with "1" bits corresponding to input bits that are forced to 0. The sense of the mask bits may be reversed for convenience in an implemented design. Also not shown in this table is the zero size control that forces the mask to all "1's" and the lane data to zero. Zeroing is asserted when the lane is deselected and when the floating-point exponent appropriate for the mode and lane is 0. Mask generation is part of the Z input exponent and control logic.

[0183] Z-input SIMD mode is not necessarily the same as multiplier SIMD mode. For SIMD dot product and complex multiply modes, the multiplier combiner reduces the number of lanes, resulting in a different mode in the Z-input and accumulator than that of the multiplier. Floating-point modes require the assertion of a hidden bit that is part of the IEEE and Bfloat formats. The hidden bit is asserted in the associated lane when a floating-point mode is selected. The hidden bit is always "1" except when forced to 0 by an exponent of 0 or when forcing the lane against a configuration control of 0. The hidden bit vectors are tabulated by mode in Table 12. The fixed input logic is masked <= (hidden OR (Z-inANDNOTmask)) and not zeroed.

[0184] [Table 11]

[0185] [Table 12]

[0186] FIG. 32 is a block diagram showing the configuration of shift network 458. The shift network for each lane expands the lane to 128 bits and left shifts the lane data from 0 to 127 bit positions based on a 7-bit control for each lane that occurs in the Z input exponent logic. As bits are shifted left, 0 bits are shifted right to fill. Each lane's shifters are 7 layers of 2:1 matrix, each shifting by a power of 2 greater than the previous shifter. To minimize the width of the shift network, the smallest shifts are done first.

[0187] The configuration of the shift network 458 is shown in Figure 32. The width of the first stage is input width + 1, the width of the second stage is input width + 1 + 2, and the third stage is input width + 1 + 2 + 4. The width of all stages is limited to 128 bits, so any bits beyond 128 bits are lost. The inputs for lanes 0-3 are each 9 bits (8 bits + extension for sign extension), and lane 4 has 32 bits + sign extension input (used for 64 bits only). The shift control is a function of the mode, which is the exponent for each lane in case of floating point mode, and the exponent for each lane in case of Z axis shift control. The shift control is taken from the Z input exponent logic. In case of signed integer mode, the shift network 458 sign extends the input to the width of the lane. To do this, the width of each stage of the shifter is increased by 1 bit, and that extended bit is duplicated to the next mux with 2k most significant bits on the unshifted input. The first layer mux sets the additional bit to overlap the most significant bit for signed integer mode, and 0 otherwise. For two-lane and one-lane signed integers, only the most significant lane of the lanes is combined and the sign of the wider lane is extended: the lower 8 sublane extension input bits are set to "0".

[0188] The output of each shift network 458 lane requires a lane mask to keep the output within the lane, otherwise the sign extension will propagate to the next most significant lane and the right shift for floating-point alignment will underflow to a lower lane. The bit ranges passed through the data for each lane in SIMD mode are shown in Table 13 below. If the mask is enabled, ranges outside the bit ranges shown are forced to 0. Lane masking is required in arithmetic mode; it can be disabled in logical mode to change the order of lanes. If signed integers are used for arithmetic shifts, it must be applied in logical mode. Lane reordering is only valid for unsigned inputs. This is because sign extension requires a lane mask to constrain the sign extension, but lane reordering moves the lane data outside the lane mask.

[0189] [Table 13]

[0190] The leftmost bit of the input lane is interpreted as the sign bit for both floating-point and signed integers, and as a data bit for the integer (this bit is masked into the shifter for floating-point formats, but is used by the exponent logic block to control negation and two's complement conversion).

[0191] The 128-bit output from each lane's shift network is logically ORed with the 128-bit output of all other lane shifters to form a single 128-bit composite output (from 464). Setting the shifters to 0 for all lanes places each lane's data least significant bit in bit 0 of the output. The shift values ​​on each lane are biased in the exponent logic block to give each lane a different shift and prevent overlapping lanes for arithmetic operations. The OR logic also contains a selectable inversion for each 32-bit lane of output that inverts all bits of the associated output lane (i.e. performs a one's complement on the lane data). The inversion is also controlled from within the exponent block as a function of the mode and sign bit. When used in arithmetic, the inversion forms part of the two's complement operation and is completed by sign extension and adding a one on the arithmetic output. The output of the lane combine and invert logic is sent to the arithmetic output and rotate image logic for logic output. Since the inversion and two's complement logic for each lane is controlled by the same lane of input, no reordering of lanes is allowed on the arithmetic output. Figure 33 shows the bit alignment by mode.

[0192] The operation output of the Z-input rotate / shift logic 330 is connected to the post-multiplier shifter combiner network 310 where it is added to the product or sum of products calculated within the same RAE 300. The operation output is two's complement signed data for each lane represented in carry save format as a pair of 128-bit vectors where the sum of each lane is a two's complement value that is added to the sum of products from the multiplier. The number of lanes depends on the accumulator SIMD mode, which may be the same or different than the multiplier SIMD mode. The lanes are 32-bit for SIMD-4, 64-bit for SIMD-2, and 128-bit for single operation. The sum vector is the shift-with-inversion Z input for each lane (if inversion is selected). The carry vector contains +1 to complete the two's complement in each lane. Since all other bits of the carry vector are always 0, these bits are not physically implemented so the connection to the post-multiply shift / combiner network is single ended and increments by one bit in each lane. The increment is done in the carry vector, eliminating the need to propagate the carry through the arithmetic output of the Z-input logic.

[0193] The rotated image 466 OR is a copy of the shifted data, left shifted by the input SIMD lane width so that the data is two concatenated copies. The logic output is windowed (468) and as the concatenated data is shifted through the window, the data in the window appears to be rotated. The bit positions in Figure 33 are shown for a 0 shift. The shift moves the lane input up by the number of shifted bits so that when a left shift is added, the bits shifted from the top of the window appear to re-enter the bottom of the window. When a shift rather than a rotate is selected, the red legend data is set to 0 instead of the offset shifted image, so a 0 shift results in no data in the window, and as the shift distance is increased, the most significant bits appear at the bottom of the window, with the maximum shift leaving only the LSB at the top of the window. In rotate mode, the rotated image requires an unsigned input because the OR with the sign extension is masked by the sign extension.

[0194] The logical output re-merges SIMD lanes into lanes of the original size by selecting only the bits within the lane window depending on the mode. Select via a 4:1 mux which selects the window for 4x8 SIMD, 2x16 SIMD, 32-bit or 64-bit output. The upper 32 bits are nulled to 0 when not in 64-bit mode.

[0195] Figure 34 is a block diagram showing IEEE single-precision to radix-32 floating-point format conversion. In floating-point mode, the exponent must be processed in addition to manipulating the mantissa data path according to the exponent value. The exponent of the product of two floating-point values ​​is the sum of the exponents of the multiplicands. In floating-point addition, the exponents of each addend must be the same in order to be added. If the addend exponents are not equal, the addend with the smaller exponent is shifted right by the number of bits represented by the difference of the exponents. After the right shift, both addends share the larger exponent and can be summed. If there are more than two addends to be summed, it is necessary to determine the largest exponent among the addends and shift the addend with the smaller exponent right by a number of bits equal to the difference of the exponents.

[0196] To minimize the amount of shifting in the accumulator 315 loop, the RAE 300 uses an unconventional internal format in which floating-point numbers are pre-shifted left by 31 bits to convert to a base-32 exponent. In adjusting the exponent to counter the left shift, the least significant 5 bits of the exponent are zeroed and then discarded, and all downstream alignment shifts are multiples of 32 bits. This modification significantly reduces the complexity of the exponent comparisons and shift logic in the critical accumulator loop, at the expense of a wider accumulator. Furthermore, the sum occurring before the accumulator 315 requires additional shift logic before the accumulator 315, and since there is more than one adder, each pass requires its own shifter. The conversion to a base-32 exponent is shown in FIG. 34 and is performed by the exponent logic circuit 335.

[0197] 7. Exponential Logic Circuits 335 35 is a block diagram illustrating the exponent logic circuit 335, which includes Z input exponent logic 465, overshift logic 470, and multiplier exponent logic 475, each of which is described in more detail below. In an exemplary embodiment, the accumulator 315 includes its own exponent logic.

[0198] The RAE circuit 300 also supports an inner product mode that sums multiple products and associated additional inputs from as many as four RAEs 300. Summing these products requires finding the maximum exponent from all addends and calculating the difference between each exponent and its maximum to determine the right shift distance for each addend's mantissa. IEEE half-precision and quarter-precision values ​​are converted to integers with a base-32 exponent conversion, so no exponent processing is required other than the conversion shift and shift bias to properly align the results in each lane. The accumulator 315 estimates the redundant sign bit and left shifts by a multiple of 32 bits when possible without overflow, and the accumulator exponent is decremented accordingly (the accumulator exponent is the left-most bit after removing the 5 lsbs). The post-accumulation final adder, rounding and normalization stage (340) renormalizes the accumulated sum and adds the normalization shift distance to the accumulator exponent value to reconstruct the full IEEE or Bfloat exponent as part of the normalization.

[0199] The exponent logic circuit 335 is the exponent processing before the accumulator 315. The functions of the exponent logic circuit 335 can be summarized as: summing the multiplier exponents to compensate for exponent bias, converting all floating-point inputs to base-32 exponents by left-shifting, finding the maximum excess exponent (excess is a base-32 exponent) among all adders including the exponents from other RAEs 300 in the RAE circuit quad 450, calculating the shift distance of each addend as 32 times its difference from the maximum value, adding a mode-dependent shift bias for correct output alignment, generating shifter settings for the Z input shifter 330 and the multiplier shift combiner network 310, and forcing the mantissa and exponent back to zero (converting denormality to zero) upon detecting an exponent of zero.

[0200] The excess shift logic 470 is the logic that determines the maximum exponent, including links to other RAEs 300 in the RAE circuit quad 450. The multiplier exponent logic 475 includes the summation of the multiplier exponents and the derivation of the shift network control for the shift combiner shifters. The Z input exponent logic 465 calculates the shift control for the Z input shifter 330.

[0201] Denormalized inputs are replaced with 0 (if the exponent is 0, the data path is forced to 0). In the rare cases where a denormalized number is needed, comparison block 320 and other logic in RAE 300 can be used to detect the denormalization and direct an alternate processing path to process denormalization using integer multiplication and addition, in accordance with the IEEE standard.

[0202] The 32-bit X, Y and Z inputs 365, 370, 375 are input to the exponent logic 335 to access the floating-point exponent and sign. These include multiple sets of exponents in SIMD mode.

[0203] Each RAE 300 outputs its local maximum 3-bit base 32 exponent as a 7 wire bar code signal. It converts the 3-bit exponent to turn on the number of consecutive wires indicated by the 3-bit code. These 7 wires are connected to each of the other three RAEs 300 in the RAE circuit quad 450 (not shown separately). They share the maximum exponent of each RAE 300, or in double mode, transmit the resolved excess shift to all RAEs 300 in the RAE circuit quad 450.

[0204] The shift controls for the 6 layer shifters and zero gates for each lane of the multiplier shifter combiner network 310 are generated by the exponent logic circuit 335. The four shift controls for the second level multiplier shifters are also generated by the exponent logic circuit 335. The shift controls for the 7 layer shifters and zero gates for each lane of the Z input shifter 330 are also generated by the exponent logic circuit 335. The four shift controls for the second level multiplier shifters are also generated by the exponent logic circuit 335.

[0205] The configuration of the Exponent Logic 335 generally includes controls for Z integer shift / rotation distance, Z shift source control (X input, set, exponent), numeric mode (SIMD lane, Float format) control, exponent mask (set numeric mode and SIMD) control, and enable controls for lane and neighbor RAE 300 inputs.

[0206] The excess shift logic 470 determines the number of 32-bit right shifts required for each adder. The Z inputs and products are summed for the general case of a fused multiple-add operation. This summation occurs before the accumulators 315 and before the outputs of adjacent RAE 300 product trees are combined. For clarity, the excess logic is discussed for both the Z input exponent logic 465 and the product adders.

[0207] The extra shift refers to the right 32-bit shift required to align the addends to complete the sum. In modes with more than four bits of exponent, the excess shift logic is needed to determine how much each addend needs to be right shifted. The excess shift logic 470 must first determine the maximum exponent among all the addends. Then, for each addend, it subtracts its exponent from the maximum to determine the amount of right shift that needs to be applied.

[0208] Up to eight addends with 8-bit exponents must be combined (four fused multiply-add products, each with a floating-point Z addend, with single-precision dot product). The Z inputs are added to the sum after adjacent RAE 300 products, but all summed products should be shifted to the same weighting, and the Z inputs of each product must be weighted similarly. Thus, the exponent logic circuit 335 looks at all active Z inputs, even if adjacent RAE Z inputs do not contribute to the local sum. This requires communication between the four RAEs 300 in the RAE circuit quad 450 to determine the maximum exponent.

[0209] In Bfloat16 mode, there are two floating-point values ​​with independent 8-bit exponents per FPMAC. For the BFLOAT dot product, the two products from each FPMAC and one Z input addend are summed, requiring up to 12 addends with exponents. BFLOAT without the dot product does not allow for fused sums of adjacent RAEs, as the inter-RAE exponent connection does not support two exponents. Finally, in double-precision floating point, a single fused multiple-add is possible combining four RAE cores. Modes with excess exponent shifts are summarized in Table 14.

[0210] [Table 14]

[0211] FIG. 36 is a block diagram showing the overshift logic 470 for the Z-shifter 330 and the multiplier-shifter-combiner network 310. FIG. 37 is a block diagram showing a 3-bit index to 8-bit bar circuit 480 with two input x fan output 2 (2×2) gates, where the "1" shown is a buffer. FIG. 38 is a block diagram showing a tally circuit 485 that converts the XOR difference of multiple bars to an index using a full adder. FIG. 39 is a block diagram showing an 8-bit bar to 3-bit index circuit 490 with two input x fan output 2 (2×2) gates.

[0212] The excess shift logic 470 contains a 12 addend process as its core, with logic added for special handling required by the wider exponents and inherent distribution requirements of double precision. An extra copy of the large addend process is used for the second BFLOAT16 lane in SIMD mode. The excess shift logic 470 simplifies the task of comparing up to 12 3-bit excess exponents by converting each 3-bit exponent to an 8-bit bar representation (the representation of the bar is similar to a one-hot decode, but in addition to the one-hot bit, all bits lower than the decoded bit are also on). This is a less complex decode than a 1-hot, and this design has advantages. To find the maximum exponent, the most significant 7 bits of each bar are bitwise ORed (the least significant bit of the bar is always a "1", so it is discarded). The tallest bar takes precedence over the shorter bars and corresponds to the maximum exponent. The OR tree is split into local 3-inputs by 8-bit ORs to precombine one or two product exponents and the Z input exponent from within the RAE 300. The OR is constructed from AND-OR-INVERT gates 471 so that each input to the OR has a gate to block the selected input. The local maximum of the seven lines is sent to each of the other three RAEs in the RAE circuit quad 450 via a dedicated 7-bit connection between the RAEs 300.

[0213] Each RAE's receiver has three 7-bit inputs from the other RAEs 300 and an internal 7-bit input from itself. These are ORed together within each RAE 300, with each RAE holding a copy of the max bar. The RAE combiner structure is also an AND-OR-INVERT gate, so that inputs from other RAEs can be blocked at the input to this RAE (allowing RAEs to be used in independent sums or paired with independent sums). The max exponent bar is bitwise exclusive-ORed with each local BAR source individually. The exclusive-OR output has a "1" bit only on those bar bits that differ from the max value. The count of "1" bits indicates the difference of the exponent to its addend. This difference is recovered as a binary index using a 7-bit tally addition to count up 1 bits (these are consecutive, but can be anywhere in the 7-bit field) using tally circuit 485.

[0214] The maximum actual shift is a 332-bit shift, or 96 bits. Beyond that, the shift is 128 bits or more, so the addend is zero. The value of the two least significant bits of the tally adder corresponds to a shift of 0, 1, 2, or 3 32-bit shifts. The remaining tally adder bits, a '1', make the addend zero. This difference is the maximum value minus the local exponent, so it always results in a non-negative shift.

[0215] The difference max-Z is the excess shift of the Z input, and similarly the difference max-Product is the excess shift of the product. These extra shifts are applied to the associated shifter network via the encoding block to control the added right shift. The max bar is also decoded into an index representing the maximum exponent. This is used by the accumulator as the exponent of the accumulator input. The tally adder 485 could also be used to decode the accumulator exponent, but since the output is always a bar, the decoding is simpler and does not require the full adder of the tally adder. The second bfloat lane has a local-only version of the same extra logic to find the maximum of the input and product of lane 1Z. There are no links outside the RAE of this second max, so it is simply a local OR of the excess exponents of the two addends. The max is converted to the binary exponent of the accumulator, and the extra shift distance is calculated the same as for the primary.

[0216] The logic for double precision is different because the exponent excess is 6 bits instead of 3 bits, and there are only two addends (the z input and the product, there is no dot mode for doubles). Double precision is unique because the multiplier is distributed to four RAEs, and as a result the product excess shift must be distributed to other RAEs 300 in the RAE circuit quad 450. The double precision excess logic resides in the same RAE 300 that contains the product of the most significant X and Y bits, and both exponents are calculated. Additionally, the Z input logic uses an input expansion function, which must be the least significant half for the Z input logic to reside in the same RAE as the more significant input. Because both the X and Y inputs use the multiplicand, the Z expansion input is taken from the Z input of the adjacent RAE. The bias of the expansion in the least significant bit of the Z shifter is corrected in the Z input for this special case (double inverted HL).

[0217] The double excess logic performs X+YZ using a carry-save adder that provides a 12-bit final sum to find the difference between the product exponent and the addend exponent. This is done in a separate adder rather than having the delay and additional space of two layers of look-ahead adders to get the fast (X+Y)-Z. A sign bit is added to the 12-bit difference to identify which is the larger one. The 12-bit sum is fed to a decoder that directly re-encodes the 12-bit binary into a pair of saturated 5-bit BAR values ​​for the excess product shift and excess Z input shift. The truth table for the decoder is shown in Table 15. Each bar value is "0" padded on the left to an 8-bit bar and the least significant bit is not calculated to arrive at a 7-bit bar similar to that used in the primary excess circuit. The product bar is wired to a local AND-OR-invert max so that it has a path to distribution to other RAE300s.

[0218] In double mode, the other input to the AND-OR-INVERT is disabled and the product excess shift is output unchanged. At the receiving end of each RAE, only the input from the RAE that computes the double excess is enabled. Double mode turns off the other input to the lane 3 excess shift logic, allowing the product excess shift to be decoded into the correct shift. In RAEs that contain arithmetic double excess difference logic, the Z excess bar is wired within the same RAE and connected directly to the Z excess shift tally adder via a multiplexer, which converts directly to the Z shift distance.

[0219] The MSB of the difference adder output is used to select which of the 6 most significant bits of the multi-exponent sum X_PLUS_Y or Z exponent is used as the accumulator exponent. The MUX controlled by the DOUBLE MODE selects between that maximum double exponent and the maximum decoded exponent from the primary excess logic described above (the exponent is 0 extended 3 bits to the left in the accumulator to use the same exponent logic for both double and single precision).

[0220] [Table 15]

[0221] FIG. 40 is a block diagram illustrating the multiplier (and shift combiner) exponent logic 475. A separate product exponent must be maintained for each SIMD lane. The product exponent is the sum of the multiplier exponents for that lane. Additionally, each multiplier exponent must be checked for equality to zero. Also, if any one in the lane is zero, the product for that lane will be zero since denormality is treated as zero. The exponent adder 476 for each lane may be extended by one bit to detect exponent overflow. If implemented, the exponent overflow can be sent to the suffix (and / or conditional flag) output 405 of the RAE for use in generating infinity using additional resources.

[0222] The least significant product exponent bit of each lane is added to the removed mode-specific bias and provided to the shift combiner logic to control the exponent pre-shift. For modes where multiple products and / or Z input addends are summed (dot and complex multiplication), the maximum product exponent must be selected and each product must be shifted to the right by the difference between its exponent and the maximum exponent to align the mantissa.

[0223] The calculation of the maximum exponent was described in the previous section, Calculating the Excess Shift. The shift to align the mantissa is a right shift by a multiple of 32 bits. Shifts of 128 bits or more will underflow the adder width, so if the extra shift exceeds 3*32 bits, the adder or product is replaced with zeros. The maximum base 32 exponent is passed to the accumulator as the exponent of the sum of the product and addend. Figure 40 shows the multiplier exponent logic 475, which is described in more detail below.

[0224] Four separate exponents are maintained for each RAE300 to accommodate all SIMD modes. In four lane mode all four exponents are used, in two lane mode two of them (lanes 1 and 3) are used, and in the remaining modes only one (lane 3) is used. Double precision floating point formats have an 11-bit exponent and only use lane-3 exponent logic. Single precision floating point has an 8-bit exponent and only use lane-3 exponent logic with the 3 LSBs disabled by masking them to 0, leaving 8 bits active. Bfloat16 is a two lane SIMD with an 8-bit exponent. The top lane has the 3 lsbs masked, and the bottom lane uses the 8-bit lane 1 exponent.

[0225] Half-precision is also two SIMD lanes, using lanes 3 and 1, but because the exponent in half-precision is 5 bits, all but the most significant 5 bits of the exponent in these lanes are masked for half-precision and no extra shifts occur. Quarter-precision is a four-lane SIMD with a 4-bit exponent. The exponents in lanes 0 and 2 are only used in quarter-precision, so the exponent logic in these lanes is fixed at 4 bits. The exponents in lanes 1 and 3 are masked to use only the 4 MSBs in each of these lanes for quarter-precision. As with the half-precision IEEE format, the exponent is less than 6 bits, so there are no extra shifts.

[0226] There is also zero-detect logic for each multiplicand exponent, masked to match the current mode exponent width. If any of the lane's multiplicand exponents is zero or the excess shift is greater than 3x32, a force lane 0 signal is generated. A set of multiplexers selects the appropriate force 0 signal to apply to each lane depending on the SIMD mode.

[0227] A second set of multiplexers selects the appropriate 5 LSBs from the appropriate product exponent to control the radix-32 shift in each lane. Because the multiplier product is not folded before the accumulator, there is no need to adjust the product exponent. The mantissa data path width allows for extra bits to the left of the radix point and growth when summing products.

[0228] The lane shift is calculated by summing the lane exponent 5lsbs with the mode dependent shift bias. The lower 4 bits of that sum directly control the initial 0:15 shift. The upper bit of the biased exponent is added to the overshift distance from the overshift logic for lanes 1 and 3, and the sum is then recorded in the shift control for the multiplexer in the combiner stage.

[0229] The shift distance for the post-multiplication shift combiner is tabulated in FIG. 25 (where E4 and E5 represent the 4 and 5 LSBs of the product exponent, respectively, a negative shift is a right shift, a positive shift is a left shift, and "0" indicates that the lane is forced to all "0's", and "0" indicates a 0 shift). Note that the shift distance is affected by the mode, the exponent LSB, and in some modes the difference between the exponent associated with the shifter and the maximum exponent of the sum value. Post-Multiplication Shifter-Combiner Shift Distance

[0230] FIG. 41 is a block diagram illustrating the Z input exponent logic 465. The Z shifter 330 should align the Z input with the shifted multiplied sum of products in each lane to sum the product and Z component. The multiplier 305 product is pre-shifted to an exponent that is a multiple of 32 to remove the least significant 5 exponent bits. Similarly, the Z input exponent logic 465 pre-shifts the Z input data to remove the 5 least significant exponent bits using the 5 exponent LSBs to perform the shift. A mode-dependent shift bias is added to the shift of each lane to perform the appropriate shift and place the mantissa in the lane properly. The exponent logic also has an input for an integer shift specified by configuration or from the X input.

[0231] For modes with more than 5 exponent bits (double and single precision IEEE and BFLOAT16), an additional shift beyond the pre-shift is required to align the Z input to the multiplier. The additional shift is determined by the excess shift logic already described in the Exponent Excess Shift section. The excess shift is multiplied by -32 and added to the biased shift to get the 0:127 bit shift distance for each lane. The per lane shift biases tabulated by mode are detailed in Figure 29A. The shift total is 8 bits and an extra msb is used to detect shifts beyond the 0:127 bit shift range. This shift overflow is used to force a lane to 0 when it is shifted beyond 127 bits.

[0232] The exponent logic also has a compare-to-zero circuit for the exponent of each input lane to detect zero exponents. For lanes 1 and 3, the exponent LSB is masked depending on the mode to select an 11, 8, 5 or 5 bit exponent. Lanes 0 and 2 have no exponent or only a 4 bit exponent. Detection of the exponent equal to zero for each lane is selected by the mode selector to generate the 0 lane logic, the output of which is combined with the shift overflow for the lane (not shown) to generate a force lane 0 signal for each lane.

[0233] 8. Accumulator 315 42 is a block diagram illustrating accumulator 315. Accumulator 315 is a fused 128-bit accumulator designed to accumulate the sum of products provided by multiplier-shifter-combiner network 310. Accumulator 315 is multi-mode offering a variety of floating-point and fixed-point formats and supports 1-lane, 2-lane and 4-lane SIMD operations.

[0234] The accumulator is a register adder arranged to sum successive inputs with one input fed by its previous output and the other input being the sum of the successive inputs by the multiplier shift combiner network 310 logic (the sum of the Z input and the products from this RAE 300 multiplier 305 and the appended RAE 300 multiplier products). The inputs, outputs and internal data paths of the accumulator 315 are in carry-save format. The accumulator 315 supports one 128-bit, two 64-bit or four 32-bit integer arithmetic lanes, or one 128-bit (IEEE double or single) or two 64-bit (Bfloat16) floating point lanes. The accumulator 315 includes an accumulator exponent operator 513 and a shifter 511 that supports base-32 exponents (shifts by multiples of 32 bits). Shifter 511 serves to renormalize left shifts by 32 bits and right shifts by a multiple of 32 bits to the smaller of the multiplier input (Z input) or accumulator feedback to align the radix point for addition.

[0235] In summary, accumulator 315 operates as follows. 1. Sum consecutive inputs in a format of your choice. 2. Supports 1 x 28-bit lane, 2 x 64-bit lane, and 4 x 32-bit lane integer accumulation. 3. Supports IEEE double-precision and single-precision floating-point accumulate (1 lane). Supports 4.2 lanes of BFLOAT16 floating point accumulation. 5. To align the radix point for the addition, the accumulated sum before the floating-point or Z input is right shifted (the lesser of the exponents is shifted) by a multiple of 32 bits. 6. When driving in 2-lane or 4-lane mode, use carry blockers and shift blockers to separate lanes as needed. 7. Calculate and maintain the accumulator exponent for each floating point lane. The exponent is a base 32 exponent, which is 3 bits except for double, where it is 6 bits. 8. To renormalize base 32 values, left-shift the accumulator output by a multiple of 32 bits (and adjust the accumulator exponent accordingly). Single register delay around accumulator loop with 9.1GHz timing. 10. Floating-point right shifts require the auxiliary rounding bit to be set for each lane to support rounding towards even. 11. The extra bits on the left side should be detected to preserve adder overflow and perform a right shift and exponent increment to correct floating-point overflow. 12. Integer overflow needs to be detected and latched with the sign and passed to the final adder logic for integer saturation logic. 13. If the right shift exceeds the lane width, either the Z input or the accumulator feedback is forced to zero. 14. Initialize the accumulator by forcing the feedback input to 0 upon the first valid input at the Z input. 15. Preserving initialization conditions for all inputs allows for fused multiply-add (without accumulators). 16. The leading code predictor output is fed to the final adder. The leading sign predictor indicates n or n-1 repetitions of the sign bit (used to control the internal shifts in multiples of 32 bits and to control finer shifts in the final adder). 17. Register the input and output of accumulator Z. 18. Convert integers to floats, 1, 2 or 4 lanes (if attached to the final addition logic).

[0236] Referring to FIG. 42, for fixed-point arithmetic, all accumulator shifts are forced to zero shifts and the exponent register is ignored or unused. If the initialization flag is '1', the shift right logic of the accumulator feedback forces the feedback accumulator value to '0', allowing the accumulator to copy the value present at the Zin input in two's complement carry-save format. If initialization is '0', the current value in the accumulator output register is fed to the right input of the 4:2 compressor 509, unshifted, and added (in carry-save format) to the unshifted Zin input data, with the carry-save sum being placed back in the accumulator register. If the addition causes an overflow into the extra MSB, the overflow flag for the lane in question is set and remains until the accumulator is reinitialized. Fixed-point operation allows two-lane (64-bit each) and four-lane (32-bit each) SIMD modes in addition to the default 128-bit single-lane mode. In the multiple lane case, the 4:2 compressor 509 has a carry blocking gate between each lane, and each lane is fitted with an auxiliary MSB to detect overflow. The input shifter 511A is always set to 0 shift to perform fixed point accumulation. The output shifter 511B may be used at the designer's discretion to select one of the four 32-bit fields for output if timing and functional requirements can be met to reduce logic gate count.

[0237] The accumulator uses a base-32 exponent to simplify the shift logic in the critical accumulator loop. The input data is pre-shifted left by 31 bits so that the lowest 5 exponent bits are zero. These zeroed exponent bits are dropped, leaving only the exponent bits on the left. All alignment and normalization shifts in the accumulator are done in multiples of 32 bits. This implementation reduces the layers of shifters in the accumulator and also significantly reduces the accumulator exponent logic, helping to close the timing. The IEEE 1 / 2 and 1 / 4 precision formats (with 5 and 4 exponent bits respectively) are effectively converted to integers by a base-32 exponent conversion done in the shift combiner and Z-shift logic. For these two formats, the accumulator operates in the appropriate integer mode. The accumulator design omits SIMD Bfloat since this mode is a special case that requires significant additional hardware. The accumulator floating-point mode is always single precision lane, with rounding to single precision in the final adder if single precision is selected. In integer mode, the accumulator can operate as one 128-bit lane, two SIMD64-bit lanes, or four SIMD32-bit lanes. In floating-point addition, the radix point of both addends must be the same. This means that one of the addends must be shifted relative to the other until both exponents match. In this design, the adder with the smaller exponent for the right shift (4:2 compressor in the diagram) is selected by the number of 32-bit shifts required for alignment. Each 32-bit right shift corresponds to adding 1 to the exponent associated with that input. The exponent logic calculates the direction and distance of the required shift, and the shift logic right-shifts the smaller input by the correct multiple of 32 bits. For shifts of 128 bits or more, the smaller input is shifted out of the 128-bit width of the adder, so the larger shift shifts in 0 instead of shifting the input. Shifting also sets the IEEE round, guard, and sticky bits added to the lsb end of the 128-bit accumulator to support IEEE round to nearest even mode.In floating-point two-lane SIMD (only used in BFLOAT16), three bits for rounding are added to the LSBs of both lanes. If the signs of the two addends are opposite to each other, the accumulator result may have more leading sign bits than either of the inputs. If the number of leading sign bits is large enough to allow a left shift without losing sign, the output shifter left shifts the data by a multiple of 32 bits to remove the extra leading sign bits, thereby renormalizing in a radix-32 exponent system. The accumulator exponent is decremented by the number of 32-bit shifts to adjust the exponent for the left shift. The exponent logic is 8 bits wide, i.e., 6 bits (11 to 5 bits) corresponding to the IEEE double exponent, plus an additional 2 bits to detect exponent overflow and underflow.

[0238] Accumulator 315 has three extra bits on the left side, enough to absorb any overflow (extra bits are also present in later stages of the multiple shift-combiner logic chain). When an overflow into these bits occurs, the accumulator output shift performs a 32-bit right shift and associated increment of the accumulator exponent to correct the overflow. Accumulator 315 does not support SIMD floating point, and half and quarter precision IEEE are converted to integers by radix-32 exponent conversion. The inventors chose not to support Bfloat16 SIMD with the accumulator to substantially reduce the complexity of the accumulator. For floating point SIMD-2 (BFLOAT16 only), the extra MSB is added to both lanes. In floating-point SIMD-2 mode, the bit 64 lane blocker of the 4:2 compressor is active to prevent lane 0 from affecting the lane 1 total, and all shifters require additional gates to replace data shifted from the lower lane to the upper lane with zeros, and data from the upper lane to the lower lane with an extended sign.

[0239] The accumulator 315 encodes the mantissa, primary and secondary exponents (to support SIMD-2) along with the valid data from the multiplier shift combiner network 310. It also provides common settings for all SIMD lanes, initialization of accumulator flags, reset and clock inputs. Block outputs include accumulated data, primary and secondary exponents, estimated number of leading sign bits, and accumulated data valid flag.

[0240] The Zin signed mantissa input 502 portion is presented in carry-save format (actually, 3-bit extension in the lsb of each SIMD-2 lane, a TBD bit in the msb of each SIMD2 lane, and a TBD bit in the msb of each SIMD4 lane) 128. The input is registered on entry to the accumulator logic, which is clocked by the data valid input signal. The Zin mantissa can be one 128-bit lane, two 64-bit lanes, or four 32-bit lanes, with auxiliary extension for IEEE rounding in the lsbs, and an extended sign for overflow detection / correction in the msbs of each lane. The data is signed 2-s complement represented in carry-save format.

[0241] The 6-bit Zin primary exponent input 504 is a base 32 exponent that corresponds to the 11-bit IEEE double exponent. It is also used as a 3-bit base 32 exponent for the upper lane (lane 1) of IEEE single and SIMD-2 BFLOAT16. The exponent is converted to base 32 for BFLOAT and IEEE single, and modulo 1023 for IEEE double, also converted to base 32. The exponent may be extended by one bit to aid in detecting and handling exponent underflow and overflow.

[0242] The 3-bit Zin secondary exponent input 506 is a base-32 exponent that corresponds to the 8-bit BFLOAT exponent corresponding to lane 0 when floating-point SIMD-2 mode is selected. The secondary exponent input is ignored for all other modes, but designers may request that the primary exponent be replicated in the secondary input for other modes to simplify logic in the accumulator's critical timing loop. The exponent may be extended by one bit to aid in detecting and handling exponent underflow and overflow.

[0243] The accumulator logic holds its current state except when valid Zin data 508 is asserted. A "1" condition indicates input data on the Zin mantissa and the exponent is valid for the selected mode. If the initialization flag is "1" at the same time that Zin data is valid, the value of Zin is copied to the accumulator register without adding anything (a normalizing left shift can be -32, 0, 32, 64, or 96 bits if there is an overflow (right shift) or if there are enough leading sign bits resulting from a subtraction in the shift combiner to allow for a normalizing shift). If the initialization flag is "0" and ZinDataValid="1", the data at the Zin input is added (with the appropriate alignment shift) to the current value of the accumulator output.

[0244] In an exemplary embodiment, the tlast flag 510 is used to output the accumulated sum and reinitialize the accumulator with the next valid input. Tlast is set to "1" for the last valid sample in the accumulated series of samples. The accumulator asserts valid output data when the last input sample outputs the added sum and reinitializes with the next valid data input (reinitializing means reading without adding anything to the ZIN data). When Tlast goes to "1" without any valid data, the accumulator reinitializes with the next valid data without outputting any valid data.

[0245] In another embodiment, the initialization flag 510 forces the accumulator feedback to the adder to zero so that the value on Zin is copied to the accumulator. The copied value is renormalized when the mode is floating point if the input's data has an overflow or has more than 31 leading zeros. The initialization flag also gates valid accumulator data so that it is only asserted on the same clock that the accumulator is written with new initial data. This gate is overridden by the accumulation configuration bit so that there is valid accumulator data for all valid inputs.

[0246] The output 128-bit mantissa 512 is represented in carry-save format (two 128-bit vectors). The output can be one 128-bit lane, two 64-bit lanes, or four 32-bit lanes. Data is a signed 2-s complement number represented in carry-save format. Data is valid only if the AccumulatorDataValid flag is present. Data out is asserted one clock after valid data, and data out is the accumulated value before replacing the accumulated sum with new initial data in the accumulator register.

[0247] The estimated leading sign bit output 514 indicates the number of leading sign bits in the accumulator before the internal 32-bit and 64-bit renormalizing left shift or the 32-bit overflow correcting right shift. It is an encoded output that indicates the number of repeated sign bits in the accumulator output. This estimate can have an error of 1 bit indicating n or n-1 repeated sign bits depending on the distribution of bits between the carry and save vectors. The encoded leading sign bit is used by the final adder logic to renormalize the data and exponent to IEEE format. The final adder logic (340) decodes the data to determine if additional shifts are needed to complete the renormalization.

[0248] The primary accumulator exponent output 516 is nominally 8-bit over-127 for IEEE single and bfloat, and 11-bit over-1023 for IEEE double. These are changed to 12-bit over-2047 codes for all floating point, allowing floating-point overflows and underflows to be easily detected and exception flagged. The shift combiner and Z input shift circuit convert the 12-bit exponent to a 7-bit base 32 exponent by left-shifting the mantissa from the 5lsbs of the exponent to 0 and dropping these zeroed bits. If the accumulator configuration is not in floating-point mode, the accumulator exponent output is undefined.

[0249] The secondary accumulator output 518 is the most significant 3 bits of the 8-bit over-127 exponent used only for floating-point SIMD-2 (BFLOAT16 only) mode. This output is undefined in other modes, but designers should use them to replicate the lsbs of the primary exponent output if they wish to simplify accumulator or final adder logic. The exponent may be extended by one bit to aid in detecting and handling exponent underflow and overflow. The exponent output is also undefined when the accumulator is operating in any of the fixed-point modes.

[0250] Optionally, the accumulator data valid output, when it is "1", indicates valid data on the accumulator output, including leading sign, mantissa, and exponent (some of these fields are undefined in some modes). Otherwise, the data is considered invalid. Valid accumulator data is "1" one or two clocks after valid data depending on configuration, gated by the initialization flag and accumulation configuration.

[0251] The settings include, for example: 1. It may include a control for SIMD settings, and a control to set the number of lanes for fixed-point operations: 00=1 lane, 10=2 lanes, 11=4 lanes; 2. Fixed-point or floating-point control of floating-point selection, In the case of floating point, SIMD has internally forced control to “00” and 3. Control without the accumulation bit (passing the input to the output every cycle) is equivalent to holding init=1, 4. Control of the cumulative sum, Cumsum, bit, which outputs valid data each time an input is added to the sum; 5. Control of the Cumsum control bit; 6. Format bits (3) set the numeric format, fixed / float, control the number of lanes, 7. Control of the no accumulator bit (which allows external accumulator operations to be performed) similar to holding init=1, 8. Can be combined with CUMSUMM, data valid delay bit control and can be included.

[0252] When the accumulation configuration bit is set, the valid data out of the accumulator 315 will be "1" corresponding to all ZinDataValid. This allows for the generation of a cumulative sum such as used for counters and integrations. If cumsum="0", the valid data is only valid for the clock cycle before the accumulator register is updated with new valid data that arrives at the same time as the initialization flag="1". Cumsum also needs to delay the valid data by one clock so that the output is accumulated after adding the latest input. Examples of formatting for floating point and fixed point formats and lane counts are shown in Table 16.

[0253] [Table 16]

[0254] The no-accumulate configuration bit forces the accumulator 315 feedback to always be 0 when set to "1". This makes the accumulator a normalized pass-through for floating point and a simple pass-through for fixed point. Internally, this is the same as forcing the initialize flag to always be "1". This configuration bit can be removed if there is an external means (in the condition flag logic) to force the initialize flag to "1".

[0255] Figure 43 is a circuit diagram showing the accumulator 315 with the exponent in the second lane (Bfloat only) greyed out to highlight the critical path. The RAE accumulator 315 uses a radix-32 shift to minimize logic levels in the critical feedback path from the accumulator output register, through the accumulator, and back to the register.

[0256] Fig. 44 is a circuit diagram showing an N*32 shift circuit 517 used in the accumulator 315. Fig. 45 is a circuit diagram showing the structure of a tally-to-bar circuit 519 having a depth of log2(n) with logic added for SIMD splitting, which is also used in the accumulator 315.

[0257] 9. Boolean Logic Circuits 325 FIG. 46 is a circuit diagram showing Boolean logic stages 520 of Boolean logic circuit 325, where 32 bits can be independently configured using Boolean logic stages 520 for each bit input to Boolean logic circuit 325. Boolean logic circuit 325 provides a configurable bitwise Boolean logic circuit 325 that is used to complement the RAE 300 ALU functions with a full set of two input Boolean functions. Each bit on the 32 bit data path has an independently programmed Boolean logic stage 520 capable of any two input Boolean function of the input bit in the same bit position. Boolean logic circuit 325 also provides a way to provide a bitwise 2:1 selection controlled by X input 365. The 32 bit output is complemented by a 32 input NAND 522 with a 32 bit output and sent to the condition flag output logic.

[0258] The Z input is connected from an index counter in the compare block 320 through a Z rotator, allowing the counter to be used as an address generator. There is also a selectable wired bit reversal on this path before the Z input shifter for use in FFTs built from mixed-radix algorithms.

[0259] In addition to general use, the Boolean logic circuit 325 is specifically designed to allow count permutations to generate complex address sequences, including bit-reversal, mask and rotate (combination of Z-shift logic) permutations of the input counts, which can also be generated within the RAE 300 by the index counter in the compare block 320. The Boolean logic is also designed to allow simple field merges, including rotation of one source and bit-wise selection between the rotated source and a second fixed source.

[0260] The Z input is one of the primary 32-bit inputs to the Boolean logic circuit 325. It is connected to either the Z input shifter 330 output or the compare block 320 Z output (which doubles as the count output) via a selector 397 (shown as a third data selection (steering) multiplexer 397). This Boolean logic circuit 325 includes an input selector so that the Boolean logic circuit 325 has separate Z shift and Z compare inputs. The bits of the Z input function as one of two Boolean variables for each bit in logic mode or as a selection variable in selection mode. When Z is "0", the output is one of the two lower register bits as selected by the Y input 370. When Z is "1", the output is one of the two upper register bits selected by the Y input in logic mode or the X input 365 in selection mode.

[0261] The Y input 370 is one of the primary 32-bit inputs to the Boolean logic circuit 325. It is connected to the Y output of the compare block 320 (which can pass the Y input). The Y input 370 selects an even register bit when it is "0" and an odd register bit when it is "1". The upper two bits (selected when Z="1") are addressed by Y when in logic mode and by X when in select mode. The compare block 320 can be programmed to connect the Y or ZRAE input to the Y output, providing a way to perform bitwise operations with Z and shifted Z.

[0262] The X input to Boolean logic circuit 325 is an auxiliary input that is used only if the selection mode is set. The 1-bit function of X defined by the upper two register bits is selected if Z is "1" and the selection mode is set. Otherwise the X input is ignored.

[0263] The configuration interface 524 serves to access the configuration register 526 bits. There are four configuration bits for each of the 32 bits of the Boolean logic circuit 325 to set the Boolean function for each bit position independently. There are two additional configuration bits (534) to globally set the mode to normal or select mode and to set the input select input from either the Z shift or the comparator for Z.

[0264] The Boolean logic circuit 325 has a 32-bit Q output 528. Each output bit is the result of a Boolean logic function of that bit programmed into a configuration register. In a select mode, the logic function is changed to replace Y with X in some of the select logic inputs. The flag output 532 provides a means to generate a 1-bit output that is a function of any or all of the X, Y and Z input bits. The flag output is a 32-bit NAND function of the 32-bit Q output.

[0265] The configuration of the Boolean logic circuit 325 includes a 4x32 register file 526 that holds a 4-bit logic configuration for each bit slice, and a 2-bit global register 534 with one bit that selects logic (0) or select mode (1) for the entire block, and one bit that selects the source of the Z input (0=logic compare, 1=Z shifter). The 4-bit configuration of each bit slice sets the output value for that bit slice when in logic mode for the four possible combinations of Y and Z bit inputs. In select mode, when selecting the register contents to output, if the Z input is "1", the value of the X input is replaced by the value of the Y input. The bit functions by register code and mode are shown in Table 17 below.

[0266] In logic mode, the logic of each bit slice is a four-input selector addressed by the Z and Y bit inputs to the slice. There are four input combinations for two-input logic functions. For register bit selection, the Z input has weight 2 and the Y input has weight 1. By appropriately setting the four configuration register bits, any Boolean function of the two inputs can be programmed when the mode is set to logic mode. In select mode, Z selects a one-bit logic function of X and Y. In select mode, the select input of the first layer upper selector is changed from the Y input to the X input, and the Z input selects a one-input function of Y (0, ~Y, Y, or 1) set by registers 0 and 1 when Z = "0", or a one-input function of X set by registers 2 and 3 when Z = "1".

[0267] [Table 17]

[0268] The Z input is after the Z shift and has the option to input either the RAE Z input or the Z output of the compare logic (which can be connected to the index count logic of the compare logic). The Z connection on the input side of the shifter also has a connection for wired bit inversion of the 32-bit input. This configuration provides very flexible address generation capabilities where the address field can be shifted or rotated anywhere within the 32-bit range, bits can be selectively masked with 0 or 1, or the count bit can be inverted. Wired bit inversion before the Z shift also allows for the generation of the rotated bit-reversed sequence required for the mixed radix construction fast Fourier transform. The output of the Boolean logic circuit 325 also has a 32-input NAND gate 522 that aggregates the bits to provide a single bit output 532 for use as a decode or data-dependent condition flag. This can be extended to provide 4-bit output flags each relating to the 8 bits in each SIMD lane and a combining network providing one bit per lane regardless of SIMD size.

[0269] 10.Comparison of Circuit 320 FIG. 47 is a high level circuit and block diagram illustrating min / max sort and compare circuit 320 (more commonly referred to as compare circuit 320). FIG. 48 is a detailed circuit and block diagram illustrating min / max sort and compare circuit 320 of comparator 556a. Compare circuit 320 adds the ability of RAE circuit 300 to change data flow and sequence based on the comparison results of the inputs, internal index counts and internal constants. Compare circuit 320 is separable to support two or four SIMD lanes with separate compare results for each lane.

[0270] This comparison circuit 320: 1. A function that accumulates the minimum value of the stream using the index of the first occurrence of the minimum value, 2. A function to accumulate the maximum value in a stream with the index of the first occurrence of the maximum value, 3. Sort two inputs (1-lane, 2-lane, 4-lane SIMD) and swap if larger, 4. A function for counting samples that can run simultaneously with the accumulator 315 and be reset at the same time; 5. A function to zero all samples except when the current index count matches the index input, and output the other input; 6. Threshold positive (samples above the threshold are passed, smaller samples are replaced with a constant, and samples above the threshold are counted) function; 7. Threshold negative (samples above the threshold are replaced by a constant, and samples below the threshold are counted) function; 8. The ability to pass inputs unchanged (flow-through for input to Boolean logic circuit 325); 9. A function that passes only inputs that satisfy the comparison conditions (gate data is valid), 10. Ability to pass input only before or after a trigger condition and 11. Equality and less-than flag output (1-lane, 2-lane, 4-lane SIMD) function; 12. (You can use rotator and Boolean to do bit reversals, rotations and masks) Generate address counts (All of the above modes apply to 1, 2 or 4 SIMD lanes of all supported floating point, signed integer, unsigned integer and 32-bit data, in SIMD mode all lanes must share the same configuration and decoder mapping, each lane is treated separately in this block, when SIMD mode is selected the 32-bit index count is also split into a like number of SIMD lanes) Functions and Fulfill this.

[0271] The Y input 542 is accompanied by Y_valid (546). If either valid value is "0", the comparison is not processed unless bypassed (typically when constant or feedback is selected as the input). The 32-bit Z input 544 is fed by the Z-shifter logic output so that the shifter can be used for shifting or rotating as part of lane swapping as well as fused comparison operations. The most significant bit of the input is inverted when a signed input is selected to properly use the unsigned comparator for a signed input. The flag input (546) is an additional validation on the comparison result and can be used to terminate streaming of min or max, tag (pass through) samples, reset counters or trigger events, and other control events. The flag input is fed from the FC200 sequence counter or from the flag output of an adjacent RAE300. The reset input (546) resets the counter and data output registers regardless of valid Y and Z when a "1" is asserted.

[0272] The Y output 548 is the primary data output. It is data selected from the Y or Z input or the Y or Z constant registers. The selection of the Y or Z source depends on the programming of the compare result and result decode. The selection of live data or constant is set for Y and Z individually by configuration settings. The Y output valid (552) indicates that the Y output is valid for downstream blocks. The Y output valid signal is a programmable function of the compare condition, the input flags, and the Y and Z data input valid signals. The programmable decode also controls the clock enable and reset of the Y output register, allowing the output to capture and hold data or count depending on the compare condition.

[0273] The Z output 554 also has a valid Z output (552). The Z output is a secondary data output where the output is either the Y output select (Yin if Y output is Zin, Yin if vice versa) or the inverse of the index number depending on the configuration setting. The Z output valid signal is a programmable function of the compare condition, the input flags, and the Y and Z data input valid signals. The programmable decode also controls the clock enable and reset of the Z output register, allowing the output to capture and hold data or count depending on the compare condition. The condition flag output (552) is an auxiliary control signal that is a programmable logic function of the compare result, the flags in, the Y and Z data valid inputs, and the reset. This can be used by the downstream RAE300 as a condition flag control, and by the Fractal Core 200 sequencer to affect sequencing. If flags are used to control the FC200 sequencer, care must be taken to include pipeline delays.

[0274] The compare circuit 320 has many operating modes defined by a set of configuration bits that select the connections. The configuration also includes the setting of three constant registers. The configuration consists of the setting of seven data path selectors, the selection of SIMD mode (2 bits), the definition of the input sign type (2 bits), the compare decode to control mapping (49 bits), and the setting of three 32-bit constant registers. The configuration is divided into configuration and constants. The configuration includes seven data path selection bits and two SIMD mode selection bits.

[0275] The compare circuit 320 includes a SIMD magnitude comparator 556, a data steering selector 564, registers, an adder / counter 562 (with counter 572), and a programmable decoder 558 to control the data and counter paths and registers. The 32-bit comparator 556 has modes for one 32-bit lane, two 16-bit lanes, or four 8-bit lanes. It generates "Equal-to" and "Less-Than" outputs for each lane. The decoder 558 decodes the comparison condition for each lane and gates it with valid and flag inputs to generate the data steering control for each lane, and the counter 572, a register flip-flop clock enables and resets for each lane, for the data output register and counter register, respectively. The inputs to the comparator 556 can come from the Y and Z inputs of the block, the Y and Z constant registers, or the Y output register for the Z input, or the counter register for the Y input. This provides the flexibility to generate counts based on comparison conditions, the ability to accumulate minimums or maximums, generate counts, and other uses.

[0276] Referring to FIG. 48, the magnitude comparator 556 determines the relative magnitude of its two inputs and uses the result signals (equal and less than) to control the steering of data in the rest of the block. In its basic form, the magnitude comparator 556 compares two 32-bit words and generates two outputs from the comparator 568: A equals B, A less than B. The comparator 556 contains a split gate that allows it to operate as one 32-bit, two 16-bit or four 8-bit arithmetic comparators corresponding to one, two or four SIMD lanes in the 32-bit word. A set of eight 3:1 muxes 566 select the appropriate compare tree output for each lane depending on the SIMD mode. For less than four SIMD lanes, the signal output is duplicated and output separately for each 8-bit slice in the SIMD lane. Outside of the comparator and counter 572 logic, the rest of the block treats all data as four independent 8-bit lanes. Additional optimizations can be exploited by replacing the 8-bit comparisons with continuations in the tree structure, resulting in 1-bit comparisons at the input. The input layer is a half adder with one input inverted. This reduces the tree depth by one gate layer and requires the addition of a blocking gate for SIMD4 mode similar to that for SIMD2. The optimized tree has 258 2-input gates without counting buffers and 12 gate delays, excluding sign correction and SIMD output selection. The latency and resource (for 2 input gates) metrics for the optimal binary comparison are T(n)=2(log(n)+1) and C(n)=nlog(n)+3n-1.

[0277] The comparator 556 also has corrections for signed two's complement and sign-magnitude inputs. The comparator 556 assumes that both inputs have the same number system. In the two's complement case, the comparison incorrectly compares negative values ​​as greater than positive values. This is corrected by inverting the sign bit whenever the number system is two's complement (regardless of sign). In the sign-magnitude case, inverting the sign causes negative numbers to test correctly as less than positive numbers, but two negative inputs will result in the opposite of the expected comparison result since the more negative the number, the more negative the number. This is corrected to provide a correct comparison result for the sign magnitude by always inverting the sign bit and inverting the remaining bits only if the sign is negative. This performs a one's complement of negative numbers, mapping -0 to -1, -1 to -2, etc. The change still gives a correct comparison result even if the numeric representation is changed. Negative numbers are reduced by one to allow for a unique -0 to be stored. The sign correction for each bit, as a function of signed mode, is shown in Table 18 for each SIMD mode. Normalized floating-point values ​​produce correct comparison results when interpreted as integers of sign magnitude using the corrections above. Denormalized and infinite floating-point values ​​also compare correctly using the sign and magnitude corrections.

[0278] [Table 18]

[0279] The SIMD select after the comparators selects between four 8-bit compare result pairs, two copies of two 16-bit results (one result per 8-bit lane, with the same control for the two upper and two lower lanes), or four copies of a single 32-bit compare signal pair. This is implemented as a pair of 3:1 multiplexers 566, one per 8-bit lane, using the encoded SIMD setting as the selection. Outside of the compare and counter 572, all data is treated as 4-lane SIMD, and the lanes have overlapping controls if less than SIMD-4.

[0280] FIG. 49 is a circuit diagram showing the decoder circuit 558 (27 control, 49 configuration bits). The flexibility of the compare circuit 320 depends on the programmability of the decoder 558, which generates the control signals. The inputs to the decoder 558 are the 2-bit comparison results for each 8-bit lane, and single bit reset, flag, and Y and Z data valid signals from the block input. The controls generated include data steering mux per lane, count_bypassmux per lane, Y, Z, and count register clock enables per lane, count register reset per lane (Z register uses count register reset if Z-mux selects counter 572 and Y and Z data outputs do not use reset), and flag, and Y and Z data valid outputs. The configuration bits for each control output apply to all lanes, but each lane has a separate gate so that the comparison results for each lane can affect the output of each lane individually. The internally generated INIT signal is set when the reset input is asserted regardless of data validity, cleared when the flag input is 0, and is optionally verified by input data validity. INIT is optionally set again when the flag is asserted so that it can be used at the beginning of a new data block as register initialization with the next valid sample. In most flagged operations, the flag is asserted to mark the end of a data block, thereby resetting the index counter 572 and / or restarting the accumulating min / max (for example). The comparators generate a "less than" and "equal" output for each lane. When lanes are combined, the output of the composite lane is replicated for every 8-bit lane output. The decoder 558 has a global compare select circuit that generates an additional "greater than" signal and selects which of the three comparison results to forward to the rest of the decoder. Each control decoder can gate each control separately, selecting the selected comparison result or its inverse or a "1" or "0".The initialization and flag inputs have enable controls that allow these signals to be logically ORed with the fully decoded local compare signals and then ANDed with a valid composite data, which can be Y or Z or (Y and Z) or "1", to generate each local control. The settings for each local control are shared across all four lanes, but use the compare inputs for that lane. Some control functions do not use all input signals, so these unused inputs are tied to constants and optimized out of the design.

[0281] Table 19 summarizes the configuration inputs for each control. The decoder 558 has 49 configuration bits associated with it to generate 27 controls (some of which have 4 copies for the 4 lanes). There are additional configuration bits to set the input sign mode and SIMD mode.

[0282] [Table 19]

[0283] The compare circuit 320 includes a 32-bit adder / counter 562 to generate the index count for internal and external use. It can also be configured as an adder to modulate the threshold to introduce hysteresis in the threshold operation. The output of the counter's adder is routed to two identical registers with separate clock enables. One of these is the count register, whose output is fed back to the counter adder and one input of the comparator logic block for internal use. The second register (the Z output register) is separately clock enabled and is intended to conditionally capture the count to hold the index of the minimum or maximum value of the streaming data. One input of the adder 562 is selected from either the Y input or the Kz constant or the counter 572 feedback, and the other input is the increment constant from the block configuration. The index counter's adder is split into SIMD lanes when SIMD operations are selected by gating off the carry between the lanes depending on the SIMD mode. The increment constant must be adjusted to include the increment for each lane for 2-lane and 4-lane SIMD modes. For index counting, counter 572 is typically incremented by 1 and the count register can be clocked for valid samples. Counter 572 is reset by steering logic bypassing the adder with feedback mux set to Yin and count bypass mux set to clock enable. This loads the counter register with the value of Yin (an additional constant register and mux could equally well be used rather than relying on a correct reset value for Yin). The increment of counter 572 can be changed to something other than 1 to support counters shifted up from the lsb and negative counts. Thresholding with hysteresis sets the feedback of counter 572 to Yin, inputs a threshold of half the hysteresis deadband width to Y, and loads the deadband width into the increment value constant. The output of counter 572 is fed to one input of a comparator block and compared to the index on the Zin port.A counter register mux selects either Yin or Yin+increment for the modified threshold based on the result of the previous comparison. Yin of counter 572 can be replaced by a constant Kz using a counter kmux set by configuration. The output of counter 572 is via the Z output, which is connected to the Z input shifter via a selectable wired bit-reverse and compare bypass, allowing fairly complex address generation by permuting the count by rotation, bit-reverse and Boolean logic.

[0284] The steering logic includes a selector (mux) 564 for the comparator input, a swap / alter mux in the data path, an output register with clock enable, and an output select to switch between the output of the counter 572 and the output of the second data path. It also includes a function and a compare result decoder to generate steering control for the steering and counter 572 logic. The data path swap / alter mux is used to swap Z and Y lanes in the sorting use case, or to replace a constant in the data in the streaming use cases of reverse pooling and thresholding. In the streaming min / max use case, the clock enable of the left register is used to update the register when a new max or min value (depending on the use) occurs, and a copy of that clock enable is used to enable the capt register to capture the current index count. In streaming mode, valid output data must be qualified with the last sample flag (AXIS-4 TLAST or equivalent). The mux controls for the clock feedback and register inputs, the left and right select muxes (not constant muxes), and the register clock enable are partially controlled by the compare result. The remaining multiplexer controls are only affected by the block configuration. Comparator and Counter 572 There is a separate configuration control for SIMD control, allowing for the use of comparator and counter 572 independent of steering if indexing is not required. There are other possible use cases not shown. The left datapath multiplexer includes a selection for input from constant registers Kx and Ky. This is used to conditionally replace data with a constant value (Kx, Ky defaults to 0) based on the configuration mode and the outcome of the comparison. Similarly, the increment value D for the index count logic is also from a constant register, with a default value of 1. The constant is loaded via any number of mechanisms (e.g., but not limited to, as part of a configuration word, via some kind of serial constant load interface, or by a clock, enabled e.g. via the X, Y, Z inputs).

[0285] Examples of use cases include streaming min or max using an index, two input sorting (simultaneous min / max of two inputs), inverse max pooling (streaming data is replaced with 0s unless the internally generated index number matches the streaming index), sample count index generation, data steering, data substitution, address generation, compare flag output, and thresholding by either threshold sample count or hysteresis.

[0286] FIG. 50 is a detailed circuit and block diagram showing streaming min / max with index application using the comparison circuit 320. The comparison circuit 320 also performs streaming min or max by comparing the current Y input with the previous min or max held in the Y output register. The Y register is fed back to the comparator Z input, and new data input to the Y input is input to the comparator Y input, where the new input is compared with the previous extreme value in the Y register. The count register is enabled for every valid Y input (Y_valid_in="1"), so the count is the number of valid samples (plus the initial value) after reset. The steering bypass max and count bypass max are static in this application (except for initialization), so the Y data and next count are always present in the Y and Z register inputs, respectively. When the new value exceeds the current register value, the clock enable turns on the Y and Z output registers, and these registers are updated with the new extreme value and the corresponding index count. The last sample should be flagged input="1" to indicate the end of the input set. A flag matching Yin_valid will cause Yout_valid to move to "1" to validate the accumulating max or min value and the index of the sample at output. Table 20 summarizes the settings for both streaming min and streaming max use cases.

[0287] To find the minimum or maximum, data must be sent to the data register of the first sample of the set, regardless of the comparison result, and counter 572 is set to the initial index value (usually 0, but can be offset). The initial value of the data register is forced using the decoder's init signal, set after the reset input or enable flag input. This causes the first Y value to be accepted as the initial extremum, regardless of the comparison result. The count value can be initialized in one of two ways. When initialized to 0, the init signal simply resets the Z and count registers to 0. If non-zero, an alternative method is used which involves asserting count bypass to load counter 572 with Kz when init is asserted. Alternative configurations for initial index other than zero are shown in the right hand column of Table 22 for configurations that differ from the initial index=0 case. The route following Kz in Figure 50 shows the initialization of counter 572 from a constant. A lane reset is used instead of initializing to 0 by resetting the count register. Streaming min / max applications also work with SIMD data, with each lane maintaining its own extremum and index. A SIMD operation requires that all lanes be enabled simultaneously, since valid data applies to all SIMD lanes, and all data sets across the lanes start and end with the same samples on all lanes.

[0288] [Table 20]

[0289] Figure 51 is a detailed circuit and block diagram showing a two-input sort application using a comparison circuit. In a two-input sort, the values ​​of the Y and Z inputs are compared. If Z>Y, Z is placed at the Z output and Y is placed at the Y output. Otherwise, the data is swapped to the opposite output. As a result, the minimum of the pair is on the Y axis and the maximum is on the Z axis. This application supports SIMD operations where each lane of SIMD represents its maximum value at Z and its minimum value at Y. SIMD requires that all lanes view and generate data together. The counter 572 cannot be used as its output is not visible in this mode. Table 21 shows the configuration for this two-input sort.

[0290] [Table 21]

[0291] The decode logic can be set to simply pass (or swap) the Y and Z data to the Y and Z outputs as a special case of a two input sort. All that is required is to set the mux to a fixed value and copy the effective value of the data to the respective output. This mode may be required when connecting Y or Z data to a Boolean logic block. If the Z register mux is set to counter, the data path through remains for the Y output and the Z output is fed by the counter 572 logic. The compare logic is not used for pass through, so in this mode it is still available for comparison with the output to the flag or for use with the index counter 572 when the steering mux is set to pass through.

[0292] 52 is a detailed circuit and block diagram illustrating a data substitution application using the comparison circuit 320. The comparison circuit 320 has a data substitution function that uses a comparison of the input stream against a constant, a second input, or an index count to control the substitution of a constant or a second input for the primary input. In the comparison result, the data can be replaced with a constant or an input from another stream. The index count can also be used as an output. Configuration options for the comparator circuit 320 include: Case 1a: Compare Zin with an index and assign Yin or Ky to the Z stream; Case 1b: Compare Zin with the index and assign Zin or Kz to the Y stream; Case 2a: Compare Zin with a constant (Ky) and assign Yin or the same constant (Ky) to the Z stream; Case 2b: Compare Zin with a constant (Ky) and assign Zin or a constant (Kz) to the Y stream. Case 3a: Compare Zin and Yin and assign Yin or Ky to the Z stream, Case 3b: Compare Zin and Yin and assign Zin or Kz to the Y stream; Case 4a: Compare Yin to a constant (Kz) and assign Yin or Ky to the Z stream; and Case 4b: Compare Yin with a constant (Kz) and assign Zin or Kz to the Y stream; There is.

[0293] Each case is a different permutation of the input mux and the polarity of the steering control. Each subcase has the same setup except for the interpretation of the steering mux. The counter 572 may be initialized with a register reset or by initializing to non-zero with the count bypass mux and Kz (or Yin) as described above. In FIG. 52, the comparison Yin and comparison Zin μx and the steering constant μx are shown without connections configured to illustrate the different modes. The setup for the above four cases is shown in Table 22.

[0294] The reverse pool accepts synchronized index and data streams while maintaining a local index count. If the index stream equals the index count, the data value is passed through; otherwise, the output data is set to zero. This function is achieved with data permutation, case 1 with the Kz constant set to zero, index input to Z, and data input to Y. The setup is included in the penultimate column of Table 22. Reverse pooling may also be achieved by fixing the steering multiplexer to output Y to the Y output, and using the comparison result to assert a Y register reset when Zin does not equal the index counter. This alternative configuration of max pooling may result in a slight reduction in power consumption, but the data permutation method allows the unequal data to be set to something other than zero. The alternative setup is included in the last column of Table 22.

[0295] [Table 22]

[0296] Data substitution may also be used to threshold the data so that data below the threshold is replaced with a constant (typically the threshold value or 0) and data above the threshold is passed. Alternatively, data below the threshold can be passed and data above the threshold can be replaced with a constant (such as saturation). Cases 2 and 4 are in Table 22, where one input comes from the Y or Z input for comparison and the other is set to a threshold constant. Setting the threshold constant in the steering multiplexer logic provides the various thresholds listed in Table 23. Thresholds can also be provided through inputs not used for data. The index counter 572 can be used to count samples above or below the threshold (if the threshold is from a constant register), to count valid samples, or as an independent event counter 572 using valid data on the flag input or unused data input.

[0297] [Table 23]

[0298] FIG. 53 is a detailed circuit block diagram showing threshold with hysteresis using the comparator circuit 320. Threshold with hysteresis shifts the threshold a fixed distance from the nominal threshold away from the current data value. The purpose is to reduce the chance of signal noise exceeding the threshold. This is achieved by using the counter's adder and bypass mux to specify whether to add an offset to the threshold depending on the comparison result. The output of the counter 572 is fed to the comparator Y input and data is input via the Z input. The comparison result selects the count bypass mux and steering mux. The values ​​programmed are the threshold and the delta, which is the distance between the upper and lower thresholds. The delta can be positive or negative and the threshold can be either upper or lower.

[0299] [Table 24]

[0300] FIG. 54 is a detailed circuit and block diagram showing the flag trigger event application using the compare circuit 320. The compare circuit 320 can be configured to wait in one state for a trigger event, then switch state and remain in the second state until a reset input. The general case is triggered by the flag input and reset to the initial state by the reset input. This is only valid if all lanes are triggered and reset by the same trigger, as it is dependent on the flag and reset. In the initial state, the cnt register is reset to 0 and is forced when the reset input is asserted. The count increment constant is set to 0 and the Kmux connects to Kz such that the input to the count register is always Kz. Kz is any constant other than 0. The clock enable for the count register is connected to the flag input through a decoder, and when the flag is asserted, the register is loaded with Kz. In this way, the count goes to 0 until the trigger event, at which point it goes to Kz. It stays at Kz until the reset is asserted and the count register is reset to 0. The comparator compares the count value to Kz and decodes the comparison output to control the steering mux and / or gate the Y and Z data valid or flag outputs. In this way data can be started, stopped, replaced, swapped or redirected on a trigger event. The Z output can be connected to a count register to provide a direct connection to a state (0 or Kz) or to a data mux for data steering and swap applications. For data steering, a constant can be used as long as it is Kz if a non-zero Kz is used.

[0301] FIG. 55 is a detailed circuit and block diagram showing threshold trigger event application using a comparison circuit. In the general case, it is necessary to generate a flag outside the comparison block, and in the case of a trigger based on comparison, a second RAE300 is required to provide the flag. In the special case where a threshold crossing triggers an event, it can be implemented with a single RAE300 comparison circuit 320. The latch logic for this uses a counter 572 set up in the same way as the "threshold with hysteresis" use case, but the threshold is set so that the trigger event moves the threshold to either the minimum or maximum value representable by the threshold, and the comparison functions are set to be less than or greater than the threshold respectively, so that once the comparison condition is met (the threshold is exceeded), it cannot become unmet. The comparison circuit 320 is reset to its original state by forcing the count bypass control to bypass using a flag or reset input. Using the comparison condition, constants can be replaced with data (note that Kz cannot be used as it is used for the threshold unless the threshold is supplied externally via Yin), data outputs can be exchanged, or data can be manipulated over the data's valid period. Also, using the data validity of both the Z-stream and the Y-stream, the data mask can be made stationary and the data flow interrupted or started. The setup of the triggered event is similar to the threshold with hysteresis, except that the Kinc value is specifically set in the threshold so that the sum is the minimum representable value - the sum is the minimum representable value. If the trigger occurs in response to a signal exceeding the threshold, the sum of the thresholds set by Kinc and Kz must be the minimum value representable in numeric mode (signed, unsigned, or sign-magnitude / floating point), and the comparison must be Z>=cnt, so the signal cannot be less than the shifted threshold. If the trigger occurs when the signal falls below the threshold, the sum of Kinc and the threshold must be set to the maximum representable value. The comparison condition must instead be Z=<cnt so as not to exceed the shifted threshold. The threshold trigger also operates in SIMD mode, but note that all lanes are reset simultaneously.

[0302] [Table 25]

[0303] Figure 56 is a detailed circuit and block diagram showing a data steering application using a comparison circuit. The control decode allows the data valid for Yout and Zout to be controlled separately by the comparison result. By setting the data validity so that one is valid when the comparison is true and the other is valid when the comparison is false, data propagation is sent from only one output to different connections. There are several ways to set the configuration to set the various comparison options. Case 1: Compare Zin with the index number and steer Y to Yout or Zout. Case 2: Compare Zin with a constant and steer Y to Yout or Zout. Case 3: Compare Zin and Yin and steer Y to Yout or Zout. Case 4: Compare Yin with a constant and steer Y to Yout or Zout. Case 5: Compare index with a constant to steer Y to Yout or Zout. Case 6: Use flag input to steer Y to Yout or Zout. The settings for each case are shown in Table 26. The Z path through data steering requires caution as the connected output Z is invalid. For power considerations, it is possible to connect the Z input to Kz and the register clock enable to Y valid (valid values ​​are abbreviated as Yv and Zv in the table) to prevent the invalid output from propagating when deselected. The count can be reset using the reset input, which can be verified with the data valid input if required. If Ky is not used within the compare logic, it can be used to initialize the counter 572 as described for streaming min / max. Data steering uses the data valid signal to steer the data, so it can only be used with non-SIMD (32-bit lane) operations.

[0304] [Table 26]

[0305] Figure 57 is a detailed circuit and block diagram showing a modulo-N counting application using the compare circuit 320. The index counter 572 in the compare block is designed to count samples of the sample index. It can also be used for address counting. The counter increment is set by the increment constant and can be set to any 32-bit value. The register input is from a selector that selects between the count adder or bypassing the input, providing a means to initialize the count to a value other than zero. The counter register and carry are split into 8-bit segments to handle two and four SIMD lanes. The compare circuit 320 is placed before the rotator and Boolean logic to allow these blocks to handle address counting of more complex sequences including corner turns and FFT bit reversal and corner turn addressing. The setup for the various use cases of the count logic is shown in Table 27.

[0306] The basic use is as a simple counter (linear counting) with an increment value set by the Kinc constant register. For simple counting, the Kinc register is set to 1. It can also be set to any 32-bit value to change the increment. The counter's clock enable increments the count when the count ce decoder condition is met. CE can be used to increment on valid data, compare conditions, flag inputs, or a combination of these. In simple use, the register reset is used to clear the counter to 0. The register reset is a logical function of the programmable enable, flag, and reset inputs and the compare result. If the counter needs to be initialized to a different value, when the reset condition is decoded and the counter CE is asserted, it switches the counter bypass mux to load the counter register with the value selected by the counter's Kmux (Kz or Yinput). Note that the bypass mux and reset using Kz may interfere with use of the comparator or steering mux of Kz, in which case the constant may be supplied by Yin instead. Compare and data steering are not used for linear counting. These portions of the compare block are available for comparison applications that do not interfere with the counting logic used.

[0307] The compare circuit 320 can be used to limit the count and freeze the count once the limit is reached. To limit the count, the compare is set to count limit and the clock enable is gated by the compare result. This disables the count increment once the count reaches the terminal count until it is reset. The limit counter connections are the same as for modulo counting except that the counter CE is gated for limit count rather than reset. A flag output can be driven by the compare result to provide an external indication of the limit count. The compare result can also be used to select or gate data flow from unused inputs and constants (Kz is used for the limit value). The count limit can also be a variable if specified by Zinput rather than a constant Kz.

[0308] The compare circuit 320 can also be used to synchronously reset the count for the next clockable clock when the terminal count is reached, resulting in a modulo-N count when the terminal count is set to N-1 and the reset is caused by the comparison result using the counter's register reset. Figure 57 shows the connections for a modulo-N counter. If N-1 is applied via the Z input rather than being a Kz constant, the modulo becomes variable.

[0309] [Table 27]

[0310] Figure 58 is a block diagram showing the derivation of corner turned addresses. Corner turned addressing reorders the addresses of a matrix stored in memory in row major order to access them in column major order. For arrays with two-dimensional power, corner turned addressing can be generated by rotating the left address bits by the log2 minor axis dimension (if the rotate field is the same size as the address). This is equivalent to swapping the bit field positions corresponding to the rows with the bit field positions corresponding to the columns. For 8-bit and 16-bit cases, the z-input shift rotate can be used directly to obtain the rotated address. However, in the general case, the built-in rotate is insufficient because the shift distance to generate the rotation is fixed at 8, 16, 32, or 64 bits. To perform the rotation, a copy of the address count must be placed right next to the actual count. The address count can be modified to generate two identical counts in adjacent bit fields as long as it does not overflow the address width. Setting a modulo count or bounded count can be used to ensure that overflow does not occur. Two adjacent counts can be generated by changing the increment to have a "1" in the lsb of each field, so for a 9=bit address count the count increment would be 0x0201 as shown at the top of Figure 58. This generates two adjacent counts, one with the lsb of bit 0 and the msb of bit 8, and one with the lsb of bit 9 (shown in Figure 58 as "Index Count Entering Z Shift"). To prevent the lower counter from overflowing into the lsb of the upper counter, it is necessary to ensure that the count does not exceed all "1's". Using a modulo count setting and setting a limit equal to the two count fields that hold the largest number will result in a proper modulo count.This combined counter pair is then shifted by Z-shift logic to put the correct rotation of the bits into the least significant bits of the shift window (the shift window for a 32-bit input is bits 63:32), and then the result is masked with Boolean logic to discard bits outside the shift window. The Boolean mask can be used to set the upper bits to select a page in memory.

[0311] Figure 59 is a block diagram showing the derivation of the FFT bit reverse corner turn address. The design includes a selectable wired 32 bit reversal between the compare block and the Z-shift logic used to reverse the bit order for bit-reversed addressing to support the Fast Fourier Transform. The Fast Fourier Transform consists of radix 2 and radix 4 stages that are combined using a mixed radix algorithm. There is a corner turn address between each stage, and the inputs and outputs of the stages are bit-reversed addressed (lsb becomes msb and vice versa). If the data is stored in memory in natural order, the read and write addressing is one corner turn of the bit-reversed address at each stage (but of different size at each stage). The addressing is a modification of the corner turn addressing above to account for the relocation of bits when bit-reversing. The count logic setup is identical to the corner rotate setup, but the 32 bit count output is first bit-reversed before the Z-shifter, which places the relevant bit at the most significant end of the word. The shift distance is adjusted to account for this, and the remaining steps are the same as for the corner rotate case. Figure 59 shows the bit alignment for the derivation.

[0312] 11. Input reordering queue 350 and output reordering queue 355 FIG. 60 is a detailed circuit and block diagram showing the logical circuit structure of the RAE input reordering queue 350 and the RAE output reordering queue 355. These multiple RAE input reordering queues 350 serve three main purposes: (1) they allow the reordering of data in time and redistribute data between the X and Z inputs; (2) they provide adjustable delays to aid in pipeline latency balancing; and (3) they allow the storage and ordering of a number of constants that are applied to the RAE inputs 365, 370, 375. The use of the reordering function greatly simplifies data processing for certain algorithms that involve complex data that must be viewed as I / Q pairs, but that require I and Q interleaving two samples at a time for processing efficiency. An example of this is the Fast Fourier Transform (FFT) element operation called the butterfly. The two samples of the butterfly follow almost the same processing (only differing in a change of sign), so for efficiency, the I components of both samples are processed alternately with the Q components of both samples. Other complex arithmetic algorithms also benefit from interleaving the I and Q components and processing two samples at a time. In this application, a reordering queue four samples deep is used.

[0313] The RAE output reordering queue 355, which may be shared by two RAE circuits 300 of the same RAE circuit quad 450, has the same structure as the RAE input reordering queue 350, except that it does not have a Y data path, as shown in FIG. 60, and does not require conditional multiplexing logic. The input to the RAE output reordering queue 355 comes from the RAE 300X outputs 420 (e.g., accumulator 315 outputs) of the two RAEs 300 in the same half of the RAE circuit quad 450. The output reordering queue 355 allows for swapping between the two RAEs 300 to re-interleave I and Q for FFT, perform half-complex multiplication, and short-distance reordering of sample sequences to the four most recent samples. Including these RAE output reordering queue 355 circuits in the RAE 300 simplifies the algorithm design and layout for algorithms that require IQ or even-odd interleaving and similar operations (e.g., fast Fourier transform). In the exemplary embodiment, for each pair of RAEs 300 there is one set of RAE output reordering queues 355 .

[0314] The adjustable pipeline delay functions are a subset of the functions provided by the reordering queue. There are applications that require one or more constant inputs to the multiplier. The reordering queue registers 580 can be reused to hold constant values ​​that can be sequenced using the reordering queue sequencer. The constant load mechanism links the 32-bit registers in the reordering queue in a daisy chain (not shown separately) so that these constants are input 32 bits per clock and propagate down the chain so that at the end of the 12th clock the reordering queue is filled with 12 constant values. The value remains in the register during operation as long as the expiration of the data is gated. The output of the last register in the chain is linked in a chain of other constant registers in the RAE 300, including the registers in the compare block and the Boolean function table in the Boolean logic circuit 325, allowing sequential loading of the entire chain of constant registers. For clarity, the constant load chain and write logic are not shown in FIG. 60. The load data is input via the Y input. The final Y register is connected to the X chain via a mux585 at Xin, and the output of the X chain is connected to the Z chain via another 32-bit mux590.

[0315] The reordering queue has three 32-bit X, Y and Z data inputs corresponding to the RAE 300 inputs 365, 370, 375. Each of the X, Y and Z inputs 365, 370, 375 is associated with a valid data 595, 596, 597, respectively. Data is considered valid only if the valid data for the same (corresponding) input is "1". Data is shifted into the RAE input reordering queue 350 on each rising edge of the clock when the corresponding valid data is "1". If the valid data is "0", the data for the corresponding input is not transferred to the reordering queue register 580. Multiple data valids 595, 596, 597 allow shifting of data into the RAE input reordering queue 350.

[0316] The RAE input reordering queue 350 has three 32-bit X, Y and Z data outputs 582, 584, 586 respectively. Data on the outputs is selected from either the delay queue registers or the corresponding inputs depending on the state of the currently addressed sequencer memory. The data outputs are accompanied by a data valid output flag indicating the validity of the data. The valid data output is a delayed version of the valid data, with a programmable delay of up to 4 clocks corresponding to the intended reordered data delay due to reordering. This may require a certain number of samples to be collected and output in groups using a state machine. The output data valid and sequence counters must be synchronized with the input samples. Valid out data exists even if the queue is holding a constant, but can be turned off using a configuration bit. The reset flag resets the sequence counter 575 to the 00 state. The sequence count is provided on the output interface for use by sequence instructions or condition flag logic (not shown separately).

[0317] The data output selection from the RAE input reordering queue 350 is determined by the contents of four registers 602 addressed by the sequence counter 575. Each of these registers 602 contains a 3-bit multiplexer 604, 608 to select for the X and Z outputs, a 2-bit multiplexer 606 to select for the Y output, one bit each for the X, Y, and Z bypass selectors, and two bits of next state allocated for the sequencer. The source of programming for the sequencer registers can be loaded as part of a constant load mechanism, in which case it constitutes two 32-bit words containing 13 bits each for the two sequencer states. To hold the 42-bit sequential load chain, the six unused bits in each operation also have registers, and the spare bits can be brought out to block pins via the sequencer output selectors for use as sequencer outputs elsewhere in the RAE 300. Additional configuration includes conditional multiplexing selection for each data output, and possibly valid output data enable, and control of valid data and flag regeneration.

[0318] The RAEX, Y, and Z inputs include a small four sample reordering queue 610 (illustrated with registers 580) designed to allow independent short-range data reordering on all three inputs, and sequence swapping between the X and Z inputs to support sequence modification for Fourier transforms, complex multiplication, I / Q interleaving and deinterleaving, and similar operations. Also, registers 580 in the reordering queue 610 can be loaded and then held with constants to allow for the rotation of up to four input constants for each of the X, Y, and ZRAE inputs 365, 370, 375, which is useful for dot products with constants (used for filters, correlators, etc.). The input reordering logic includes paths for the sign of Y to select or bypass the constant register to facilitate conditional multiplicand operations where the X input is Xin if Y is non-negative and a constant stored in one of the constant registers if Y is negative. The output selectors for the X and Z outputs are 8:1 selectors 605, 590 respectively followed by a 2:1 bypass select (masses 604, 608 respectively). Each 8:1 selector selects between four delayed samples of the same input or four delayed samples of the opposite input. The X and Y selects are controlled by two 4-bit values ​​from one of four configuration registers selected by a sequence counter 575. The Y input has a similar 4-deep shift register queue with a 4:1 multiplexer 607 to select which queue tap is directed to the output of each sequencer state. This is also followed by a 2:1 queue bypass multiplex 606 controlled by the sequence counter 575.

[0319] Figure 61 is a detailed circuit and block diagram showing the logic circuit structure of the sequencer 575 for the I / O reordering queues 350, 355. The sequence counter 575 is a non-branching state machine whose next state is determined by two bits in a configuration state register. Each configuration register is 16 bits, two are written per 32-bit configuration word write. Two of the configuration bits are the next state of the register. Eleven of the selected configuration bits drive data selection multiplexers in the data path as shown in Figure 60. The remaining three bits are currently unused, but remain in the register to allow the configuration data to be propagated down the chain in order.

[0320] 12. Data Packet and Routing Control FIG. 68 is a diagram of a representative data packet 850 used with a reconfigurable processor. In a representative embodiment, the data packet 850 is 37 bits including a compute core 200 36-bit payload 852 and control bits 853. The payload 852 includes a 32-bit data payload 854 and suffix bits as a 4-bit suffix 856. The 32-bit data 854 supports a variety of potential data formats including integer, floating point, and SIMD representations as shown in FIG. 69. As mentioned above, the suffix 856 is primarily used for zero compression by arrays, but can also support other functions such as carrying various flags, conditional operations, operation indexes, etc. The control (data type) bits 853 are used only by the interconnect 120 and are not carried within the compute core 200.

[0321] FIG. 69 is a diagram of representative data payload 854 types utilized in data packet 850, including 64-bit floating point for IEEE 754 double precision floating point (FP64) (in two packets 858), 32-bit floating point for IEEE 754 single precision floating point (FP32) (862), 16-bit floating point for IEEE 754 half precision floating point (FP16) (864), 16-bit floating point for BFLOAT16 (BFLOAT16) (865), and 16-bit floating point for IEEE 754 double precision floating point (FP64). These include, but are not limited to, 8-bit floating point for IEEE 754 Quarter Precision Floating Point (FP8) (868), 32-bit integers for Signed and Unsigned 32-Bit Integer Values ​​(Int32) (872), 16-bit integers for Signed and Unsigned 16-Bit Integer Values ​​(Int16) (874), and 8-bit integers for Signed and Unsigned 8-Bit Integer Values ​​(Int8) (876).

[0322] 70 is a block and circuit diagram of a routing controller 820 used with input multiplexers 205 and output multiplexers 110 for data to and from the computation core 200, respectively, and may optionally include a program sequencer 825. The routing controller 820 includes an output selection multiplexer 830 controlled by a dynamic output selection 832 that selects a control output 836 from the output selection multiplexer 830, either a dynamic output selection 832 or a static or programmed output selection 834. The control output 836 is then utilized to select the output of the corresponding input multiplexer 205 or output multiplexer 110 (from the interconnection network 120, 220) from the inputs available to the corresponding input multiplexer 205 or output multiplexer 110.

[0323] As described above, the reconfigurable processor 100 utilizes a data flow, as part of which data producers assert (842) data transmission request signals ("REQ") indicating that they have data to transmit, and data consumers assert (844) data transmission grant signals ("GNT") indicating that they are available to accept data. A data transmission coordinator circuit 840 is utilized to transmit such data transmission grant signals (GNT), including a first data transmission multiplexer 846 that receives the data transmission request signals (REQ) and is controlled by a dynamic output selection 852 to pass the data transmission request signals (REQ) to the corresponding input or output registers 230, 242, respectively. A second data transmission multiplexer 848 receives the data transmission grant signals (GNT) and is controlled by a dynamic output selection 852 to return the data transmission grant signals (GNT) from the corresponding input or output registers 230, 242, respectively, to the requesting data transmitter. It may include an optional program sequencer 825 that provides inputs to first and second data transfer multiplexers 846, 848, respectively, under the control of a program 854 that has access to a shared program memory 856 (such as the output programs 272, 274, 276).

[0324] This request and grant mechanism is also utilized to control data flow under various circumstances, such as maintaining data order when data packets are sent to multiple destinations. For example, if data is branched to multiple locations, the data transmitter should receive a data transmission permission signal (GNT) from each data receiver before sending the data. For example, if data is merged from multiple sources to a single destination, the data receiver should receive multiple data transmission request signals (REQ) and issue a combined data transmission permission signal (GNT) toward each data transmission device, and each data receiver should receive a data transmission permission signal (GNT) before sending the data. For example, if data is switched from multiple sources to one destination, the data receiver should receive multiple data transmission request signals (REQ) and issue an individual data transmission permission signal (GNT) to each individual data transmission device, and each data receiver should receive a corresponding data transmission permission signal (GNT) before sending the data. For example, if data is steered to selectable locations, the data transmitter should receive a data transmission permission signal (GNT) from the selected data receiver before sending the data.

[0325] 13. Suffix Control Circuit and Zero Compression / Decompression Figure 71 is a block diagram of an exemplary embodiment of suffix control circuit 390. Figure 72 is a block and circuit diagram of zero compression circuit 800. Figure 73 is a diagram of an exemplary sequence of zero compressed data packets. Figure 74 is a block and circuit diagram of zero decompression circuit 805.

[0326] 71-74, in a representative embodiment, the suffix control circuit 390 includes a zero compression circuit 800 that performs zero compression, a zero decompression circuit 805 that performs zero decompression, and, optionally, a control logic and state machine circuit 810 to perform other activities related to the suffix 856 that may be determined by a user, such as conditional logic, branching, condition flag handling and generation. In another representative embodiment, for example, when the zero compression circuit 800 and the zero decompression circuit 805 are implemented in other parts of the computation core 200 (as shown in FIG. 4), the suffix control circuit 390 typically includes the control logic and state machine circuit 810. The zero compression circuit 800 includes a zero counter 802 and a packet generator 804. When zero compression is enabled, zero compression prevents valid zero values ​​from being propagated. Instead, each valid zero value is tracked with a zero count using the zero counter 802. During a stream of zero values, the zero count increases until it reaches a maximum value of 15. In this case, the next valid data transfer, regardless of value, is propagated to DATA_OUT as a data packet from packet generator 804 (i.e., propagating the original data packet but replacing its suffix bits with a count of 0), the zero count is included in suffix 856, and the zero count is rolled over or reset to zero. For a string of non-zero transfers, the data propagates normally with a suffix 856 of 0, indicating that there was no previous value of 0.

[0327] FIG. 73 shows an example of a data sequence with zero compression enabled. The first two transfers 806 propagate normally. Values ​​91 and 92 are sent to DATA_OUT as a data packet (814) with the bit in suffix 856 set to zero to indicate that there are zeros before the zeros. Input transactions 3 through 5 (808) are not propagated, but the zero count is incremented with each valid input transaction. In input transaction 6 (812), a non-zero value 93 arrives and is propagated through suffix 856 to DATA_OUT (816) with an accumulated zero count of 3. That is, there were 30 values ​​before value 93. The zero count is also reset with a non-zero value. In the example shown, 24 input transfers enter the zero compression circuit and only 5 output transfers result, with the advantage that there is no loss of information.

[0328] 74, the zero decompression circuit 805 includes a suffix counter 818 and a packet generator 804. When a data packet arrives having a data payload 854 and a non-zero count in the suffix 856, the suffix counter 818 determines a zero count in the suffix 856 and signals the packet generator 804 to issue (on DATA_OUT 819) that number of data packets having zeros in the payload 854 before transmitting the actual data payload (which has a non-zero value in its suffix 856) that arrived in the packet.

[0329] As described above, instead of being located within the suffix control circuit 390, the zero compression circuit 800 and the zero decompression circuit 805 may be distributed throughout the computation core 200, such as to include a zero decompression circuit 805 for receiving data from the input multiplexer 205 and decompressing any zero compression, and to include a zero compression circuit before the output multiplexer 110, and to include a zero compression circuit 800 for performing zero compression before selection and transmission of output data packets on the various interconnect networks 120, 220.

[0330] 14.Typical Applications The RAE circuit 300 can be used to generate an interpolation LUT (look-up table), for example, using two multipliers 305 (for multiplication) and two multiplier shift combiner networks 310 (for addition), using memory 150. A brute force approach to obtain coefficients directly from memory is prohibitive from a memory utilization perspective. Fortunately, the function representing the set of coefficients is a smooth function (approximately a sinc function), so compressing and generating the coefficients in real time is attractive from a resource utilization perspective. The coefficient set is approximately a sinc function sampled at intervals of 1 / (P*F), where P*F is the length of the filter, P is the polyphase branch length, and F is the FFT size. The coefficients are distributed across the polyphase branches, and successive taps on one branch are associated with C(k), C(k+F), C(k+2 F), ... The coefficients provided to a particular multiplier 305 are continuous coefficients, so for multiplier m, the coefficient is C(T*F=m), where T is the number of taps and F is the FFT length. This means that the coefficients at any one multiplier 305 are continuous segments of a sinc function. This allows the use of an interpolation scheme to reduce the memory requirements for storing the coefficients.

[0331] The interpolation method used in the design is a quadratic spline generated from quadratic coefficients stored in a small memory (512x72) implemented with a single block RAM per coefficient generator. Instead of storing the coefficients, we store the quadratic coefficients for a curve fitted to the neighborhood represented by the most significant bit of the coefficient index. The least significant bit of the index is then applied to the quadratic equation as an offset from the coefficient position indicated by the most significant index bit. The most significant 9 bits address a 512x72 bit memory containing the three quadratic coefficients of the curve, and the least significant 6 bits (for 32768 points) are used to calculate the interpolated value y=Ax2+Bx+C. The contents of the memory are the scaled A, B, and C coefficients, which can be found by fitting a quadratic equation to a segment of the filter's impulse response using the MathlabPolyfit function.

[0332] FIG. 62 shows the combination of FFTs using a mixed-radix algorithm. FIG. 63 shows a detailed circuit and block diagram of an RAE 300 pair for performing a radix-2 FFT kernel. FIG. 64 shows a detailed circuit and block diagram of an RAE 300 pair configured for a full rotator. FIG. 65 shows a detailed circuit and block diagram of an RAE circuit quad 450 for performing a radix-4 FFT (butterfly) kernel. FIG. 66 shows a detailed circuit and block diagram of multiple RAE 300 cascaded pairs for performing FFT kernels and other applications. With reference to FIG. 62, the number of rows is equal to the size of the first transform, the number of columns is the size of the second transform, and rows x columns is the size of the composite transform. Four (radix-4) complex FFT kernels + half of the bi-rotator can be built in a single RAE circuit quad 450 as shown in FIGS. 63, 64, and 65. The RAE circuit quad 450 processes one FFT point per clock (e.g., a 4-point transform is completed in 4 clocks, accepting and outputting one sample per clock). This implementation includes a complex multiplication on the input that is used as a phase rotator when cascading FFT kernels to build larger FFTs. The cascading strategy follows a mixed-radix algorithm to combine smaller FFTs for longer transform lengths. Each pair of multiple RAEs 300 simultaneously performs the real parts of both even and odd points in one clock interleaved while simultaneously performing the imaginary parts of both even and odd points using dedicated pair routing. I=Ie+ / -. The radix 4 transform is a building block and may be further cascaded, for example as shown in FIG. 66.

[0333] The associated memory can be used to store two pages of IQ data for transform lengths up to 256 points, and the cosine and sine twists of the kernel input twiddlers for transform lengths up to 512 points. Radix-4 kernels are the building blocks for larger transform lengths. Larger Fourier transforms can be constructed from smaller transform "kernels" of arbitrary size using a "mixed radix" algorithm. This algorithm essentially inputs the data into a k × n matrix, where k and n are the sizes of the component transforms for a kn-point transform. First the data is input along the rows, then the first transform is applied to the columns. The intermediate result elements are phase rotated according to their index in the matrix, a second set of transforms is applied to each row of the matrix, and finally the output is naturally ordered as the data is read column-wise. This sequence is shown in Figure 62.

[0334] The mixed radix algorithm can be applied repeatedly to build progressively larger transformations such as those shown in Figure 65. For example, a 1K-point transform might be constructed by using the mixed radix algorithm to create two 16-point transforms each from a 4-point kernel, combining one 16-point with the remaining 4 points to create a 64-point transform, and then combining that 64-point with the remaining 16 points to create a 1024-point transform. Similarly, an implementation might be constructed from 8-point and 16-point transforms using the mixed radix algorithm, first producing a 128-point transform, and then producing a 2k transform from the 128-point and 16-point by another application of the algorithm. 8-point and 16-point transforms can also be constructed from 2-point and 4-point transforms using the mixed radix algorithm. The input and output may be in bit-reversed order.

[0335] FIG. 67 illustrates a string matching use case that may also be implemented using, for example but not limited to, comparators 320 and Boolean logic circuits 325 of one or more RAE circuits 300 including one or more RAE circuit quads 450. One SIMD4 lane per string is used, with one input per SIMD lane. The input stream can be replicated across four lanes to search for four different strings simultaneously. An input delay queue can be used to make the delay due to the AND1 clock shorter than the delay due to the comparison.

[0336] 15. Conclusion

[0337] The reconfigurable processor 100 provides a high-performance and energy-efficient solution for mathematically intensive applications including, but not limited to, artificial intelligence, neural network calculations, digital currency, encryption, decryption, blockchain, Fast Fourier Transform (FFT) calculations, and machine learning.

[0338] Moreover, the reconfigurable processor 100 can be configured for any of these various applications, some such examples are described in more detail below. Such reconfigurable processors 100 are easily scalable to millions of computational cores 200 or the like, have low latency, are computationally energy efficient, can process streaming data in real time, are reconfigurable to optimize the computational hardware for a selected application, and are capable of massively parallel processing. For example, multiple reconfigurable processors 100 can be arrayed on a single chip and connected using an interconnection network 120 to provide hundreds to thousands of computational cores 200 per chip. Multiple such chips can then be arrayed and connected on a circuit board to provide thousands to millions of computational cores 200 per board. Any selected number of computational cores 200 can be implemented within the reconfigurable processor 100, any number of reconfigurable processors 100 can be implemented on a single integrated circuit, and any number of such integrated circuits can be implemented on a circuit board. In this manner, a reconfigurable processor 100 having an array of computational cores 200 is scalable to any selected degree (subject to other constraints such as, but not limited to, routing and heat dissipation).

[0339] 16.General matters The processor circuitry 130 may be any type of processor and may be embodied as one or more RISC-V or other processors configured, designed, programmed, or otherwise adapted to perform the functions described herein. As the term processor circuitry 130 is used herein, the processor circuitry 130 may include the use of a single integrated circuit ("IC"), or may include the use of multiple integrated circuits or other components connected, arranged, or grouped together, such as controllers, microprocessors, digital signal processors, parallel processors, multi-core processors, custom ICs, application specific integrated circuits, field programmable gate arrays ("FPGAs"), adaptive computing ICs, associated memory (RAM, DRAM, ROM, etc.), and other ICs and components, whether analog or digital. As a result, as used herein, the term processor circuitry 130 may refer to the microprocessor memory or additional RAM, DRAM, SDRAM, SRAM, MRAM, ROM, FLASH, EPROM, or ERAM. 2It should be understood to equally mean and include a single IC, or a custom IC, ASIC, processor, microprocessor, microprocessor, controller, FPGA, arrangement of adaptive computing ICs, or other grouping of integrated circuits performing the functions described below, together with associated memory such as a PROM. The processor circuitry 130, together with associated memory, may be adapted or configured (by programming, FPGA interconnection, or hard-wiring) to perform the methodology of the present invention, as described above. For example, the methodology may be programmed and stored within the processor circuitry 130, together with associated memory (and / or memory) and other equivalent components, as a set of program instructions or other code (or equivalent configuration or other program) for subsequent execution when the processor circuitry 130 is operational (i.e., powered on and functioning). Similarly, if the processor circuitry 130 may be implemented in whole or in part as an FPGA, custom IC, and / or ASIC, the FPGA, custom IC, or ASIC may also be designed, configured, and / or wired to implement the methodology of the present invention. For example, the processor circuitry 130 may be implemented as an arrangement of analog and / or digital circuits, controllers, microprocessors, DSPs, and / or ASICs, collectively referred to as "controllers," each of which is hardwired, programmed, designed, adapted or configured, possibly in combination with memory, to implement the methods of the present invention.

[0340] The memory 150, 155, which may include a data repository (or database), may be embodied in any number of forms, including, but not limited to, any computer or other machine-readable data storage medium, memory device or other storage or communication device for storing or communicating information, whether now known or later available, such as a memory integrated circuit ("IC") or memory portion of an integrated circuit (such as resident memory in a processor), RAM, FLASH, DRAM, SDRAM, SRAM, MRAM, FeRAM, ROM, EPROM or ERAM, whether volatile or non-volatile, removable or non-removable. 2 It may include any other form of memory device, including but not limited to PROM, or other machine-readable storage or memory medium such as a magnetic hard drive, optical drive, magnetic disk or tape drive, hard disk drive, floppy disk, CD-ROM, CD-RW, digital versatile disk (DVD) or other optical memory, or other types of memory, storage media, or data storage devices or circuits, as are known or become known depending on the embodiment selected. The memories 150, 155 may be adapted to store various look-up tables, parameters, coefficients, other information and data, programs or instructions (of the software of the present invention), and other types of tables, such as database tables.

[0341] As described above, the processor circuitry 130 is hardwired or programmed to execute the methods of the present invention, for example, using the software and data structures of the present invention. As a result, the systems and methods of the present invention can be embodied as software providing programming or other instructions, such as a set of instructions and / or metadata embodied in a non-transitory computer-readable medium as described above. Additionally, metadata can be utilized to define various data structures of a lookup table or database. Such software can be in the form of, but is not limited to, source code or object code. Source code can further be compiled into some form of instructions or object code (including assembly language instructions or configuration information). The software, source code or metadata of the present invention can be implemented as any type of code, for example, C, C++, SystemC, LISA, XML, Java, Brew, SQL and variants thereof (e.g., SQL99 or proprietary versions of SQL), DB2, Oracle, or any other type of programming language that performs the functionality described herein, including various hardware definition or hardware modeling languages ​​(e.g., Verilog, VHDL, RTL) and the resulting database files (e.g., GDSII). As a result, "construct," "program construct," "software construct," or "software," as used equivalently herein, means and refers to any programming language of any kind, having any syntax or signature, that provides, or can be interpreted to provide, a specified associated function or methodology (e.g., when instantiated or loaded and executed on a processor circuit 130 or computer, including processor circuit 130).

[0342] The software, metadata, or other source code of the present invention, and the resulting bit files (object code, databases, or lookup tables) may be embodied in any tangible, non-transitory storage medium, such as a computer or other machine-readable data storage medium, as computer-readable instructions, data structures, program modules, or other data as described above with respect to memory 140 as described above, e.g., a floppy disk, CD-ROM, CD-RW, DVD, magnetic hard drive, optical drive, or other type of data storage device or medium.

[0343] The present disclosure should be considered as an exemplification of the principles of the invention, and is not intended to limit the invention to the specific embodiments illustrated. In this regard, it should be understood that the invention is not limited in its application to the configuration and arrangement of components illustrated in the drawings or described in the examples, described above and below. Systems, methods, and apparatus consistent with the invention are capable of other embodiments and can be practiced and carried out in various ways, all of which are equivalent and considered to be within the scope of the disclosure.

[0344] Although the present invention has been described with respect to specific embodiments thereof, these embodiments are merely illustrative of the present invention and are not limiting. In the description herein, numerous specific details are provided, such as examples of electronic components, electronic and structural connections, materials, and structural modifications, in order to fully understand the embodiments of the present invention. However, those skilled in the art will recognize that the embodiments of the present invention may be implemented without one or more of the specific details, or with other devices, systems, assemblies, components, materials, parts, and the like. In other instances, well-known structures, materials, or operations are not specifically shown or described in detail to avoid obscuring aspects of the embodiments of the present invention. Additionally, the various figures are not drawn to scale and should not be considered limiting.

[0345] Throughout this specification, reference to "one embodiment," "one embodiment," or a particular "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of the invention, but not necessarily in all embodiments, and further, does not necessarily refer to the same embodiment. Moreover, the particular features, structures, or characteristics of any particular embodiment of the invention can be combined in any suitable manner and in any suitable combination with one or more other embodiments, including the use of selected features without the corresponding use of other features. Moreover, many modifications may be made to adapt a particular application, situation, or material to the essential scope and spirit of the invention. It should be understood that other variations and modifications of the embodiments of the invention described and illustrated herein are possible in light of the teachings herein and are considered to be part of the spirit and scope of the invention.

[0346] In the recitation of numerical ranges herein, each intervening numerical value is expressly contemplated with the same degree of precision. For example, for the range 6-9, the numbers 7 and 8 are contemplated in addition to 6 and 9, and for the range 6.0-7.0, the numbers 6.0, 6.1, 6.2, 6.3, 6.4, 6.5, 6.6, 6.7, 6.8, 6.9, and 7.0 are expressly contemplated. Moreover, all intervening subranges within the ranges are contemplated in any combination and are within the scope of the disclosure. For example, for the range 5 to 10, the subranges 5 to 6, 5 to 7, 5 to 8, 5 to 9, 6 to 7, 6 to 8, 6 to 9, 6 to 10, 7 to 8, 7 to 9, 7 to 10, 8 to 9, 8 to 10, and 9 to 10 are contemplated within the disclosed range.

[0347] It will also be understood that one or more elements shown in the figures may be implemented in a more separate or integrated manner, or may be removed or rendered inoperative in certain cases, as may be useful depending on the particular application. Combinations of integrally formed components are also within the scope of the invention, particularly in the case of embodiments where the separation or combination of individual components is unclear or indistinguishable. Furthermore, use of the term "coupled" herein means and includes direct or indirect electrical, structural or magnetic coupling, connection or attachment, or adaptation or capability for such direct or indirect electrical, structural or magnetic coupling, connection or attachment, including integrally formed components and components that are coupled through or via other components, including various forms such as "coupled" or "connectable."

[0348] Additionally, any signal arrows in the drawings / figures should be considered as illustrative only and not limiting unless otherwise indicated. Combinations of process components are also contemplated within the scope of the present invention, especially when the ability to separate or combine is unclear or predictable. As used throughout this specification and the following claims, the disjunctive term "or" is generally intended to mean "and / or" having both a conjunctive and disjunctive meaning (and not limited to an "exclusive or" meaning), unless otherwise indicated. As used throughout this specification and the following claims, "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Also, as used throughout this specification and the following claims, the meaning of "in" includes "in" and "on," unless the context clearly dictates otherwise.

[0349] The foregoing description of the illustrated embodiments of the invention, including those described in the Abstract or Summary, is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein. From the foregoing, it will be seen that numerous variations, modifications and substitutions are ...

Claims

[Claim 1] a first interconnection network; a second interconnection network; and a processor coupled to the first interconnection network; A reconfigurable processor circuit comprising a plurality of computation cores arranged in an array, the plurality of compute cores are coupled to the first interconnection network and to the second interconnection network, the second interconnection network coupling adjacent compute cores of the plurality of compute cores; Each computing core includes a memory circuit and a reconfigurable arithmetic circuit; The reconfigurable arithmetic circuit includes: at least one input reordering queue; a multiplier-shifter-combiner network coupled to said at least one input reordering queue; Accumulator circuit, at least one control logic circuit coupled to the multiplier-shifter-combiner network and to the accumulator circuit; and A reconfigurable processor circuit comprising: a comparison circuit coupled to the at least one input reordering queue and configured to perform data steering.

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